RISC Processor

RISC stands for Reduced Instruction Set Computer Processor, a microprocessor architecture

with a simple collection and highly customized set of instructions. It is built to minimize the

instruction execution time by optimizing and limiting the number of instructions. It means each

instruction cycle requires only one clock cycle, and each cycle contains three parameters: fetch,

decode and execute. The RISC processor is also used to perform various complex instructions by

combining them into simpler ones. RISC chips require several transistors, making it cheaper to

design and reduce the execution time for instruction.

Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC processors, RISC-V.

Advantages of RISC Processor

1. The RISC processor's performance is better due to the simple and limited number of the

instruction set.

2. It requires several transistors that make it cheaper to design.

3. RISC allows the instruction to use free space on a microprocessor because of its simplicity.

4. RISC processor is simpler than a CISC processor because of its simple and quick design, and

it can complete its work in one clock cycle.

Disadvantages of RISC Processor

1. The RISC processor's performance may vary according to the code executed because

subsequent instructions may depend on the previous instruction for their execution in a cycle.

2. Programmers and compilers often use complex instructions.

3. RISC processors require very fast memory to save various instructions that require a large

collection of cache memory to respond to the instruction in a short time.

RISC Architecture

It is a highly customized set of instructions used in portable devices due to system reliability such as

Apple iPod, mobiles/smartphones, Nintendo DS,

Features of RISC Processor

Some important features of RISC processors are:

1. One cycle execution time: For executing each instruction in a computer, the RISC

processors require one CPI (Clock per cycle). And each CPI includes the fetch, decode and execute

method applied in computer instruction.

2. Pipelining technique: The pipelining technique is used in the RISC processors to execute

multiple parts or stages of instructions to perform more efficiently.

3. A large number of registers: RISC processors are optimized with multiple registers that

can be used to store instruction and quickly respond to the computer and minimize interaction with

computer memory.
4. It supports a simple addressing mode and fixed length of instruction for executing the

pipeline.

5. It uses LOAD and STORE instruction to access the memory location.

6. Simple and limited instruction reduces the execution time of a process in a RISC.

CISC Processor

The CISC Stands for Complex Instruction Set Computer, developed by the Intel. It has a large

collection of complex instructions that range from simple to very complex and specialized in the

assembly language level, which takes a long time to execute the instructions. So, CISC approaches

reducing the number of instruction on each program and ignoring the number of cycles per

instruction. It emphasizes to build complex instructions directly in the hardware because the

hardware is always faster than software. However, CISC chips are relatively slower as compared to

RISC chips but use little instruction than RISC. Examples of CISC processors are VAX, AMD,

Intel x86 and the System/360.

CISC Processors Architecture

The CISC architecture helps reduce program code by embedding multiple operations on each

program instruction, which makes the CISC processor more complex. The CISC architecture-based

computer is designed to decrease memory costs because large programs or instruction required

large memory space to store the data.

Add m1.m2 Load r1.m1

Load r2,m2

Add r1,r2

Sta m,r1
Advantages of CISC Processors

1. The compiler requires little effort to translate high-level programs or statement languages

into assembly or machine language in CISC processors.

2. The code length is quite short, which minimizes the memory requirement.

3. To store the instruction on each CISC, it requires very less RAM.

4. Execution of a single instruction requires several low-level tasks.

5. CISC creates a process to manage power usage that adjusts clock speed and voltage.

6. It uses fewer instructions set to perform the same instruction as the RISC.

Disadvantages of CISC Processors

1. CISC chips are slower than RSIC chips to execute per instruction cycle on each program.

2. The performance of the machine decreases due to the slowness of the clock speed.

3. Executing the pipeline in the CISC processor makes it complicated to use.

4. The CISC chips require more transistors as compared to RISC design.

5. In CISC it uses only 20% of existing instructions in a programming event.

Difference between the RISC and CISC Processors

CISC RISC

A large number of instructions are present in the Very few instructions are present. The number of
architecture. instructions is generally less than 100.

Some instructions with long execution times.

These include instructions that copy an entire
No instruction with a long execution time due to a
block from one part of memory to another and
very simple instruction set.
others that copy multiple registers to and from
memory.

Variable-length encodings of the instructions. Fixed-length encodings of the instructions are used.
Example: IA32 instruction size can range from Example: In IA32, generally all instructions are
1 to 15 bytes. encoded as 4 bytes.

Multiple formats are supported for specifying

operands. A memory operand specifier can have Simple addressing formats are supported. Only base
many different combinations of displacement, and displacement addressing is allowed.
base, and index register.

CISC supports array. RISC does not support an array.

Arithmetic and logical operations only use register

operands. Memory referencing is only allowed by
Arithmetic and logical operations can be applied
loading and storing instructions, i.e. reading from
to both memory and register operands.
memory into a register and writing from a register to
memory respectively.
CISC RISC

Condition codes are used. No condition codes are used.

Registers are being used for procedure arguments

The stack is being used for procedure arguments
and return addresses. Memory references can be
and returns addresses.
avoided by some procedures.

Unsuccessful pipeline Successful pipeline with one instruction per cycle

Heavy use of RAM More efficient use of RAM

Registers Involved In Each Instruction Cycle:

Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies the

address in memory for a read or write operation.

Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the value to

be stored in memory or the last value read from the memory.

Program Counter(PC) : Holds the address of the next instruction to be fetched.

Instruction Register(IR) : Holds the last instruction fetched.

In computer organization, an instruction cycle, also known as a fetch-decode-execute cycle, is the basic

operation performed by a central processing unit (CPU) to execute an instruction. The instruction cycle

consists of several steps, each of which performs a specific function in the execution of the instruction. The

major steps in the instruction cycle are:

Fetch: In the fetch cycle, the CPU retrieves the instruction from memory. The instruction is typically stored

at the address specified by the program counter (PC). The PC is then incremented to point to the next

instruction in memory.
Decode: In the decode cycle, the CPU interprets the instruction and determines what operation needs to be

performed. This involves identifying the opcode and any operands that are needed to execute the instruction.

Execute: In the execute cycle, the CPU performs the operation specified by the instruction. This may

involve reading or writing data from or to memory, performing arithmetic or logic operations on data, or

manipulating the control flow of the program.

There are also some additional steps that may be performed during the instruction cycle, depending on the

CPU architecture and instruction set:

Fetch operands: In some CPUs, the operands needed for an instruction are fetched during a separate cycle

before the execute cycle. This is called the fetch operands cycle.

Store results: In some CPUs, the results of an instruction are stored during a separate cycle after the execute

cycle. This is called the store results cycle.

Interrupt handling: In some CPUs, interrupt handling may occur during any cycle of the instruction cycle.

An interrupt is a signal that the CPU receives from an external device or software that requires immediate

attention. When an interrupt occurs, the CPU suspends the current instruction and executes an interrupt

handler to service the interrupt.

These cycles are the basic building blocks of the CPU’s operation and are performed for every instruction

executed by the CPU. By optimizing these cycles, CPU designers can improve the performance and

efficiency of the CPU, allowing it to execute instructions faster and more efficiently.

The Instruction Cycle – Each phase of Instruction Cycle can be decomposed into a sequence of elementary

micro-operations. In the above examples, there is one sequence each for the Fetch, Indirect, Execute and

Interrupt Cycles.

The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always followed by the

Fetch Cycle. For both fetch and execute cycles, the next cycle depends on the state of the system.

Registers Involved In Each Instruction Cycle:

 Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies
the address in memory for a read or write operation.
 Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the
value to be stored in memory or the last value read from the memory.
 Program Counter(PC) : Holds the address of the next instruction to be fetched.
 Instruction Register(IR) : Holds the last instruction fetched.
In computer organization, an instruction cycle, also known as a fetch-decode-execute cycle, is the basic
operation performed by a central processing unit (CPU) to execute an instruction. The instruction cycle
consists of several steps, each of which performs a specific function in the execution of the instruction.
The major steps in the instruction cycle are:
1. Fetch: In the fetch cycle, the CPU retrieves the instruction from memory. The instruction is typically
stored at the address specified by the program counter (PC). The PC is then incremented to point to
the next instruction in memory.
2. Decode: In the decode cycle, the CPU interprets the instruction and determines what operation needs
to be performed. This involves identifying the opcode and any operands that are needed to execute the
instruction.
3. Execute: In the execute cycle, the CPU performs the operation specified by the instruction. This may
involve reading or writing data from or to memory, performing arithmetic or logic operations on data,
or manipulating the control flow of the program.
4. There are also some additional steps that may be performed during the instruction cycle, depending on
the CPU architecture and instruction set:
5. Fetch operands: In some CPUs, the operands needed for an instruction are fetched during a separate
cycle before the execute cycle. This is called the fetch operands cycle.
6. Store results: In some CPUs, the results of an instruction are stored during a separate cycle after the
execute cycle. This is called the store results cycle.
7. Interrupt handling: In some CPUs, interrupt handling may occur during any cycle of the instruction
cycle. An interrupt is a signal that the CPU receives from an external device or software that requires
immediate attention. When an interrupt occurs, the CPU suspends the current instruction and executes
an interrupt handler to service the interrupt.
These cycles are the basic building blocks of the CPU’s operation and are performed for every instruction
executed by the CPU. By optimizing these cycles, CPU designers can improve the performance and
efficiency of the CPU, allowing it to execute instructions faster and more efficiently.
The Instruction Cycle –
Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro-operations. In
the above examples, there is one sequence each for the Fetch, Indirect, Execute and Interrupt Cycles.
The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always followed by
the Fetch Cycle. For both fetch and execute cycles, the next cycle depends on the state of the system.