2022-2023

a. Transform the following C code to assembly instruction. Store the value of s1, s2, t1 , t2 and
t3 in registers $s1, $s2, $t1, $t2 and $t3 respectively.

if (s1 == s2)
t3 = (t1 - t2) + (s1 - s2);
else
t3 (t1 + t2) - (s1 + s2);
ANS:
# Assuming sl, s2, tl, t2, t3 are integers
# $sl, $s2, $tl, $t2, $t3 are registers

# Load sl, s2, tl, t2 into respective registers

lw $sl, sl_address # Load sl into $sl
lw $s2, s2_address # Load s2 into $s2
lw $tl, tl_address # Load tl into $tl
lw $t2, t2_address # Load t2 into $t2

# Compare sl and s2
beq $sl, $s2, equal_case # Branch to equal_case if sl == s2

# Not equal case

add $t3, $tl, $t2 # t3 = tl + t2
add $t3, $t3, $sl # t3 = t3 + sl
sub $t3, $t3, $s2 # t3 = t3 - s2
j end # Jump to the end

# Equal case
equal_case:
sub $t3, $tl, $t2 # t3 = tl - t2
sub $t3, $t3, $sl # t3 = t3 - sl

end:

Qb

#initialize register

#start of procedure

START:

addi $t1, $t1, -1

addi $t2, $t2, 5

addi $t3, $t3, -2

bne $t1, $0, START

li $v0, 10

syscall

i. Specify the additional MIPS instruction required to initialize register $tl, $t2 and $t3 with
immediate values as following: $tl = 10 , $t2 = 20 , $t3 30 (3 marks)
li $t1, 0 # Initialize $t1 with 0
li $t2, 20 # Initialize $t2 with 20
li $t3, 30 # Initialize $t3 with 30

ii. For code snippet in Figure 1, write the equivalent CIC++ code. Assume that the register
$t1, $t2 and $t3 are integer t1, t2 and t3 respectively.

t1 = 0;
t2 = 20;
t3 = 30;

START label
while (t1!= 0) {
t1 = t1 - 1;
t2 = t2 + 5;
t3 = t3 - 2;
}

// System call to exit

exit(0);

iii. By referring to MIPS Reference Data, convert 0x2 1AC0043 machine instruction in
hexadecimal into assembly code. Explain how you get the answer.

0x21AC0043

Binary: 0010 0001 1010 1100 0000 0000 0100 0011

addi $t3, $t2, 67

a. By using a suitable diagram, illustrate the relationship between the data path and CPU
clocking when applied on Single Cycle CPU and Multiple Cycle CPU. (6 marks)

In a Single Cycle CPU, each instruction is executed in a single clock cycle. The data path includes all
necessary components required for instruction execution, and the clocking mechanism ensures that
each part of the data path operates within the same clock cycle.

In a Multiple Cycle CPU, each instruction is divided into several stages, and each stage takes one
clock cycle. The data path is broken down into stages, and the clocking mechanism ensures that each
stage completes its operation within the specified clock cycle.
b. Refers to the given instruction, explain the process which is required for each stage of
the data path: add $t0, $t2, $t1 (5 marks)

1. Instruction Fetch (IF):

o The instruction is fetched from memory and placed in the instruction register
(IR).
o The program counter (PC) is updated to point to the next instruction.
2. Decode (ID):
o The opcode of the instruction is decoded.
o Registers $t2 and $t1 are read to get their values.
3. Execute (EX):
o The ALU adds the values from registers $t2 and $t1.
o The result is stored in a temporary location.
4. Memory Access (MEM):
o No memory access is needed for this operation.
5. Write Back (WB):
o The result is written back to register $t0.

Discuss THREE (3) possible hardware and its functionality involves during execution of an
instruction. (6 marks)

Instruction Memory: This is the hardware that stores the instructions of the program and
provides them to the CPU when requested. It has an input for the instruction address and an
output for the instruction word.

Register File: This is the hardware that stores the values of the registers and allows reading and
writing to them. It has two inputs for the register numbers to be read, two outputs for the
register values to be read, one input for the register number to be written, one input for the
register value to be written, and one input for the write enable signal.

ALU: This is the hardware that performs arithmetic and logic operations on the operands and
produces the result and the zero flag. It has two inputs for the operands, one input for the
operation code, one output for the result, and one output for the zero flag.

d. Justify how the implementation of Pipeline able to improve execution of data path for
a single cycle CPU. Use the given information to calculate the speed for the pipeline
performance.

Each stage equally takes 200 picoseconds

Number of instructions involves are 5 lines

Speed of Pipeline=5×200picoseconds=1000picoseconds
a. Figure 2 illustrates a typical organization of a personal computer. Based on Figure 2, discuss the
relationship among access time, memory cost, and capacity for register, L1 cache and L2 cache.

1. Registers:
o Access Time: Registers are the fastest and smallest form of memory directly
accessible by the CPU. Access to registers is almost instantaneous.
o Memory Cost: Registers are expensive to manufacture and have a limited capacity.
They are usually built directly into the CPU.
o Capacity: Registers have very limited capacity, typically ranging from a few bytes to
a few kilobytes. They store a small amount of data that is currently being operated
on by the CPU.
2. L1 Cache (Level 1 Cache):
o Access Time: L1 cache provides fast access to frequently used data and instructions.
It is faster than accessing main memory but slower than registers.
o Memory Cost: L1 cache is more expensive than main memory but less expensive
than registers. It is often integrated into the CPU chip.
o Capacity: L1 cache has a limited capacity compared to main memory, typically
ranging from tens of kilobytes to a few hundred kilobytes.
3. L2 Cache (Level 2 Cache):
o Access Time: L2 cache is slower than L1 cache but faster than main memory. It
serves as a larger and slower cache that complements L1 cache.
o Memory Cost: L2 cache is less expensive than L1 cache but more expensive than
main memory. It may be located on the CPU chip or on a separate chip.
o Capacity: L2 cache has a larger capacity compared to L1 cache, typically ranging
from a few hundred kilobytes to several megabytes.

Figure 3 illustrates a cache memory that can hold up to four pieces of data. In Figure 3, three pieces
of data, which are 4, I and 7 have been accessed by the processor. Exp1ain how the Least Recently
Used (LRU) replacement algorithm is used to allocate the memory space in the cache memory for
the following data sequence 10,4,8, l (7 marks)

4 1 7
Figure 3: A four-slot cache memory
Figure 4 shows a hard drive with four logical strips. Refer to Figure 4 for Question c(i) and (ii).

Block 4 Drive 1 Figure 4: A hard drive Drive 1 with four logical stril

1. Identify which RAID level should a user implement if the user wants to achieve 100%
redundancy for Drive 1 but with only one extra hard drive?

If the user wants to achieve 100% redundancy for Drive 1 with only one extra hard drive, the
appropriate RAID level is RAID 1 (Mirroring).

Explanation:

• RAID 1 (Mirroring) duplicates the data on Drive 1 onto the extra hard drive (Drive 2
in this case).
• Both Drive 1 and Drive 2 contain identical copies of the data, providing 100%
redundancy.
• If Drive 1 fails, the system can continue to operate using Drive 2 without any loss of
data.

2. Referring to Drive 1 in Figure 4, explain the characteristics of the RAID level from Question
c(i)?

2. Characteristics of RAID 1:
o Redundancy: 100% redundancy is achieved as data is mirrored between the
drives.
o Capacity: The effective capacity of a RAID 1 array is equal to the capacity of
a single drive since all data is duplicated.
o Performance: Read performance is improved as data can be read from both
drives simultaneously. Write performance is typically similar to that of a
single drive.
o Fault Tolerance: RAID 1 provides excellent fault tolerance. The failure of
one drive (e.g., Drive 1) doesn't result in data loss, as the system can still
operate using the mirrored drive (e.g., Drive 2).
o Number of Drives Required: At least two drives are required for RAID 1.
o Capacity Utilization: RAID 1 offers less capacity compared to the total
capacity of all drives combined because all data is duplicated.
In summary, RAID 1 is a good choice when the primary concern is redundancy, and the user
wants to ensure that data remains available even if one drive fails. The trade-off is the
effective capacity, which is limited to the capacity of a single drive in the array.

a.An external device connected to an I/O module is often referred to as a peripheral device.
We can broadly classify external devices into three categories. List THREE (3) categories and
give an example for each category. (6 marks)

a. Three Categories of External Devices:

1. Storage Devices:
o Example: Hard Disk Drive (HDD)
2. Input Devices:
o Example: Keyboard
3. Output Devices:
o Example: Printer

b. Input/Output (I/O) Module is an interface to processor, memory and peripheral devices.

Describe TWO (2) function of (I/0) Module. (4 marks)

1. Data Transfer: The I/O module facilitates the transfer of data between the processor,
memory, and peripheral devices. It manages the flow of data between these
components, ensuring efficient communication.
2. Control and Timing: The I/O module provides control signals and timing
mechanisms necessary for coordinating the data transfer between the processor,
memory, and external devices. It synchronizes the operations to ensure proper
functioning.

c. In addition to the processor and a set of memory modules, another key element of
computer system is a set of Input/Output (I/O) modules. There are three techniques possible
for Input/Output (1/0) operations. Compare all THREE (3) techniques in terms of strengths or
weaknesses for the possibility oflnput/Output (I/O) operations. (9 marks)

Programmed I/O: In this technique, the processor initiates and controls the data transfer
between the I/O module and the peripheral device. The processor issues commands to the
I/O module, and then polls the status of the I/O module until the data transfer is complete.
The processor is busy during the entire I/O operation, and cannot perform other tasks. The
advantages of this technique are simplicity and reliability. The disadvantages are low
efficiency and high processor overhead.
Interrupt-driven I/O: In this technique, the processor initiates the data transfer between the
I/O module and the peripheral device, but then resumes its other tasks. The I/O module
generates an interrupt signal to the processor when the data transfer is complete or when
an error occurs. The processor then responds to the interrupt and handles the I/O operation.
The advantages of this technique are higher efficiency and lower processor overhead. The
disadvantages are increased complexity and potential conflicts with other interrupts.
Direct memory access (DMA): In this technique, the processor delegates the data transfer
between the I/O module and the peripheral device to a special hardware device called the
DMA controller. The processor only sets up the parameters of the data transfer, such as the
source and destination addresses, the amount of data, and the mode of transfer. The DMA
controller then takes over the system bus and transfers the data directly between the I/O
module and the memory, without involving the processor. The processor is notified by an
interrupt when the data transfer is complete. The advantages of this technique are highest
efficiency and lowest processor overhead. The disadvantages are increased cost and
complexity, and potential bus contention with the processor.

d.Illustrate serial and parallel interface block diagram. (6 marks)

In both diagrams, the device connects to a communication controller, which interfaces with
a data link controller. The controllers manage the flow of data between the device and the
system, ensuring proper communication. The difference lies in the nature of the interface,
with serial transmitting data sequentially over a single line, and parallel transmitting multiple
bits simultaneously over separate lines.