Development of SVPWM Switched Three Level

Inverter fed Induction Motor Drive

Prashant Jain1, S. Eswar Rao2, Bishnu Prasad Muni3
[email protected], [email protected], [email protected]
BHEL R&D, Hyderabad

Abstract —This paper presents the implementation of simplified

Space Vector Pulse Width Modulation (SVPWM) Scheme for II. SPACE VECTOR PWM SIGNALS FOR THREE-LEVEL NPC
Neutral Point Clamped (NPC) inverter fed induction motor INVERTER
drive. The paper also presents the superiority of three level
Voltage Source Inverter (VSI) fed drive as compared to two level
VSI fed drive in terms of Harmonics of output waveform. The
validity of the SVPWM scheme is verified by experiment on
10kW three-level Insulated Gate Bipolar Transistor (IGBT)
inverter using TMS320F2810 based Microcontroller.

Keywords— SVPWM, Three Level NPC, TMS320F2810

I. INTRODUCTION
MULTILEVEL inverters are being used in high-power
medium voltage applications due to their superior
performance compared to two-level inverters, The inverter can
be generally configured as a three, five, seven level topology,
Fig 2.1 Three Level NPC Inverter
but mostly three-level NPC inverter has found wide
application in high-power medium voltage (MV) drives. The 2.1 Three Level NPC inverter
main features of the NPC inverter includes : The diode-clamped inverter is also called the NPC inverter.
No dynamic voltage sharing problem A three-level diode-clamped inverter is shown in Fig 2.1. In
Each of the switches in the NPC inverter withstands only this circuit, the dc-bus voltage is split into two series-
half of the total dc voltage during commutation. connected bulk capacitors, C1 and C2. The middle point N of
Static voltage equalization with out using additional the two capacitors can be defined as the neutral point. The
components output voltage Van has three states: Vdc/2, 0, and -Vdc/2. For
The static voltage equalization can be achieved when the voltage level Vdc/2, switches S1 and S2 need to be turned on;
leakage current of the top and bottom switches in an inverter for -Vdc/2, switches S11 and S21 need to be turned on; and for
leg is selected to be lower than that of the inner switches. the 0 level, S2 and S11 need to be turned on. . The switch status
Low THD and dv/dt and definition of state for phase A of inverter is shown in
The waveform of the line-to-line voltage is composed of Table 2.1.
five voltage levels, which leads to lower THD and dv/dt in
comparison to the two-level inverter operating at the same
voltage rating and device switching frequency. Switch status State Phase A voltage
Among various modulation techniques for a NPC inverter, S1=ON , S2=ON,
SVPWM is an attractive candidate due to the following merits.
S11=OFF, S12=OFF S=2 VAn=Vdc/2
It directly uses the control variable given by the control
system and identifies each switching vector as a point in D1=OFF , D2=OFF
complex (α, β) space. It is suitable for Digital Signal S1=OFF , S2=ON,
Processor (DSP) implementation. It can optimize switching S11=ON , S12=OFF
sequences. The location of the reference voltage vector and D5 and D6 will conduct depending S=1 VAn=0V
the dwell times of the space vectors can be calculated very
on the polarity of the load current
easily and higher output voltage in linear modulation region.
The proposed methods are verified by experimental results S1=OFF, S2=OFF,
and discussed in detail in following parts. S11=ON , S12=ON S=0 VAn=-Vdc/2
D1=OFF , D2=OFF

Table 2.1 Diode Clamped Inverter: Switches Status

(V0),Small voltage vector (V1 to V6),Medium voltage vector
The operation of the each inverter phase leg can be (V7 to V12 ),Large voltage vector (V13 to V18) as shown in
represented by three switching states 0, 1 and 2.Taking all below Table 2.3
three phases in account there are altogether 27 switching
states in diode-clamped three-level inverter shown in Table2.2. Vector classification Space vector Vector magnitude

Zero vector V0 0
The switches The corresponding
A B C voltage vectors Small vector V1 toV6 1/3 Vdc
states
Medium vector V7 toV12
S1 0 0 0 V0 3 /3 Vdc
S2 1 1 1 V0 Large vector V13 toV18 2/3 Vdc

S3 2 2 2 V0

S4 1 0 0 V1 Table 2.3 Vector Classification and its Magnitude

S5 1 1 0 V2 The plane can be divided into 6 major triangular sectors (I to

VI enclosed by solid lines) by large voltage vectors and zero
S6 0 1 0 V3 voltage vector. Each section represents 60° of the fundamental
S7 0 1 1 V4
cycle. Within each major sector, there are 4 minor triangular
sectors (enclosed by the dotted lines). There are totally 24
S8 0 0 1 V5 minor sectors in the plane and the vertices of these sectors
represent the voltage vectors as shown in Fig 2.2
S9 1 0 1 V6

S10 2 1 1 V1

S11 2 2 1 V2

S12 1 2 1 V3

S13 1 2 2 V4

S14 1 1 2 V5

S15 2 1 2 V6

S16 2 1 0 V7

S17 1 2 0 V8

S18 0 2 1 V9

S19 0 1 2 V10

S20 1 0 2 V11 Fig 2.2 Space vector Sectors and Regions of Three level Inverter
S21 2 0 1 V12
2.2 Determination of Vα, Vβ, Vref, and angle (θ)
S22 2 0 0 V13
Assuming that the operation of the inverter is three phase
S23 2 2 0 V14
balanced. We have
S24 0 2 0 V15
VA (t)+VB (t)+VC (t)=0
S25 0 2 2 V16 Where VA (t),VB(t),VC (t) are the instantaneous load phase
S26 0 0 2 V17 voltages.
To implement the space vector PWM, the voltage
S27 2 0 2 V18 equations in the abc reference frame can be transformed into
Table 2.2 Switching State and corresponding Switching Vector
the stationary αβ reference frame that consists of the
horizontal (α) and vertical (β) axes.
The Vα, Vβ, Vref, and angle (θ) can be determined as
They correspond to 19 voltage vectors (V0 to V18) whose follows:
positions are fixed. Based on their magnitude, the voltage Transformation of three phase variable to two phase
vectors can be classified into four groups: Zero voltage vector variable
 1 1  VAN  m= Vref /[(2/3) Vdc ] (2.3.5)
 1 − −
 
Vα
2 2  VBN  As shown in Fig. 2.3, the boundaries of modulation ratio
Vβ  =  3

− 3  
(2.2.1)
  0 VCN 
are ml, m2 and m3. The equation forms of them are obtained as
 2 2    follows:
m1 = ( 3 /2) / ( 3 cos θ + sin θ) (2.3.6)
 Vα  m2 = ( 3 /2 ) / ( 3 cos θ - sin θ) , θ <= Π /6 (2.3.7)
θ = tan −1   (2.2.2)
 V  3 /4) / sin θ , θ /6< θ <= Π /3
 β  =(
2 2 m3 = ( 3 ) / ( 3 cos θ + sin θ) (2.3.8)
V ref = (Vα + V β ) (2.2.3)
2.3.2 Determination of time duration Tx,Ty, Tz
2.3 Dwell time calculation
Here takes an example. As illustrated in Fig 2.3, we can
If the triangle sector is defined by vector Vx, Vy, and Vz, suppose that the rotating voltage Vref falls into sector I
then Vref can be synthesized by Vx, Vy, and Vz. The Dwell (0<θ<60°). Notice that there are 4 minor sectors, D1, D7, D13
time calculation is based on ‘Volt-Second balancing principle’, and D14 in this sector, then X, Y, and Z can be calculated with
that is, the product of Vref and the sampling period Ts is equal the following four cases, respectively.
to the sum of the voltage multiplied by the time interval of
chosen space vector. A. When the modulation ratio m<ml, the rotating voltage
For instance, when Vref falls in region D1 of sector I as vector Vref is in sector D1. As shown in Fig.2.3, Vref is
shown in Fig 2.3 synthesized by V1, V2 and V0. Using to Eqn. (2.3.4), the
following equation is acquired

X = 2m [cos θ – (sin θ / 3 )]
Y = 4m (sin θ / 3) (2.3.9)
Z = 1- 2m [cos θ + (sin θ / 3 )]

B. Similarly, when ml <m< m2, Vref is in sector D7. Vref can

be synthesized by V1, V2 and V7 .

X = 1- 4m (sin θ / 3)
Y = 1- 2m [cos θ - (sin θ / 3 )] (2.3.10)

A Fig. 2.3 The Space Vector Diagram of Sector I Z = 2m [cos θ + (sin θ / 3 ]-1
Vx Tx + Vy Ty + Vz Tz = Vref Ts C. When m2<m< m3 and 0°< θ <30°, Vref is in sector D13.
Tx +Ty +Tz =Ts V1, V13 and V7 are selected to synthesize Vref.

Then X, Y, and Z can be defined as the following equations:

X =2 - 2m [cos θ + (sin θ / 3 )]
X = Tx / Ts (2.3.1) Y = 2m [cos θ - (sin θ / 3 )]-1 (2.3.11)
Y = Ty / Ts (2.3.2)
Z = Tz / Ts (2.3.3) Z = 4m (sin θ / 3)
Based on the principle of vector synthesis, the following
equations can be written: D. When m2<m< m3 and, 30°< θ <60°, Vref is in sector D14.
Vectors V14, V2 and V7 will be employed to generate the
Vx X+ Vy Y+ Vz Z= Vref (2.3.4) required voltage.

2.3.1 Determination of m, m1, m2, m3 X =4m (sin θ / 3 ) -1

The modulation ratio of three-phase three-level inverter is Y =2 - 2m [cos θ + (sin θ / 3 )] (2.3.12)
represented as follows
Z =2m [cos θ - (sin θ / 3 )]
When the reference vector falls into the others major 100 200 210 211
sectors, similar argument can be applied. Replacing θ of Eqns. R1
(2.3.9) to (2.3.12) by θ -60°, θ -120°, θ -180°, θ -240°, and θ -
300° respectively, the calculation of the entire coordinate R2
plane can be established.
Y1
2.4 Determination of Switching Sequence
Y2
The PWM switching pattern for top two switches S1 and S2
(Fig 2.1) for each phases in different regions of Sector-1 B1
based on equation (2.3.1, 2.3.2, 2.3.3) is shown below in
Fig.2.4(a), 2.4(b), 2.4(c), 2.4(d) B2

Region-1: 000,100,110,111,211,221,222 Ty/4 Tz/2 Tx/2 Ty/4

Region-2: 100,110,210,211,221
Region-3: 100,200,210,211 Ts/2
Region-4: 110,210,220,221
Fig. 2.4(c) Timing switching sequence in Region 3(Sector I)
000 100 110 111 211 221 222

R1
110 210 220 221
R2
R1

Y1 R2

Y2 Y1

B1 Y2

B2 B1

B2
Tz/8 Tx/4 Ty/4 Tz/4 Tx/4 Ty/4 Tz/8

Ty/4 Tz/2 Tx/2 Ty/4

Ts/2

Ts/2
Fig. 2.4(a) Timing switching sequence in Region 1(Sector I)

100 110 210 211 221

Fig. 2.4(d) Timing switching sequence in Region 4(Sector I)
R1
Switching sequence for bottom switches S1’ and S2’ (Fig
2.1) are the complement of switching pattern of switches S1
R2
and S2 of respective phase.
In PWM sequence above, we can see that switching mode
Y1 of each phase changes twice during one PWM period. This
can be fulfilled very easily with the Event Manager A and
Y2 Event Manager B in TMS320F2810 DSP.

III EXPERIMENTAL RESULTS

B1

The proposed SVPWM method was implemented with the

B2 Tx/4 Ty/4 Tz/2 Tx/4 Tz/4 TMS320F2810 DSP board and 10 kW NPC Three Level
IGBT based Inverter was used for the experiment.
Ts/2
The waveforms shown in Fig. 3.1(a) and 3.1(b) are the
Fig. 2.4(b) Timing switching sequence in Region 2(Sector I) voltage waveform of three level and two level operation test
results driving 415 V, 3.7 kW induction motor at 600 V dc-
link voltage respectively. The waveform shown in Fig. 3.1(c) HARMONIC ANALYSIS Three Level Two Level

is the motor current. 4

The Harmonic Analysis of Three Level and Two Level 3.5
voltage waveform done using MATLAB/SIMULINK Fig 3
3.1(d) compares Two Level and Three Level Total Harmonic 2.5
Distortion (THD) at different Modulation Index. THD at

THD
2
different MI is also verified experimentally using
1.5
TMS320F2810 DSP.
1

0.5

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
MI

Fig 3.1(d)Harmonic Analysis of voltage waveform at different MI (f1 = 50

Hz, Fs = 900Hz)

IV CONCLUSION

The validity of SVPWM method is verified by

experimental result with NPC inverter fed induction motor
using TMS320F2810 based microcontroller. The superiority
Fig. 3.1(a)Voltage waveforms of the NPC inverter (f1 = 50 Hz, Fs = 900Hz, of three level as compared to two level is verified using both
m = 0.7) MATLAB simulation and DSP implementation.

V ACKNOWLEDGMENT
The author thanks the management of BHEL R&D to carry
out the work and report the result to this conference.
.

REFERENCES

[1] Bin Wu, “High-Power converters and AC Drives”, Wiley & Sons,
Publication, pp. 143–179.
[2] Lei Lin,Yunping Zou,Jie Zhang,Xuodong Zou “Digital implementation
of Diode-clamped Three-phase Three-level SVPWM Inverter” pp 1413 -
1417 IEEE Tran. Ind Appl., 2003.
[3] User Manual TMS320F28xx Available online: http://www.ti.com
Fig 3.1(b)Voltage waveforms of Two level inverter (f1 = 50 Hz, Fs = 900Hz, [4] Nabae,I Takahashi and H. Akagi.”A new neutral point-clamped PWM
m = 0.7) inverter”,IEEE Tran. Ind Appl, Vol.IA-17, pp. 518-523, Sept./Oct.
1981..

Fig 3.1(c)Current waveforms of induction motor (f1 = 50 Hz, Fs = 900Hz)