Qi, Explain the basic architectural features of programmable DSP devices. Ans; Th hardware features are, On-chip registers to store intermediate results 2. Onchip memories for signal samples (RAM). 3.___ On-chip program memory for programs and fixed data, QZ. List the basic characteristics of digital signal processor. ‘The basic characteristics of digital signal processor are, °, : It can be used as a direct memory access device in supporting or host environments. 2. They take analog signals asiput, conver them to digital form, process the signals and then converts them back io analog form, : - pers, et, 80) ‘Apert, Sa, 280) ‘They do not provide hardware that supports multtysing. Tey ate equipped to handle real time processing, Vote tof pani Pe Apris6, S002, 210) ges Tatras of DAP poms ty: The DSP processors prom fas provesing of aay, ‘They need only one clock eycle to execute instructions. ‘ se processor pein parle exciton ofinuctins! : “, They have separate program and dala memories, : a4. ee Ans: : * ‘atts, Sub, 000, + 1h igloo OIE Ce Me _ : 1°” AND epniversion ecrors , “3. DA conversion eno. sii ans Nase ie Ry 8 a oeop or.mi ee DIGITAL SIGNAL PROCESSING [JNTU-KAKINADAI UNIT- ‘G5. What is MAC? Draw its Block diagram, (G8. Listthe special addressing modes and on-chip. ant Ans: Me! Paper 24) peripherals of programmable DSPs. is | ‘A Dfuliptyand Accumulate (MAC) initis a combination ‘of two wits namely multiply unit end an accurmlstor register. Figure shows the block diagram ofa MAC wit An accumulator slong with add/subtract unit is used to store the product, a8 a result of sequence of consecutive multiplication operations which are required in application. Muir np Andis) B (ob) a ‘Provinct Register Proxdvet (2n bits) \_ aon _/ =m a = gore: Matipy and Aecumaat (AC) Unit ‘26. Explain multiple access memory. Ans: Wodet Papert at) ‘The memory that enables muttiple access per clock period is referred to as multiple access memory. With the help of ehigh speed meniiy, the mer of memory acesses/clock petiod is increased. Two memory accessesilock period is obtained with he dual acess RAM (Rastdom Access Memory). ‘By using Harvard architecture iti possible to connect multiple |. RAM to the processing unit of programmable DSP. Four | memory accesses/lock pciod can also be obtained with dual ‘access RAM, when itis connected to programmable DSP with to separate address and data buses, Q7. What are the advantages of VLIN architecture? same _ Aor, Seba, atin ‘Note: In question VLIW is mispeinted as VLIN. ‘The advantages of VLIW architecture ae, Performance is high. . . Easy to program. Highly scalable. More umber of execution units tan b added allowing increased length of instruction in VLIW. 28. Wat rte ferent stage i ppg? sens co) List the ori-chip peripherals. ‘Apt, 63, 010) Ane: Special addressing modes ‘The special addressing, mode’ of programmable DSPs 1. Shor immedite addressing 2. Short rec sessing 3, Memory mapped atesing 4. Indirect addressing Su. Bitrevred adéressing 6. Circular addressing. On-chip Peripherals ‘The on-chip petipherals of programmable DSPs sre, ‘On-chip timer ‘Serial port TDM serial port Parle port BitVO ports Host port ‘Comim ports: ‘AdorD and Dio‘A converters. |.Q10. Explain the role of on-chip peripherals for Programmable digital signal processors. ‘ae, Seb, a) “The functions performed by on-chip petipherals are,” 1. The feature of inteyfcing with exteral devices lke coer aera Aen cere heat ‘using on-chip peripherals, 2 ‘Onchip wthheclie codons hese ities Se 2 ae ee Ans: © Ans: mer v |The differen stages of pipelining ae, help of processors. % Hardware mer isan on-chip down counier which is ‘dpcessary in real time systern implementation with the”LUNIT:6 (hiroducton To DSP Processors and Architecture of TMS320C5%) ce np rf. Mention various goneratlons of dgltal signal processors. - me Anis: ‘ oeh6, at ‘The various generation of Digit Signal Processor (TMS320) are, i asa20cix assanczx “TMS32003x TMSI2004x TMS320C5x TMS32006x ‘TMs32008x 3 Here, CIX represents fist generation; C2X represents second generation; ee. ‘The TMSS2001X, C2X and CSK are 16 bit ited point processors and TMS320CS4X isthe advanced) ‘The TMS520C3X, 4X are 32 bit loting point processors. Q42. What are the functional units present In the TMS320C54XX processor? Ans: ae ‘The following are the functional units that are present in TMS320CS4XX processor. . © Obit ALU . 40-bit Accumulators Bare shifter, 17 17-it miler ‘CSSU (Compare, Select and Store Unit) Exponent encoder mn SPA awe ee Q13. Write any four features of TMS320C54X st special feature of DSP arctiecture. ‘The features of TMS320C54X process are, 1. The performance of TMS320C54X processor high. 2, TMS320CS4X isa low power consumption processor. 3. headed masher which provi envi 1 ta memory Iepovides 408 itn Loge Unt (ALU), which oss of 40 ae shiteo_o SISITAL SIGNAL pRocessy r lay Foster in TUS20CH SSING LINTU.KAKIADAL Explain a Ma Poet Sah aR ites 80. ARD a, : Origen CALLS pe tld the oped td mon Iie Unt (ARAU. The ses sed indirect ade sre Ashe Gs What are the differences between find type Ae, So, a0 Beswee xed and Noating poi cess ae — Rating Polat Proceasr ‘tie Pl pce «mney mcd ae ie Product of vo tipped suber, te Manisa an exponent. M6432. oan pit DSP proce . In his pres, under o ovetow enor do not ca ‘xed point processor, a binary point is used Floating point processr oes igh ccurney — icrag tp an range.DAL aun liary rage. ann {yeu unvoaucnon 10 USP Procossors and Architecture of TMS320C5X) Qt. Listhe Toajorarehiigeiral atures used in DBP aysiom fo poMavs high apeed program execilon Ans: ‘Ao, $3, a) ‘In Digital Signal Processing (DSP) atchitectre there tide Features are t be considered, For high speed of operation. To achueve this, the folowing 1. Architecture of Hardwate There are algorithms for processing sighs that ned fo impleent functions like muliptication, ling, loops and repeats ‘and special moves of addressing such functions need to be performed in minimum ime by the architec intended fo sig processing. This is possible by designing hantware circuits to carry out above funciona ik, wing # parallel maker fr performing ‘multiplication operation that is executed within one clock pulse. Likewise, different haxdwarg units are designe a cary aut ‘other functions, us decreasing the operating cst and achieving high speeds, Programs execution speed is high im harvardarcitectur, since program memory i isolated fromm data inamory by proving individual bases for both. When there are two data memories, operands can be accessed fron individual memories a tune, by providing two separate buses, Instead of using eitemal menor that need separate external bises for each; thas increasing the com aod decreasing sccessing speed, itis better to use on-chip memories with an instruction cache. They inrease the exeopion speed, in aditon, it ‘is possible to access on-chip memories two times within one clock puse. Therefor, i isnot necessary to use multiple memory devices that need separate bus. 2. Parallelism Paral son ofthe technique emploedtin Digital Signal Processing (DSP) architectures for achieving high peation speeds. Here parallelism refers to performing diffeent functions simultincously. This is achieved by pro¥iding multiple funtticeal units that can work parallel, this increasing the output driving capacity. For instance, o cary cut any address calculations t is beter to provide Separate ALU apart from main ALU so that only datacalulations are donc in inain ALU. On the other band copeations lke add, muliply, shift et., can be perforaic at ate by providing diferent functional was, “The speed of operation of DSP architectures may become high with the provision of many functional blocks. Theicmaxiraum. ‘capacity must be wilized by arranging instructions for performing necessary operations simultaneously. Bu the circuit used for controlling all finctiona units is compl since its hardwited that is poeferred for high speed of operation. The architecture hat ene tb capable feng nut and meat ine om be memo ” Bxample ” na ip acm UAC) pein ate oe ta atc simultaneously in one clock cycle are given below, (0) Fetching the instructions along with the necessary operands fr evaluation. (i) Shing te fetid data to nreasederease its value (scaling). (Gi) Performing mutiplication between operands, © wv) gen ot in inn cot vn cp . (0) cep sete fal eatin te memory - Wi) Sy Ses ila a ee a -Ppetining cnpayed Processing high is another method in (Se) architectures fo achieving high speeds of ee oan hi ea eames es architecture, — Consider an instruction that split int five pats smn th nc pe he, sing This ition equi ig ara uni for is xenut a re DIGITAL SIGNAL PROCESSING [JNTU-KAKINADA] [ntally the frst parti, instruction fetch operation is carried out by te fist unt in the first time slot. Inthe second time {los second pat i. instruction decode operation i cated hye Second nit. Inthe third time slo, operand fetch operations iu a The three: units i m © : ioe oo es See eek eli sd iter 7. DSP processors have stro interupt structure and timers. at ‘They possess on-chip program memory and data memory. « * Look for the SIA GROUP Loco". ae een ep———_Uitoducton To DSP Processors arid Architecture of TMS320C5x) 18. Explain the implementation of convldut with single multipeyladder Ans: i" dasoey sezicatons the inplementation of conolver wt ingle mutes is dane by the say uli Fie ae ataame atin wed to perform both convolution and corelation operations The implemen ofa ‘With single multiplier or adder is shown in figure i x [x [Restor eeu Tee a Regt Fiore: lngtementation sf Convetvor with Single Mutter or Adder Inrealtine, ama lip arecoramonly employe to proces the sigs. The process of wray mitigation finished prior tothe aval ofthe nex sample atthe inpat of ray Ths, thisprocess needs the hardware cleneon op, and accumulation. The sbove problem can be solved by following two different approaches, (0° Asingle hardware unit comprising dedicated MAC unit that integrates multiplier and accumulator Example: Motorola DSPS600X processor: Gi) Separate multiplier and accumulator units, i ‘Example: TI DSP320CSX processor. . In this method, the multiplier output is stored into the product, register whose content is aed to secumulatey the central arithmetic logic unit. . ‘Thus, in both the methods, only single clock cycle is used to complete the multiplier accumulator (MAC) From the figure, the array X, correspcnding to present and past R-1 samples of input is given as, AUK Mga Snell 4 ‘And the array h is given by, h= [hy hyo shy, Then, the output at x sampling instant is obtained as, Y= X.h T,y=Xh 5x, Saino by right shitting “by one aaa aU ET cena rk ni oe @20. Write short critical notes on each of the following concepts, using diagrams where 4ole that while pet ant, orming frst forthe last aces like (fering, FFT), ingle dala vale in one fterntive necmization ted Of DSP operat ns. DSP process jrovite Se pnt he ‘digital signal processor. Sketch ‘Suitable configuration for the: MAC, Explain, briefly and with the ald of a timing Ans: at Cons multiplier cui wi tie pp sup essen gu eon | 3, chUNIT-6 (introduction To DSP Processors and Architecture of TMS340C5X) 6.9 Where, T- Tine units org the nine producers. The inpit samples of correct combination with thee pipe stages is sed to compute thre of i racic sy gd a ultiplexers are given to MAC at any and filter coefficients are applied to thie respective multiplexers. The outputs of these m time unit umber Inthe MAG, a prodct is computed and then added tothe previous accumulated sum. These threpoutputsate added afer Time's. tr 3 time units, anew sample ean be applied to the fier for further computation of next output sample. Henee, N+} ‘the output in this MAC FFD), 22. Explain Memory Access schemes in DSPs. ‘pe, 50, a7) Apt, St, a, n one ation (on Explain the modified bus structutes and memory access schames in digital signal processors. Ans: $ : ode Paper i) The MACD insirction is a rulipicr accumulator operation with data move. For every instruction cycle, MACD instruction requires four memory accesses. They are, = Fetching of MACD instruction from the program memory ny is 2. Fetching any one operands from the program memory. e the . Z i 3. Fetching of second operand from the data memory, ‘The 4. The data memory content with address “dma’ ‘written into the location with address “dma + 1". vard In program memory, coefficients of relatively static impulse response are stored, whereas in data memory, te input data with samples are stored. 7 ee — ‘Von Neumann Architecture Kes a ving, ‘Figure (1) shows the Von Neumann architecture, ¢ A . sia) co Ft on ean ety , a mittee gmc meteteteratnrents overcome the deawback with VnNeunana achietue,Harvardarhitetueiswel( 10 DIGITAL SIGNAL PROCESSING [JNTU-KAKINADA ij Harvard Architecture Figure (2) shows the Harvard architecture. Resuksloperans Privessing ae ‘mit Data meron a Ans ‘Address bas ® Figure 2k Horved Architecture - In Harvard architecture, two separate buses, one address bus for prograt memory and one address bus for data memory - sxe available to parllelly acces their content. Instruction code it applied tothe control unit from program memory whereas eee ee nae ee ee ae shifts etc.) of processing unit re known a dt path Example: Motorola DSP processor 600X and 96002. Modiied Harvard Architecture ‘De pn Dts ese wh emit He ce Te ie Tr ah y pmmecregee i Feet tar Ain i edie VP Nps so coed eff Sasa en sande a inte ares ass data eon ny. tire aar yepUNIT-6 (Introduction To DSP Processors and Architecture of TMS320C5X) G23. Explain why traditional measures such as processor clock speed, MIPS and 7a suitable for comparing the execution performance of DSP processor. Suggest, with justificat alternative method of comparing executioh performance, Ans: eyo, In DSP processors, the metrics like processor clock speed, MIPS [Millions of Instructions Per Second] and. [Millio of Floating-Point Operations Per Second] are not suitable measures for comparing the execution performance, ‘single instruction is of N-Step iterative operation and thus, [more memory and consumes more time. Hence, to such draivbacks an altemative method called benchinarking is employed for comparing the execution performance, DSP} ‘software pregram used to measure the performances nd i is adopted due to the following reasons 1. DSP benchmark is writen in» high level language and hence itis portable 2, Ikpossess wide distribution ean etsly represent the typeof programm like system, commercial or numerical. Q24, Explain the different techniques adopted for Increasing the number of memory accesses/i cycle. : oct Pape ‘The various techniques that are used to increase the number of memory accesses/instruction cyclé are as follows, ‘Maltiple Access Memory For answer refer Unit-VI, Q6. Multiported Memory Maultiporied memory is also used to increase the mumber of aecésses/clock period. The basic diagram of a dual-por ass shown in the figure below. Dan best ‘Address bust Dualpext ‘Address bud mecery Data bx? - Figore: Dust pert Memory In the figure, the addresi bus!, address bus? and ‘data bus!, data bui2 are independent buses. Therefore. by ‘memory two memory accesses/¢ldck period can be achieved. Multiported memories allow simultaneous access 10 Prog ata memory. The cost of dual-port memory is higher than the cost of two single port memories of sare capacity bec _ requirement of lager chip area and increased numberof pins. A larger and more expensive package is required forthe ‘numberof UO pins. The modified Harvard architecture withthe doal-ported menicries are combined by some programe “Example for a single-ported program memory and a dual-ported data memory is Motorola DSP processor $61X- ‘with the motorola processor, one program memory access and two data memory accesses per clock peried can be cha 25. Explain te VLIW architecture with ts block clagram. pate ; : ocel YAW [Very Long instiction Word) achitectr® is wed i programmable DSPs such as TMS20C&X and it as ‘fom the memory. The basic block diagram of VLIW architecture is as shown in the figure below. 7: — DIGITAL SIGNAL PROCESSING UNTU-KAKINADA} Res progranmable DSPs posses many dita pals fich my Shite; maliperacumulaor wis, egthmetic gic ae oe ae aay ta as to be caied oat by evey pce a Specified by VLIW arcttectre. From te al Toe ads nang operand sorng the rena doga egies is shared by the multiple rem ats. The radtrte cos bain VLIW archer sppone Parallel random tocess by multiple functional unis to the mukiportd register file. The multiple func Simultaneously terween a RAM and the register fle src fatten selection for DSP application ad te, suber of frnctn Sce paen the higher cughpu of VLIW antes casa Accumulator adds register ‘to its curent ist: : p=xty ~+Mukiplies the registers x and y: g yo*O+y 9 The result is stored in the produt reser. B=*pt++ > xand y registers are loaded ya‘ues at the memory locations of registers 10 and pt 2 “Dat-staionary Programming Mode : 1a datestatonry node all infomation relates t al processing aspects of single dat item are specifi in oe and the sae instruction imespetve of te when the processing is cared out Ti eel on se of dt ser model stort ae ‘ almal (SHAH SH Data stationary model usually enables ap Sea coe s eical cb nent arena informatioa specified in instructions. Ps np a yd i ei hn | stationary model is easy to implement. — G2. Wt ats pg ag om . i Tein fins pipelining are, ees sp Tiere app gira tng ps ty dg ron } 2.” Cerin renstacs sch s pipeline fates he incadg cade branes riers ins the ftv execution of instvtons rogaine. J cs, DF hat oot nse to eect : set wl hs ac eon nl ee 3. Inpiptining data haar aie when on instucion dean ont oto pvt sexton 4, Ti ete ef tae xcs cel 5 toeducd ought and ote imitation, TEIN LOREEN RR aREROTEROOT ————— ein aa AK ee ee aisit DIGITAL SIGNAt PROCESSING [JNTU-KAKINADA] 30, Explain th Model Paper TID) cil deresing modes In programmable DSPs (or) Describe any four data addressing modes of TMS320¢54xx processor. ‘os7, 82,070) (on) With examples explain the different addressing formats supported by DSP processors for various signal processing applications. ‘ors, 9063, 7) (or) What are the various addressing modes used In the TMS320C5X processor? ‘Ao, Sot, TB) (on). Explain in detail the circular addressing mode and bit-eversed addressing mode, : Aor, S379) Ans: ‘hppa DSPs pint i tye pea ning mn Tye, Short Immediate Addressing ris ‘In short immediate addressing mode, the operand is considered as a short constant whose length relifs on the programmable DSP and the instruction type. The short constant constitutes a portion of a single word instruction. For examiple, an 8-bit constant * a ee ae () Short Direct Addressing. “ Wit edn fa at eo oh li of erlang wd instrcjon. nthe cae of Texas Instruments like TMS320CXX DSPs, the data page pointer stores the higher bits ofthe memory a ee eels Fes hence ae en with a 6-bit address esing short direct addressing. “(ii) Memory Mapped Addressing In memory mapped addressing mode, if CPU registers and the UO registers of programmable DSPs are stored atthe beginning or end of the page in memory space, then they canbe accessed as memory location, ; ‘ ‘The CPU registers and VO registers are stored at page 0 it TMS320CSX and at final page with 64 locations in Motorola “tablet tints ocak Coane ida Go ly pe ie instrument DSPs and | in Motorola DSPs, 2 (iv) Tniirect Addressing es E in accusing Teh horn we aes WSR dT We storing. Any one of che indirect address registers (also called as autiliry registers in Texas instrument processor), is used to store the operand’s address. When an additional ALU is present in the CPU core, the auxiliary or indirect address registers hw pn ich mab Tice oc of given bone asa {in steps of 1) or specified steps of offset register content, The offset register in Texas instruments is known as INDEX register whereas in analog devices of programmable-DSP's, i is known as modifier }address of auxiliary ALU is used to fetch the usable indirect addressing mode operand instead of curent instruction | that i performing decode and execution operation, Hence, in Texas instruments 5X DSPs indirect addressing mode i refered to as indirect addressing mode” ‘ith post-incrementilectementIn contrast té Texas instruments, Motorola DPSS63XX uses updated address to fetch the current ison per Ths cle indies eng mode wt pero. Teas inet TMSSDOCSCK 1rs) ae aoa ae RES Eeaa a ee: UNIT-6 _({ntroduction To DSP Processots:aitt Architecture of TMS320C5X) o ofthe number. Therefore, the leet significant bit ofthe bit reversed muimber changes to most significant bit of the nat ‘number and vice versa! In this addressing mode, the bit reversed mumber increases or decreases the address (ot). Cres is processed is constanily stored in other memory space which can be inseribed onto the output device. Here, the Bit Reversed Addressing. ‘particular decimal nmberis converted into a binary umber by writing the reverse order ofthe natura binary dressing, {In circular addressing, the memory continuolsly stores the input signal for realtime signal processing. The ‘output program is very simple with limited siz. Hence, with linear addressing mode, when the data is copied tothe ‘input signal is processed, the total memory space disappears after some period of tnt. In order to overcome this, Vetification is required to check the limit whichis an overhead. A circular bifer in circular addressing mode retuces tig by using starting and ending memory addresses. When the address pointer gets incremented, itis compared with, address. If it is more than the ending memory address, then the beginning address is alloted to it. De abierates nhl die wie avallable oni programmable digital signal processors their functions? = Ans: . () Sampling clocks generation for the analog to digital converters. eee ATA ‘The on-chip peripherals available on programmable digital signal processors ae, On-chip Timer On-chip timer ig one of the peripherals availsble on programmsble DSPs. This on-chip timer is Programmable DSPs. ‘Most common applications of on-chip timers are, (@) , Periodic interrupts generation tothe programmable DSPs. only transmit and receive data lines are used. In this ease, from either ends, bit clock is transmitted. ‘Figura (tt Receive Operative of Burst Mode SerialPort i clock signal and frame synchronous signal from ou oe Sot tof ae cmd synchronous signal.6.16 TDM Serial Port A special serial port of the program, omumpunisation of progres [, with 8 time sles is as shown i DM) sil por. i, ae nti mig Te = ifs ome ft 104d eyes 8 7M face — tae dress channel is used Yo tans rune M8 UE Ose Ti, “= Lele Beach of the set Te fou . erates Ou ns aie ed fers - Se =e communication wo Be Res Teste wte etic spied & Tides omit ie TDM dt cra ta TDM serial port, the bi-tir So td TADD wed ase 8 TA a 4 ialgawing TOM channel “WY th ote devices Figue oy hows tae aa Se by ay . me. ap he data transmission waveforng , oxae\./ | 17a val mee, Fre Tari te eg TOM Cha 4 Parallel Port : Sle aaa The different approaches to assign the lines for puale por are,” (The data bus itself is used for parallel por 7) ea a esi tra 5.” Bit VO Ports . dna 0 pened pap @ Single bit wide - ‘ i (Wi) Operated individually ns a. Gil) Do not have any handshaking signals. : 3 Ths pe cin sing it amas : & Host Port Essel sl pc tT smn nwt\ UNIT-6 (Introduction To DSP Processors and Architecture of TMS320C5X) 6.17 7.” Comm Ports Comin ports ate parallel ports and are 8-bits wide, The'comm ports are used for interprocess communicationbetween programmable-DSPs in a multiprocessor system. Progranumable-DSPs from analog devices and Texas Instruments have 6 t08 comm ports. Example; ADSP 2106X. 8% Acto-D and D-to-A Converters mn The P-DSPs which ae used for voice applications lke answering michines, mobiles et, have on-chip A40-D and D-to-A Example: Motorola DSPS6IXX, ADSP 21MSP5X. in synthronous mode, the transmissdn of bit lock signa ad frame synchronous signal is fom UO port to the sak port and serial pot wo the UO device. The stating ofthe fist bit ofthe data that is trnsmied in synchronous mode 3° is represeated by bit lock signal and fame synchronous signa ry ns Q32. Explain the features of TMS320C54X DSP processor. ah a Mora Papers ay ‘The following are the features of TMS320C54X DSP processor, 1. The performance of TMS320C5X prorasor i hight “2. TMS320C54X isa low power consumption processor. nro heii node inp es bus 4 po Ag) homie tad ie ni accumulator. ¥ 8. Anion pip nan poem i ‘cycle Multiply/Accumulated (MAC) operation. a 6 iTS pcan ong ein it op chy Cnp Set a St : , (CSSU). i tscpanurtanepnainnir al dean apmtieds natn, one clock cycle.” 8. vit espe wiry iin ad we Ay Rogie het Uns ARAUS. +. 9. nas data buses with weak lh teu (bus holder capability, Which hols its previous vale 10. “TMs320C54% processor provides single aston pat and block-epeat operons fr progam code, aL a 12" i tet ta cn peta tr (nd epi ny i a ee, 3 jot nb rs od pe td gsi s-vig % i « _ TMSSICSA por has Paes Loop PL) elk eer Wiha esta olor or exealck SPECTR GLAN-ORE JOURNAL FoR ENGINEERING STODENTS San oe és 7 \DIGITAL SIGNAL PROCESSING [JNTU-KAKINADA} ‘the major block diagram of the TMS32003X. : i ‘oe. 46, 83, C70) (on) Draw and explain the memory architecture of the TMS320C3X processor. Ans: ‘Apa.t6, Sat2, 7a) ‘igure (1 shows the itera architecture of TMS320C3X proceso The min Blocks of TMS320C3X processor are 1. Cental roessing ni 2 Memory uni 3. Peripherals & DMA controter = Central Processing Unit (CPU) Ihe central processing mit of TMS320C3X processors have a register ised architecture. The units of CPU architecture °C Internal buses ‘CD Tmeper and Hating point ALU (i) Bart siter (¥) Autiliary register arithmetic units (vi) CPU register file:UNIT-6. (Introduction To DSP Processors and Architecture of TMS320C5X) Integer and Posting Point Multiplier “The 2Adit integer and 32-i: floating point values are mltiplied by the integer and floating point maltipie se ale cyte Te eating pont operations ar alowed by TMS*2003X implementation of foating pont speeds upto 3 nosecfinstrction cycle. Parallel instructions are used for getting speed more than 33, fi ‘ele. Paalel mukiply and arithmetic logic nit operations are performed by parallel instructions with in a Internal Bases ‘The infernal buses of CPU are CPU, CPU2, REQ! and REG2. In CPU intemal buses the data is carried by to the CPU. ALU, register fle nd two datn memary operands to the multiplier are carried by the CPU} and for every inachine cycle. REGI and REG? are two buses internal tothe CPU. (iD Integer and Floating Polat ALU ‘Arithmetic and logical operations are performed by ALU. Single cycle integer and floating conversions are ‘by ALU. The integer and floating point ALU always maintain results at 40-bit floiting point o 32-bit integer (io) Barret Shifter The operands are shifted upto 32 bits tight or 32 bits left in a single cycle by barrel shifter. (@) _Ausiliary Register Arithmetic Units (ARAU) F : ‘The auxiliary repstr arithmetic units of TMS320C3X processors are ARAUO and ARAUI. Two addresses by ARAUO and ARAUI in a single cycle. Generally auxiliary register arithmetic units operated parallel multiplier, Indirect addressing mode is used by ARAUs. Circular and bit-reversed addressing modes also sul register arithmetic unit, (wD CPU Register File a, ‘The CPU register file of TMS320C3X family processors have 28 registers in a multiport register. The CPU register files are, _ fae @ bebe bbe de eu gue ‘C30 and C31 family and 256 * 32 cessor. The RAM bi 32 for C30 and C31 processors and 256 x 32 for C32 processor. The ~ 4K X32 fot C30 processor and boot loader in C31 tel C2 aly proses Sagh eye dal soe by RAM and ROM blocks. The muber of off-chip accesses are reduced by the 64 32 program cache.TMS520C31 procesior TMS520C32 processor destination mgisers and transfer counuer. , (Own address and data buses of DMA controller minimizes the DMA controle is performed independently The piocty of DMA “eater or CPU is provide, if they access the same external memory location o sae oop.‘ADA ess bus zes the fDMA UNIT-6 (Introduction To DSP Processors and Architecture of TMS320C5X) 6.21 Q34, Discuss in detail the Basic Architectural features of programmable DSP devices. ‘ies, Sot aT(e) (on) Explain with the help of block diagram the architecture of TMS320C5X processor. (or) Describe the multiplier/adder ynit of TMS320c54xx processor with a neat block diagram, ‘Apes, satan) Khiladi atid (on Explain the function of Barrel shifter in the digital signal processor: ‘Ape, at a7)= DIGITAL SIGNAL PROCESSING (JNTU-KAKINADA] uNn 1 Bas Sractare Tnorder to improve the processor's expebility tis necessary to allt a mumber of buses o different sections of memory oF Peripheral devices, so that they canbe accessed simultaneously. There ae 8 such buses of 16-bit each, present in the architecture nen of TMI20CS4XX processor as shown in irre. These buses ae paired up forming four pairs containing address bus and data tus in each pi ‘The four ir are (PAB, PB), (CAB, CB), (DAB, DB) aid (EAB, EB). The pi (PAB, PB) is kiown as program bus pir thi is used to transfer instruction codes from the program memo. ‘Te oer thre pairs (CAB, CB), (DAB, DB) and (EAB, EB) are referred tos data bus pairs whieh lnk different blots present in the CPU. Also, data present in the dia memory can be read using (CAB, CB) an (DAB, DB) data bus pairs whereas data an be transfered to data inerory sing (EAR, EB) dath bus pai. There are two winilary register arithmetic units ARAL, and ARAL inside the dtu adress generition logic (DAGEN) wit with which a maximum of two data-memory addresses can be ‘eneratedin one eyele. Thus, its possi to acess two operands time 2» Central Processing Unit (CPU) ‘The central processing imit present in TMS320CS4XX is standard CPU cipoyed inal he processors. There are various uns jresent in a CPU. They ae, * Arithmetic Logic Unit (ALU) of 40-bit {i Two'Accumaiators (A & B) of 40-bit each Gi) Bare Shifter )_Maliptier (17-bit 17-bit) (0) Adder (402i (vi) Compare, Select and Store Unit (CSSU) ‘il Exponent Bncoder (EXP) ‘i Data Address Generation Unit (AGEN) and (G2) Program Address Generation Unit (PAGEN), of Al 8 ain 2 sass 23NADA) emory or hitecture and data bits each, UNIT-6 (Introduction To DSP Processors and Architecture of TMS32005X) (GH _ Accumalators (Awnd B) The renut of ALU operation or is stored in these accumulators thus, forming he second inpt oF ALU unit. There are three sections present in individual accumulator. (@) Bits from 39 to 32 represent guard bits ()_ Bits fom 310 16 represent higher order bits (©) Bits from 15 to 0 represent lower order bits. It is possible to access each part of accumilator separately (i), Barrel Shier ‘The magnitude of an operand can be scaled up oF scaled down while peforming read or write operations, using abarel shifter. The barrel siftet provided in TMS320CS4XX, processors is capable of sifting the input data to lef (about 0 to 31-bits) and right (sbout 0 to 16-bits). The number of bit postions to be shifted and other requirements canbe specified inthe instruction atthe field of shift count, inthe status register (STI) atthe field of shift count o inthe temporary register (1). } The barrel shifter fanctional diagram is as shown in figure (3). eam c= aa (ie) Maltipier/Adder Unit “This unit i capoble of carrying out 17» 17 ‘complement multiplication operation along with (Gobi within one nstrction cycle. A multiple ‘contains, a 17 * 17 bit multiplier, 40-bit adde for computing integers and fractions and a temporar (7 of 16, The muliplie/adter wit Fonctional as shown in figure (4). Figure (ft: Mattiphier/ Adder Unit Fanctional (+) Compare, Select amd Store Unit (CSSU) igor FnetonlDigrem f Barrel hier n TS32OCS48X ‘ Processor : Input ta cn be noise within oe yee in an ‘tecumulator using a barrel shifter and exponent encodet, The ‘output contaitis zeros filled in their LSB positions and MSB positions containing either zeros or sign extended as per the ‘status of sign extension inode bit present in the status register (ST) Apert fm te abe mano ting. texto, ‘extended arithinetic, overflow prevention operations can be + erred out in the processor.ree! CESSING LiNTY, DIGITAL sign at PRO Sed separately RAN OM repress in al Pe ie, SARAM, The AKINADA| utr. ite Process Wier RAM is ofda Bastion ofcnchip Ran the pote isin mas ee ang ee adeno lokeap bles en ie, COD HAY, day jan ROM to carry ripich are capable af lcating the nemery dees of at ofl the CPU regen al peg ae ami ' erp Flag Reiter rr = i. oe segssers (STO, ST1) = ee or regis (AL,AH,AG, BL i, 30) ¥ register (TREG) = 4 ee register (TRN) se * (ARO-AR7) cae ee & Pe ween : a Block repeat counter (BRC) e Block repeat start address (RSA) Block repeat cad adress (REA) ‘Figure (Sk Processor Mada Status Registr Format Sls Arise suse roc : Ans: ‘Aor, St ization as shown in figure below. itcture for buses end memory organization a ‘ ‘ harward_ DSP processors employUNIT-6 _(nieuction To DSP Processors and Architecture of TMS3206: 6.28 Tn gure gparte memory Bock ae asigned oe for slring he aeses ad Te oer fr data soaps. Also, each locks alloted with separate buses. Tho reason behind spliting he memory nto program and data meron isha, it the speed of exeeution of program, since tot the memories can be accessed simultaneously through thr respective There are two data meiory blocks presen inthe architecture, For instuuctions that require ane operand (ie inp dita) ‘for their execution, it is fetched from one of the two data memories. In case if one instruction requires two operartls\for its execution, bo the operands can be fetched simullaoeosly ram th two da memories respectively er example iy gut "ultiplication operation, two operands are require, ane for sup andthe ote fr muhipiand. So, along wiles ‘memory two data memory blocks ate required to carry out execution of such operations in single cycle. Apart ton tig om ‘and data memeries another kind of memory must be employed refered to as ack. In ode o increase the speed feet Subroutines, interrupt cll and ets, tack nemo i sed tha can be accessed to directly by a Program Couey Q36, What are the different buses of TMS320C5X processor and their functions? aa Ans: = 7MS320¢3X proceso famiy rice with CMOS iC ecology Lisa fied point 6 digital apy and operates at a frequency of 40 Miz It possesses the advanced Harvard architecture with separate program, The TMS320C5X architecture uses the following buss, LPB’ + Program bus 2 PAB - Program addres bus 3,. DB ~ Dataread bus 4. DAB - Data ead address bus. In TMS320C5X architecture, the functions performed by separate program and data buses ae, ae 41. Processing power maximization 4 : = 2. Providing high degree of parallelism. ~ All the buses enable the processor to function at high speed i, different buses enable different actions to take place "simultaneously and bene increase te operating speed ofthe processor. eS 1, PB-Program Bus i ‘PB bus involves carrying of information like, the instruction code and immefiate operands from program memory 0 CPU. 2. PAB-Program Address Bus i : E “The main function of PAB bus isto allocate adresses to program memory space forthe operations like read and wrt. ‘The instructions to be assigned in @ particular address are passod to the respective memory location through this bus. ene, the instructions are stored accordingly atthe memory locations indicated by the BAB. _ 3. DB-Data Read Bus rs a = The mai futon of DB busi to intxconnes the CPU to data rnemory pace. Therefore the various elements ike ALU, PLU, dire are comet othe dia memory pce Ths he tained betwen the registers of CPU to memory space and vice versa i, the various elements of CPU performs the operation (accocding tthe commands in the program) on the supplied data. The result ofthe operation is then stored back onthe data memory space using "data read bus”. 4. DAB-Data Read Address Bus “DAB bus cries the addresses to access th particular data memory space, The operations tobe performed on the data are not possible in the absence ofthis bus as it prov of epee dan (8 defined in the Q37. Discuss In detail the Pipeline Operation of TMSS2DCE4XX Processors. ‘Ans: 1s ; . : ape et, [A six-stage-decp instruction pipeline is txhibifed by the CPU's of TMS320CS4XX devices, in which each level has no dependency on the other. This pipe lining feature permits overlapping execution of instructions. Depending on the stage of “processing, one of six different instructions can be function for any given cycle, The six different stages of pipeline operation ~ ae discussed below, ; ~ "Inthis +e the address ofthe next instruction tobe fetched is stored onto the Progrum Address Bus (PAB). 2, Fetch s y 4 % : ‘ ; During pogram felch, an instruction word fom the Program Bus (PB) is fetshed und loaded nt the Instruction Regier (IR), which is referred as instruction fetched sequence, : ‘ _ isa ao a Fon rene eR —————sx emoue ds6.26 \| 3. Decode DIGITAL SIGNAL PROCESSING [JNTU-KAKINADA] | Inthis stage the tstrction > tion Register (IR) is stored with the Program Bus (PB) content. Now, the contents of Instruction Register (IR) re decoded wf, } ‘€) Memory access operation type i} The necessary control signals for data-addess generation unit and CPU. | Sea socecen ‘ap "Daring program access, the read operand’s address ie plact on the Data Address Bus (DAB), However, the another gh: mur Riders bus CAB is stored with arelevant adress on requirement of second operand. In this stage, the updation of wuxiiary So, ba RPT nines adrsing mode wd the Ste Pinter (Si do, : {ating program rend, the valle dat operand re ead om the data buses (.., DB and CB) In this ape, the end Fat phase read process begins the two-phase write process. The available data address of the write operation is stored the data writ address bus Le, EAB. Yip, the operand write sequence is ended after writing data with the help of data write bus i.e, EB. During program te, the instructions also et executed. ‘six different stages ofthe pipeline are as shown in figure below. Prefer} Fetch | Decate| Acces| Read | Rxecutelwrie — Tee Figar: Pipeline Operation of TMS320CS4XX Processors ‘038. Draw the block diagram of TMS320C50 digital signal processor and explain the functionality of Central Arithmetic Logie Unit (CALU) and Parallel Logic Unit (PLU). * Ans: . The block diagram cf T45320C50 digital signal proceso is shown in fig. q N \ \ N N N : N N N N N N N N N N N N N SS ‘Dats DARAM RGIK19) BI (SI2* 16) BAH RARALE i N N N= N° N. SN SSS HoH ISSSDAI ction lary ag UNIT-6 (Introduction To DSP Processors and Architecture of TMS320C5X) The Central Processing Unit (CPU) contains, 1. Central Ariehmeti Logie Unit (CAL) it by the CPU is that, its capable of computing 2's complement arithmetic The ‘There ae some blocks present in this unit. They ae, (Parallel multiplier (16 * 16) (i) Accumiltor (ACC) (32 bit) (ii), ACC Buffer (ACCB) (2-bi0) (iv) Product Register (PREG) (#) Shifters (vo Arithmetic Logic Unit (ALU) (32-bit) Parallel multiplier supports all 32-bit signed/insigned multiplication operations in one machine cycle. Ln this a signed multiplication operation is performed by the mutply instruction, but not MPYU (unsigned mitipticaicn) ‘Thetwo input operands to the multiplier are derived from 16-bit temporary register © (TRGO) and data asp ‘The output ic, the multiplication result is stored in the product register. ‘The 32-bit ALU along with 16-bit accumulator executes arithmetic and logic operations within one machine sccumulitr gives on ofthe inputs tothe ALU whereas product register, Accurnulator Buffer (ACB) or scaling shit ‘gives the second input. Also, the accumulator stores the output of ALU. ‘The input tothe scaling shifter is derived from the 16-bit data bus. Is output is given as input to the 32-bit ALU. in purpose of using this sits tsd to pero ef shift peatioh on the 16 biting with hes cout specified bythe nese ore i (TREG!) or the instruction word. 2 Parallel Lagie Unit (PLU) ‘The other logic unit of CPU 4s the parallel logic unit which performs logical operations whose results do sccumulator contents. A suliplier bit preseat in a statis/contol register canbe set reset, ested or toggled by this “Explain the purpose of six registers used In the TMS3Z0G2X processor. Explain the memory interface block diagram for the TMS320C5x processor. Ans: ‘The purpose of six registers used in the TMS320C2X processor are, 1. Auiliary Register ‘ ‘The TMS 320C5X has eight auxiliary registers (ARO-AR7) each of length 16-bit. These registers Ch Siete Loge Un (CALL i bl te oad and modified by either‘ “Pall Lag: Unt ( Zari lime Ui (ANAT) Tha eps tr df es srg fia memory rh ego 2 abla Regie Auxiliary register arithmetic unit during indirect addressing uses a 16-bit index register (INDX) to ‘Stofed in the auxiliary registers in steps. Thie INDX can be added or subtracted from the current auxiliary reversal addressing, INDX register can design te address block dimensions. 3. Auriliary Register Compare Register (ARCR) ‘The ARCR is a 16-bit register which is wed to compare address boundary. I limits blocks of dats and ‘compérisons between the current‘AR. and ARC in conjunction with th instruction CMPR. placed inthe TC bit of ST1, ae5 jad nepeny ond fe reer geh aa eee Perey, ey olan PFE Oo eda mea) those foe CPU, thera data memory ys = iy "te ata memory space to alow throws ith 100 word instruction inthe TMS320C5ix processor? > ee, ts, aro) (or) 'S320C541x processor, ores.) er i + Wpimicroptice Sos, nterrupi are the signal hat beak the, i r. {mfat execution of instructions sod ane the conta o program called Interrupt Service Routine (ISR) Thus, afer te P ee ess The sn ld Different Classes of Interrupts The various itu types supponied by TMS320C5X proceso are INTIG-INT. Thee 16 inp ae kzownas er saskable mterrupis. INT4-INT} are the external ‘iterrupt lines. The internal intecupts are generated by the times (TINT) by the ‘emai por (RINT, XPNT, TRIN, TXNT, BRNT and BXNT) by hos por interface (HINT), trough software (NTR, NMI and TRAP), The reset (RS), NMI ace the two extemal non-maskable intemupts, In these 16 interupts, highest pitty goes to BS fiserapt and the lowest piocity goes to INT6. The interrupt vecor locations, pistes and fncion of each nterupt i shown inable. E a2 g55e 245UNIT-6 (niraducion To DSP Proosssors and Architecture of TMS320C5X) 6.29 5 41.” Compare TMS3Z0C fixed and floating polnt processors. ay Ans: The comparicin between fied and floating pint TMS320C processor is given below. Fixed Point Processor Floating Polat Processor ; Tin fixed point processor, binary pots wed T] nonin point proceso, «number is wedi acigie =|” ‘to illustrate binary fraction. ‘the product of two signed numbers, ic., Mantissayant exponent. as 2] itis 16-bit xed point DSP processor. 2 | itis 0 32-i oating point DSP processoc yyy? 3. Itrequres signal sealing in order o avoid 3. | In this processor, under or overflow erors dono a overflow errors os iedtia ia. 4) Ried pint prover offs resticedaccuney | 4. | Foting pit processor fe igh coun ‘ sd smal dynamic range, increasing large dynamic range. e 5] Itpecforms high-speod operations 5. | ttperfoms time consuming operations 6 Fixed point processors are relatively economical’ | 6, Floating point processor are more expensp di sane ‘and consumes less power ‘complex. ee 7] Application: Small computers. 7.| Applications: Video conferencing, network pic a ‘switching, cellular base station, radars and digials’" hi 3 — (042. What are the advantages of CISC? Ans: ‘CISC (Complex Instruction Set Computer) isa philosophy for designing chips that are easy to program and which make as user ‘efficient use of memory. Each instruction in a CISC instruction set might perform a series of operations inside the processor. byte ‘This reduces the nurmber of instructions required to implement a given program and allows the programmer to lear a small but aos flexible set 6 instructions. . sens Advantages of CISC ; ‘The instruction set of CISC processor has the instructions such as MACD, FIRS, a 2 The instruction st of CISC processors very rich and it supports “oe, “while” end “if soagiton true then do”. 3. The assembly language program of a CISC processor is very short and easy o follow. 4. Forlow cost applications, CISC processors are more preferred than RISC. 5. 6 ‘Micro-programming i easier to implement and muck less expensive than hard-wiring a control wnt. The ease of micro-coding new instructions allows CISC machines to be upwardly conipatible (a new computer would * “contain a superset of the instructions ofthe earlier computes). 7. As each instruction became more capable, fewer instructions could be ised to implement a given task: This made more flicicat use of the relatively slow main memory. Es © & Because micro-program instruction sets can be written to match the constructs of high-level languages, the compiler uced ee ae ; ‘The fllowing ae the advaniges of RISC processor, : ie I : 41, In RISC processor, the contol unit uses around 20% ofthe chip area. Hence, remaining area is used for incorporating 2: The delayed branch and cal instructions improve the speed ofthe RISC: processor. 3. The execution time required fr al the instructions of RISC processors same, a oe 4. The RISC processor have smaller and simpler control nit. Hence, its speed increases, atid ‘ = Since a simplified instruction st allows fora pipelined, superscalar design, RISC processors often achieve two to four {times th pcfamance of CISC pocesors by wing comparable semiconductor technology with same clock rates. ‘6. Because the instruction st ofa RISC processor is imple, ituss lesser chip pace than & CISC processor. Extra functional "unis sch ¢ memory management unto fatng poat ritmetic ui, can be placed op the same chip, 1 the conealng CSC ag ne ey tke rage of eal depots SPECTROM ALLAN-ONE JOURNAL, FOR ENGINEERING STUDENTS eae ak Kk A loi =DIGITAL SIGNAL PROCESSING [JNTU-KAKINADA} ‘Q44, White short notes on the following, i) “Program controller Fim controller consists of logic cirenity which is used to decode the operational instructions, handle the pipetine the CPU operations status tis aowsed to decode the condition operations. The program cntellerencompasies he 16. aes of infernal or extemal prgram memory to fetch the inetroctions ‘Satara Control Regters -Gireular buffer contol register Process mode satus register Sta repsier STO ad ‘Status register ST. ‘ (1 Hisrdware Stack » The stack if 16-bit wide and 8 levee, which icc rough th ston PUSH nd POP. This is used to save snd restore the PC contents at the time of interrupts'and Subeoutines: (jy) Program Memory Addresses Generation isc tifa epi | oe er nf. rograt: adress bus is only used to access the program memory. (*) Instrection Registers a ‘i se i et te pet nt ain (©) On-chip Memory: + pene Software PLL. . — in this. PLL programizabe and the desired CPU clock factor ‘eof es nih faateiaahose ruttiplication stleton unde stare ol The Insta md of htingTUSINCS OK procs, cock sci ety cnn ate dev Deseret are re de TSS yyw fo device to device.