COMPUTER ORGANIZATION & ARCHITECUTRE

MODULE 1
Basic Structure of Computers: Computer Types, Functional Units, Basic Operational Concepts, Bus
Structures, Software, Performance -Processor Clock, Basic Performance
Equation(upto1.6.2ofChap1ofText).

Machine Instructions and Programs: Numbers, Arithmetic Operations and Characters, IEEE standard
for Floating point Numbers, Memory Location and Addresses, Memory Operations, Instructions and
Instruction Sequencing (up to 2.4.6 of Chap 2 and 6.7.1 of Chap 6 of Text).
BASIC CONCEPTS
• Computer Architecture (CA) is concerned with the structure and behaviour of the computer.
• CA includes the information formats, the instruction set and techniques for addressing memory.
• In general covers, CA covers 3 aspects of computer-design namely: 1) Computer Hardware, 2)
Instruction set Architecture and 3) Computer Organization.
1. Computer Hardware
 It consists of electronic circuits, displays, magnetic and optical storage media and
communication facilities.
2. Instruction Set Architecture
 It is programmer visible machine interface such as instruction set, registers, memory
organization and exception handling.
 Two main approaches are 1) CISC and 2) RISC.
(CISCComplex Instruction Set Computer, RISCReduced Instruction Set Computer)
3. Computer Organization
 It includes the high level aspects of a design, such as
→ memory-system
→ bus-structure &
→ design of the internal CPU.
 It refers to the operational units and their interconnections that realize the architectural
specifications.
 It describes the function of and design of the various units of digital computer that store and
process information.

FUNCTIONAL UNITS
• A computer consists of 5 functionally independent main parts:
1) Input
2) Memory
3) ALU
4) Output &
5) Control Units

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Input Unit
Computers accept coded information through input units. The most common input device is the
keyboard. Whenever a key is pressed, the corresponding letter or digit is automatically translated into its
corresponding binary code and transmitted to the processor.
Many other kinds of input devices for human-computer interaction are available, including the touchpad,
mouse, joystick, and trackball. These are often used as graphic input devices in conjunction with
displays.
Microphones can be used to capture audio input which is then sampled and converted into digital codes
for storage and processing.
Similarly, cameras can be used to capture video input.
Digital communication facilities, such as the Internet, can also provide input to a computer from other
computers and database servers.

Memory Unit
The function of the memory unit is to store programs and data. There are two classes of storage, called
primary and secondary.
Primary Memory
Primary memory, also called main memory, is a fast memory that operates at electronic speeds.
Programs must be stored in this memory while they are being executed. The memory consists of a large
number of semiconductor storage cells, each capable of storing one bit of information. These cells are
rarely read or written individually.
Instead, they are handled in groups of fixed size called words. The memory is organized so that one
word can be stored or retrieved in one basic operation. The number of bits in each word is referred to as
the word length of the computer, typically 16, 32, or 64 bits.
To provide easy access to any word in the memory, a distinct address is associated with each word
location. Addresses are consecutive numbers, starting from 0, that identify successive locations.
Instructions and data can be written into or read from the memory under the control of the processor. A
memory in which any location can be accessed in a short and fixed amount of time after specifying its
address is called a random-access memory (RAM). The time required to access one word is called the
memory access time. This time is independent of the location of the word being accessed. It typically
ranges from a few nanoseconds (ns) to about 100 ns for current RAM units

Cache Memory
As an adjunct to the main memory, a smaller, faster RAM unit, called a cache, is used to hold sections of
a program that are currently being executed, along with any associated data. The cache is tightly coupled
with the processor and is usually contained on the same integrated-circuit chip. The purpose of the cache
is to facilitate high instruction execution rates.
At the start of program execution, the cache is empty. As execution proceeds, instructions are fetched
into the processor chip, and a copy of each is placed in the cache. When the execution of an instruction
requires data, located in the main memory, the data are fetched and copies are also placed in the cache.
If these instructions are available in the cache, they can be fetched quickly during the period of repeated
use.

Secondary Storage
Although primary memory is essential, it tends to be expensive and does not retain information when
power is turned off. Thus additional, less expensive, permanent secondary storage is used when large
amounts of data and many programs have to be stored, particularly for information that is accessed
infrequently. Access times for secondary storage are longer than for primary memory. The devices
available are including magnetic disks, optical disks (DVD and CD), and flash memory devices.

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Arithmetic and Logic Unit

Most computer operations are executed in the arithmetic and logic unit (ALU) of the processor. Any
arithmetic or logic operation, such as addition, subtraction, multiplication division, or comparison of
numbers, is initiated by bringing the required operands into the processor, where the operation is
performed by the ALU.
When operands are brought into the processor, they are stored in high-speed storage elements called
registers. Each register can store one word of data. Access times to registers are even shorter than access
times to the cache unit on the processor chip.

Output Unit
Output unit function is to send processed results to the outside world. A familiar example of such a
device is a printer. Most printers employ either photocopying techniques, as in laser printers, or ink jet
streams. Such printers may generate output at speeds of 20 or more pages per minute. However, printers
are mechanical devices, and as such are quite slow compared to the electronic speed of a processor.
Some units, such as graphic displays, provide both an output function, showing text and graphics, and an
input function, through touch screen capability. The dual role of such units is the reason for using the
single name input/output (I/O) unit in many cases.

Control Unit
The memory, arithmetic and logic, and I/O units store and process information and perform input and
output operations. The operation of these units must be coordinated in some way. This is the
responsibility of the control unit. The control unit is effectively the nerve center that sends control
signals to other units and senses their states.
I/O transfers, consisting of input and output operations, are controlled by program instructions that
identify the devices involved and the information to be transferred.
Control circuits are responsible for generating the timing signals that govern the transfers. They
determine when a given action is to take place. Data transfers between the processor and the memory are
also managed by the control unit through timing signals. A large set of control lines (wires) carries the
signals used for timing and synchronization of events in all units.

The operation of a computer can be summarized as follows:

• The computer accepts information in the form of programs and data through an input unit and stores it
in the memory.
• Information stored in the memory is fetched under program control into an arithmetic and logic unit,
where it is processed.
• Processed information leaves the computer through an output unit.
• All activities in the computer are directed by the control unit.

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BASIC OPERATIONAL CONCEPTS

• An Instruction consists of 2 parts, 1) Operation code (Opcode) and 2) Operands.
OPCODE OPERANDS
• The data/operands are stored in memory.
• The individual instruction are brought from the memory to the processor.
• Then, the processor performs the specified operation.
• Let us see a typical instruction
ADD LOCA, R0
• This instruction is an addition operation. The following are the steps to execute the instruction:
Step 1: Fetch the instruction from main-memory into the processor.
Step 2: Fetch the operand at location LOCA from main-memory into the processor.
Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the contents of register R0.
Step 4: Store the result (sum) in R0.
• The same instruction can be realized using 2 instructions as:
Load LOCA, R1
Add R1, R0
• The following are the steps to execute the instruction:
Step 1: Fetch the instruction from main-memory into the processor.
Step 2: Fetch the operand at location LOCA from main-memory into the register R1.
Step 3: Add the content of Register R1 and the contents of register R0.
Step 4: Store the result (sum) in R0.

MAIN PARTS OF PROCESSOR

• The processor contains ALU, control-circuitry and many registers.
• The processor contains „n‟ general-purpose registers R0 through Rn-1.
• The IR holds the instruction that is currently being executed.
• The control-unit generates the timing-signals that determine when a given action is to take place.
• The PC contains the memory-address of the next-instruction to be fetched & executed.
• During the execution of an instruction, the contents of PC are updated to point to next instruction.
• The MAR holds the address of the memory-location to be accessed.
• The MDR contains the data to be written into or read out of the addressed location.
• MAR and MDR facilitates the communication with memory.
(IR  Instruction-Register, PC  Program Counter)
(MAR  Memory Address Register, MDR Memory Data Register)

STEPS TO EXECUTE AN INSTRUCTION

1) The address of first instruction (to be executed) gets loaded into PC.
2) The contents of PC (i.e. address) are transferred to the MAR & control-unit issues Read signal to
memory.
3) After certain amount of elapsed time, the first instruction is read out of memory and placed into
MDR.
4) Next, the contents of MDR are transferred to IR. At this point, the instruction can be decoded &
executed.
5) To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a result,
the operand is transferred from memory into MDR, and then it is transferred from MDR to ALU.
6) Likewise required number of operands is fetched into processor.
7) Finally, ALU performs the desired operation.
8) If the result of this operation is to be stored in the memory, then the result is sent to the MDR.
9) The address of the location where the result is to be stored is sent to the MAR and a Write cycle is
initiated.
10) At some point during execution, contents of PC are incremented to point to next instruction in the
program.

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BUS STRUCTURE
• A bus is a group of lines that serves as a connecting path for several devices.
• A bus may be lines or wires.
• The lines carry data or address or control signal.
• There are 2 types of Bus structures: 1) Single Bus Structure and 2) Multiple Bus Structure.
1) Single Bus Structure
 Because the bus can be used for only one transfer at a time, only 2 units can actively use the
bus at any given time.
 Bus control lines are used to arbitrate multiple requests for use of the bus.
 Advantages:
1) Low cost &
2) Flexibility for attaching peripheral devices.
2) Multiple Bus Structure
 Systems that contain multiple buses achieve more concurrency in operations.
 Two or more transfers can be carried out at the same time.
 Advantage: Better performance.
 Disadvantage: Increased cost.

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• The devices connected to a bus vary widely in their speed of operation.
• To synchronize their operational-speed, buffer-registers can be used.
• Buffer Registers
→ are included with the devices to hold the information during transfers.
→ prevent a high-speed processor from being locked to a slow I/O device during data
transfers.

Note:
Explanation similar to functional unit

Software

 System software is a collection of programs that are executed as needed to perform functions:
 Receiving and interpreting user commands
 Entering and editing application programs and storing them as files in secondary storage devices
 Managing the storage and retrieval of files in secondary storage devices
 Running standard application programs such as word processors, spreadsheets, or games, with data supplied
by the user
 Controlling I/O units to receive input information and produce output results
 Translating programs from source form prepared by the user into object form consisting of machine
instructions
 Linking and running user-written application programs with existing standard library routines, such as
numerical computation packages.
 System software is responsible for the coordination of all activities in a computing system.
 Application programs are usually written in a high-level programming language, such as C, C++, Java, or
Fortran
 Independent of the particular computer used to execute the program.
 A programmer using a high-level language need not know the details of machine program instructions.
 Compiler translates the high-level language program into a suitable machine language program.
 Text editor - used for entering and editing application programs.
 File - a sequence of alphanumeric characters or binary data that is stored in memory or in secondary storage.
 Operating system - a large program, or actually a collection of routines, that is used to control the sharing of
and interaction among various computer units as they execute application programs.
 Consider a system with one processor, one disk, and one printer.
 Assume that the application program has been compiled from a high-level language form into a machine language
form and stored on the disk.

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PERFORMANCE
• The most important measure of performance of a computer is how quickly it can execute programs.
• The speed of a computer is affected by the design of
1) Instruction-set.
2) Hardware & the technology in which the hardware is implemented.
3) Software including the operating system.
• Because programs are usually written in a HLL, performance is also affected by the compiler that
translates programs into machine language. (HLL High Level Language).
• For best performance, it is necessary to design the compiler, machine instruction set and hardware ina co-
ordinate way.

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examine the flow of program instructions and data between the memory & the processor.
• At the start of execution, all program instructions are stored in the main-memory.
• As execution proceeds, instructions are fetched into the processor, and a copy is placed in the cache.
• Later, if the same instruction is needed a second time, it is read directly from the cache.
• A program will be executed faster
if movement of instruction/data between the main-memory and the processor is minimized
which is achieved by using the cache.

PROCESSOR CLOCK
• Processor circuits are controlled by a timing signal called a Clock.
• The clock defines regular time intervals called Clock Cycles.
• To execute a machine instruction, the processor divides the action to be performed into a sequence
of basic steps such that each step can be completed in one clock cycle.
• Let P = Length of one clock cycle
R = Clock rate.
• Relation between P and R is given by

• R is measured in cycles per second.

• Cycles per second is also called Hertz (Hz)

BASIC PERFORMANCE EQUATION

• Let T = Processor time required to executed a program.
N = Actual number of instruction executions.
S = Average number of basic steps needed to execute one machine instruction.
R = Clock rate in cycles per second.
• The program execution time is given by

------(1)
• Equ1 is referred to as the basic performance equation.
• To achieve high performance, the computer designer must reduce the value of T, which means
reducing N and S, and increasing R.
 The value of N is reduced if source program is compiled into fewer machine instructions.
 The value of S is reduced if instructions have a smaller number of basic steps to perform.
 The value of R can be increased by using a higher frequency clock.
• Care has to be taken while modifying values since changes in one parameter may affect the other.

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CLOCK RATE
• There are 2 possibilities for increasing the clock rate R:
1) Improving the IC technology makes logic-circuits faster.
This reduces the time needed to compute a basic step. (IC  integrated circuits).
This allows the clock period P to be reduced and the clock rate R to be increased.
2) Reducing the amount of processing done in one basic step also reduces the clock period P.
• In presence of a cache, the percentage of accesses to the main-memory is small.
Hence, much of performance-gain expected from the use of faster technology can be realized.
The value of T will be reduced by same factor as R is increased „.‟ S & N are not affected.

INSTRUCTION SET: CISC AND RISC

RISC CISC
Simple instructions taking one cycle. Complex instructions taking multiple cycle.
Instructions are executed by hardwired control Instructions are executed by microprogrammed
unit. control unit.
Few instructions. Many instructions.
Fixed format instructions. Variable format instructions.
Few addressing modes, and most instructions Many addressing modes.
have register to register addressing mode.
Multiple register set. Single register set.
Highly pipelined. No pipelined or less pipelined.

Problem 1:
List the steps needed to execute the machine instruction:
Load R2, LOC
in terms of transfers between the components of processor and some simple control commands.
Assume that the address of the memory-location containing this instruction is initially in register PC.
Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory.
And, then wait until it has transferred the requested word into register MDR.
3. Transfer the instruction from MDR into IR and decode it.
4. Transfer the address LOCA from IR to MAR.
5. Issue a Read command and wait until MDR is loaded.
6. Transfer contents of MDR to the ALU.
7. Transfer contents of R0 to the ALU.
8. Perform addition of the two operands in the ALU and transfer result into R0.
9. Transfer contents of PC to ALU.
10. Add 1 to operand in ALU and transfer incremented address to PC.

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Problem 2:
List the steps needed to execute the machine instruction:
Add R4, R2, R3
in terms of transfers between the components of processor and some simple control commands.
Assume that the address of the memory-location containing this instruction is initially in register PC.
Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory.
And, then wait until it has transferred the requested word into register MDR.
3. Transfer the instruction from MDR into IR and decode it.
4. Transfer contents of R1 and R2 to the ALU.
5. Perform addition of two operands in the ALU and transfer answer into R3.
6. Transfer contents of PC to ALU.
7. Add 1 to operand in ALU and transfer incremented address to PC.

Problem 3:
(a) Give a short sequence of machine instructions for the task “Add the contents of memory-location A
to those of location B, and place the answer in location C”. Instructions:
Load Ri, LOC
and
Store Ri, LOC
are the only instructions available to transfer data between memory and the general purpose registers.
Add instructions are described in Section 1.3. Do not change contents of either location A or B.
(b) Suppose that Move and Add instructions are available with the formats:
Move Location1, Location2
and
Add Location1, Location2
These instructions move or add a copy of the operand at the second location to the first location,
overwriting the original operand at the first location. Either or both of the operands can be in the
memory or the general-purpose registers. Is it possible to use fewer instructions of these types to
accomplish the task in part (a)? If yes, give the sequence.
Solution:
(a)
Load A, R0
Load B, R1
Add R0, R1
Store R1, C
(b) Yes;
Move B, C
Add A, C

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Machine Instructions and Programs

Number Representation and Arithmetic Operations

1.4.1 Integers
Consider an n-bit vector : B = bn−1 . . . b1b0 where bi = 0 or 1 for 0 ≤ i ≤ n − 1.

We need to represent both positive and negative numbers. Three systems are used for
representing such numbers:
• Sign-and-magnitude
• 1‟s-complement
• 2‟s-complement

In all three systems, the leftmost bit is 0 for positive numbers and 1 for negative numbers.

In 1’s-complement representation, negative

values are obtained by complementing
each bit of the corresponding positive
number. Thus, the representation for −3 is
obtained by complementing each bit in the
vector 0011 to yield 1100.

In the 2’s-complement system, forming the

2‟s-complement of an n-bit number is done
by subtracting the number from 2n. Hence,
the 2‟s-complement of a number is
obtained by adding 1 to the 1‟s-
complement of thatnumber.

There are distinct representations for +0 and

−0 in both the sign-and magnitude and
1‟s- complement systems, but the 2‟s-
complement system has only one
representation for 0.

Addition of Unsigned Integers

The sum of 1 and 1 is the 2-bit vector 10, which represents the value 2. We say that the sum is 0 and the
carry-out is 1. We add bit pairs starting from the low-order (right) end of the bit vectors, propagating
carries toward the high-order (left) end. The carry-out from a bit pair becomes the carry-in to the next
bit pair to the left.

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Addition and Subtraction of Signed Integers
The 2‟s-complement system is the most efficient method for performing addition and subtraction
operations.
Unsigned integers mod N is a circle with the values 0 through N – 1. The decimal values 0 through 15
are represented by their 4-bit binary values 0000 through 1111.
The operation (7 + 5) mod 16 yields the value 12.
To perform this operation graphically, locate 7
(0111) on the outside of the circle and then move 5
units in the clockwise direction to arrive at the
answer 12 (1100).
Similarly, (9 + 14) mod 16 = 7; this is modeled on
the circle by locating 9 (1001) and moving 14 units
in the clockwise direction past the zero position to
arrive at the answer
7 (0111).
Apply the mod 16 addition technique to the
example of
adding +7 to −3. The 2‟s-complement
representation for these numbers is 0111 and 1101,
respectively.
To add two numbers, add their n-bit representations, ignoring the carry-out bit from the most
significant bit (MSB) position. The sum will be the algebraically correct value in 2‟s-complement
representation if the actual result is in the range −2 n−1 through+2 n−1 − 1.
To subtract two numbers X and Y , that is, to perform X − Y , form the 2‟s-complement of Y , then add it
to X using the add rule. Again, the result will be the algebraically correct value in 2‟s-complement

Representation if the actual result is in the range −2 n−1 through +2 n−1 − 1.

Assumptions:
 4-bit machine word
 16 different values can be represented
 Roughly half are positive, half are negative

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MEMORY-LOCATIONS & ADDRESSES

• Memory consists of many millions of storage cells (flip-flops).
• Each cell can store a bit of information i.e. 0 or 1 (Figure 2.1).
• Each group of n bits is referred to as a word of information, and n is called the word length.
• The word length can vary from 8 to 64 bits.
• A unit of 8 bits is called a byte.
• Accessing the memory to store or retrieve a single item of information (word/byte) requires distinct
addresses for each item location. (It is customary to use numbers from 0 through 2k-1 as the
addresses of successive-locations in the memory).
• If 2k = no. of addressable locations;
then 2k addresses constitute the address-space of the computer.
For example, a 24-bit address generates an address-space of 224 locations (16 MB).

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BYTE-ADDRESSABILITY
• In byte-addressable memory, successive addresses refer to successive byte locations in the memory.
• Byte locations have addresses 0, 1, 2. . . . .
• If the word-length is 32 bits, successive words are located at addresses 0, 4, 8. . with each word
having 4 bytes.

BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS

• There are two ways in which byte-addresses are arranged (Figure 2.3).
1) Big-Endian: Lower byte-addresses are used for the more significant bytes of the word.
2) Little-Endian: Lower byte-addresses are used for the less significant bytes of the word
• In both cases, byte-addresses 0, 4, 8. ............ are taken as the addresses of successive words in the
memory.

Consider a 32-bit integer (in hex): 0x12345678 which consists of 4 bytes: 12, 34, 56, and 78.
 Hence this integer will occupy 4 bytes in memory.
 Assume, we store it at memory address starting 1000.
 On little-endian, memory will look like
Address Value
1000 78
1001 56
1002 34
1003 12

 On big-endian, memory will look like

Address Value
1000 12
1001 34
1002 56
1003 78

WORD ALIGNMENT
• Words are said to be Aligned in memory if they begin at a byte-address that is a multiple of the
number of bytes in a word.
• For example,
 If the word length is 16(2 bytes), aligned words begin at byte-addresses 0, 2, 4 . . . . .
 If the word length is 64(2 bytes), aligned words begin at byte-addresses 0, 8, 16 . . . . .
• Words are said to have Unaligned Addresses, if they begin at an arbitrary byte-address.

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To retrieve information from memory, either for one word or one byte (8-bit), addresses for each location are
needed.
A k-bit address memory has 2k memory locations, namely 0 – 2 k -1, called memory space.
24-bit memory: 224 = 16,777,216 = 16M (1M=220)
32-bit memory: 232 = 4G (1G=230)
1K(kilo)=210
1T(tera)=240

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ACCESSING NUMBERS, CHARACTERS & CHARACTERS STRINGS

• A number usually occupies one word. It can be accessed in the memory by specifying its word
address. Similarly, individual characters can be accessed by their byte-address.
• There are two ways to indicate the length of the string:
1) A special control character with the meaning "end of string" can be used as the last character
in the string.
2) A separate memory word location or register can contain a number indicating the length of
the string in bytes.

MEMORY OPERATIONS
• Two memory operations are:
1) Load (Read/Fetch) &
2) Store (Write).
• The Load operation transfers a copy of the contents of a specific memory-location to the processor.
The memory contents remain unchanged.
• Steps for Load operation:
1) Processor sends the address of the desired location to the memory.
2) Processor issues „read‟ signal to memory to fetch the data.
3) Memory reads the data stored at that address.
4) Memory sends the read data to the processor.
• The Store operation transfers the information from the register to the specified memory-location.
This will destroy the original contents of that memory-location.
• Steps for Store operation are:
1) Processor sends the address of the memory-location where it wants to store data.
2) Processor issues „write‟ signal to memory to store the data.
3) Content of register(MDR) is written into the specified memory-location.

INSTRUCTIONS & INSTRUCTION SEQUENCING

• A computer must have instructions capable of performing 4 types of operations:
1) Data transfers between the memory and the registers (MOV, PUSH, POP, XCHG).
2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR, NOT).
3) Program sequencing and control (CALL.RET, LOOP, INT).
4) I/0 transfers (IN, OUT).
REGISTER TRANSFER NOTATION (RTN)
• The possible locations in which transfer of information occurs are: 1) Memory-location 2) Processor
register & 3) Registers in I/O device.
Location Hardware Binary Address Example Description
Memory LOC, PLACE, NUM R1  [LOC] Contents of memory-location LOC
are transferred into register R1.
Processor R0, R1 ,R2 [R3]  [R1]+[R2] Add the contents of register R1 &R2
and places their sum into R3.
I/O Registers DATAIN, DATAOUT R1  DATAIN Contents of I/O register DATAIN are
transferred into register R1.

ASSEMBLY LANGUAGE NOTATION

• To represent machine instructions and programs, assembly language format is used.
Assembly Language Format Description
Move LOC, R1 Transfer data from memory-location LOC to register R1. The contents of LOC
are unchanged by the execution of this instruction, but the old contents of
register R1 are overwritten.
Add R1, R2, R3 Add the contents of registers R1 and R2, and places their sum into register R3.

BASIC INSTRUCTION TYPES

Instruction Syntax Example Description Instructions
Type for
Operation

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Three Opcode Source1,Source2,Destination Add A,B,C Add the contents of C<-[A]+[B]
Address memory-locations A & B.
Then, place the result into
location C.
Two Address Opcode Source, Destination Add the contents of Move B, C
Add A,B
memory-locations A & B. Add A, C
Then, place the result into
location B, replacing the
original contents of this
location.
Operand B is both a source
and a destination.
One Address Opcode Source/Destination Load A Copy contents of memory- Load A
location A into accumulator. Add B
Add B Add contents of memory- Store C
location B to contents of
accumulator register &
place sum back into
accumulator.
Store C Copy the contents of the
accumulator into location C.
Zero Opcode [no Source/Destination] Push Locations of all operands Not possible
Address are defined implicitly.
The operands are stored in
a pushdown stack.
• Access to data in the registers is much faster than to data stored in memory-locations.
• Let Ri represent a general-purpose register. The instructions: Load A,Ri
Store Ri,A
Add A,Ri
are generalizations of the Load, Store and Add Instructions for the single-accumulator case, in which
register Ri performs the function of the accumulator.
• In processors, where arithmetic operations as allowed only on operands that are in registers, the task
C<-[A]+[B] can be performed by the instruction sequence:
Move A,Ri
Move B,Rj
Add Ri,Rj
Move Rj,C

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INSTRUCTION EXECUTION & STRAIGHT LINE SEQUENCING

• The program is executed as follows:
1) Initially, the address of the first instruction is loaded into PC (Figure 2.8).
2) Then, the processor control circuits use the information in the PC to fetch and execute
instructions, one at a time, in the order of increasing addresses. This is called Straight-Line
sequencing.
3) During the execution of each instruction, PC is incremented by 4 to point to next instruction.
• There are 2 phases for Instruction Execution:
1) Fetch Phase: The instruction is fetched from the memory-location and placed in the IR.
2) Execute Phase: The contents of IR is examined to determine which operation is to be
performed. The specified-operation is then performed by the processor.

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Program Explanation
• Consider the program for adding a list of n numbers (Figure 2.9).
• The Address of the memory-locations containing the n numbers are symbolically given as NUM1,
NUM2…..NUMn.
• Separate Add instruction is used to add each number to the contents of register R0.
• After all the numbers have been added, the result is placed in memory-location SUM.
BRANCHING
• Consider the task of adding a list of „n‟ numbers (Figure 2.10).
• Number of entries in the list „n‟ is stored in memory-location N.
• Register R1 is used as a counter to determine the number of times the loop is executed.
• Content-location N is loaded into register R1 at the beginning of the program.
• The Loop is a straight line sequence of instructions executed as many times as needed.
The loop starts at location LOOP and ends at the instruction Branch>0.
• During each pass,
→ address of the next list entry is determined and
→ that entry is fetched and added to R0.
• The instruction Decrement R1 reduces the contents of R1 by 1 each time through the loop.
• Then Branch Instruction loads a new value into the program counter. As a result, the processor
fetches and executes the instruction at this new address called the Branch Target.
• A Conditional Branch Instruction causes a branch only if a specified condition is satisfied. If the
condition is not satisfied, the PC is incremented in the normal way, and the next instruction in
sequential address order is fetched and executed.

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CONDITION CODES (To understand better refer class notes we solved problems)
• The processor keeps track of information about the results of various operations. This is accomplished
by recording the required information in individual bits, called Condition Code Flags.
• These flags are grouped together in a special processor-register called the condition code register (orstatue
register).
• Four commonly used flags are:
1) N (negative) set to 1 if the result is negative, otherwise cleared to 0.
2) Z (zero) set to 1 if the result is 0; otherwise, cleared to 0.
3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0.
4) C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0.

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IEEE Standard for Floating-point Numbers (For problem refer class notes)

A binary floating-point number can be represented by

 A sign for the number
 Some significant bits
 A signed scale factor exponent for an implied base of 2
The basic IEEE format is a 32-bit representation, shown in Figure 6.24a
Based on 2008 version of IEEE (Institute of Electrical and Electronics Engineers) Standard 754, labelled 754-2008.

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 The leftmost bit represents the sign, 𝑆, for the number.

 The next 8 bits, 𝐸′, represent the signed exponent of the scale factor (with an implied base of 2)
 The remaining 23 bits, 𝑀, are the fractional part of the significant bits.
 The full 24-bit string, B, of significant bits, called the mantissa, always has a leading 1, with the binary point
immediately to its right.
 Therefore, the mantissa 𝐵 = 1. 𝑀 = 1. 𝑏−1𝑏−2 … 𝑏−23 has the value V(𝐵) = 1+ 𝑏−1 × 2 −1 + 𝑏−2 × 2 −2 + ⋯ +
𝑏−23 × 2 −23
 By convention, when the binary point is placed to the right of the first significant bit, the number is said to be
normalized.
 Instead of the actual signed exponent, 𝐸, the value stored in the exponent field is an unsigned integer
𝐸′ = 𝐸 + 127.
 This is called the excess-127 format.
 𝐸′ is in the range 0 ≤ 𝐸′ ≤ 255.
 The use of the excess-127 representation for exponents simplifies comparison of the relative sizes of two
floating-point numbers.
 32-bit representation – single-precision
 8-bit excess-127 exponent 𝐸′ with range 1 ≤ 𝐸′ ≤ 254 for normal values
 0 and 255 indicate special values
 The actual exponent, 𝐸′, is in the range
 −126 ≤ 𝐸′ ≤ 127 providing scale factors of 2 −126 to 2 127 (approximately 10±38).
 The 54-bit mantissa provides a precision equivalent to about 7 decimal digits.
 64-bit representation – double-precision
 11-bit excess-1023 exponent 𝐸′ with range 1 ≤ 𝐸′ ≤ 2046 for normal values
 0 and 2047 indicate special values
 The actual exponent, 𝐸′, is in the range −1022 ≤ E ≤ 1023, providing scale factors of 2 −1022 to 2 1023
(approximately 10±308).
 The 53-bit mantissa provides a precision equivalent to about 16 decimal digits

 Two basic aspects of operating with floatingpoint numbers

First, if a number is not normalized, it can be put in normalized form by shifting the binary point and
adjusting the exponent.
 Underflow

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 Second, as computations proceed, a number that does not fall in the represent able range of normal numbers
might be generated.
 Overflow

Special value
 The end values 0 and 255 of the excess-127 exponent 𝐸′ are used to represent special values. When 𝐸′ = 0
and 𝑀 = 0, the value 0 is represented.
 When 𝐸′ = 255 and 𝑀 = 0, the value ∞ is represented.
 When 𝐸′ = 0 and 𝑀 ≠ 0, denormal numbers are represented.
 When 𝐸′ = 255 and 𝑀 ≠ 0, the value represented is called Not a Number (NaN).

Solve: Write the equivalent IEEE floating point format

1. (88.125) =?
2. (32.134)=?
3. (0.065)=?

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