CISC and RISC Architecture

Subject: Computer Organization and Architecure

Cource Code: CS208 Semester: IV Unit: I

Dr. Varun Kumar

varun [email protected]

Indian Institute of Information Technology, Vadodara

International Campus Diu (IIITV-ICD)

Subject: Computer Organization and ArchitecureCource

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Outlines

1 Broad classification of ISA

Complex instruction set computer
Reduced instruction set computer

2 Initial computer architecture

Von-Neumann architecture
Havard and Modified Havard architecture

3 MIPS32 architecture

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Growth in processor performance

Subject: Computer Organization and ArchitecureCource

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Broad classification of ISA
⇒Complex instruction set computer→ CISC
⇒ Reduced instruction set computer→ RISC
Key points to remember → CISC
⇒ More traditional approach
⇒ Main features
Complex instruction set
Large number of addressing mode
Special purpose register
Variable length instruction → Complex instruction encoding
Instruction decoding is more complex.
Pipeline implementation is quite complex.
CISC example
⇒ IBM 360/370→ 1960-70, VAX 11/780→ 1970-80, Intel
x86/Pentium→ 1985
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RISC architecture

⇒ Simpler instruction, hence simple instruction decoding.

⇒ Instruction comes under size of one word.

⇒ Instruction takes a single clock cycle to get executed.

⇒ More general-purpose registers.

⇒ Simple Addressing Modes.

⇒ Fewer Data types.

⇒ A pipeline can be achieved.

RISC example
⇒ CDC 6600 → 1964, MIPS family → 1980-1989, SPARC, ARM
Microcontroller family

Subject: Computer Organization and ArchitecureCource

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Comparative study

Subject: Computer Organization and ArchitecureCource

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Von-Neumann architecture → Princeton architecture

Processing unit Control unit

⇒ Arithmetic logic unit ⇒ Instruction register
⇒ Processor registers ⇒ Program counter
Memory unit Input and output unit
⇒ Stores data and instructions
⇒ External mass storage
Note: Same system bus was used for carrying instruction and data.

Subject: Computer Organization and ArchitecureCource

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Havard architecture

Key points to remember

⇒ Developed in Havard university.
⇒ Separate program and data memory.
⇒ Faster compare to Von Neumann architecture.
⇒ Processor can’t simultaneously read instruction and data
(Von-Neumann) but not in Havard.

Subject: Computer Organization and ArchitecureCource

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Modified Havard architecture

Key points to remember

⇒ Combination of Princeton and Havard architecture.
⇒ Cache memory → Integral part of processor
⇒ Processor execute instruction through cache → Havarad architecture
⇒ Processor access backing memory → Princeton architecture

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SISD SIMD MISD MIMD → Computer architecture

Instruction set architecture→ Classification

SISD → Single instruction single data → Von-Neumann architecture
SIMD → Single instruction multiple data
MISD → Multiple instruction single data
MIMD → Multiple instruction multiple data

Subject: Computer Organization and ArchitecureCource

Dr. Code:
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Kumar / Lecture-5
Semester: IV Unit: I Dr. Varun Kumarvarun
10 / 14
kuma
Example

Subject: Computer Organization and ArchitecureCource

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MIPS32 architecture
Microprocessor without Interlocked Pipelined Stages
MIPS32 is a RISC architecture

MIPS32 CPU register

⇒ 32, 32 bit general purpose register R0 to R31

⇒ A special purpose 32 bit register, i.e program counter PC
Points to the next instruction in memory to be fetched and executed.
Not directly visible to the programmer.
Affected only by indirect instruction set. Ex- call, Ret, jmp

⇒ A pair of 32 bit register HI and LO are used for storing large size of
data.
⇒ Missing register in MIPS32
Flag register (Zero, Overflow, Sign, Carry)
Stack pointer→ PUSH, POP, CALL, RET
Index register
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Continued–
Key points to remember
⇒ R0 is hard wired value of zero.
⇒ Can be used as a source, when zero value is needed
⇒ R31 is used to store the return address when a function call is made.

Example 1
⇒ LD R4 , 50(R3 ) → R4 = Mem[R3 + 50]
⇒ ADD R2 R1 R4 → R2 = R1 + R4
⇒ SD R2 R5 R0 → R2 = R5
Example 2
Main: ADDI R1 R0 35
ADDI R2 R0 56
JAL GCD
..
.
GCD
JR R31
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Continued–

Usage of HI and LO register

⇒ It is a special purpose register.

⇒ HI→ Store high 32 bit value in the register.

⇒ LO→ Store low 32 bit value in the register.

MIPS assembly language conventions
QtSPIM

Subject: Computer Organization and ArchitecureCource

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