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Series connection of power switches in high input voltage with wide range power
supply for gate driving application

Article · September 2011

DOI: 10.1109/ECCE.2011.6064171

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Series Connection of Power Switches in High
Input Voltage with Wide Range Power Supply for
Gate Driving Application
S. Buonomo, F. Distefano, F. Chimento A. Raciti, IEEE Senior Member,
A. Gaito, R. Scollo IEEE Member S. Tomarchio, D. Armenia
STMicroelectronics ABB AB Corporate Research University of Catania, DIEEI
Stradale Primosole 50 Forskargränd 8 Viale Andrea Doria, 6
95121, Catania 721 78, Västerås, Sweden 95 125, Catania, Italy
[email protected] [email protected] [email protected]

Abstract— In high power systems design an important voltage devices often do not match the designer needs in
issue is to provide low voltages, in the range of tens of Volt, terms of the switching frequency. Therefore in
tapping from high voltage input line, which is usually in the applications requiring a high switching frequency such as
range between hundreds of Volt to kilovolt, by means of high voltage power supplies for color television, medical
switching power supplies. Low voltages are needed to supply equipments or railway motor drives, a series connection of
logic control systems and power semiconductors driving the MOSFETs is the most advantageous solution and may
applications. The supply system has to deal, consequently, sometimes be considered the only viable [4] [5]. In fact by
with both wide input voltage range and electrical insulation. connecting MOSFETs in series allows obtaining the
The evaluation of the operative conditions of a driving
equivalent of a fast high voltage switch but with only a
system for IGCT devices, used in a transmission system
application with wide input voltage range, is described. The
fraction of the voltage applied to each single device. In
design of a 100W supply converter is shown considering all spite of this, however some additional problems arise since
the issues related with the series connection of power devices small differences in the switching times of the series
and the needs of insulation. Converter design, modeling and connected devices may cause an unequal voltage sharing
experimental results are shown together with the evaluation during the commutations. This is a problem since voltage
of the efficiency of the proposed solution. imbalances may lead some devices to exceed their
maximum forward blocking voltage causing failures.
Index Terms – MOSFETs, gate driving, power supply, Since voltage imbalances cannot be avoided, since depend
series connection, IGCT. on the usual parameter spread of MOSFETs, in order to
avoid any device failure a reliable voltage balancing
I. INTRODUCTION strategy is required, during switching transients and also in
One of the main problems besetting the power supply steady state [6].
designers today is to design a switching power supply that A power supply for power devices driver has been
is able to operate in the power systems within their studied and designed. A series connection of power
international marketplaces according to the available devices, with an insulated power stage, allows high voltage
voltage supply in the specific setup. When the DC input switching and operation at high frequency in order to
voltage to a buck converter has a wide range, it becomes obtain a low voltage ripple in the regulated output. A
important to select a suitable switching regulator integrated design procedure for a converter providing the power
circuit (IC) for the application, and to select the power needed by four driving circuits is detailed in this paper. In
components able to handle the worst-case input voltage. particular, the analysis focuses on both the insulation
For a given component, the worst-case may be the issues and the control. Finally, the experimental results on
maximum input voltage or the minimum input voltage, but a full scale prototype are discussed.
in fact may also be somewhere in between. The study
which will be described in this paper concerns the II. THE BUCK CONVERTER DESIGN
development of a high voltage buck converter for gate The main purpose of the analysis in this paper is the
drive applications [1]-[3]. Usually, these converters are design of the first power stage, not isolated DC/DC
used to feed the gate driving unit (GU) of IGBTs or converter shown in Fig. 1. The gate drive units are fed by
IGCTs. In particular this study will focus on IGCTs gate the DC voltage and so the energy is taken from a high
driver which needs a greater power then an IGBT gate voltage DC link that in this case may have a voltage up to
driver because of the higher current necessary to operate 3000 V. The DC supply is composed of two stages. The
the switching of the device. The IGBT or IGCT are used input voltage is first stepped down by a not isolated
in HVDC or FACTS applications and the gate drive unit DC/DC converter from the DC link high voltage to a
takes energy from the high DC voltage input. regulated 300 V DC. Two independent DC/DC converters
In the field of high voltage power conversion and low are used in parallel, for redundancy. This voltage is then
current, series connected MOSFETs have reached a wide fed to insulated DC/DC converters which feed the gate
diffusion mostly due to the fact that other types of high drive units with the required 24 V DC.

978-1-4577-0541-0/11/$26.00 ©2011 IEEE 2985

The first not isolated stage represents the most critical maximum voltage in this application is 3000 V. In order
part of the design for the isolation implications and the to guarantee a safe switching, three diodes in series
necessity to deal with wide input voltage range operation. connection have been used and each diode can withstand a
The topology used is a buck converter. In this one, the maximum voltage of 1000 V. In order to avoid voltage
reference of the gate drive signal of the power MOSFET is imbalance, capacitors in parallel connection with the
floating. Therefore, the gate drive circuit needs isolation diodes are used. The main features of the used diodes are
from the ground of the system, which is obtained by means VRRM = 1200 V and IF = 1 A.
of suitable optocouplers. The use of these electronic
devices allows transmitting signals keeping a galvanic
isolation between the two parts of the circuit. The main
schematic of the circuit used for IGCTs GUs supply is
depicted in Fig. 2. In particular, a function generator is
used to drive the power MOSFETs, Vpulse. In the following
sub-sections a description of the specifications and the
design of the several parts composing the DC-DC
converter are carried out in detail.

DC GDU GDU
DC

DC
DC
GDU GDU

Fig. 1: Overall solution for providing gate drive power from the DC link,
composed by a not isolated first stage and isolated second stage
switching converter.

A. Main circuit requirements for IGCT GU supply

The power supply for the IGCTs gate driver (STAGE
I) is fed from the DC link which has an input voltage
varying within a wide interval. The main design quantities
for the converter are given in Table I.

Table I: Main design quantities for the converter.

Fig. 2: Schematic of the low power solution adopted for IGCT driver
Input voltage 400 – 3000 V
supply as not isolated first stage switching converter.
Output voltage 300 V
Output rated power 100 W
Output voltage ripple (%) 20% (output voltage) The converter has been designed to operate in
Switching frequency 30 kHz continuous current mode (CCM). In order to guarantee the
Efficiency (@ 2.4 kVDC) 80% converter to work in CCM in all the possible input voltage
states there has been the need to evaluate the minimum
duty cycle value. According to the buck converter
B. Design of power switches and passive components equations [7]:
The first step on the converter design is the choice of Vout
the switches. The maximum input voltage, as previously G min Ÿ ton ,min G min Ts (1)
shown, is 3000 VDC, so that three MOSFETs should Vin, max
support the high voltage and the breakdown voltage of
In equation (1) the input voltage Vin = VDClink; Ts = 1/fs,
each power MOSFET has to be at least 1000 V. In order
where fs is the switching frequency and ton,min is the
to guarantee the safe operation of the system, the device of
minimum conduction time value of the power MOSFETs,
choice has been power MOSFET of the series
that is equal to 3μs. The equation (1) provides the values
SuperMESH3, that have a 1200 V breakdown voltage and
needed to design the minimum inductor value, Lmin that
3 A rated current. The mentioned rating has been chosen
allows the continuous mode.
in order to minimize the on state losses.
In a buck converter, when the switch is in on state, the Vin, max Vout
L ! Lmin t on ,min # 10mH (2)
total DC input voltage is applied across the cathode and I peak
anode of the diode and, as previously shown, the
2986
where Ipeak is the peak value of the inductor current when where COSS is the intrinsic equivalent output capacitance of
the duty cycle is minimum, Gmin; Iin,rms is the rms input the MOSFET device and CSN is the equivalent capacitor
current. In the buck converter, the minimum inductor given by the series of C1 and C2. The resistors R3 and R4
value that guarantees the continuous current mode are balancing ones and they have high value (about 3 M).
operation is 10mH, and the value taken into account in the Their main function is to allow the static voltage balance
design is 15mH. With reference to the output stage, the on the device. When the device is in on state, the diode is
output capacitor value depends on the design constraints reverse biased and the capacitor will discharge with a
on the voltage ripple, and this value is fixed at 20%. constant time 2.
From the characteristic equations of the buck converter 2 = R1(COSS + CSN) (5)
is then possible to calculate the value of the capacitor to be
The value of the equivalent capacitor CSN was designed
considered to obtain the desired voltage ripple. The main
greater than COSS. In particular, the value taken into
values to take into account are then the capacitance and the
account is the equivalent COSS capacitance. This latter is
parasitic Equivalent Series Resistance (ESR), [7] [8].
defined as a constant equivalent capacitance giving the
Cout = C’out + C’’out same charging time as COSS when VDS increases from 0 to
80% of VDSS. The value shown in the datasheet is 40 pF
65 ˜ 10 6 Ts2 V0 (3) (VGS = 0, VDS=0 to 960 V).
'
Cout ''
Cout 1 G
ESR 8L 'V0
Where C’out is the output capacitance contribute due to
the ESR and C’’out is the one to consider in order
minimizing the output voltage ripple V0.
C. Series connection
As described in the previous sections, the input voltage
may change in the range between 400 V to 3000 V, so that
more power devices connected in series are needed. In
order to do not have failures in the system all of these
devices must behave like one device thus being triggered
at the same time with an optimized synchronization
between their driving stages. Therefore, every power
MOSFET used as switch must have the same dynamic
characteristics in order to avoid issues of imbalance [9].
Since, as known, possible parameters spread among power Fig. 3: Snubber RCD circuit used for each power switch in the series
devices is unavoidable, the series connection driving has to connection.
be realized as effective through the use of proper snubber
circuits [10], or rather a passive network that guarantees If the value of CSN is too big, the turn off switching is
the correct balance of the bus voltage on every device very slow. In order to have a good switching the time to
when this ones are on off state (static balance) and during charge and discharge the capacitor has to be less then ton
the switching (dynamic balance). If the voltage is not and toff. The design of this circuit was done considering
equal on every switch failures may happen. The problem the extreme case when the input voltage is 3000 V and the
may arise from the following issues: duty cycle is the minimum, as shown by (1). This
condition provides the minimum ton that allows fixing the
• spread on the leakage current; constant time of the capacitor’s discharge. The value of
• different delay time among the gate signals; the time constant 2 is calculated according to the
following expressions:
• different input impedance.
Tdisch t on , min (6)
Thus, if the system operates in a correct way, the same
dv/dt on the series connected devices will appear, and such According to (6), it is possible to obtain the discharge
a condition may be ensured by an appropriate design of the time constant value Tdisch < 3μs and because the discharge
snubber circuit [11]. The circuit used on every device is a time is about 4 – 5 times the time constant 2, this is fixed
RCD one, as shown in Fig. 3. Two paths, having different as follows:
resistance, are used to control the dynamic voltage during
Tdisch
the turn-on time and the turn-off time. A diode is used to W2 (7)
separate the two paths of charge and discharge of the 5
capacitors, but can be omitted in some cases. The value of the capacitor (CSN) is fixed at 410pF by
means of two capacitors in series connection (C1 and C2)
When the power device is in off state the diode D1 is in having 820pF, while R1 value is 5k.
forward state and (neglecting the two resistors R3 and R4)
the series connection of the capacitors C1 and C2 is charged The time constant 2 sets the discharge time of the
with a time constant 1. capacitor during on time, while during turn off state the
slope is fixed by the time constant 1. Choosing R1 >> R2
1 = R1//R2·(COSS + CSN) (4) and CSN >> COSS, the constant time relation can be
simplified as follows:
2987
W 1 # R2CSN (8) constant output power of 100 W. The outline of the
experimental evaluated scenarios is the following:
Experimental measurements have shown that a good
matching between voltage imbalance and turn off time (of 1. Evaluation of synchronous operation among the
the voltage VDS of each device) is obtained by fixing the series connected switches;
time constant 1=7ns, so the value of resistor R2 is 45. 2. System efficiency and device temperature.
In order to evaluate the power losses in the snubber The performance of the system has been evaluated for
circuit, the energy stored in the snubber capacitor is different values of the input voltage. The evaluation is
considered. During the turn off and turn on switching, the focused on the power losses during the switching
energy of the capacitor ( EC SN ) is dissipated by the resistors transients, during the conduction and on the snubber
R1 and R2. The power losses in the resistors, Ploss,R1 and circuit. In particular RDS,on has, for power MOSFETs, a
Ploss,R2 are given by the following relations, where Ich,rms positive thermal coefficient as shown in Fig. 5. The
and Idisch,rms are respectively the rms current of charge and effects on the system temperature and the efficiency have
discharge of the equivalent capacitor CSN, and V is the consequently been evaluated.
voltage drop on it.

2 1
Ploss,R1 R1 I ch, rms CSNV 2 f s
2
2 1
Ploss,R 2 R2 I disch, rms CSNV 2 f s (9)
2
1
ECSN CSNV 2
2
In this way the power losses in the snubber circuit,
Ploss,tot, are obtained by the product between the switching
frequency fs and the double of the energy stored in the
equivalent capacitor CSN.

Ploss, tot Ploss,R1 Ploss,R 2 f s CSNV 2 (10) Fig. 5: Normalized RDS,on value @25°C vs.
temperature (from device datasheet).
As shown by equation (10), the losses increase with the
square of the voltage drop on the capacitor, being constant The selection of the components is important in order
the switching frequency and the snubber capacitor. In Fig. to fulfill the system requirements. The spread of the
4 the power losses in each snubber circuit and the total parameters in the device may cause a different start time at
power losses at different input voltages are shown. turn on and turn off, and causes a voltage imbalance
between the devices. Other important feature is the
isolation between the input and output obtained by means
of the optocouplers, which will guarantee isolation up to
3000 V.

VGS1
VGS2
VGS3

Fig. 4: Power losses of the snubber circuits vs. voltage input.

Fig. 6: Gate voltages during turn off switching;
VGS1, VGS2, VGS3 5 V/div; time 20 ns/div.

III. EXPERIMENTAL VALIDATION

In Fig. 6 and Fig. 7 the waveforms of the gate signal in
Experimental tests have been done in different the three devices are shown, during the turn off and turn on
conditions of input voltage (from 400 V to 3000 V) and switching transients. In particular, in Fig. 6, it is possible

2988
to see the turn off sequence of the devices, T3, T2 and T1 In Fig. 8 and Fig. 9 the switching transients and the
respectively. This one causes a greater voltage drop on the power losses for the three devices are shown at Vin=3000
device T3 and lower in T1 and T2, (see Fig. 8). V. Higher losses at turn on than at turn off are clearly
shown. This is caused by the snubber circuit because
during the turn off, the VDS slope is reduced on each
device and the cross between voltage and current is lower.
In a similar way in Fig. 10 and Fig. 11, the switching
transient and the power losses are shown at Vin =400 V.
VGS1 In this case the power losses in the devices are lower than
VGS2 in the first case, because the cross between voltage and
VGS3 current is lower. Thus by reducing the voltage drop on
the devices the power losses get reduced.

Fig. 7: Gate voltages during turn on switching;

VGS1, VGS2, VGS3 5 V/div; time 50 ns/div.

In Fig. 7, instead, the turn on sequence of the device, is

T3, T1 and T2 respectively. The unbalances are due to the
parameters spread of the optocouplers and of the passive
components.

Fig. 10: Turn off switching; VDS1, VDS2, VDS3 50 V/div, ID 1 A/div; P1
(VDS1·ID), P2 (VDS2·ID), P3 (VDS3·ID) 50 W/div; time 500 ns/div.

Fig. 8: Turn off switching; VDS1, VDS2, VDS3 200 V/div, ID 100 mA/div;
P1 (VDS1·ID), P2 (VDS2·ID), P3 (VDS3·ID) 100W/div; time 500 ns/div.

Fig. 11: Turn on switching; VDS1, VDS2, VDS3 50 V/div, ID 1 A/div; P1

(VDS1·ID), P2 (VDS2·ID), P3 (VDS3·ID) 100 W/div; time 200 ns/div.

In Table II a summary of the main results coming from

the experimental tests at different input voltages are
shown.
In Fig. 12 and Fig. 13 the evaluation of the distribution
of the temperatures among devices is shown in an infrared
camera capture for two different cases of input voltage
(Vin=400 V and Vin=3000 V). In agreement with Table II
the devices temperature is higher on the device with
greater losses than device with lower losses.
In Fig. 14 and Fig. 15 the temperatures and the power
losses on the devices are shown at different input voltage,
Fig. 9: Turn on switching; VDS1, VDS2, VDS3 200 V/div, ID 2 A/div; P1 and in Fig. 16 and Fig. 17 are shown respectively the
(VDS1·ID), P2 (VDS2·ID), P3 (VDS3·ID) 500W/div; time 100ns/div. voltage drop on each devices and the relative voltage

2989
unbalance ('V%) at different input voltage. This latter has
been evaluated in the following way:

VN Vavg
'V % 100 (11)
Vavg

Where VN is the voltage drop on the N device (N = 1,

2 or 3), and Vavg is Vin/3.
Table II: Summary of the power losses in the three series
connected switches.
VIN POFF PCOND
Device PON [W] PTOT [W]
[V] [10-3W] [10-3 W]
400 T1/T2/ T3 0.44/0.43/0.25 29/40/67 146/146/146 0.61/0.61/0.46
1200 T1/T2/ T3 0.74/0.98/0.38 19/18/26 20/20/20 0.77/0.99/0.42
1500 T1/T2/ T3 0.73/0.98/0.38 19/18/26 20/20/20 1.12/1.51/0.68
Fig. 15: Power losses on the devices (T1, T2, T3) vs. input voltage (Vin).
2000 T1/T2/ T3 1.82/2.25/1.18 78/62/117 8/8/8 1.91/2.32/1.31
2500 T1/T2/ T3 2.67/3.35/1.89 48/71/59 6/7/6 2.62/3.40/1.94
3000 T1/T2/ T3 3.82/4.66/3.24 114/32/40 6/7/4 3.90/4.70/3.28

Fig. 12: Thermal image by T1, T2 and T3 with Vin=400V.

Fig. 16: Drain- source voltage vs. input voltage.

Fig. 13: Thermal image by T1, T2 and T3 with Vin=3000V.

Fig. 17: Percentage relative voltage imbalance vs. input voltage.

After the measurements of the switching and the

conduction losses on all three devices, and the evaluation
of the power losses on the snubber circuits, the efficiency
was estimated. Fig. 18 shows as the efficiency changes at
Fig. 14: Temperature on the devices (T1, T2, T3) vs. input voltage (Vin). different input voltage.

2990
Fig. 18: Efficiency (output power /input power) vs. input voltage.
Fig. 21 Drain- source voltage (T3) vs. input voltage.
The efficiency of the system goes under 80% up to
2200 V because the power losses on the snubber increase
with the square of the input voltage.
The system without snubber has been tested and the
voltages drop, VDS, for each device is shown from Fig. 19
to Fig. 21 and compared with the voltage drop with
snubber circuit.

Fig. 22: Switching overall without snubber circuit; VDS1, VDS2, VDS3 200
V/div, ID 500 mA/div; time 25 μs/div.

In Fig. 22 the drain–source voltage on each power

MOSFET of the series and the drain current, ID are shown.
The maximum input voltage reached without snubber
circuit is 2460V, because the voltage drop on the device
T3 reaches a value near the VDSS.
In Fig. 23 the relative voltage imbalance on the power
MOSFETs in the series connection is shown. In order to
test the strength of the snubber circuit, simulations were
done considering a modification of the delay time of gate-
source driving signal of the power MOSFET at 3000V
input voltage. In particular the gate source signal of T2
and T3 was delayed form 50ns to 1μs, the voltage on each
Fig. 19: Drain- source voltage (T1) vs. input voltage.
device was taken into account and the relative imbalance
was evaluated, as shown in Fig. 24 and Table III.

Fig. 20: Drain- source voltage (T2) vs. input voltage. Fig. 23: Percentage relative voltage imbalance without snubber circuit
vs. input voltage.

2991
By this comparison it can be observed that the snubber order to obtain a better RDS,on than a single device and a
circuit allows a safer operation especially at higher input breakdown voltage up to 3000 V. In general, the series
voltage levels making it possible to have a lower relative connection is able to work at higher frequency than a
voltage imbalance than in the case when it is not used (see single device with same breakdown voltage and nominal
Fig. 17 and Fig. 23). current.
In order to avoid voltage imbalance a suitable snubber
circuit has been used in parallel connection with the
devices and optocouplers have been used to drive the gate
of each device and to ensure galvanic isolation between
power side and the driver (signal side). Design procedures
and experimental results have been shown and the
efficiency of the realized prototype has been evaluated.

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