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Exercise Chapter 2

This document discusses several benchmark programs run on different computer architectures and processors. It analyzes the execution times, clock frequencies, instruction counts, and CPI values to determine MIPS rates and compare performance. Parallelization across multiple cores and the use of caches to improve memory access times are also examined.

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12 views

Exercise Chapter 2

This document discusses several benchmark programs run on different computer architectures and processors. It analyzes the execution times, clock frequencies, instruction counts, and CPI values to determine MIPS rates and compare performance. Parallelization across multiple cores and the use of caches to improve memory access times are also examined.

Uploaded by

tuanminhdo1203
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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2.10 A benchmark program is run on a 40 MHz processor.

The executed program consists


of 100,000 instruction executions, with the following instruction mix and clock cycle
count:
Instruction Type Instruction Count Cycles per Instruction
Integer arithmetic 45,000 1
Data transfer 32,000 2
Floating point 15,000 2
Control transfer 8000 2
Determine the effective CPI, MIPS rate, and execution time for this program.
CPI=1.55
MIPS=f/CPI=40/1.55=25.8
EX time=3.875s
2.11 Consider two different machines, with two different instruction sets, both of which
have a clock rate of 200 MHz. The following measurements are recorded on the two
machines running a given set of benchmark programs:
Instruction Count
Instruction Type Cycles Per Instruction
(millions)
Machine A
8 1
Arithmetic and logic
4 3
Load and store
2 4
Branch
4 3
Others
Machine A
10 1
Arithmetic and logic
8 2
Load and store
2 4
Branch
4 3
Others
a. Determine the effective CPI, MIPS rate, and execution time for each machine.

CPI A=2,22

MIPS A = f/CPI=90

Time=I/MIPS=18/90=0,2s

CPI B=1,92

MIPS B=104

Time=0,23s
b. Comment on the results.

Số triệu câu lệnh trên giây của A nhỏ hơn của B nhưng thời gian A ít hơn B

2.12 Early examples of CISC and RISC design are the VAX 11/780 and the IBM RS/6000,
respectively. Using a typical benchmark program, the following machine characteristics
result:

Clock Performanc
CPU Time
Processor Frequency e
(seconds)
(MHz) (MIPS)
VAX 11/780 5 1 12 x
IBM RS/6000 25 18 x
The final column shows that the VAX required 12 times longer than the IBM measured
in CPU time.
a. What is the relative size of the instruction count of the machine code for this
benchmark program running on the two machines?

VAX 11/780=MIPS x T=12x

IBM RS/6000=18x
18x/12x=1.5
b. What are the CPI values for the two machines

Regarding to the VAX 11/780, the CPI = (5 MHz) / (1 MIPS) = 5

Regarding to the IBM RS/6000, the CPI = (25 MHz) / (18 MIPS) = 1.4

2.13 Four benchmark programs are executed on three computers with the following
results:
Computer Computer
Computer C
A B
Program 1 1 10 20
Program 2 1000 100 20
Program 3 500 1000 50
Program 4 100 800 100
The table shows the execution time in seconds, with 100,000,000 instructions executed in each of the four programs. Calculate
the MIPS values for each computer for
each program. Then calculate the arithmetic and harmonic means assuming equal
weights for the four programs, and rank the computers based on arithmetic mean and
harmonic mean

2.16 Consider the example in Section 2.5 for the calculation of average CPI and MIPS rate,
which yielded the result of CPI = 2.24 and MIPS rate = 178. Now assume that the
program can be executed in eight parallel tasks or threads with roughly equal number
of instructions executed in each task. Execution is on an 8-core system with each
core (processor) having the same performance as the single processor originally used.
Coordination and synchronization between the parts adds an extra 25,000 instruction
executions to each task. Assume the same instruction mix as in the example for each
task, but increase the CPI for memory reference with cache miss to 12 cycles due to
contention for memory.
a. Determine the average CPI.
b. Determine the corresponding MIPS rate.
c. Calculate the speedup factor.
d. Compare the actual speedup factor with the theoretical speedup factor determined by Amdhal’s law.

2.17 A processor accesses main memory with an average access time of T2. A smaller cache
memory is interposed between the processor and main memory. The cache has a
significantly faster access time of T1 < T2. The cache holds, at any time, copies of some
main memory words and is designed so that the words more likely to be accessed
in the near future are in the cache. Assume that the probability that the next word
accessed by the processor is in the cache is H, known as the hit ratio.
a. For any single memory access, what is the theoretical speedup of accessing the
word in the cache rather than in main memory?
b. Let T be the average access time. Express T as a function of T1, T2, and H. What is
the overall speedup as a function of H?
c. In practice, a system may be designed so that the processor must first access the
cache to determine if the word is in the cache and, if it is not, then access main
memory, so that on a miss (opposite of a hit), memory access time is T1 + T2.
Express T as a function of T1, T2, and H. Now calculate the speedup and compare
to the result produced in part (b).

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