Solved Question Paper Computer Engineering 4th Sem.

Computer Organization & Architecture

SECTION-A

Note: Multiple Choice Questions. All questions are

Compulsory. (10x1=10)

Q.1 Input device is

a. Keyboard b. Printer

c. Monitor d. Plotter

Ans. A

Q.2 RISC stands for

a. Reduced Instruction set computer

b. Read Instruction set computer

c. Reduced Instruction set coming

d. Reduced Input self computer

Ans .(A)

Q.3 1 GB = _____ Bytes (CO1)

a. 1,000 b. 1,000,000,000,000

c. 1,000,000 d. 1,000,000,000

Ans D

Q.4 RAM is

a. Volatile memory b. Static Memory

c. Garbage memory d. Low speed memory

Ans. A

Q.5 An address generated by CPU is generally referred as_______

a. Physical Address b. Associative Address

c. Referral Address d. Logical Address

Ans. D

Q.6 Which of the following is not type of ROM

a. PROM b. EEPROM

c. EAROM d. MEPROM
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
Ans. D

Q.7 RAM can be______

a. SRAM, DRAM b. ROM

c. PROM d. MEPROM

Ans. A

Q.8 A_____ buffer can be used for fetch segment

a. MIFO b. SIFO

c. FIFO d. LIFO

Ans. C

Q.9 Name the parallel processing

a. SIMD, MIMD b. MISD

c. SISD D. All of above

Ans. D

Q.10 Parallel processor is

a. Distributed architecture b. pipelining

c. BIOS d. RISC

Ans. A

Section B

Note: Objective type Questions. All Questions are compulsory.

Q.11 The ___ stores intermediate data used during the execution of the instructions

Ans. Register

Q.12 ALU performs micro operations for executing the

Ans. arithmetic and logical operations

Q.13 Register that hold the address for the stack is

called_____ Ans. Stack pointer

Q.14 The ____ points at the address of the next

instruction in the program. Ans. Program counter

Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
Q.15 Memory refers to the ____ of a computer system.

Ans. Storage

Q.16 Parts of primary memory are ___ and ____

Ans. RAM (Random Access Memory) and ROM (Read-Only Memory)

Q.17 EPROM stands for ______

Ans. Erasable Programmable Read-Only Memory.

Q.18 Access time = _____ + _____

Ans. Seek Time + Latency (or Rotational Delay)

Q.19 I/O Bus consists of ____, ____ and ____

Ans. Data Lines, Address Lines, and Control Lines.

Q.20 A parallel MIMD systems, communication is

essential for processing.

Ans. Yes, in parallel MIMD (Multiple Instruction, Multiple Data) systems, communication between
processors is essential for coordinating tasks and processing data efficiently.

Section C

Q.21 Explain One-Address Instructions?

Ans. One-address instructions are a type of machine language instruction format that uses a single
address field. This address can point to a memory location or a register where the operand is stored. The
typical structure of a one-address instruction includes an opcode, which specifies the operation to be
performed, and an address field, which specifies the location of the operand. An accumulator register
often acts as the implicit second operand and the destination for the result. The process involves
fetching the operand from memory, performing the specified operation with the accumulator, and then
storing the result back in the accumulator. This format simplifies the instruction set and reduces the
complexity of the hardware needed to decode instructions.

Q.22 Explain 1) Direct Address Mode, 2) Indirect Address Mode (CO-1)

1. Direct Address Mode: In direct address mode, the address field of the instruction specifies the
memory location where the operand is directly stored. This mode allows for fast access to
operands because the address is explicitly stated in the instruction, eliminating the need for
further memory reference. However, it limits the addressable memory space due to the fixed
length of the address field.
2. Indirect Address Mode: In indirect address mode, the address field of the instruction refers to a
memory location that contains the effective address of the operand. This mode allows for
accessing a larger memory space since the effective address can be stored in a memory location.
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
However, it requires additional memory fetches, which can slow down instruction execution
compared to direct addressing.

Q.23 What are the steps followed by CPU when an interrupt occurs?

When an interrupt occurs, the CPU follows a specific sequence of steps to handle it:

1. Interrupt Signal Recognition: The CPU recognizes the interrupt signal sent by an I/O device or
software interrupt.
2. Save Current State: The CPU saves the current state of execution, including the program
counter, registers, and other status information, typically on the stack.
3. Interrupt Vector Lookup: The CPU uses the interrupt vector table to find the address of the
interrupt service routine (ISR).
4. ISR Execution: The CPU jumps to the ISR address and begins executing the code to handle the
interrupt.
5. Restore State: After the ISR has finished executing, the CPU restores the saved state from the
stack.
6. Resume Execution: The CPU resumes normal execution of the program from the point where it
was interrupted.

Q.24 Compare internal interrupts and external interrupts.

• Internal Interrupts: These are generated by internal conditions within the CPU, such as
arithmetic overflow, division by zero, or illegal instructions. They are often referred to as
exceptions or traps and are used to handle errors and exceptional conditions within the CPU
itself.
• External Interrupts: These are generated by external hardware devices, such as keyboards,
mouse, or network cards, requiring the CPU's attention. External interrupts are asynchronous
and can occur at any time, prompting the CPU to handle I/O operations or other hardware
events.

Q.25 Write short note on 1) SRAM, 2) DRAM

1. SRAM (Static RAM): SRAM is a type of semiconductor memory that uses bistable latching
circuitry to store each bit. It is called static because it retains data as long as power is supplied,
without the need for periodic refresh cycles. SRAM is faster and more reliable than DRAM but is
more expensive and consumes more power, making it suitable for cache memory and other
high-speed applications.
2. DRAM (Dynamic RAM): DRAM stores each bit of data in a separate capacitor within an
integrated circuit. Because capacitors leak charge, DRAM requires periodic refreshing to
maintain the stored data. It is slower than SRAM but is cheaper and has higher storage density,
making it ideal for main system memory where large capacity is required.

Q.26 Why virtual memory is used in computer system?

Virtual memory is used in computer systems to extend the apparent amount of physical memory by
using a portion of the disk storage as additional RAM. This allows a system to run larger applications and
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
handle more processes simultaneously than the physical memory alone would permit. Virtual memory
improves system stability and multitasking capabilities by isolating the memory spaces of different
applications, thus preventing them from interfering with each other. It also provides a more efficient
and flexible use of physical memory through techniques like paging and segmentation, ensuring that
memory is allocated dynamically based on the needs of running applications.

Q.27 What is memory mapping? Explain.

Memory mapping is the process of translating logical addresses used by a program into physical
addresses used by the computer hardware. This translation is managed by the memory management
unit (MMU), which allows the CPU to access data and instructions stored in memory efficiently. Memory
mapping supports the implementation of virtual memory, enabling programs to use more memory than
physically available by mapping parts of their address space to disk storage. It also provides isolation
between processes, ensuring that each process runs in its own protected memory space, thereby
enhancing security and stability.

Q.28 What are the components of memory management unit?

The components of a Memory Management Unit (MMU) typically include:

1. Translation Lookaside Buffer (TLB): A cache that stores recent translations of virtual addresses
to physical addresses to speed up memory access.
2. Page Table: A structure that holds the mapping between virtual addresses and physical
addresses.
3. Segment Table: Used in systems that implement segmentation, holding the base address and
limit for each segment.
4. Memory Protection Unit (MPU): Ensures that a program can only access its allocated memory
regions, preventing unauthorized access.
5. Address Translation Logic: The circuitry that performs the actual translation from virtual to
physical addresses.

Q.29 What is difference between static RAM and dynamic RAM?

The primary differences between static RAM (SRAM) and dynamic RAM (DRAM) are:

• Storage Technique: SRAM uses bistable flip-flops to store each bit, whereas DRAM uses
capacitors to store each bit.
• Speed: SRAM is faster than DRAM because it does not require refreshing.
• Cost: SRAM is more expensive than DRAM due to its complex circuitry.
• Power Consumption: SRAM consumes more power than DRAM.
• Density: DRAM has higher storage density than SRAM, allowing for larger memory capacities.

Q.30 What are the major functions of BIOS?

The Basic Input/Output System (BIOS) performs several critical functions in a computer system:
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
1. Power-On Self-Test (POST): Checks the hardware components and ensures they are working
properly before booting the operating system.
2. Bootstrap Loader: Locates the operating system and passes control to it.
3. BIOS Setup Utility: Provides a user interface to configure hardware settings, such as system
clock, boot sequence, and hardware configurations.
4. Hardware Abstraction: Provides a layer of abstraction between the operating system and
hardware, enabling the OS to interact with hardware components without needing to know
their specifics.

Q.31 Write short note on synchronous and asynchronous data transfer.

1. Synchronous Data Transfer: In synchronous data transfer, data is transmitted at regular

intervals that are synchronized by a clock signal. Both the sender and receiver share a common
clock, which ensures that data is sent and received at predictable times. This method is efficient
for transferring large volumes of data quickly and is commonly used in systems with high-speed
communication requirements.
2. Asynchronous Data Transfer: Asynchronous data transfer does not rely on a shared clock signal.
Instead, data is sent in a sequence with start and stop bits to indicate the beginning and end of
each byte or character. This method is more flexible and can accommodate varying transmission
rates, making it suitable for communication over longer distances or in systems where data is
sent sporadically.

Q.32 Explain briefly interrupt priority encoder.

An interrupt priority encoder is a hardware component that manages multiple interrupt requests by
assigning priority levels to each request. When several interrupts occur simultaneously, the priority
encoder determines which interrupt has the highest priority and should be serviced first. It generates a
corresponding priority code and sends it to the CPU, which then handles the interrupt accordingly. This
mechanism ensures that critical tasks are addressed promptly, maintaining system stability and
efficiency by preventing lower-priority interrupts from delaying the processing of higher-priority ones.

Q.33 Explain types of parallel processing?

Parallel processing can be classified into several types based on the architecture and the way tasks are
executed:

1. Single Instruction, Multiple Data (SIMD): Executes the same instruction on multiple data points
simultaneously. Commonly used in vector processors and GPUs.
2. Multiple Instruction, Multiple Data (MIMD): Executes different instructions on different data
points concurrently. Found in most modern multiprocessor systems and distributed computing
environments.
3. Single Instruction, Single Data (SISD): Executes a single instruction on a single data point.
Represents traditional sequential processing.
4. Multiple Instruction, Single Data (MISD): Executes multiple instructions on a single data point.
Rarely used in practical systems but can be found in certain specialized applications like fault-
tolerant computing systems.
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
Q.34 What is Reverse Polish Notation?

Reverse Polish Notation (RPN), also known as postfix notation, is a mathematical notation in which
operators follow their operands. For example, the expression "3 + 4" in conventional infix notation is
written as "3 4 +" in RPN. This notation eliminates the need for parentheses to indicate the order of
operations, as the position of the operator inherently determines the precedence. RPN is advantageous
for computer processing because it allows for efficient stack-based computation and simplifies the
parsing of mathematical expressions.

Q.35 What are the various characteristics of multiprocessors?

Multiprocessors have several key characteristics that enhance their performance and capabilities:

1. Parallelism: Ability to perform multiple operations simultaneously, increasing computational

speed and efficiency.
2. Scalability: Can be scaled by adding more processors to handle larger workloads.
3. Fault Tolerance: Enhanced reliability and fault tolerance due to redundancy; failure of one
processor does not halt the entire system.
4. Shared Memory: Processors can share a common memory space, facilitating communication
and data exchange between them.
5. Interconnection Networks: Use of high-speed interconnection networks to connect processors,
enabling efficient data transfer and coordination.

Section C

Q.36 Explain the characteristic of RISC architecture

Reduced Instruction Set Computer (RISC) architecture is designed to simplify the instructions executed
by the CPU to increase performance. The key characteristics of RISC architecture include:

1. Simple Instructions: RISC processors use a small set of simple instructions, each of which can be
executed in a single clock cycle. This contrasts with Complex Instruction Set Computer (CISC)
architectures, which have a larger set of more complex instructions that may take multiple
cycles to execute.
2. Load/Store Architecture: RISC separates memory access operations from computational
operations. Data is loaded from memory into registers, and all computations are performed
using these registers. Results are then stored back in memory. This approach simplifies
instruction decoding and execution.
3. Pipelining: RISC architectures are designed to maximize instruction throughput using pipelining,
where multiple instruction stages are processed simultaneously. This allows for the overlapping
of instruction execution, significantly increasing CPU efficiency and performance.
4. Fixed Instruction Length: Instructions in RISC are typically of a fixed length, simplifying the
instruction fetch and decode stages of the CPU pipeline. This uniformity enhances predictability
and reduces the complexity of the control unit.
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
5. Few Addressing Modes: RISC architectures limit the number of addressing modes to simplify
instruction decoding and execution. Common addressing modes include register, immediate,
and displacement addressing.
6. Compiler Optimization: RISC architecture relies heavily on optimizing compilers to efficiently
translate high-level language code into machine code. The simplicity of RISC instructions allows
compilers to generate optimized code that maximizes performance.
7. High Register Count: RISC processors have a large number of general-purpose registers to
minimize memory access and improve performance. By using registers for most operations, RISC
reduces the number of slow memory accesses.
8. Delayed Branching: To mitigate the impact of branch instructions on the instruction pipeline,
RISC architectures often use delayed branching. This technique delays the execution of a branch
instruction by filling the pipeline with useful instructions, reducing pipeline stalls.

Overall, RISC architecture's focus on simplicity, efficiency, and high-speed instruction execution makes it
well-suited for applications requiring high performance and low power consumption.

Q.37 Write short notes on

1. Virtual Memory: Virtual memory is a memory management technique that provides an

"idealized" abstraction of the storage resources that are actually available on a given machine.
This creates the illusion to users of a very large (main) memory. The primary benefits of virtual
memory include increased address space, which allows larger programs to run on a system, and
isolation between processes, which enhances security and stability by preventing one process
from interfering with another. Virtual memory relies on a combination of hardware and
software, including the use of a page table to map virtual addresses to physical addresses and
the swapping of data between RAM and disk storage to manage limited physical memory
effectively.
2. Demand Paging: Demand paging is a technique of virtual memory management where pages of
data are brought into memory only when they are needed, or "demanded," by the running
process. This contrasts with pre-paging, where pages are loaded in advance. Demand paging
reduces the amount of memory used by only loading necessary pages, which can lead to more
efficient use of memory and reduced loading times. However, it can also cause page faults,
which occur when a referenced page is not in memory and must be loaded from disk, potentially
causing delays.
3. Associative Memory: Also known as content-addressable memory (CAM), associative memory
allows data to be accessed based on content rather than a specific address. This type of memory
is useful in applications requiring high-speed searches, such as caching and memory
management in computers. In associative memory, data is stored along with a tag or key, and a
search operation can be performed to find all data entries matching a given key. The main
advantage of associative memory is its ability to perform parallel searches, significantly speeding
up the retrieval of information compared to traditional memory systems.

Q.38 Write short note on

1. Explain Various Types of Pipelining: Pipelining is a technique used in CPU design to increase
instruction throughput by overlapping the execution of multiple instructions. There are several
types of pipelining:
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture
o Instruction Pipelining: This divides the instruction execution process into several stages,
such as fetch, decode, execute, and write-back. Each stage processes a different
instruction simultaneously, allowing for one instruction to be completed per clock cycle.
o Arithmetic Pipelining: Used in floating-point units and other arithmetic operations,
arithmetic pipelining breaks down complex arithmetic operations into simpler stages
that can be executed in parallel.
o Super pipelining: Increases the number of pipeline stages, allowing for even finer
granularity and higher instruction throughput. This type of pipelining requires careful
management of pipeline hazards to maintain efficiency.
o Superscalar Pipelining: Executes multiple instructions in parallel within the same clock
cycle by using multiple pipelines. This requires additional hardware complexity and
sophisticated scheduling mechanisms to handle instruction dependencies and hazards.
2. Discuss Characteristics of Computer Architecture: Computer architecture refers to the
conceptual design and fundamental operational structure of a computer system. Key
characteristics include:
o Instruction Set Architecture (ISA): Defines the set of instructions that a processor can
execute, including the instruction formats, addressing modes, and supported data types.
o Microarchitecture: Describes the implementation of the ISA within a processor,
including the design of the data path, control unit, and memory hierarchy. It determines
the efficiency and performance of instruction execution.
o Memory Hierarchy: Organizes memory into a hierarchy of levels, each with different
speeds and sizes, from fast, small cache memory to slower, larger main memory and
disk storage. This hierarchy optimizes the trade-off between speed and cost.
o Parallelism: Involves techniques such as pipelining, superscalar execution, and
multiprocessing to perform multiple operations concurrently, increasing overall system
performance.
o I/O Systems: Manages input and output operations, including the design of interfaces,
communication protocols, and data transfer methods between the processor, memory,
and peripheral devices.
o Power Efficiency: Focuses on reducing power consumption while maintaining
performance, an essential consideration in modern portable and embedded systems.
Techniques include dynamic voltage scaling, power gating, and energy-efficient
instruction execution.
Solved Question Paper Computer Engineering 4th Sem.
Computer Organization & Architecture