Tricore Architeture Overview

TC1.3.1
Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System
7. Trap System
8. Protection System.
9. Programming model.
10. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 2

TriCore™ combines µC, DSP and RISC

Microcontroller RISC Processor

+ Peripherals + 32-bit Harvard architecture
+ Bit Processing + Super-scalar pipeline
+ Fast interrupt response + C/C++ and RTOS support
+ Fast context switch + Memory Protection
+ Real Time Control + Floating Point Unit

DSP
+ Dual Integer MAC Unit
+ Floating Point MAC Unit
+ DSP Addressing Modes
+ Rounding, Saturation
+ Zero Overhead Loop
TriCore™ Block Diagram

Data Register :
Floating Point Unit
PMI D0-D15 DMI
Program Data
Instruction Address Register :
Memory Control Unit
Integer Execution Unit
A0-A15 Memory
Interface 64 64 Interface
System Register :
Load/Store Unit
PC,PSW,PCXI
(RAM/ (RAM)
Cache)
TriCore Core Special Function
Register

Interrupt
Control Unit 64

Local Memory Bus

64
EBU PMU LFI DMA
External Bus Program Memory Unit Bridge Direct Memory
Unit (Flash) Access
32
Peripheral Bus
Key Features

 32 bit Harvard superscalar architecture.

 Little-endian byte ordering.
 4 GByte address space.
 16 & 32 bit instructions.
 Most instruction executed in 1 cycle.
 Strong Bit handling
 Dual MAC unit & DSP support.
 Zero Overhead Loop.
 Flexible interrupt prioritization scheme.
 Low interrupt latency & fast context switching.
 Single precision floating point unit.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 5

AUDO-Future: TC1767 Block diagram
FPU DMI SPRAM: Scratch-Pad RAM
PMI ICACHE: Instruction cache
DCACHE: Data Cache
16 kB SPRAM TriCore 68 kB LDRAM
LDRAM: Local Data RAM
8 kB ICACHE 64 (TC1.3.1) 128 4 kB DCACHE BROM: Boot ROM
(SW configurable)
(SW configurable) PFlash: Program Flash
CPS DFlash: Data Flash
OVRAM: Overlay SRAM
Local Memory Bus PRAM: Parameter RAM In PCP
PCODE: Code RAM in PCP
LMB: Local Memory Bus
BCU 64 SPB: System Peripheral Bus
M OCDS
PMU JTAG

SMIF
DMA
8 Channels 1.5V / 3.3V / (5V)
2 MB PFLASH MEMCK
64 KB DFLASH LFI Bridge Ext. Supply
M/S
8 KB OVRAM
16 KB BROM MLI0

System Peripheral Bus 5V

Ext. ADC Supply
Interrupt 32
System 8 KB PRAM STM
FPI-Bus Interface

ASC0 ADC0 28
Interrupts

16 Channels
PCP2 SCU (5V max)
Core ADC1
ASC1 16 Channels
4
Ports
16 KB PCODE
FADC (3.3V)
4 diff ch. (3.3V max)
4
GPTA0 SSC0
fFPI
Ext. MultiCAN PLL
Request (64 Buffers)
MSC0 SBCU fCPU
LTC0 (0-31) (LVDS)
Unit SSC1
0 1
AUDO-Max: TC1782 Block diagram
FPU DMI SPRAM: Scratch-Pad RAM
PMI ICACHE: Instruction cache
DCACHE: Data Cache
24 kB SPRAM TriCore 124 kB LDRAM
LDRAM: Local Data RAM
16 kB ICACHE 64 (TC1.3.1) 128 4 kB DCACHE BROM: Boot ROM
(SW configurable)
(SW configurable) PFlash: Program Flash
CPS DFlash: Data Flash
OVRAM: Overlay SRAM
Local Memory Bus PRAM: Parameter RAM In PCP
PCODE: Code RAM in PCP
LMB: Local Memory Bus
BCU 64 SPB: System Peripheral Bus
M OCDS
PMU JTAG

SMIF
DMA
16 Channels 1.3V / 3.3V / (5V)
2.5 MB PFLASH MEMCK
128 KB DFLASH LFI Bridge Ext. Supply
M/S
8 KB OVRAM
16 KB BROM MLI0

System Peripheral Bus 5V

Ext. ADC Supply
Interrupt 32
System 16 KB PRAM STM
FPI-Bus Interface

ASC0 ADC0 28
Interrupts

16 Channels
PCP2 SCU (5V max)
ASC1 Core ADC1
16 Channels
E-Ray 4
(2 Channels)
Ports
32 KB PCODE
FADC (3.3V)
4 diff ch. (3.3V max)
SSC0 4
GPTA0
PLL fE-Ray
Ext. SSC1
MultiCAN E-RAY
Request (128 MO)
MSC0 SBCU
LTC0 (0-31) (LVDS)
Unit SSC2 PLL fCPU
0 1 2
Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System
7. Trap System
8. Protection System.
9. Programming model.
10. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 8

Pipeline : General

 TriCore has 3 pipelines: Integer Pipeline, Load/Store Pipeline

and Loop Pipeline.

Instruction 1
Instruction
Instruction 1
1 MAC MAC
Instruction 2 Execute
Write
Execute
Back
32Bit
Integer
Decode
The
The Issue
Issue Unit
Unit forwards
forwards
Instruction 1
Fetch The Fetch
multiple Unit
Integer
multiple Instruction
Instruction
Execute
Fetches
Instruction
into
1
into the
the
64 bit Integer Pipeline
& multiple
four Instructions
four pipelines(
pipelines( 1-3)in
1-3)
Issue parallel (2-4)
Load/ Load/
32Bit Store Store Instruction Write
2 Load/Store Pipeline
Decode InstructionBack
Execute Instruction 21
Instruction 2
Instruction 3
2
Instruction
Instruction 4
3
Loop Instruction 2
3
1 Loop Pipeline
Cache Loop Write
Buffer Execute Back

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 9

Pipeline : Pipeline Stages

Cycle 1 Cycle 2 Cycle 3 Cycle 4

MAC Execute 1

Integer
MAC Execute 2
Integer Write
Integer Execute
Decode Back
Fetch

Load /
Store
Load / Store Load / Store Write
Decode Execute Back

Loop
Loop Cache Loop Write
Buffer Execute Back
Pipeline : Super-scalar Execution

Integer Load / Store Loop

Pipeline Pipeline Pipeline

Triple Issue Arithmetic Load / Store Loop

Dual Issue Arithmetic Load / Store

Dual Issue Arithmetic Loop

Dual Issue Load / Store Loop

Single Issue Arithmetic

Single Issue Load / Store

Single Issue Jump/Loop

Typical code: ~1.3 Instruction per Cycle (IPC)

Pipeline : Super-scalar Execution Example

lea a7,int_ram ; load effective address

mov.a a15,#9 ; move constant to address register
mov d15,#0 ; move constant to data register
L_1:
add d15,d7 ; integer instruction
ld d7,[a7+] ; load instruction
loop a15,L1 ; loop instruction

Integer mov add add

Load / Store lea mov.a ld ld

Loop loop loop

Pipeline function

 Integer pipeline:
 Integer arithmetic and logic instructions.
 Bit operations.
 Divide and MAC instructions.
 Etc.
 Load /Store pipeline:
 Load / Store instructions.
 Context operations.
 Address arithmetic instructions.
 Etc.
 Loop pipeline:
 Loop instructions.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 18

Floating Point Unit(FPU) - tightly coupled
Coprocessor

Coproc. Pipeline

Coproc. Coproc. Coproc.

Decode Execute Execute

Integer MAC MAC

Register
Decode Execute Execute
Write
Back
Register
Read
Integer
Execute
Integer Pipeline

Passing Instructions and Register Passing result from Coprocessor to

Content to Coprocessor Register
1

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 19

Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System
7. Trap System
8. Protection System.
9. Programming model.
10. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 20

Architectural Registers

A15 (implicit address) D15 (implicit data) PCXI

E14
A14 D14 PSW
A13 D13 PC
E12
A12 D12
A11 (Return Address) D11
E10
A10 (Stack pointer) D10
A9 (Global Address) D9
E8
A8 (Global Address) D8

A7 D7
E6
A6 D6
A5 D5
E4
A4 D4
A3 D3
E2
A2 D2
A1 (Global Address) D1
E0
A0 (Global Address) D0

Address Data System

Core Special Function Registers (CSFR)

General Purpose Registers CPU Interrupt and Trap Control

D0-D15 Data Register ICR Interrupt Control Reg.

A0-A15 Address Register BIV Base Address of Interrupt Vect

BTV Base Address of Trap Vect. Table

System Register

PC Program Counter Memory Protection

PSW Program Status Word DPRx_0..3 Data Segment Protection Regs

PCXI Previous Context Information. CPRX_0..1 Code Segment Protection Regs.

CPMx Code Protection Mode Reg. x

Context Management

FCX Free CSA List Head Pointer Stack management

LCX Free CSA List Limit Pointer ISP Interrupt Stack Pointer
Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System
7. Trap System
8. Protection System.
9. Programming model.
10. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 23

Memory Map : Genaral

 The address space of TriCore is 4 GB.

 It is divided into 16 segments of 256MB.
 The upper 4 bits of an address select the specific segment

32-bit address

31 28 27 0
Segment 28 – bit address within a segment.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 24

Memory Map : Segmant

Segment Description

0xF Internal Peripheral Space,

Peripheral
CSFR, etc.
Non-Cached 0xE LFI view of PMI / DMI

0xD DMI, view of PMI, BROM…

RAM
Cached 0xC PMI (non cached)

0xB Reserved (FPI space).

Non-Cached
0xA Flash, EBU, OVRAM.

0x9 Reserved (FPI space).

FLASH
Cached
0x8 Flash, EBU, OVRAM.

0x7 Reserved (MMU space)

MMU not . .
. .
implemented . .
in TC179x
0x0 Reserved (MMU space)

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 25

Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System
7. Trap System
8. Protection System.
9. Programming model.
10. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 26

Type of Context

 Tricore defines two contexts:

 The upper context (task specific)---automatically saved on call,
interrupt or trap.
 The lower context (for parameter passing)---has to be saved
explicitly with an instruction

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 27

Context Handling

A15 D15
E14
A14 D14
Upper A13 D13
E12
Context A12 D12
A11 (Return Address) D11
E10
A10 (Stack Pointer) D10
PSW A9 (Global Address) D9
E8
PCXI A8 (Global Address) D8

A7 D7
E6
A6 D6
Lower A5 D5
E4
Context A4 D4
A3 D3
E2
A2 D2
Saved PC A1(Global Address) D2
E0
PCXI A0 (Global Address) D0
Address Data
Upper/Lower Context Saving and Restoring

Upper Context Lower Context

CALL
store to context STLCX
Interrupt
save area BISR
Trap
Regular context
switch
restore from RET
RSLCX
context save area RFE

store to an STUCX STLCX

absolute address <address> <address>
Context switch
for task handling
reload to an LDUCX LDLCX
absolute address <address> <address>
Context Save Area Organization
 Context Save areas can hold 1 upper or 1 lower context.

 CSA are aligned on a 16-word boundary.

Lower CSA Data memory Upper CSA
D7 D15
D6 D14
D5 D13
D4
Lower
D12
A7 A15
A6 A14 16 words
A5 A13
A4 A12
Upper
D3 D11
D2 D10
D1 D9
D0 D8
A3 A11
A2
Upper
A10
A11 PSW
PCX (link word) PCX (link word)
16- words boundary
10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 30
CSA Link Registers

 CSAs are linked via their link word in lists:

 FCX : ―Free Context List‖ for unused CSA.
 PCX : ―Previous Context List‖ for used CSA.

 Hardware automatically handles allocation & freeing of CSAs.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 31

Before Saving in CSA

μC CSFR CSA in local Memory

CSA 3 CSA 4 CSA 5

FCX Link to 4 Link to 5 “0”

Free Context List

CSA 2 CSA 1

PCX Link to 1 “0”

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 32

Saving Process in CSA

 Send CSA3.PCX to New FCX.

 Replace CSA3.PCX with PCX.
 Send FCX to PCX.
 Replace FCX with New FCX
3 FCX 4

PCX New FCX

CSA 3
2 1
Link to 4
10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 33
After Saving in CSA

μC CSFR CSA in local Memory

CSA 4 CSA 5

Link to 5 “0”
FCX

Free Context List

CSA 3 CSA 2 CSA 1

PCX Link to 2 Link to 1 “0”

Previous Context List

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 34
Efficient context operations

fast shadowed context

save/restore operation
in 2/4 CPU cycles
Task State Regs
 approx. 2.7 cycles
Upper Upper
 Fast Interrupt/Function Call:
16 Addr.-REGS 16 Data-REGS
 Automatic Upper Context
Lower Lower Save at Call/Interrupt/Trap
 Branch to target address
64 bits 64 bits  Fetch target instruction
 HW- managed linked lists
Context Contextn-1 =>Zero Software overhead
Linked
Save Contextn
Lists
Area Contextn+1

DMI
Context Area: Initialization in cstart.c

int i, k;
int no_of_csas;
int * csa;
unsigned int seg_nr, seg_idx, pcxi_val=0;
_Bool first=true;
for (i=0; i < MAX_NR_OF_CSA_AREAS; i++)
{
/* first calculate nr of CSAs in this area */
no_of_csas = (csa_area_end[i] - csa_area_begin[i]) >> 4;
for (k=0; k < no_of_csas; k++)
{
csa = csa_area_begin[i] + k*16;
/* Store null pointer in last CSA (= very first time!) */
*csa = pcxi_val;
seg_nr = __extru( (int) csa, 28, 4) << 16;
seg_idx = __extru( (int) csa, 6, 16);
pcxi_val = seg_nr | seg_idx;
if (first)
{
first = false;
__mtcr(LCX, pcxi_val);
}
}
__mtcr(FCX, pcxi_val);
}
10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 38
Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System.
7. Trap System.
8. Protection System.
9. Programming model.
10. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 39

Interrupt System Basic
Features Benefits
 Common approach for interrupt and  Ease programming and High flexibility
DMA request processing  Large Number of SRNs
 2 x 255 request nodes (SRN),  Flexible grouping of request into
concurrently supported priority groups
 Dedicated Arbitration Pipeline (ICU)  Short arbitration phase: max 4 cycles
 Zero Software overhead

7 6 5 4 3 2 1 0
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral

SRN SRN SRN SRN SRN SRN

SRC SRC SRC SRC SRC SRC

Arbitration Bus

FPI Bus
TC1797 @ 180 Mhz
• 150 ns interrupt response time Int. Ack.
Interrupt
until execution of first instruction Control
Unit (ICU)
within Interrupt Service Routine Int. Req.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 40

Interrupt Nodes and Service provider

 An interrupt request is serviced

by CPU or PCP, called ―Service
Provider‖
 Interrupt requests are called
―Service Request"
 Each interrupt source is
connected to a Service Request
Node (SRN)
 Interrupt Control Unit (ICU)
arbitrates service requests for
the CPU and administers the
CPU Interrupt Arbitration Bus
Service Request Control Register

xx_SRC

15 14 13 12 11 10 9 8 7 0
SET CLR
SRR SRE TOS res SPRN
R R

Request Local Type of Priority Check Global service if

enable Service for PIPN enable PIPN>CCPN

ICR.IE
SRR SRE TOS 0
xx_SRC.SRPN
Periperals

Service
On-Chip

0 00 =0...255
1
1 01 PICU

Software
SETR=1
Service Request Priority Number(SRPN)

 SRPN indicates the priority of a service request

 Each active source selecting the same Service Provider must
have a unique SRPN value to differentiate its priority
 SRPN is used to select an Interrupt Service Routine (ISR) or
Channel Program (in case of the PCP) to service the request
 ISRs are associated with Service Request Priority Numbers by
an Interrupt Vector Table located in each Service Provider

Priority does not depend on HW

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 43

Arbitration Process and Duration

 Two factors determining the duration of the arbitration process:

 Number of arbitration cycles, N
 Duration of arbitration cycles, d

Arbitration = (N+1) * d +1 FPI clocks

1 or 2 clocks

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 44

Interrupt Response Time

 Example:TC1766@60MHz fast interrupt response time with

arbitration setup for 15 interrupts (ICR.CABCYC = 2).
9 cycles

5 cycles
CPU Task Priority Check ISR

Acknowledge
ICU to CPU
Arbitration

Execute
Decode
Context

to ICU
Fetch
Save

Interrupt Interrupt
Issued Served
Interrupt Vector Table
Interrupt Vector Table
Priority 255 // Interrupt defined w/ PPN = 3
void __interrupt(3) stm_isr()
{
// user code
}
9 // Interrupt defined w/ PPN = 4
8 void __interrupt(4) asc_isr ()
{
7 j gpta_isr // user code
6 }
5 // Interrupt defined w/ PPN = 7
4 j asc_isr void __interrupt(7) gpta_isr()
{
3 j stm_isr
// user code
2 }
1
0
Interrupt Grouping
Interrupt Vector Table
Priority 255 void __interrupt(3) __bisr_(5) isrA()
{
// CCPN = 5, IE = 1
}
void __interrupt(4) __bisr_(5) isrB()
{
9
// CCPN = 5, IE = 1
8 }
7 void __interrupt(5) __bisr_(5) isrC()
{
6 j isrD
// CCPN = 5, IE = 1
5 j isrC }
Priority void __interrupt(6) isrD()
4 j isrB
Group {
3 j isrA
// CCPN = 6, IE = 0
2 }
1
0
Interrupt Routine Entry Point

Interrupt Control Register

31 27 26 24 16 9 8 0
C
ICR 0 ONE
CYC
CARBCYC PPN 0 IE CCPN

OR
Begin Interrupt Vector
31 13 5 0

BIV x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 x x x x 0

Priority 255 8 words Entry Point of Interrupt Service Routine

is calculated by

3 8 words BIV | (ICR.PPN<<5)

2 8 words
1 8 words
0 8 words
Spanning ISRs Across Vector Entries
Interrupt Vector Table
Priority 255 // Interrupt defined w/ PPN = 2
void __interrupt_fast(2) isr()
{
// Interrupt routine located
// directly in the vector table
9
// If code size is > 8 words the
8 ISR may // following PPN(s) could not be
7 span // used
6 several
entries
5 e.g. // user code
4 64 words }

3 (256KByte)

2
BIV
1 8 words
0 8 words
Interrupt System Example(1)

MEMORY

Program (after)
Priority

Program (before)
N Jump ISR RFE
RFE

ISR

0 Program Program

Jump Prio N

IVT
BIV
10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 50
Interrupt System Example(2)

Int. 8

ICR.CCPN 0 0 3 3 8 3 0
ICR.PIPN 0 3 0 8 0 0 0
PCXI.PCPN 0 0 0 0 3 0 0
ICR.IE 1 1 0 1 0 1 1

ISR 8

ISR 3 ISR 3

Main Main
Program Program
10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 51
Interrupt System in TC1797

Total of 205 Service

Request Nodes

PCP Arbitration bus CPU Arbitration bus

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 52
Notes for nest interrupt

 Enabling Interrupt Requests: __enable_, __bisr_()

During the execution of an interrupt service routine or trap service routine, the
system blocks the CPU from taking further interrupt requests. You can
immediately re-enable the system to accept interrupt requests:
__interrupt(vector) __enable_ isr(void)
The compiler generates an enable instruction as first instruction in the routine.
The enable instruction sets the interrupt enable bit (ICR.IE) in the interrupt
control register.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 53

Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System.
7. Trap System.
8. Protection System.
9. Programming model.
10. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 54

Trap : General Concept(1)

 Allows the CPU to service conditions that are so critical that

they must not be postponed e.g. major failure

 Traps events break the normal execution of code much like

interrupts, however a trap doesn’t change the CPU’s priority, so
the CCPN is not changed.

 Trap Service Routines (TSRs) reside in the Trap Vector Table,

separate from the Interrupt Vector Table

 The CPU aborts the instruction in progress when a Trap occurs

and forces execution of the appropriate TSR

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 55

Trap : General Concept(2)

 A trap occurs as a result of:

 non-maskable Interrupt (NMI)
 instruction exception
 illegal access

 Traps are always active

 cannot be disabled by software

 A trap is completely identified by:

 Trap Class Number (TCN)
 Trap Identification Number (TIN)

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 56

Trap Types

See the TC1.3.1 Architecture manual for full details,Several new

traps added in addition to those from TC1796
 Trap Class 0 – MMU - not used on TC1797
 Trap Class 1 – Internal Protection
 Trap Class 2 – Instruction Errors
 Trap Class 3 – Context Management
 Trap Class 4 - System Bus and Peripheral Errors
 Trap Class 5 – Assertion Traps (TRAPV, TRAPSV)
 Trap Class 6 – System Call
 Trap Class 7 - NMI

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 57

Trap Class 1(internal protection)
MPP MEMORY

Read/Write Peripheral Space

access in user 0
Data Protection MPW
Registers Read

Write Data Area

MPR
Code Protection MPX
Registers PRIV

Code Area User Mode 1: mtcr, bisr, cachea.i

User Mode 0: enable / disable

MPN A9 GRWP
A8 Write with
A1 PSW.GW=0
Address 0
A0
access
10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 59
Trap Class 2(Instruction Fetch)

MEM MEMORY

Invalid memory
address
(e.g. write on a
CSFR without mtcr)
ALN

Data Area Data Alignment

Instruction error error

(OPD) (UOPC) IOPC

Code Area
Access

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 60

Trap Class 3(CSA management)
Free CSA
PSW . . . CDE CDC
CSA 1

link FCX
CSA 2
Call depth overflow: CDO
link
Call Depth underflow: CDU
CSA 3
Nesting error: NEST
link LCX

PCX = 0 CSU

FCX = 0 FCU

LCX = FCX FCD

PCXI.UL does not CTYP

match context type:
10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 61
Trap Class 4(System Buss Error)

CAE
PIE
FPU DIE
64 bits 128 bits

PMI DMI

PSE DSE DAE

Bus system

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 62

Trap Class 5,6&7

 Class 5 (Assertion traps) :

– Trap on arithmetic overflow: TRAPV
– Trap on sticky arithmetic overflow: TRAPSV

 Class 6 (System call) :

– SYSCALL

 Class 7 (NMI) :
– NMI Trap. (Watchdog timer error, PLL unlock, etc).

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 63

Trap handling(1)

 When a trap occurs:

1. The return PC is saved in the return address register (A11)
2. trap identifier is generated by hardware:
¬ TIN - loaded into D15
¬ TCN - used to index into trap vector table
- is left-shifted by 5 bits &

- ORed with address in BTV register

»BTV register specifies the base address of trap vector table

»trap entries in trap vector table are fixed

- to generate entry address of the trap handler

¬ Trap with the lowest TIN wins during arbitration

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 64

Trap handling(2)

 When a trap occurs (continued)

:
3. the upper context of the current task is saved

4. register A11 gets the ―return address‖

¬ For synchronous traps, this is the instruction that caused the trap
¬ For asynchronous traps, this is the instruction that was executing
when the trap occurred.

5. the interrupt system is globally disabled

6. the stack pointer is set for using the interrupt stack

7. the Trap Vector Table is accessed to fetch the first instruction

of the TSR
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Trap Vector Table

MEMORY Trap Class

Number
Code

8 Words
7
8 Words
6
8 Words
5
8 Words
4
8 Words
3
No MMU in 8 Words
TC1797 2
8 Words
1
8 Words
BTV 0
Code
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Trap Vector Table Entry

31 7 5 0

BTV 000 0

TCN

3-bit

OR

Trap Vector Table Entry Address

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Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System.
7. Trap System.
8. Protection System.
9. Programming model.
10. Instruction Set.

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Protection System Conception

 Tricore protection system aims at :

 Protect core system functionality.
 Protect application against each other.
 Provide test and debug functionality.

 Tricore protection system is based on:

 Traps.
 Permission levels.
 Memory protection.

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Permission Privilege Level

Program Status Word (PSW)

31 16

C V SV AV SAV res
15 11 10 0

res PRS IO IS GW CDE CDC

IO = "00" User-0

IO = "01" User-1

IO = "10" Super-
visor

permission privilege levels

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Permission level : User-0

Address Space IV
PR Supervisor-only instructions
Segment 15 (MTCR, BISR, MMU instructions,
peripheral cache instructions)
P registers
Segment 14 MP
Segment 13

Segment 12
User-0
Segment 11

Segment 10
User-1

Segment 9

Segment 8 Super-
visor
Segment 7

Segment 6

Segment 5

Segment 4

Segment 3

Segment 2
IV
Segment 1 PR
enable or disable
Segment 0 the interrupt system

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Permission level : User-1

Address Space IV Supervisor-only instructions

PR
Segment 15 (MTCR, BISR, MMU instructions,
peripheral cache instructions)
Segment 14 registers

Segment 13

Segment 12 User-0
Segment 11 ac
ce
ss User-1
Segment 10

Segment 9

Segment 8 Super-
visor
Segment 7

Segment 6

Segment 5

Segment 4

Segment 3

Segment 2

Segment 1
enable or disable
Segment 0 the interrupt system

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Permission level : Supervisor

Address Space Supervisor-only instructions

Segment 15 (MTCR, BISR, MMU instructions,
peripheral cache instructions)
Segment 14 registers

Segment 13

Segment 12 User-0
Segment 11
ac
ce User-1
Segment 10 ss

Segment 9

Segment 8 Super-
visor
Segment 7

Segment 6

Segment 5

Segment 4

Segment 3

Segment 2

Segment 1
enable or disable
Segment 0 the interrupt system

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Memory Protection

 Hardware mechanism that protect memory ranges from

unauthorized :
 data read/write access.
 instruction fetch access.
 An invalid access generates a trap.
 Memory protection can be globally disabled.

Note: Memory protection system can also be used for debugging.

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Memory Protection System

 The user selects which set of register is active:

PSW:

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Memory Protection Register Set

 Each set of register defined

several data/code ranges.
 Each range is defined by :
 An upper boundary register.
 An lower boundary register.
 A permission mode.

 Permission mode:
 Data Range: Read enable, write
enable (or both)
 Code Range: Instruction fetch
enable.

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Memory Protection Example

Upper bound 3
Data protection
register sets Mode 3
Range 3
Lower bound 3
Set 1
Upper bound 2
Set 0
Mode 2
Range 1
Lower bound 2
Range 1+2
Upper bound 1
Code protection
register sets Mode 1
Range 1
Lower bound 1
Set 1
Upper bound 0
Set 0
Mode 0 Range 0

Lower bound 0

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Example for Data and Code memory Protection

Libraries Globals
read/write

Read only globals

“Owned” globals
for current task

Read only globals

Private code
for current task Static data and
static space
for current task

Code range table Data range table

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Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Interrupt System
7. Trap System
8. Protection System.
9. Programming model.
10. Instruction Set.

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Data Types

 The TriCore instruction set supports operation on:

 Bit
 Bit String
 Byte / Half Word / Word / Double Word (signed, unsigned).
 Signed Fraction
 Address
 Signed / Unsigned integer
 IEEE-754 Single Precision Floating point Numbers

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Data Type Modifier

mov.a a0,d5 ; move to address register

adds.u d5,d5,d4 ; unsigned saturated addition
add.b d0,d2,d4 ; add byte (packed arithmetic)
add.bu d0,d2,d4 ; add unsigned byte (packed arith.)
ld.h d0,[a4+] ; load half—word (sign—extended)
add.hu d0,d2,d3 ; add unsigned half-word
ld.w d0,[a2+] ; load word
lt.wu d11,d3,d1 ; compare (less than) unsigned word
ld.d e2,word_var ; load double word
add.f d0,d2,d3 ; add floating point
madd.q d2,d1,d4,d5uu,#1 ; multiply/add Q-format
; D4/D5 upper half is used
jz.t d0:3,LABEL ; jump if bit 3 is equal to zero
Instruction Format

; TriCore assembler
ADDR CODE ASSEMBLER
00000000 C600 mov16 d15,#0 ; move constant 0 to d15
00000002 C050F27F0 lea a15,#999 ; loop count value
00000006 947F st16.w [a7+],d15 ; store value
00000008 C21F add16 d15,#1 ; value + 1
0000000A A4rFrrrrr st.w var_3,d15 ; store word
0000000E 5667 or16 d7,d6 ; bitwise OR
Absolute Addressing

Segment number Segment offset

4 14
18-bit offset

4 14 14
00000000000000 32-bit address

; Example
; Variable in the first 16K
~ ~
; of a 256 MByte segment
ld.w d3,near_addr

16 KB
Segment base ~ ~
address
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Addressing via long offset

16-bit offset

+ Base address

32-bit address

~ ~
; Example
; load word from a3 + 0x1000
; store word at a3 - 10000
movh.a a3,#@his(far_addr) Base address
lea a3,[a3]@los(far_addr) 64 KB
ld.w d3,[a3]0x1000
st.w [a3]-10000,d3

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Addressing via short offset

10-bit offset

+ Base address

32-bit address

~ ~
; Example 1 a3=0x80000100
ld.h d3,[a3]10 ; adr=0x8000010A
ld.b d3,[a3]-3 ; adr=0x800000FD

; Example 2 a3=0x80000100 Base address

1 KB
ld.w d3,[a3+]10 ; a3=0x8000010A
ld.b d3,[-a3]8 ; a3=0x80000102
ld.h d3,[+a3]-2 ; a3=0x80000100

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Addressing Modes

ld.w d0,var ; absolute addressing

lea a3,var_addr ; load absolute 18-bit address to a3
movh.a a2,#0xC000 ; move 16-bits into high part of a2
lea a2,[a2]0x4000 ; a2 = [a2] + sign-extended offset
ld.w d0,[a2]+0x48 ; load word at 0xC0004048
ld.w d0,[a2]-0x10 ; load word at 0xC0003FF0
ld.w d0,[+a2]4 ; [a2] = 0xC0004004
; load word at 0xC0004004
ld.w d0,[+a2]6 ; load word at 0xC000400A
; [a2] = 0xC000400A
ld.b d0,[a2-]1 ; load byte at 0xC000400A
; [a2] = 0xC00040009
Circular Addressing

length index A_odd

base A_even

Effective Address = Base + Index tmp = index + offset10

if (tmp<0)
index = tmp + length
Example: ld.w d0, [a2/a3+c]2 elseif (tmp ≥ length)
index= tmp – length
else
index=tmp

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Bit Reverse Addressing

modifier index A_odd

base A_even

effective_address= base + index

index = reverse [reverse(index) + reverse (modifier)]

Example: ld.w d0, [a2/a3+r]

X0 X0
X1 X4
X2 X2 Modifier = Buffer size (byte) / 2.
X3 X6 Effective Address = Base + Index
X4 X1
X5 X5
X6 X3
X7 X7

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Contents

1. Overview and Key features.

2. Pipelines.
3. Core Registers.
4. Memory Map.
5. Context management.
6. Protection System.
7. Programming model.
8. Instruction Set.

10.02.2010 Copyright © Infineon Technologies 2010. All rights reserved. Page 89

Instruction Set
ABS BSPLIT EQZ.A JZ MADDSU.H MSUBRS.Q QSEED.F STLCX
ABS.B CACHEA.I EXTR JZ.A MADDSUM.H MSUBS RET STUCX
ABS.H CACHEA.W EXTR.U JZ.T MADDSUMS.H MSUBS.H RFE SUB
ABSDIF CACHEA.WI FTOI LD.A MADDSUR.H MSUBS.Q RFM SUB.A
ABSDIF.B CADD FTOQ31 LD.B MADDSURS.H MSUBS.U RSLCX SUB.B
ABSDIF.H CADDN FTOU LD.BU MADDSUS.H MTCR RSTV SUB.F
ABSDIFS CALL GE LD.D MAX MUL RSUB SUB.H
ABSDIFS.H CALLA GE.A LD.DA MAX.B MUL.F RSUBS SUBC
ABSS CALLI GE.U LD.H MAX.BU MUL.H RSUBS.U SUBS
ABSS.H CLO IMASK LD.HU MAX.H MUL.Q SAT.B SUBS.H
ADD CLO.H INS.T LD.Q MAX.HU MUL.U SAT.BU SUBS.HU
ADD.A CLS INSERT LD.W MAX.U MULM.H SAT.H SUBS.U
ADD.B CLS.H INSN.T LDLCX MFCR MULR.H SAT.HU SUBX
ADD.F CLZ ISYNC LDMST MIN MULR.Q SEL SVLCX
ADD.H CLZ.H ITOF LDUCX MIN.B MULS SELN SWAP.W
ADDC CMOV IXMAX LEA MIN.BU MULS.U SH SYSCALL
ADDI CMOVN IXMAX.U LOOP MIN.H NAND SH.AND.T TLBDEMAP
ADDIH CMP.F IXMIN LOOPU MIN.HU NAND.T SH.ANDN.T TLBFLUSH.A
ADDIH.A CSUB IXMIN.U LT MIN.U NE SH.EQ TLBFLUSH.B
ADDS CSUBN J LT.A MOV NE.A SH.GE TLBMAP
ADDS.H DEBUG JA LT.B MOV.A NEZ.A SH.GE.U TLBPROBE.A
ADDS.HU DEXTR JEQ LT.BU MOV.AA NOP SH.H TLBPROBE.I
ADDS.U DISABLE JEQ.A LT.H MOV.D NOR SH.LT TRAPSV
ADDSC.A DIV.F JGE LT.HU MOV.U NOR.T SH.LT.U TRAPV
ADDSC.AT DSYNC JGE.U LT.U MOVH NOT SH.NAND.T UNPACK
ADDX DVADJ JGEZ LT.W MOVH.A OR SH.NE UPDFL
AND DVINIT JGTZ LT.WU MSUB OR.AND.T SH.NOR.T UTOF
AND.AND.T DVINIT.B JI MADD MSUB.F OR.ANDN.T SH.OR.T XNOR
AND.ANDN.T DVINIT.BU JL MADD.F MSUB.H OR.EQ SH.ORN.T XNOR.T
AND.EQ DVINIT.H JLA MADD.H MSUB.Q OR.GE SH.XNOR.T XOR
AND.GE DVINIT.HU JLEZ MADD.Q MSUB.U OR.GE.U SH.XOR.T XOR.EQ
AND.GE.U DVINIT.U JLI MADD.U MSUBAD.H OR.LT SHA XOR.GE
AND.LT DVSTEP JLT MADDM.H MSUBADM.H OR.LT.U SHA.H XOR.GE.U
AND.LT.U DVSTEP.U JLT.U MADDMS.H MSUBADMS.H OR.NE SHAS XOR.LT
AND.NE ENABLE JLTZ MADDR.H MSUBADR.H OR.NOR.T ST.A XOR.LT.U
AND.NOR.T EQ JNE MADDR.Q MSUBADRS.H OR.OR.T ST.B XOR.NE
AND.OR.T EQ.A JNE.A MADDRS.H MSUBADS.H OR.T ST.D XOR.T
AND.T EQ.B JNED MADDRS.Q MSUBM.H ORN ST.DA
ANDN EQ.H JNEI MADDS MSUBMS.H ORN.T ST.H
ANDN.T EQ.W JNZ MADDS.H MSUBR.H PACK ST.Q
BISR EQANY.B JNZ.A MADDS.Q MSUBR.Q PARITY ST.T
BMERGE EQANY.H JNZ.T MADDS.U MSUBRS.H Q31TOF ST.W
Instruction Set Overview(1)

 Most instructions executed in 1 cycle

 Branch instructions in 1, 2 or 3 cycles (using branch prediction)
 16-bit and 32-bit instructions for reduced code size
 Multiply and Accumulate instructions (MAC):
 dual 16 x 16, 16 x 32, 32 x 32
 Instruction types:
 arithmetic, address arithmetic, comparison, address comparison,
logical, MAC, shift, coprocessor, bit logical, branch, bit field,
load/store, packed data, system instructions & MMU specific
instructions (Not implemented in TC1797)—about300 instruction
 Addressing modes:
 Absolute, base+offset, pre-increment, pro-increment, circular and
bit-reverse (for DSP)
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