ChipDesignFlow

ByVenkateshPrasad
05/29/09 1

LAYOUT
The transformation of circuit description into a geometric description Layout is a process of specifying the physical placement of and interconnections between all of the devices in a circuit Layout is used to generate all of the mask layers used for chip fabrication Layout for Analog circuits:
Few transistors Few transistors are minimum size Transistors are sized to minimized offsets Focusing to minimize individual effects

Layout for Digital circuits :

Number of transistors are more Transistors of minimum size Transistors are sized for minimize delays Interconnection focus between modules
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IC Flow
An IC consists of :
Digital Blocks
Like any Adder, Multiplier

Analog Blocks
Like PLL, Filters, ADC

Techniques to implement the flow

Full Custom
The designer creates layout masks by hand Long design cycle Fast & Power efficient design

Semi Custom
Short design cycle Not so good power efficient design w.r.t. to Full-custom
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Full-Custom Flow

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Analog Flow

Automated Analog Flow

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Full-Custom Flow
Design Flow
System level design
create high level behavioural representation of design using VHDL, Verilog or System-C.

Logic design & verification

Translate system level description into transistors
schematic representation

Circuit design
Transistor sizes Performance evaluation with complex models (H-Spice)

Layout
Translate circuit into layout
DRC rules should be taken care Need not be necessary that layout is too exact to schematic

Verification
Compare netlists

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IC Flow
Full Custom layout supports 3 different flavours for automation and migration of technologies Data-path layout Analog Cell All three types are driven by a schematic based design style versus a language based design style.

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IC Flow
Data-path full custom layout
Area limitation Specific application Example : Memory design
need repeated complex structures like adders, multipliers etc. Memory layout design depends on the memory cell layout design Cell efficiency Need good layout designers to develop the smallest cell size Interface blocks must match the pitch of memory cell and provide the functionality Might be iterate so many times with circuit designer

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IC Flow
Analog full custom layout
It is the place where a designer should understand the complete phenomena that happens within the device, physical connections, implants and need to have a good knowledge of semiconductor physics Margins of errors and tolerance is very less Highly process dependent , so migration of technology is not possible Device Matching
Inter-digitized common centroid

Placement is tightly controlled (use schematic driven constraints placement) Routing is crucial
Connection Identifications width of metals are specified by the schematic current, electro-migration, R, C requirements

Verification
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IC Flow
Cell Layout
Cell full custom layout applies to the cells that are part of a family of building blocks, which have common abutment rules, performance characteristics, functionality In general , use of Metal1 and Metal2 for cell layout Compatibility to intended design flow : like all pins of standard cells on a common pitch for easy and fast connection Abutment includes consideration for power routing, substrate and cell connections Examples : Standard cell & Pad libraries

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IC Flow
Digital Circuit Implementation Flow
Custom Flow Semi-custom Flow
Cell Based

Array Based

Standard Cells Compiled Cells Macro Cells Pre-diffused GATE Arrays Pre-wired GATE Arrays

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Device Matching

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Device Matching Overview

Two devices with the same physical layout never have quite the same electrical properties. Variations between devices are called mismatches. Mismatches may have large impacts on certain circuit parameters, for example common mode rejection ratio (CMRR). By default, simulators such as SPICE do not model mismatches. designer must deliberately insert mismatches to see their effects. The

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Types of Mismatches
Mismatches may be either random or systematic or combination of both.
Suppose two matched devices have parameters P1 and P2 Let the mismatch between the devices equal to = > P = P2 - P1 For a sample units, measure this : P Compute sample mean m(P) and standard deviation s(P ) and cell connections m(P) is a measure of systematic mismatch s(P) is measure of random mismatch

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Random Mismatches
Random Mismatches are usually due to process variation
These process variations are usually manifestations of statistical variation, for ex : scattering of dopant atoms Random mismatches cannot be eliminated , but they can be reduced by increasing device dimensions In a rectangular device with active dimensions W by L , an areal mismatch can be modelled as: Precision matching requires large devices
P = k
P

WL

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Systematic Mismatches
Systematic Mismatches may arise from imperfect balancing in a circuit
Ex: Differential pair mismatch generates an offset voltage Usually, the circuit can be redesigned to minimize or even to completely eliminate systematic offset

Systematic Mismatches also arises from gradients

Certain physical parameters may vary gradually across an IC.
Temperature Pressure Oxide thickness

Gradients can produce large effects

A 1 degree C change in temperature produces a -2mV in VBE which eqautes to 8% variation in IC

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Layout Rules of Device Matching

Devices on the same die match well (precision)
$(R) / R =~ 0.1%, $(C) / C =~ 0.1%

For circuit characteristics , that depends on ratio of component values,

precise matching = accurate characteristics

To improve device matching , use devices with

Unit Elements Large active area Same orientation Compact Layout Minimum spacing Dummy Segments Common Centroid geometries
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Centroid Matching Technique

It cancel linear gradients Require for moderate matching Analyzing Gradients : Assuming Linearity :

The gradient is constant over the area Electrical parameters depends linearly upon physical parameters The magnitude of the mismatch equals the product of distance between the centroids and the magnitude of the gradient along the axis of separation Therefore , we can reduce the impact of the mismatch by reducing the separation of the centroids

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Centroid Matching Technique

Rules for common centroids technique :
Coincidence Symmetry Dispersion Compactness

How to find a Centroid ( assuming linearity)

If a geometric figure has an axis of symmetry, then the centroid lies on it If a geometric figure has two or more axis of symmetry , then the centroid must lie at their intersection

Centroid

Centroid

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The Centroid of an Array

The centroid of an array can be computed from the centroids of its segments
If all of the segments of the array are of equal size, then the location of centroid of the array is the average of the centroids of the segments The centroid of an array does not have to fall within the active area of any of its segments Theoretically, A common centroid array should entirely cancel systematic mismatches due to gradients . Practically, it does not happen because of assumptions Two properly constructed array could have same centroid Virtually, all precisely matched components in integrated circuits use common centroids

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Inter-digitation Matching Technique

The simplest sort of common centroid array consists of a series of devices arrayed in one dimension
One dimensional common-centroid arrays are ideal for long, thin devices, such as resistors Since the segments of the matched devices are slipped between one another to form the array, the process is often called inter-digitation

A B B A

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Inter digitation Matching Technique

Certain arrays precisely align the centroids of the matched devices ( A, C). These provide superior matching Other arrays only approximately align the centroids. These provide inferior matching. (B)
C C o m m o n aA x x i is s o f s y m m e t r y o f s y m m e t r y o f d e v ic e A o m m o n a x is o f s y m m e t r y A x is o f s y m m o f d e v ic e B e t r y

B ( A

B )

B ( B

A )

B ( C )

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Some Other Techniques

Identical shape & size (Unit Elements)
Resistor Reference Transistor Capacitor

Good

Bad

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Some Other Techniques

Minimum Distance Place devices as close as possible

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Some Other Techniques

Cross Coupled common-centroid

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Some Other Techniques

Same Orientation Eliminates mismatches arising from anisotropic substrate, anisotropic process steps, package induced stress

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Some Other Techniques

Dummy Devices
Place dummy devices at the end of array devices Protects from processing non-uniformity (etch-rate)

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PDK

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What is PDK
PDK : Process Design Kit A Process design kit (PDK) is a collection of verified process models and process data in the appropriate technology file formats (analog/mixed signal library), which are designed to work with EDA IC tools and can be used to generate analog/mixed signal IC. It supports for fast and accurate silicon IC design. The volume of information in a PDK can be huge and the presentation inconsistent from foundry to foundry. A PDK has data files which includes schematic symbols, SPICE models, Layout Technology File, PCELLS, DRC rule-file, LVS rule-file, Extract rule-file and scripts that run EDA tools to automate the generation and verification of design data.
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What is PDK
Foundry document section describe the PDK documents, revision and dates while the EDA section covers the tools, vendors and release dates supported. The device section summarize the symbols, spice models, attributes, parametrized cells and reports the verification of each device.

PDK changes for each technology : 180nm, 130nm, 90nm, 65nm etc. PDK primarily is used to focus on analog/mixed signal market. Advantage of PDK
Design Productivity : IC designers can start design immediately and use entire design flow by using verified data sets. Design Quality : Use of foundry guaranteed data ensures manufacturing success. Profitability : Reduces design cycle and a number of costly reworks. Customer can focus on tape-outs instead of supporting design kits.
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What is PDK
It contains information specific to each design task and to specific design tools. Example : Chartered PDK data maps to the Cadence Virtuoso Platform

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PDK support Custom Flow

Process design kits that support a full custom design flow from schematic entry to final layout verification.

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PDK Support Custom Flow

Schematic symbols define available devices and their properties (device type , pins, sizes etc.) SPICE models are used for SPICE simulation Layout Technology File defines layout environments, layers to be used with attributes of layers and devices to be extracted. PCELLS are cell layouts, generated automatically, or interactively based on parameter input. PCELLS are written in scripting language e.g. LISA. DRC rule-file is used for design rule check interactively at layout or in batch mode for tape-out LVS rule-file is used for interactive LVS check at cell layout or in batch mode for tape-out
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