SWAMI KESHVANAND INSTITUTE OF TECHNOLOGY,

MANAGEMENT& GRAMOTHAN, JAIPUR

ECL-16

LABORATORY MANUAL

Subject Name: VLSI Design Lab

Subject Code: 7EC4-21

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VLSI DESIGN LAB

Table of Content

S.NO. CONTENTS PAGE NO.

1 Vision Mission and Quality Policy of SKIT 3

2 Vision Mission of ECE Department 4

3 Program Educational Objective 4

4 Program Outcome 5

5 Program Specific Outcome 6

6 Course Outcome, Mapping with CO’s/PSO’s 7

7 RTU Syllabus 8

8 List of Experiments 9
Beyond Curriculum Experiments and mapping with POs
9 10
and PSOs
10 Lab Ethics 11

11 Safety Measures 12
Step1 Write the VHDL/Verilog code using VHDL software
for following experiment and simulate them. Step 2. Burn
PART-A 14
the Written code in Xilinx Board and test the output with
real input signal.
Design and simulate all the logic gates with 2 inputs using
Exp:1 30
VHDL.
Design and simulate 2-to-4 decoder, 3-to-8 encoder and
Exp:2 36
8X1 multiplexer using VHDL.
Design and simulate half adder and full adder using VHDL
Exp:3 46
(data flow method.
Exp:4
Design and simulate D, T and J-K flip flop using VHDL. 52
Exp:5 Design a 4bit binary Asynchronous and synchronous
counter. Obtain its number of gates, area, and speed and 62
power dissipation.
Exp:6 Design a 4- bit Serial in-serial out shift register. Obtain its 76

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number of gates, area, and speed and power dissipation.

Design and simulate following experiment using SYMICA

PART-B 84
DE software.
Design and simulate all the logic gates (NOT, NAND and
Exp:7 90
NOR) with 2 inputs in CMOS Technology.
Design and simulate Y = AB (C+D), Y = A+B(C+D) and
Exp:8 100
4X1 multiplexer using CMOS Technology.
Exp:9 Design and simulate half adder and full adder using CMOS
108
Technology.
Exp:10 Design and simulate SR flip flop using CMOS Technology.
116
Exp.11 Design and Simulate any DRAM cell. 122
B1 Design and simulate 16*1 mux using different modeling
126
styles in VHDL
B2 Design and simulate SR flip-flop using VHDL.
130

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Vision Mission & Quality Policy of SKIT

Vision
To promote higher learning in advanced technology and industrial research to make our
country a global player.

Mission
To promote quality education, training and research in the field of Engineering by
establishing effective interface with industry and to encourage faculty to undertake
industry sponsored projects for students.

Quality Policy
We are committed to ‘achievement of quality’ as an integral part of our institutional
policy by continuous self-evaluation and striving to improve ourselves.

Institute would pursue quality in

 All its endeavours like admissions, teaching- learning processes, examinations, extra
and co-curricular activities, industry institution interaction, research & development,
continuing education, and consultancy.

 Functional areas like teaching departments, Training & Placement Cell, library,
administrative office, accounts office, hostels, canteen, security services, transport,
maintenance section and all other services.”

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Vision Mission of Department

Vision
To evolve the department as a center of excellence in the field of Electronics &
Communication Engineering for enriched education, higher learning, research and
development.

Mission
To empower students by imparting quality education in Electronics and Communication
Engineering for better employability and preparing them to be competent in dealing with
industrial and societal challenges.

PROGRAM EDUCATIONAL OBJECTIVES

Graduates from the Electronics and Communication Engineering Program are

expected to attain or achieve the following Program Educational Objectives within a few
years of graduation:

I. The graduates will be able to pursue their career successfully in the field of
Electronics & Communication Engineering and advance in their profession.
II. The graduates will be able to excel in pursuing higher education and life-long
learning.
III. Graduates will be able to hold high ethical standards and work effectively in
multidisciplinary teams with strong management and team work skills.

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PROGRAM OUTCOMES

After the completion of the program, engineering graduates will be able to:

1. Engineering Knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
2. Problem Analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified
needs with appropriate consideration for the public health and safety, and the
cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge
and research methods including design of experiments, analysis and interpretation
of data, and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to
complex engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities
with the engineering community and with society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of
the engineering and management principles and apply these to one’s own work, as
a member and leader in a team, to manage projects and in multidisciplinary
environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability
to engage in independent and life-long learning in the broadest context of
technological change.

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PROGRAM SPECIFIC OUTCOMES (PSOs)

After the completion of the program, engineering graduates will be able to:

1. Understand principles and applications of electronic components, circuits and

devices.
2. Develop proficiency in Electronics and Communication Engineering to enhance
employability skills.

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COURSE OUTCOMES
After successful completion of this course, students will be able to:

C7EC4-21.1: Understand the physical design process of Digital Integrated Circuits.

C7EC4-21.2: Describe principal parts in programmable circuits and procedure for circuit
designs.
C7EC4-21.3: Demonstrate the ability to use various EDA tools for digital system design
C7EC4-21.4: Implement various combinational and sequential circuits using VHDL on
FPGA.
C7EC4-21.5: Implement schematic and layout of various digital CMOS logic circuits
using EDA tools.

Mapping of COs with POs/ PSOs:-

POs→
COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
↓

2 3 1 2 2 - - - - 3 - 3 3 2
C7EC4-21.1

2 3 2 2 2 - - - - 3 - 3 3 2
C7EC4-21.2

2 3 2 3 3 - - - - 3 - 3 3 2
C7EC4-21.3

2 3 2 3 3 - - - - 3 - 3 3 2
C7EC4-21.4

2 3 2 3 3 - - - - 3 - 3 3 2
C7EC4-21.5

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RTU Syllabus
RAJASTHAN TECHNICAL UNIVERSITY, KOTA
Scheme & Syllabus
IV Year- VII & VIII Semester: B. Tech. (Electronics & Communication Engineering)
7EC4-21: VLSI Design Lab
Credit: Max. Marks: 100 (IA:60, ETE:40) 0L+0T+4P
SN Contents
1 Introduction: Objective, scope and outcome of the course.
Step1 Write the VHDL/Verilog code using VHDL software for following
experiment and simulate them.
PART-A
Step 2. Burn the Written code in Xilling Board and test the output with
real input signal
Design and simulate all the logic gates with 2 inputs using
1
VHDL/Verilog.
Design and simulate 2-to-4 decoder,3-to-8 encoder and 8X1 multiplexer
2
using VHDL/Verilog.
Design and simulate half adder and full adder using VHDL (data flow
3
method)/Verilog.
4 Design and simulate D, T and J-K flip flop using VHDL/Verilog.
Design a 4bit binary Asynchronous and synchronous counter. Obtain its
5
number of gates, area, and speed and power dissipation.
Design a 4- bit Serial in-serial out shift register. Obtain its number of
6
gates, area, and speed and power dissipation.
Step-1 Design and simulate following experiment using ECAD software
Viz. Mentor graphics, Orcade Pspice, Cadence etc.
PART-B Step-2 Draw the layout (without any DRC error) of the schematic obtain
in step 1 and obtain post layout simulation using appropriate ECAD
software.
Design and simulate all the logic gates (NOT, NAND and NOR) with 2
7
inputs in CMOS Technology.
Design and simulate Y = AB (C+D), Y = A+B(C+D) and 4X1 multiplexer
8
using CMOS Technology.
9 Design and simulate half adder and full adder using CMOS Technology.
10 Design and simulate SR flip flop using CMOS Technology.
11 Design and Simulate any DRAM cell.

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LIST OF EXPERIMENTS
Step1 Write the VHDL/Verilog code using VHDL software for following
experiment and simulate them.
PART-A
Step 2. Burn the Written code in Xilinx Board and test the output with
real input signal
EXP-1 Design and simulate all the logic gates with 2 inputs using VHDL.
Design and simulate 2-to-4 decoder, 3-to-8 encoder and 8X1 multiplexer
EXP-2
using VHDL.
Design and simulate half adder and full adder using VHDL (data flow
EXP-3
method).
EXP-4 Design and simulate D, T and J-K flip flop using VHDL.
Design a 4bit binary Asynchronous and synchronous counter. Obtain its
EXP-5
number of gates, area, and speed and power dissipation.
Design a 4- bit Serial in-serial out shift register. Obtain its number of
EXP-6
gates, area, and speed and power dissipation.
PART-B Design and simulate following experiment using SYMICA DE Software.
Design and simulate all the logic gates (NOT, NAND and NOR) with 2
EXP-7
inputs in CMOS Technology.
Design and simulate Y = AB (C+D), Y = A+B(C+D) and 4X1 multiplexer
EXP-8
using CMOS Technology.
EXP-9 Design and simulate half adder and full adder using CMOS Technology.
EXP-10 Design and simulate SR flip flop using CMOS Technology.
EXP-11 Design and Simulate any DRAM cell.
B1 Design and simulate 16*1 mux using different modeling styles in VHDL.
B2 Design and simulate S-R Flip flop using VHDL

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Beyond Curriculum Experiments and mapping with Pos and PSOs

Beyond Curriculum Experiments:

1. Design and simulate 16*1 mux using different modeling styles in VHDL
2. Design and simulate S-R Flip flop using VHDL

Mapping of Beyond Curriculum Topics

Beyond
Topics PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

B1 2 3 3 3 3 - - - - 3 - 3 3 2

B2 2 3 3 3 3 - - - - 3 - 3 3 2

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LAB ETHICS
DO’S

1. Student should get the record of previous experiment checked before starting
the new experiment.
2. Read the manual carefully before starting the experiment.
3. Before starting the experiment, get circuit diagram checked by the teacher.
4. Before switching on the power supply, get the circuit connections checked.
5. Get your readings checked by the teacher.
6. Apparatus must be handled carefully.
7. Maintain strict discipline.
8. Keep your mobile phone switched off or in vibration mode.
9. Students should get the experiment allotted for next turn, before leaving the
lab.

DON’TS

1. Do not touch or attempt to touch the mains power supply wire with bare
hands.
2. Do not overcrowd the tables.
3. Do not tamper with equipments.
4. Do not leave the lab without permission from the teacher.

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Safety Measures of Lab

1. Antivirus software is installed for protection against viruses and malwares.
2. External storage devices are not allowed to use in lab.
3. At all times follow the right procedures while starting and shutting down the
computer therefore abrupt switching on and off the computer should be avoided
since this can lead to damaging the computer.
4. Any repairs to the computer should be done by someone who has knowledge
regarding computer repairs.

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PART-A

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INTRODUCTION OF XILINX ISE TOOL

ISE Design Flow Overview:

Fig. 1: Block diagram of ISE Design Flow

Xilinx ISE (Integrated Software Environment) is a software tool produced by Xilinx for
synthesis and analysis of HDL designs, enabling the developer to synthesize (“compile”)
their designs, perform timing analysis, examine RTL diagrams, simulate a design and
configure the target device with the programmer.

STEP 1: Starting the ISE Software

To start the ISE software, double-click the ISE Project Navigator icon on your desktop, or
select
Start > All Programs > Xilinx ISE Design Suite > ISE Design Tools > Project
Navigator.

Fig. 2: Project Navigator Desktop Icon

STEP 2: Creating a New Project
To create a new project using the New Project Wizard, do the following:
1. From Project Navigator, select File > New Project.
The New Project Wizard appears.

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Fig. 3: New Project Wizard—Create New Project Page

2. In the Location field, browse to c:\xilinx_tutorial or to the directory in which

you installed the project.
3. In the Name field, enter wtut_vhdor wtut_ver.
4. Verify that HDL is selected as the Top-Level Source Type, and click Next.
STEP 3: The New Project Wizard—Device Properties page appears.

Fig. 4: New Project Wizard—Device Properties Page

Select the following values in the New Project Wizard—Device Properties page:
• Product Category: All

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• Family: Spartan3A and Spartan3AN

• Device: XC3S700A
• Package: FG484
• Speed: -4
• Synthesis Tool: XST (VHDL/Verilog)
• Simulator: ISim (VHDL/Verilog)
• Preferred Language: VHDL or Verilog depending on preference. This will
determine the default language for all processes that generate HDL files.
Other properties can be left at their default values.
Click Next, then Finish to complete the project creation.
STEP 4: Creating an HDL-Based Module
Next you will create a module from HDL code. With the ISE software, you can easily
create modules from HDL code using the ISE Text Editor. The HDL code is then
connected to your top-level HDL design through instantiation and is compiled with the
rest of the design.
STEP 5: Using the New Source Wizard and ISE Text Editor
In this section, you create a file using the New Source wizard, specifying the name and
ports of the component. The resulting HDL file is then modified in the ISE Text Editor.
To create the source file, do the following:
1. Select Project > New Source.
The New Source Wizard opens in which you specify the type of source you want to
create.
2. In the Select Source Type page, select VHDL Module or Verilog Module.
3. In the File Name field, enter debounce.

Fig. 5: New Source Wizard—Select Source Type Page

4. Click Next.
5. In the Define Module page, enter two input ports named sig_in and clk and an output

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port named sig_out for the debounce component as follows:

a. In the first three Port Name fields, enter sig_in, clkand sig_out.
b. Set the Direction field to input for sig_in and clk and to output for sig_out.
c. Leave the Bus designation boxes unchecked.

Fig. 6: New Source Wizard—Define Module Page

6. Click Next to view a description of the module.

7. Click Finish to open the empty HDL file in the ISE Text Editor.
Following is an example VHDL file.

Fig. 7: VHDL File in ISE Text Editor

STEP 6: Start to write your VHDL code after begin of architecture.

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IC design methodology:
Integrated Circuits (ICs) may be classified in many ways:
Digital, Analog, and Mixed Signal - Technology
Standard IC or Application Specific IC (ASIC) - Commercial
Full Custom, Semi Custom (standard cell), and Gate Array (FPGA) –Design Technique
IC Design Process consists of
Circuit design and Logic design (Front End)
Physical design (Layout –Back End)

Fig. 7: Typical Design flow HDL

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We can use a Hardware Description Language (HDL), such as VHDL or Verilog, for our
top-level or lower-level design files. HDL files describe the behavior and structure of
system and circuit designs. Using HDLs we can:

 Use a synthesis engine to translate our design to gates

Synthesis decreases design time by eliminating the need to define every gate. In addition,
the synthesis tool can apply automation, such as machine encoding styles or automatic
I/O insertion during optimization, resulting in greater efficiency.
 Run functional simulation early in the design cycle
we can verify your design functionality early in the flow by simulating the HDL
description. Testing your design at the Register Transfer Level (RTL) or gate level
before the design is implemented allows you to make changes early in the design
process.
 Retarget our code to different architectures

We can use the same HDL design for new architectures with a minimum of recoding.

VHDL (Very High Speed IC Hardware Description language)

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description
Language.
The other widely used hardware description language is Verilog.
The highest level of abstraction is the behavioral level that describes a system in terms of
what it does (or how it behaves) rather than in terms of its components and
interconnection between them. A behavioral description specifies the
relationship between the input and output signals. The behavioral level can be further
divided into two kinds of styles:
Data flow and Algorithmic.
The Structural level, on the other hand, describes a system as a collection of gates and
components that are interconnected to perform a desired function. A structural description
could be compared to a schematic of interconnected logic gates. It is a representation that
is usually closer to the physical realization of a system.

Summary of all steps for implementing the design on FPGA Trainer kit:-Now right
click on the device and click “Program….”.And before doing this ensure all
connections and setting on the board are correct. JTAG is plugged, power supply to the
board is on and jumper setting and DIP switch setting on the board is correct.
As the programming completes “Program Successful” message appears in the end in
blue.
If “Program Failed” in red appears then check the hardware settings and all other
connections and reprogram the device.
Similarly any other design can be implemented using the FPGA Trainer Kits.

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Fig. 8: Summary of FPGA Implementation steps

Pin Description of Various FPGAs for writing any UCF/XDC file for
Implementation of any design on FPGA

S. FPGA Name
No.
(Pin Nexys 4 Zybo Board Spartan – 6 Spartan – 3 Spartan – 2
No.) DDR Kit (Zynq Series) (XC6SLX16- (XC3S400-
(Artix-7) 2FT256C) 4PQ208) XC2S30 XC2S15
PQ208 TQ144
(ST103) (ST104)

CLK E3 L16 H4 (F_40MHz) P79 (GCLK_0) P80 P88

– – J6 (G_Clk) P80 (GCLK_01 – –

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RST – – M6 P100 P29 P30

General Purpose DIP Input Switches

0 J15 G15 F12 P123 P3 P3

1 L16 P15 B15 P124 P49 P57

2 M13 W13 B16 P125 P4 P4

3 R15 T16 C15 P126 P48 P56

4 R17 R18 (Btn0) C16 P128 P17 P20

5 T18 P16 (Btn1) D16 P130 P35 P43

6 U18 V16 (Btn2) E15 P131 P18 P21

7 R13 Y16 (Btn3) E16 P132 P34 P41

8 T8 – F15 P133 P57 P58

9 U8 – F16 P135 P110 P120

10 R16 – G16 P137 P58 P59

11 T13 – H15 P138 P109 P118

12 H6 – H16 P139 P71 P76

13 U12 – J16 P140 P94 P99

14 U11 – T12 P141 P73 P77

15 V10 – T10 P143 P90 P96

General Purpose Output LEDs

0 H17 M14 F14 P144 P5 P5

1 K15 M15 E12 P146 P47 P54

2 J13 G14 E13 P147 P6 P6

3 N14 D18 D14 P148 P46 P51

4 R18 – E8 P171 P20 P22

5 V17 – F7 P155 P33 P40

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6 U17 – E6 P156 P21 P23

7 U16 – C13 P161 P31 P38

8 V16 – D12 P162 P59 P60

9 T15 – C11 P165 P108 P117

10 U14 – D11 P166 P61 P62

11 T16 – C10 P167 P102 P115

12 V15 – C9 P168 P74 P79

13 V14 – D9 P169 P89 P95

14 V12 – D8 P205 P75 P80

15 V11 – C8 P204 P88 P94

Seven Segment Display Output Interface

A T10 – A14 P50 P42 P48

B R10 – F9 P101 P36 P44

C K16 – E10 P35 P37 P46

D K13 – C5 P172 P15 P13

E P15 – E11 P181 P16 P19

F T11 – B14 P187 P14 P12

G L18 – F10 P185 P41 P47

DP H15 – D5 P182 P10 P11

0 J17 – C7 P178 P8 P7

1 J18 – E7 P175 P45 P50

2 T9 – C6 P176 P9 P10

3 J14 – D6 P180 P43 P49

4 P14 – – – – –

5 T14 – – – – –

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6 K2 – – – – –

7 U13 – – – – –

Pmod Header JXADC (for Nexys-4 DDR) & JA-XADC for Zybo Board

N1 (P0) A14 N15 – – – –

P1 (P1) A13 L14 – – – –

N2 (P2) A16 K16 – – – –

P2 (P3) A15 K14 – – – –

N3 (N0) B17 N16 – – – –

P3 (N1) B16 L15 – – – –

N4 (N2) A18 J16 – – – –

P4 (N3) B18 J14 – – – –

Pmod Header JA

JA1 C17 – – – – –

JA2 D18 – – – – –

JA3 E18 – – – – –

JA4 G17 – – – – –

JA7 D17 – – – – –

JA8 E17 – – – – –

JA9 F18 – – – – –

JA10 G18 – – – – –

Pmod Header JB

JB1 (P0) D14 T20 – – – –

JB2 (N0) F16 U20 – – – –

JB3 (P1) G16 V20 – – – –

JB4 (N1) H14 W20 – – – –

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JB7 (P2) E16 Y18 – – – –

JB8 (N2) F13 Y19 – – – –

JB9 (P3) G13 W18 – – – –

JB10 (N3) H16 W19 – – – –

Pmod Header JC for Nexys 4 DDR Kit

JC1 (P0) K1 V15 – – – –

JC2 (N0) F6 W15 – – – –

JC3 (P1) J2 T11 – – – –

JC4 (N1) G6 T10 – – – –

JC7 (P2) E7 W14 – – – –

JC8 (N2) J3 Y14 – – – –

JC9 (P3) J4 T12 – – – –

JC10 (N3) E6 U12 – – – –

Pmod Header JD for Nexys 4 DDR Kit

JD1 (P0) H4 T14 – – – –

JD2 (N0) H1 T15 – – – –

JD3 (P1) G1 P14 – – – –

JD4 (N1) G3 R14 – – – –

JD7 (P2) H2 U14 – – – –

JD8 (N2) G4 U15 – – – –

JD9 (P3) G2 V17 – – – –

JD10 (N3) F3 V18 – – – –

USB Interface

– N6 – –
"F_USB_D<0>" – P106

"F_USB_D<1>" – – P7 P107 – –

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"F_USB_D<2>" – – P8 P108 – –

"F_USB_D<3>" – – N8 P109 – –

– L7 – –
"F_USB_D<4>" – P111

"F_USB_D<5>" – – M7 P113 – –

"F_USB_D<6>" – – L8 P114 – –

"F_USB_D<7>" – – M9 P115 – –

– N9 – –
"F_WR#" – P119

"F_RD#" – – P9 P116 – –

"F_RXF#" – – P11 P122 – –

"F_TXE#" – – M10 P120 – –

LCD Interface

– A8 – –
"F_LCD_D<0>" – P21

"F_LCD_D<1>" – – A9 P20 – –

"F_LCD_D<2>" – – A10 P19 – –

"F_LCD_D<3>" – – B10 P18 – –

– A11 – –
"F_LCD_D<4>" – P16

"F_LCD_D<5>" – – A12 P15 – –

"F_LCD_D<6>" – – B12 P13 – –

"F_LCD_D<7>" – – A13 P12 – –

"F_LCD_E" – – B8 P22 – –

"F_LCD_R/W" – – A7 P24 – –

"F_LCD_RS" – – A6 P26 – –

RS232 Interface

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"F_RS232_RXD<1>" – – R12 P205 – –

"F_RS232_RXD<2>" – – M12 – – –

"F_RS232_TXD<1>" – – T13 P204 – –

"F_RS232_TXD<2>" – – N12 – – –

STEPPER MOTOR AND RELAY

"F_MOTOR<1>" – – P34 A4 – –

"F_MOTOR<2>" – – P33 A3 – –

"F_MOTOR<3>" – – P31 A5 – –

"F_MOTOR<4>" – – P29 B5 – –

"F_MOTOREN_A" – – P28 B6 – –

"F_MOTOREN_B" – – P27 B3 – –

DAC Interface
"F_DAC_D<0>" – – P1 P85 – –

"F_DAC_D<1>" – – P2 P86 – –

"F_DAC_D<2>" – – H3 P65 – –

"F_DAC_D<3>" – – G5 P67 – –

"F_DAC_D<4>" – – G3 P68 – –

"F_DAC_D<5>" – – G6 P71 – –

"F_DAC_D<6>" – – F4 P72 – –

"F_DAC_D<7>" – – F3 P74 – –

"F_DAC_D<8>" – – F5 P76 – –

"F_DAC_D<9>" – – F6 P77 – –

"F_DAC_D<10>" – – E3 P78 – –

"F_DAC_D<11>" – – E4 P81 – –

"F_DAC1_\CS1\" – – R1 P90 – –

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"F_DAC2_\CS2\" – – D3 P93 – –

"F_DAC_\WE\" – – N1 P94 – –
(CS3)
"F_\CS4\" – – – P95 – –

ADC Interface

"F_ADC_D<0>" – – M2 P6; – –

"F_ADC_D<1>" – – M1 p63 – –

"F_ADC_D<2>" – – L1 p62 – –

"F_ADC_D<3>" – – K2 p61 – –

"F_ADC_D<4>" – – K1 p58 – –

"F_ADC_D<5>" – – J1 p57 – –

"F_ADC_D<6>" – – H1 p52 – –

"F_ADC_D<7>" – – H2 p51 – –

"F_ADC_D<8>" – – G1 p48 – –

"F_ADC_D<9>" – – F1 p46 – –

"F_ADC_D<10>" – – F2 p45 – –

"F_ADC_D<11>" – – E1 p44 – –

"F_ADC_\CONVS – – – –
C1 P40
T\"

"F_ADC_\CS\" – – B2 P36 – –

"F_ADC_\RD\" – – B1 P37 – –

"F_ADC_\WR\" – – C2 P39 – –

"F_ADC_BUSY" – – E2 P43 – –

"F_ADC_CLK" – – K3 P42 – –

VGA Interface

"F_RED<0>" – – J3 P189 – –

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"F_RED<1>" – – H5 P190 – –

"F_RED<2>" – – A2 P191 – –

"F_GREEN<0>" – – D1 P194 – –

"F_GREEN<1>" – – C3 P196 – –

"F_GREEN<2>" – – J4 P197 – –

"F_BLUE<0>" – – L3 P198 – –

"F_BLUE<1>" – – K6 P199 – –

"F_BLUE<2>" – – K5 P200 – –

"F_HOR_SYNC" – – L10 P197 – –

"F_VER_SYNC" – – T8 P97 – –

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EXPERIMENT-1

AIM: Design and simulate all the logic gates with 2 inputs using VHDL

Tools Used: Xilinx ISE 14.4/ Xilinx Vivado, NEXYS4 DDR Board

Theory:
Logic Gates: A logic gate is an idealized model of computation or
physical electronic device implementing a Boolean function, a logical
operation performed on one or more binary inputs that produces a single binary output.
Digital systems are said to be constructed by using logic gates. These gates are the AND,
OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described
below with the aid of truth tables.

1. AND Gate:

The AND gate is an electronic circuit that gives a high output (1) onlyif all itsinputs are
high.
Symbol:

Fig.1.1 AND gate

Truth Table:

2. OR Gate:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its
inputs are high. A plus (+) is used to show the OR operation

Symbol:

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Fig. 1.2 OR Gate

Truth table:

3. NOT Gate:

The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is
known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the
outputs.

Symbol:

Fig. 1.3: NOT gate

Truth Table:

A Output

0 1

1 0

4. NAND Gate:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND
gate with a small circle on the output. The small circle represents inversion.

Symbol:

Fig. 1.4: NAND gate

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Truth Table:

5. NOR Gate:
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high.The symbol is an OR gate
with a small circle on the output. The small circle represents inversion.

Symbol:

Fig. 1.5 NOR gate

Truth Table:

6. EX-OR Gate:
The ‘Exclusive-OR’ gate is a circuit which will give a high output if either, but not both,
of its two inputs are high. An encircled plus sign ( ) is used to show the EX-OR
operation.
Symbol:

Fig. 1.6: EX-OR gate

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Truth Table:

7. EX-NOR:
The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low
output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with
a small circle on the output. The small circle represents inversion.

Symbol:

Fig.1.7: EX-NOR gate

Truth Table:

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity allgates is
Port ( A,B : in STD_LOGIC;
AND1,OR1,NOT1,NAND1,NOR1,XOR1,XNOR1 : out
STD_LOGIC);
end allgates;

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architecture Behavioral of allgates is

begin
AND1<=A AND B;
OR1<= A OR B;
NOT1 <= NOT A;
NAND1<= A NAND B;
NOR1<= A NOR B;
XOR1<= A XOR B;
XNOR1<= A XNOR B;
end Behavioral;

Output:

RTL Schematic:

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Simulation Results:

Result: We have designed vhdl code for all the logic gates and simulated waveforms
have been observed. For this Software and Hardware realisation is done through Xilinx
ISE and NEXYS 4DDR. VHDL code Simulation results are shown in the form of
waveforms. Values are forced through user. Functionality of Logic gate is verified
through simulation result. Simulation result is verified on hardware (NEXYS 4DDR
kit), where output show in form of LED after applying particular input on button on
NEXYS 4DDR.
Discussion:

1. How many AND gates are required to realize Y = CD + EF + G?

2. The NOR gate output will be high if the two inputs are __________?
3. A universal logic gate is one which can be used to generate any logic function.
Which of the following is a universal logic gate?
4. Which of the following are known as universal gates?
5. The gates required to build a half adder are __________?
6. A full adder logic circuit will have __________?

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EXPERIMENT-2

AIM: Design and simulate 2-to-4 decoder, 3-to-8 encoder and 8X1 multiplexer using
VHDL.

Tools Used: Xilinx ISE 14.4, Xilinx Vivado.

Theory:

Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output
lines. One of these outputs will be active High based on the combination of inputs
present, when the decoder is enabled. That means decoder detects a particular code. The
outputs of the decoder are nothing but the min terms of ‘n’ input.

2 to 4 Decoder:

Fig. 2.1: Block Diagram of 2 to 4 decoder

Truth Table:

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From Truth table, we can write the Boolean functions for each output as
Y3=E. A1.A0

Y2=E.A1.A0′

Y1=E.A1′.A0

Y0=E.A1′.A0′

Each output is having one product term. So, there are four product terms in total. We can
implement these four product terms by using four AND gates having three inputs each
&two inverters. The circuit diagram of 2 to 4 decoder is shown in the following figure.

Fig.2.2: Circuit diagram of 2 to 4 decoder

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b: out STD_LOGIC_VECTOR(3 downto 0));
end decoder;

architecture bhv of decoder is

begin
process(a)

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begin
case a is
when "00" => b <= "0001";
when "01" => b <= "0010";
when "10" => b <= "0100";
when "11" => b <= "1000";
end case;
end process;
end bhv;

Output:
RTL Schematic:

Fig. 2.3: Schematic diagram of 2 to 4 decoder

Simulation Result:

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Fig. 2.4: Simulation waveform of 2 to 4 decoder

8 to 3 Encoder:
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It
has maximum of 2n input lines and ‘n’ output lines. It will produce a binary code
equivalent to the input, which is active High. Therefore, the encoder encodes 2n input
lines with ‘n’ bits. It is optional to represent the enable signal in encoders.

Fig.2.5: Block diagram of 8 to 3 Encoder

Truth Table:

From Truth table, we can write the Boolean functions for each output as

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A2=Y7+Y6+Y5+Y4A2=Y7+Y6+Y5+Y4

A1=Y7+Y6+Y3+Y2A1=Y7+Y6+Y3+Y2

A0=Y7+Y5+Y3+Y1

Circuit Diagram:

Fig. 2.6 Circuit Diagram of 8 to 3 Encoder

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD. all;
entity ENCODER8 is
port (A: in std_logic_vector (7 downto 0);
Y: out std_logic_vector (2 downto 0));
end ENCODER8;
architecture ARCH of ENCODER8 is
begin
process (A)
begin
If (A = "00000001") then Y <= "000";
elsif (A = "00000010") then Y <= "001";
elsif (A = "00000100") then Y <= "010";
elsif (A = "00001000") then Y <= "011";
elsif (A = "00010000") then Y <= "100";
elsif (A = "00100000") then Y <= "101";
elsif (A = "01000000") then Y <= "110";
elsif (A = "10000000") then Y <= "111";

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else Y <= "XXX";

end if ;
end process ;
end ARCH;

Output:
RTL Schematic:

Fig. 2.7: Schematic Diagram of 8 to 3 Encoder

Simulation Result:

Fig.2.8: Simulation waveform of 8 to 3 Encoder

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8:1 Multiplexer
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection
lines and single output line. One of these data inputs will be connected to the output
based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and
ones. So, each combination will select only one data input. Multiplexer is also called
as Mux.

Fig.2.9: Block Diagram of 8 to 1 Multiplexer

Truth Table:

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VHDL Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX8_1 IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN
STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC);
END MUX8_1;
ARCHITECTURE BEH123 OF MUX8_1 IS
BEGIN
PROCESS(DIN,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN(0);
WHEN"001"=>DOUT<=DIN(1);
WHEN"010"=>DOUT<=DIN(2);
WHEN"011"=>DOUT<=DIN(3);
WHEN"100"=>DOUT<=DIN(4);
WHEN"101"=>DOUT<=DIN(5);
WHEN"110"=>DOUT<=DIN(6);
WHEN"111"=>DOUT<=DIN(7);
WHEN OTHERS=>
DOUT<='Z';
END CASE;

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END PROCESS;
END BEH123;

Output:

RTL Schematic:

Fig.2.10: Schematic Diagram of 8*1 Multiplexer

Simulation Result:

Fig. 2.11: Simulation waveform of 8*1 Multiplexer

Result: We have designed VHDL code for 2*4 decoder, encoder and 8*1 multiplexer
and simulated waveforms have been observed. For this Software and Hardware
realisation is done through Xilinx ISE and NEXYS 4DDR. VHDL code Simulation
results are shown in the form of waveforms. Values are forced through user.
Functionality of circuit is verified through simulation result. Simulation result is verified

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on hardware (NEXYS 4DDR kit), where output show in form of LED after applying
particular input on button on NEXYS 4DDR.

Discussion:
1. How is an encoder different from a decoder?
2. For 8-bit input encoder how many combinations are possible?
3. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
4. How many data select lines are required for selecting eight inputs?

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EXPERIMENT-3

AIM: Design and simulate half adder and full adder using VHDL (data flow method).

Tools Used: Xilinx ISE 14.4, Xilinx Vivado

Theory:

Half Adder:
The addition of 2 bits is done using a combination circuit called Half adder. The input
variables are augend and addend bits and output variables are sum & carry bits. A and B
are the two input bits. Half Adder is a combinational logic circuit which is designed by
connecting one EX-OR gate and one AND gate.

Fig. 3.1: Circuit Diagram of Half adder

Truth Table:

Boolean Function:
Sum = x'y+xy'
Carry = xy

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HADF is

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Port (A,B : in STD_LOGIC;

S,C : out STD_LOGIC);
end HADF;
--DATAFLOW MODELING
architecture data_flow of HAdf is
begin
S<= A XOR B;
C<= A AND B;
end data_flow;

RTL Schematic:

Fig. 3.2: Schematic Diagram of Half adder

Simulation Result:

Fig.3.3: Simulation Waveform of Half adder

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Full Adder:
The half adder is used to add only two numbers. To overcome this problem, the full adder
was developed. The full adder is used to add three 1-bit binary numbers A, B, and carry
C. The full adder has three input states and two output states i.e., sum and carry.

Fig.3.4 Circuit Diagram of Full Adder

Truth Table:

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_STR is
Port (A,B,C : in STD_LOGIC;
SUM,CARRY : out STD_LOGIC);
end FA_STR;
--STURCTURAL MODELING
architecture STRUCT of FA_STR is
COMPONENT HAdf
Port ( A,B : in STD_LOGIC;
S,C : out STD_LOGIC);
end COMPONENT;
SIGNAL X,Y,Z:STD_LOGIC;
begin
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HA1:HADF PORT MAP(A,B,X,Y);

HA2:HADF PORT MAP(X,C,SUM,Z);
CARRY<= Z OR Y;
end STRUCT;

Output:
RTL Schematic:

Fig. 3.5: Schematic Diagram of Full adder

Simulation Results:

Fig.3.6: Simulation Waveform of Full adder

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Result: We have designed VHDL code for half adder and full adder and simulated
waveforms have been observed. For this Software and Hardware realisation is done
through Xilinx ISE and NEXYS 4DDR. VHDL code Simulation results are shown in
the form of waveforms. Values are forced through user. Functionality of adders is
verified through simulation result. Simulation result is verified on hardware (NEXYS
4DDR kit), where output show in form of LED after applying particular input on button
on NEXYS 4DDR.

Discussion:
1. The difference between half adder and full adder is?
2. How many AND, OR and EXOR gates are required for the configuration of full
adder?
3. If A and B are the inputs of a half adder, the sum is given by?
4. If A, B and C are the inputs of a full adder then the sum is given by?
5. Half-adders have a major limitation in that they cannot?

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EXPERIMENT-4

AIM: Design and simulate D, T and J-K flip flop using VHDL.

Tools Used: Xilinx ISE 14.4, Xilinx Vivado

Theory:
D Flip-flops are used as a part of memory storage elements and data processors as well. D
flip-flop can be built using NAND gate or with NOR gate. Due to its versatility they are
available as IC packages. The major applications of D flip-flop are to introduce delay in
timing circuit, as a buffer, sampling data at specific intervals. D flip-flop is simpler in
terms of wiring connection compared to JK flip-flop. Here we are using NAND gates for
demonstrating the D flip flop.
Whenever the clock signal is LOW, the input is never going to affect the output
state. The clock has to be high for the inputs to get active. Thus, D flip-flop is a
controlled Bi-stable latch where the clock signal is the control signal. Again, this gets
divided into positive edge triggered D flip flop and negative edge triggered D flip-
flop. Thus, the output has two stable states based on the inputs.

Fig. 4.1: Block Diagram of D Flip Flop

Truth Table:

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A D flip – flop is constructed by modifying an SR flip – flop. The S input is given with D
input and the R input is given with inverted D input. Hence a D flip – flop is similar to SR
flip – flop in which the two inputs arecomplement to each other, so there will be no
chance of any intermediate state occurs. The major drawback of SR flip – flop is the race
around condition which in D flip – flop is eliminated (because of the inverted inputs).

Fig.4.2: Circuit Diagram of D Flip Flop

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF is
Port ( PRE,CLR,CLK,D : in STD_LOGIC;
Q :inout STD_LOGIC);
end DFF;
architecture Behavioral of DFF is
begin
PROCESS(PRE,CLR,CLK)
BEGIN
IF(PRE='0') THEN
Q<='1';
ELSIF(CLR='0') THEN
Q<='0';
--ELSIF(CLK='1' AND CLK'EVENT) THEN
ELSIF RISING_EDGE(CLK) THEN
Q<=D;
END IF;
END PROCESS;
end Behavioral;

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Output:

RTL Schematic:

Fig.4.3: Schematic Diagram of D Flip Flop

Simulation Result:

Fig. 4.4: Simulation Waveform of D Flip Flop

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JK FLIP-FLOP:
The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the
shortened abbreviated letters for Set and Reset, but J and K are not. The J and K are
themselves autonomous letters which are chosen to distinguish the flip flop design from
other types.
The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The
invalid or illegal output condition occurs when both of the inputs are set to 1 and are
prevented by the addition of a clock input circuit. So, the JK flip-flop has four possible
input combinations, i.e., 1, 0, "no change" and "toggle".
The symbol of JK flip flop is the same as SR Bistable Latch except for the addition of a
clock input.
JK Flip Flop is a universal flip-flop that makes the circuit toggle between two states and
is widely used in shift registers, counters, PWM and computer applications.

Fig.4.5: Block Diagram of J K Flip Flop

Truth Table:

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Circuit Diagram:

Fig. 4.6: Circuit Diagram of J K Flip Flop

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity jkff is
Port ( clk : in STD_LOGIC;
jk : in STD_LOGIC_VECTOR (0 to 1);
q :inout STD_LOGIC := '1');
end jkff;

architecture Behavioral of jkff is

begin
process(clk)
begin
if (clk='1' and clk'event) then
case jk is
when "01" => q<= '0';
when "10" => q<= '1';
When "11" => q<= not q;
When others => null;
end case;
end if;
end process;
end Behavioral;

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Output:

RTL Schematic:

Fig. 4.7 Schematic Diagram of JK Flip Flop

Simulation Result:

Fig. 4.8: Simulation Waveform of JK Flip Flop

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T- Flip Flop:
A T flip flop is like JK flip-flop. These are basically a single input version of JK flip flop.
This modified form of JK flip-flop is obtained by connecting both inputs J and K
together. This flip-flop has only one input along with the clock input.
Block Diagram:

Fig. 4.9: Block Diagram of T Flip Flop

Truth Table:

Circuit Diagram:

Fig.4.10: Circuit Diagram of T Flip Flop

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TFF is
Port ( rst,CLK, T : in STD_LOGIC;
Q :inout STD_LOGIC );
end TFF;

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architecture Behavioral of TFF is

begin
PROCESS(rst,CLK)
BEGIN
If rst='1'
then q<='0';
elsIF (CLK='0' AND CLK'EVENT) THEN
IF(T='1') THEN
Q<= NOT Q;
END IF;
END IF;
END PROCESS;
end Behavioral;

Output:
RTL Schematic:

Fig. 4.11: Schematic Diagram of T Flip Flop

Simulation Result:

Fig. 4.12: Simulation Waveform of T Flip Flop

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Result: We have designed vhdl code for D flip flop, J-K Flip Flop, T Flip-Flop and
simulated waveforms have been observed. For this Software and Hardware realisation is
done through Xilinx ISE and NEXYS 4DDR. VHDL code Simulation results are shown
in the form of waveforms. Values are forced through user. Functionality of addres is
verified through simulation result. Simulation result is verified on hardware (NEXYS
4DDR kit), where output show in form of LED after applying particular input on button
on NEXYS 4DDR.

Discussion:
1. When both inputs of a J-K flip-flop cycle, the output will?
2. Which of the following is correct for a gated D-type flip-flop?
3. The logic circuits whose outputs at any instant of time depends only on the present
input but also on the past outputs are called?
4. In S-R flip-flop, if Q = 0 the output is said to be? The output of latches will
remain in set/reset until?

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EXPERIMENT-5

AIM: Design a 4bit binary Asynchronous and Synchronous counter. Obtain it’s number
of gates, area, and speed and power dissipation.

Tools Used: Xilinx ISE 14.4, Xilinx Vivado

Theory:
Asynchronous counters are those whose output is free from the clock signal. Because the
flip flops in asynchronous counters are supplied with different clock signals, there may be
delay in producing output. The required number of logic gates to design asynchronous
counters is very less. So they are simple in design. Another name for Asynchronous
counters is “Ripple counters”.
In asynchronous counter different lip flop are triggered with different clock not
simultaneously. Asynchronous Counter is also called Serial Counter.

Different types of Asynchronous counters:

 4 bit synchronous UP counter
 4 bit synchronous DOWN counter
 4 bit synchronous UP / DOWN counter

Circuit Diagram:

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Fig.5.1: Circuit Diagram of Asynchronous counter

Truth Table:
rst ld_count count_en u_d O/P Operation
(Dout)

1 × × × 0 Reset operation

0 1 × × Din Load the Counter with I/P Din

0 0 1 1 Q=q+1 Up Counter

0 0 1 0 Q=q+1 Down Counter

0 0 0 × × Counting disable

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity univ_cntr is
Generic (N : integer := 4);
Port ( clk, rst, ld_count, count_en, u_d : in
STD_LOGIC;
Din : in STD_LOGIC_VECTOR (N-1 downto 0);
Dout : out STD_LOGIC_VECTOR (N-1 downto 0));
end univ_cntr;

architecture Behavioral of univ_cntr is

signal tmp:STD_LOGIC_VECTOR (N-1 downto 0);
begin

process (clk, rst)

begin
if rst='1' then
tmp<= (others => '0');
elsif (clk'event and clk = '1') then
if (ld_count='1') then
tmp<= Din;
elsif (count_en = '1') then
if (u_d='1') then
tmp<= tmp + 1;
else
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tmp<= tmp - 1;

end if; end if; end if;

end process;
Dout<= tmp;
end Behavioral;
Output:

RTL Schematic:

Fig. 5.2: Schematic Diagram of Asynchronous Counter

Simulation Result:

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Fig. 5.3: Simulation waveform of Asynchronous Counter

Number of gates, area, and speed and power dissipation:

SYNTHESIS REPORT:
================================================================
=========
* Final Report *
================================================================
=========
Final Results
RTL Top Level Output File Name : univ_cntr.ngr
Top Level Output File Name : univ_cntr
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No

Design Statistics
# IOs : 13

Cell Usage :
# BELS :9
# LUT2 :1
# LUT3 :1
# LUT3_L :1
# LUT4 :4
# LUT4_L :1
# MUXF5 :1

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# FlipFlops/Latches :4
# FDCE :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 12
# IBUF :8
# OBUF :4
================================================================
=========

Device utilization summary:

---------------------------

Selected Device : 3s100evq100-5

Number of Slices: 4 out of 960 0%

Number of Slice Flip Flops: 4 out of 1920 0%
Number of 4 input LUTs: 8 out of 1920 0%
Number of IOs: 13
Number of bonded IOBs: 13 out of 66 19%
Number of GCLKs: 1 out of 24 4%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------

================================================================
=========
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst | IBUF |4 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5
Minimum period: 2.708ns (Maximum Frequency: 369.324MHz)
Minimum input arrival time before clock: 3.352ns
Maximum output required time after clock: 4.252ns
Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

================================================================
=========
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.708ns (frequency: 369.324MHz)
Total number of paths / destination ports: 11 / 4
-------------------------------------------------------------------------
Delay: 2.708ns (Levels of Logic = 2)
Source: tmp_0 (FF)
Destination: tmp_2 (FF)
Source Clock: clk rising
Destination Clock: clk rising

Data Path: tmp_0 to tmp_2

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 6 0.514 0.599 tmp_0 (tmp_0)
LUT3_L:I2->LO 1 0.612 0.103 Mcount_tmp_xor<2>111 (N11)
LUT4:I3->O 1 0.612 0.000 Mcount_tmp_xor<2>12 (Mcount_tmp3)
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FDCE:D 0.268 tmp_2

----------------------------------------
Total 2.708ns (2.006ns logic, 0.702ns route)
(74.1% logic, 25.9% route)

================================================================
=========
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 22 / 8
-------------------------------------------------------------------------
Offset: 3.352ns (Levels of Logic = 3)
Source: u_d (PAD)
Destination: tmp_2 (FF)
Destination Clock: clk rising

Data Path: u_d to tmp_2

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 u_d_IBUF (u_d_IBUF)
LUT3_L:I0->LO 1 0.612 0.103 Mcount_tmp_xor<2>111 (N11)
LUT4:I3->O 1 0.612 0.000 Mcount_tmp_xor<2>12 (Mcount_tmp3)
FDCE:D 0.268 tmp_2
----------------------------------------
Total 3.352ns (2.598ns logic, 0.754ns route)
(77.5% logic, 22.5% route)

================================================================
=========
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 4.252ns (Levels of Logic = 1)
Source: tmp_0 (FF)
Destination: Dout<0> (PAD)
Source Clock: clk rising

Data Path: tmp_0 to Dout<0>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 6 0.514 0.569 tmp_0 (tmp_0)
OBUF:I->O 3.169 Dout_0_OBUF (Dout<0>)
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----------------------------------------
Total 4.252ns (3.683ns logic, 0.569ns route)
(86.6% logic, 13.4% route)
================================================================
=========

Total REAL time to Xst completion: 6.00 secs

Total CPU time to Xst completion: 5.75 secs

-->
Total memory usage is 251856 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Synchronous Counter:
If all the flip-flops receive the same clock signal, then that counter is called
as Synchronous counter. Hence, the outputs of all flip-flops changeaffect at the same
time. Synchronous counters are sometimes called parallel counters as the clock is fed in
parallel to all flip-flops. The inherent memory circuit keeps track of the counters present
state. The count sequence is controlled using logic gates. The one advantage of
synchronous counter over asynchronous counter is, it can operate on higher frequency
than asynchronous counter as it does not have cumulative delay because of same clock
is given to each flip flop.

Different Types of Synchronous Counter:

 Synchronous Binary up counter

 Synchronous Binary down counter

Circuit Diagram:

Synchronous Binary up counter:

An ‘N’ bit Synchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to
2 − 1.

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Fig: 5.4: Block Diagram of Synchronous Binary up counter

Synchronous Binary down counter:

An ‘N’ bit Synchronous binary down counter consists of ‘N’ T flip-flops. It counts from
2 − 1 to 0.

Fig: 5.5: Block Diagram of Synchronous Binary up counter

VHDL Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity tcounter is
port(clk,rst:instd_logic;
q,qbar:inoutstd_logic_vector(3 downto 0));
end tcounter;
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architecture Behavioral of tcounter is

component tffl is
port(t,rst,clk:instd_logic;
q,qb:outstd_logic);
end component;
signal k,l,m:std_logic;
begin
k<=q(0);
l<=q(0) and q(1);
m<=q(0) and q(1) and q(2);
a1: tffl port map('1',rst,clk,q(0),qbar(0));
a2: tffl port map(k,rst,clk,q(1),qbar(1));
a3: tffl port map(l,rst,clk,q(2),qbar(2));
a4: tffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;
Output:
RTL Schematic:

Fig. 5.6: Schematic Diagram of Synchronous Up Counter

Simulation Result:

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Fig. 5.7: Simulation Waveform of Synchronos Up Counter

Number of gates, area, and speed and power dissipation:

SYNTHESIS REPORT:
================================================================
=========
* Final Report *
================================================================
=========
Final Results
RTL Top Level Output File Name : upcounter.ngr
Top Level Output File Name : upcounter
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No

Design Statistics
# IOs :6

Cell Usage :
# BELS :7
# INV :4
# LUT2 :1
# LUT3 :1
# VCC :1
# FlipFlops/Latches :4
# FDCE_1 :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :1
# OBUF :4
================================================================
=========

Device utilization summary:

---------------------------

Selected Device : 3s100evq100-5

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Number of Slices: 3 out of 960 0%

Number of Slice Flip Flops: 4 out of 1920 0%
Number of 4 input LUTs: 6 out of 1920 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 66 9%
Number of GCLKs: 1 out of 24 4%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------
================================================================
=========
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst | IBUF |4 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 2.617ns (Maximum Frequency: 382.124MHz)

Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.221ns
Maximum combinational path delay: No path found

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Timing Detail:
--------------
All values displayed in nanoseconds (ns)

================================================================
=========
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.617ns (frequency: 382.124MHz)
Total number of paths / destination ports: 10 / 7
-------------------------------------------------------------------------
Delay: 2.617ns (Levels of Logic = 1)
Source: a2/Q (FF)
Destination: a3/Q (FF)
Source Clock: clk falling
Destination Clock: clk falling

Data Path: a2/Q to a3/Q

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE_1:C->Q 4 0.514 0.651 a2/Q (a2/Q)
LUT2:I0->O 1 0.612 0.357 l1 (l)
FDCE_1:CE 0.483 a3/Q
----------------------------------------
Total 2.617ns (1.609ns logic, 1.008ns route)
(61.5% logic, 38.5% route)

================================================================
=========
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 4.221ns (Levels of Logic = 1)
Source: a1/Q (FF)
Destination: q<0> (PAD)
Source Clock: clk falling

Data Path: a1/Q to q<0>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE_1:C->Q 5 0.514 0.538 a1/Q (a1/Q)
OBUF:I->O 3.169 q_0_OBUF (q<0>)
----------------------------------------
Total 4.221ns (3.683ns logic, 0.538ns route)
(87.3% logic, 12.7% route)

================================================================
=========
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Total REAL time to Xst completion: 4.00 secs

Total CPU time to Xst completion: 3.91 secs

-->
Total memory usage is 251984 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Result: We have designed the VHDL code of a general purpose universal Counter using
behavioural modelling style and virtually verified the design by test bench and also
implemented on FPGA trainer kit for physical verification.

Discussion:
1. How many natural states will there be in a 4-bit ripple counter?
2. One of the major drawbacks to the use of asynchronous counters is that?
3. How many flip-flops are required to construct a decade counter?
4. How many different states does a 3-bit asynchronous counter have?
5. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12
ns propagation delay. The total propagation delay (tp(total)) is?

(This page is intentionally left blank)

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EXPERIMENT-6

AIM: Design a 4- bit Serial in-serial out shift register. Obtain its number of gates, area,
and speed and power dissipation.

Tools Used: Xilinx ISE 14.4, Xilinx Vivado

Theory:
The Shift Register is another type of sequential logic circuit that can be used for the
storage or the transfer of binary data. This sequential device loads the data present on its
inputs and then moves or “shifts” it to its output once every clock cycle, hence the
name Shift Register.

A shift register basically consists of several single bit “D-Type Data Latches”, one for
each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain
arrangement so that the output from one data latch becomes the input of the next latch and
so on. Data bits may be fed in or out of a shift register serially, that is one after the other
from either the left or the right direction, or all together at the same time in a parallel
configuration.

The number of individual data latches required to make up a single Shift Register device
is usually determined by the number of bits to be stored with the most common being 8-
bits (one byte) wide constructed from eight individual data latches.

Generally, shift registers operate in one of four different modes with the basic movement
of data through a shift register being:
 Serial-in to Parallel-out (SIPO) - The register is loaded with serial data, one
bit at a time, with the stored data being available at the output in parallel
form.
 Serial-in to Serial-out (SISO) -The data is shifted serially “IN” and “OUT”
of the register, one bit at a time in either a left or right direction under clock
control.
 Parallel-in to Serial-out (PISO) -The parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time
under clock control.
 Parallel-in to Parallel-out (PIPO) -The parallel data is loaded
simultaneously into the register, and transferred together to their respective
outputs by the same clock pulse.

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Circuit Diagram:

Fig.6.1: Circuit Diagram of Serial in Serial Out Shift register

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity SISO is

Port ( sin,clk,rst : in STD_LOGIC;

sout : out STD_LOGIC);

end SISO;

architecture Struct of SISO is

signal x:std_logic_vector (0 to 4);

component dff

port(D,clk,reset : in std_logic;

Q: out std_logic);

end component;

Begin

X(0)<= sin;

L1: For i in 0 to 3 generate

L2:dff port map (x(i),clk,rst,x(i+1));

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End generate;

Sout<= x(4);

end Struct;

Output:

RTL Schematic:

Fig. 6.2: Schematic Diagram of Serial in Serial Out Shift register

Simulation Result:

Fig.6.3: Simulation waveform of of Serial in Serial Out Shift register

Number of gates, area, and speed and power dissipation.

SYNTHESIS REPORT:
================================================================
=========
* Final Report *
================================================================
=========
Final Results

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RTL Top Level Output File Name : SISO.ngr

Top Level Output File Name : SISO
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No

Design Statistics
# IOs :4

Cell Usage :
# FlipFlops/Latches :4
# FDC :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :3
# IBUF :2
# OBUF :1
================================================================
=========

Device utilization summary:

---------------------------

Selected Device : 3s100evq100-5

Number of Slices: 2 out of 960 0%

Number of Slice Flip Flops: 4 out of 1920 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 66 6%
Number of GCLKs: 1 out of 24 4%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------
================================================================
=========
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE

REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst | IBUF |4 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 1.139ns (Maximum Frequency: 877.963MHz)

Minimum input arrival time before clock: 1.731ns
Maximum output required time after clock: 4.040ns
Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

================================================================
=========
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 1.139ns (frequency: 877.963MHz)
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Delay: 1.139ns (Levels of Logic = 0)
Source: L1[2].L2/Q (FF)
Destination: L1[3].L2/Q (FF)
Source Clock: clk rising
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Destination Clock: clk rising

Data Path: L1[2].L2/Q to L1[3].L2/Q

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 1 0.514 0.357 L1[2].L2/Q (L1[2].L2/Q)
FDC:D 0.268 L1[3].L2/Q
----------------------------------------
Total 1.139ns (0.782ns logic, 0.357ns route)
(68.7% logic, 31.3% route)

================================================================
=========
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 1.731ns (Levels of Logic = 1)
Source: sin (PAD)
Destination: L1[0].L2/Q (FF)
Destination Clock: clk rising

Data Path: sin to L1[0].L2/Q

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.106 0.357 sin_IBUF (sin_IBUF)
FDC:D 0.268 L1[0].L2/Q
----------------------------------------
Total 1.731ns (1.374ns logic, 0.357ns route)
(79.4% logic, 20.6% route)

================================================================
=========
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.040ns (Levels of Logic = 1)
Source: L1[3].L2/Q (FF)
Destination: sout (PAD)
Source Clock: clk rising

Data Path: L1[3].L2/Q to sout

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Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 1 0.514 0.357 L1[3].L2/Q (L1[3].L2/Q)
OBUF:I->O 3.169 sout_OBUF (sout)
----------------------------------------
Total 4.040ns (3.683ns logic, 0.357ns route)
(91.2% logic, 8.8% route)
================================================================
=========
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.59 secs

-->
Total memory usage is 252048 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

Result: We have designed VHDL code for 4 bit serial in serial out shift registerand
simulated waveforms have been observed. For this Software and Hardware realisation is
done through Xilinx ISE and NEXYS 4DDR. VHDL code Simulation results are shown
in the form of waveforms. Values are forced through user. Functionality of SISO shift
register is verified through simulation result. Simulation result is verified on hardware
(NEXYS 4DDR kit), where output show in form of LED after applying particular input
on button on NEXYS 4DDR.

Discussion:
1. A shift register that will accept a parallel input or a bidirectional serial load and
internal shift features is called as?
2. How can parallel data be taken out of a shift register simultaneously?
3. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel
output shift register with an initial state 01110. After three clock pulses, the
register contains?

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PART-B

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Introductory Lab for Part-I (Schematic Design Tool)

1. Start SYMICA DE free software.
2. Suppose I want to design CMOS inverter circuit schematic.
3. Create new Library.
FILE New  Library
4. Give Library Name (eg. circuits) and select destination folder in directory and
click OK.
5. View  Library Manager. Library name will be displayed in library manager.
6. Select Your Library. Go to File  New  cell view (or right click on library
name and select new cell view.)

7. Give cell name (eg. Inverter). Click OK. Schematic editor window will open.

8. Place  Instance (or press “I” on keyboard). Instance window will open.

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9. Select the library and search for cell to be placed on schematic. Select the symbol
of the component and click on Place. The component symbol will be placed on schematic
Editor. Place all the required components one by one.

10. Then go to Place  Wire (or press “w” on keyboard) to make connections
between the components. To place input and output Pins go to Place  Pin (or press “p”
on keyboard)

11. For creating symbol : select Cell in library manager  right click  select new
cell view from.
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12. Choose right cell for which symbol is to be created. Click OK.
13. In Symbol Generation Options, give pin specifications and click OK. Symbol will
be created. It can be customized.
14. Now to check properties of the circuit, a test circuit can be designed by creating a
new cell naming “invertertest”. Or you can also modify the existing inverter circuit by
replacing input pin by input source.

15. Go to Simulation  Environment.

16. Simulation Environment window will open. Setup  Model Libraries. Select
library from “modellib” folder.

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17. Choosing Analyses

This section demonstrates how to view and select the different types of analyses to
complete the circuit when running the simulation.
1. In the Simulation window (ADE), click the Choose - Analyses icon. You can also
execute Analyses - Choose.

The Choosing Analysis form appears. This is a dynamic form, the bottom of the form
changes based on the selection above.
2. To setup for transient analysis
a. In the Analysis section selecttran
b. Set the stop time as 200n
c. Click at the moderate or Enabled button at the bottom, and then click Apply.
3. To set up for DC Analyses:
a. In the Analyses section, select dc.
b. In the DC Analyses section, turn on Save DC Operating Point.
c. Turn on the Component Parameter.
d. Double click the Select Component, Which takes you to the schematic window.
e. Select input signal vpulse source in the test schematic window.
f. Select ―DC Voltage‖in the Select Component Parameter form and click OK.
f. In the analysis form type startandstop voltages as 0 to 1.8 respectively.
g. Check the enable button and then click Apply.

4. Click OK in the Choosing Analyses Form.

18. Setting Design Variables

Set the values of any design variables in the circuit before simulating. Otherwise, the
simulation will not run.
1. In the Simulation window, click the Edit Variables icon. The Editing Design
Variables form appears.

2. Click Copy From at the bottom of the form. The design is scanned and all variables
found in the design are listed. In a few moments, the wpvariable appears in the Table of
Design variables section.
3. Set the value of the wpvariable:
With the wpvariable highlighted in the Table of Design Variables, click on the variable
name wp and enter the following:

Click Change and notice the update in the Table of Design Variables.
4. Click OK or Cancel in the Editing Design Variables window.

19. Selecting Outputs for Plotting

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VLSI DESIGN LAB

1. Execute Outputs – To be plotted – Select on Schematic in the simulation window.

2. Follow the prompt at the bottom of the schematic window, Click on output net Vout,
input net Vinof the Inverter. Press ESC with the cursor in the schematic after selecting it.

20. Running the Simulation

1. Execute Simulation – Netlist and Run in the simulation window to start the
Simulation or the icon, this will create the netlist as well as run the simulation.
2. When simulation finishes, the Transient, DC plots automatically will be
popped up along with log file.
In order to visualize and analyze simulation results Symica offers an analog waveform
post-processor SymProbe, which has got a full set of visualization options as well as a
built-in analog waveform calculator supporting more than 50 functions. The original data
structure of SymProbe allows fast waveform redrawing and zooming.

21. Saving the Simulator State

We can save the simulator state, which stores information such as model library file,
outputs, analysis, variable etc. This information restores the simulation environment
without having to type in all of setting again.
1. In the Simulation window, execute Session – Save State. The Saving State form
appears.
2. Set the Save as field to state1_inv and make sure all options are selected under what to

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VLSI DESIGN LAB

save field.
3. Click OK in the saving state form. The Simulator state is saved.

22. Loading the Simulator State

1. From the ADE window execute Session – Load State.
2. In the Loading State window, set the State name to state1_inv as shown:
3. Click OK in the Loading State window.
Step 5: Parametric Analysis
Parametric Analysis yields information similar to that provided by the Spectre® sweep
feature, except the data is for a full range of sweeps for each parametric step. The Spectre
sweep feature provides sweep data at only one specified condition.
You will run a parametric DC analysis on the wpvariable, of the PMOS device of the
Inverter design by sweeping the value of wp.
Run a simulation before starting the parametric tool. You will start by loading the state
from the previous simulation run.
Run the simulation and check for errors. When the simulation ends, a single
waveform in the waveform window displays the DC Response at the Voutnode.

23. Starting the Parametric Analysis Tool

1. In the Simulation window, execute Tools—Parametric Analysis. The Parametric
Analysis form appears.
2. In the Parametric Analysis form, execute Setup—Pick Name for Variable—Sweep 1.
A selection window appears with a list of all variables in the design that you can sweep.
This list includes the variables that appear in the Design Variables section of the
Simulation window.
3. In the selection window, double click left on wp. The Variable Name field for Sweep 1
in the Parametric Analysis form is set to wp.
4. Change the Range Type and Step Control fields in the Parametric. Analysis form as
shown below:

These numbers vary the value of the wpof the pmos between 1um and 10um at
ten evenly spaced intervals.
5. Execute Analysis—Start.
The Parametric Analysis window displays the number of runs remaining in the analysis
and the current value of the swept variable(s). Look in the upper right corner of the
window. Once the runs are completed the wavescan window comes up with the plots for
different runs.

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EXPERIMENT-7
AIM: Design and simulate all the logic gates (NOT, NAND and NOR) with 2inputs in
CMOS Technology.

Tools Used: Symica-DE Free

Theory:

INVERTER:
CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used
and adaptable MOSFET inverters used in chip design. They operate with very little power
loss and at relatively high speed. Furthermore, the CMOS inverter has good logic buffer
characteristics, in that, its noise margins in both low and high states are large.
This short description of CMOS inverters gives a basic understanding of the how a
CMOS inverter works. It will cover input/output characteristics, MOSFET states at
different input voltages, and power losses due to electrical current.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and
gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground
connected at the NMOS source terminal, were VIN is connected to the gate terminals and
VOUT is connected to the drain terminals. It is important to notice that the CMOS does
not contain any resistors, which makes it more power efficient that a regular resistor-
MOSFET inverter. As the voltage at the input of the CMOS device varies between 0 and
5 volts, the state of the NMOS and PMOS varies accordingly. If we model each transistor
as a simple switch activated by VIN, the inverter’s operations can be seen very easily:

Fig.7.1 Circuit Diagram of CMOS Inverter

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Transistor "switch model"

The switch model of the MOSFET transistor is defined as follows:

MOSFET Condition Stateof

on MOSFET
MOSFET

NMOS Vgs<Vtn OFF

NMOS Vgs>Vtn ON

PMOS Vsg<Vtp OFF

PMOS Vsg>Vtp ON

When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging
VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining
the voltage at VOUT to logic low.

Schematic Diagram:

Fig.7.2: Schematic Diagram of CMOS inverter

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Symbol:

Fig.7.3: Symbol of CMOS inverter

Test Circuit:

Fig.7.4: Test Circuit of CMOS inverter

Transient Analysis:

Fig.7.5: Simulation waveform of CMOS inverter

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NAND Gate:

Circuit Diagram:
Transistors Q1 and Q3 resemble the series-connected complementary pair from the
inverter circuit. Both are controlled by the same input signal (input A), the upper
transistor turning off and the lower transistor turning on when the input is “high” (1), and
vice versa. transistors Q2 and Q4 are similarly controlled by the same input signal (input
B), and how they will also exhibit the same on/off behavior for the same input logic
levels. The upper transistors of both pairs (Q 1 and Q2) have their source and drain
terminals paralleled, while the lower transistors (Q 3 and Q4) are series-connected.

Q1

Q2

Q3

Q4

Fig.7.6: Circuit Diagram of NAND gate

Case 1: VA-Low : pMOS1-ON; nMOS1-OFF

VB-Low :pMOS2-ON; nMOS2-OFF

Case 2:VA-Low : pMOS1-ON ; nMOS1-OFF

VB-High: pMOS2-OFF; nMOS2-ON

Case 3:VA-High : pMOS1-OFF; nMOS1- ON

VB-Low :pMOS 1-ON; nMOS1-OFF

Case 4: VA-High :pMOS1-OFF; nMOS1- ON

VB-High :pMOS 1-OFF; nMOS1-ON

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Truth Table:

NAND Gate Schematic:

Fig.7.7: Schematic Diagram of NAND gate

Symbol:

Fig.7.8: Symbol of NAND gate

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Test Circuit:

Fig.7.9: Test Circuit of NAND gate

Simulation Result:

Fig.7.10: Simulation waveform of NAND gate

NOR Gate:
The Logic NOR Gate gate is a combination of the digital logic OR gate and an inverter or
NOT gate connected together in series.The inclusive NOR (Not-OR) gate has an output
that is normally at logic level “1” and only goes “LOW” to logic level “0” when ANY of

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its inputs are at logic level “1”. The Logic NOR Gate is the reverse or “Complementary”
form of the inclusive OR gate we have seen previously.

Circuit Diagram:

Fig.7.11: Circuit Diagram of NOR gate

Truth Table:

Case 1: VA-Low : pMOS1-ON; nMOS1-OFF

VB-Low :pMOS2-ON; nMOS2-OFF

Case 2:VA-Low : pMOS1-ON ; nMOS1-OFF

VB-High: pMOS2-OFF; nMOS2-ON

Case 3:VA-High : pMOS1-OFF; nMOS1- ON

VB-Low :pMOS 1-ON; nMOS1-OFF

Case 4: VA-High :pMOS1-OFF; nMOS1- ON

VB-High :pMOS 1-OFF; nMOS1-ON

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Output:

RTL Schematic:

Fig.7.12: Schematic Diagram of NOR gate

Symbol:

Fig.7.13: Symbol of NOR gate

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Test Circuit:

Fig.7.14: Test Circuit of NOR gate

Simulation Result:

Fig. 7.15:Simulation waveform of NOR gate

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Result: We designed the circuit diagram on symica DE free tool. Symbol of circuit are
created. Functionality were checked with the help of simulation waveform. Test circuit
are also tested. Different logic gate are simulated and tested.

Discussion:
1. In CMOS logic circuit the n-MOS transistor acts as?
2. In CMOS logic circuit, the switching operation occurs ?
3. When both nMOS and pMOS transistors of CMOS logic design are in OFF
condition, the output ?
4. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output
is?
5. In positive logic convention, the true state is represented as?

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EXPERIMENT- 8
AIM: Design and simulate Y = AB (C+D), Y = A+B(C+D) and 4X1 multiplexer using
CMOS Technology.
Tools Used: Symica-DE Free
Theory:

CMOS COMPOUND GATES:

• These are formed by combining series and parallel structures of transistors.
• There are two important subsets of the general complex CMOS gate topology.
(1) AND-OR-INVERT (AOI): It enables the sum-of-products realization of a
Boolean function in one logic stage. The pull-down net of the AOI gate consists of
parallel branches of series-connected nMOS driver transistors and the
corresponding p-type pull-up network can simply be found using the dual-graph
concept.
(2) OR – AND-INVERT (OAI): It enables the product-of-sums realization of a
Boolean function in one logic stage. The pull-down net of the OAI gate consists of
series branches of parallel-connected nMOS driver transistors. The corresponding
p-type pull-up network can be found using the dual-graph concept.

CMOS MUX
• 2:1 multiplexer chooses output between two inputs

D0 0
Y
D1 1

Fig 8.1: Symbol of 2:1 Multiplexer

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4:1 MULTIPLEXER:

Fig 8.2: Circuit Diagram of 4*1 Multiplexer

Truth Table:
S0 S1 Y
0 0 I0
0 1 I1

1 0 I2
1 1 I3

4:1 MUX using 2:1 MUX

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Fig. 8.3: Block Diagram of 4:1 MUX using 2:1 MUX

Output:
RTL Schematic: Y = AB (C+D)

Fig. 8.4: Schematic Diagram of Y = AB (C+D)

Simulation Result:

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Fig. 8.5: Simulation waveform of Y = AB (C+D)

Y= A+B(C+D)

RTL Schematic: Y= A+B(C+D)

Fig. 8.6: Schematic Diagram of Y = A+B(C+D)

Simulation Result:

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Fig. 8.7: Simulation waveform of Y = A+B(C+D)

4*1 Mutiplexer:
2*1 MUX:

Schematic Diagram:

Fig. 8.8: Schematic Diagram of 2:1 MUX

Symbol:

Fig. 8.9: Symbol of 2:1 MUX

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4*1 MUX:

Fig. 8.10: Schematic Diagram of 4:1 MUX using 2:1 MUX

Simulation Result:

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Fig. 8.11: Simulation waveform of 4:1 MUX using 2:1 MUX

Result: We have designed and simulate Boolean expression using Symica DE free.
Truth table was also verified with simulation waveform. Also 4*1 multiplexer was also
designed with the help of 2*1 multiplexer. Truth table was also verified with waveform.

Discussion:
1. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output
is?
2. When both nMOS and pMOS transistors of CMOS logic design are in OFF
condition, the output is?

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EXPERIMENT-9
AIM: Design and simulate half adder and full adder using CMOS Technology.

Tools Used: Symica-DE Free

Theory:
An adder is a digital circuit that performs addition of numbers. In many computers and
other kinds of processors adders are used in the arithmetic logic units or ALU.

Half Adder:

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and
carry (C). The carry signal represents an overflow into the next digit of a multi-digit
addition.

Fig. 9.1: Block Diagram Truth Table and Circuit Diagram of Half adder

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Fig.9.2: CMOS Circuit of Half Adder

FULL ADDER:

A full adder adds binary numbers and accounts for values carried in as well as out. A
one-bit full-adder adds three one-bit numbers, often written as A, B, and Cin; A and B are
the operands, and Cin is a bit carried in from the previous less-significant stage. The
circuit produces a two-bit output. Output carry and sum typically represented by the
signals Cout and S. A full adder can be implemented in many different ways such as with a
custom transistor-level circuit or composed of other gates.

Fig.9.3: Block Diagram of Full adder

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Full Adder using Half Adder:

Fig.9.4 Block Diagram of Full adder using Half adder

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Output:

Schematic Diagram:

Fig.9.5: Schematic Diagram of Half adder

Symbol:

Fig.9.6:Symbol of Half adder

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Test circuit:

Fig.9.7: Test Circuit of Half adder

Simulation Result:

Fig.9.8: Simulation Waveform of Half adder

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Full Adder:

Schematic Diagram:

Fig.9.9: Schematic Diagram of Full adder

Simulation Result:

Fig.9.10: Simulation waveform of Full adder

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Result: We have designed and simulate half adder and full adder using Symica DE free.
Truth table was also verified with simulation waveform. Truth table was also verified
with waveform.

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EXPERIMENT-10
AIM: Design and simulate SR flip flop using CMOS Technology.
.
Tools Used: Symica-DE Free

Theory:
A flip-flop or latch is a circuit that has two stable states and can be used to store state
information – a bistable multivibrator. The circuit can be made to change state
by signals applied to one or more control inputs and will have one or two outputs. It is the
basic storage element in sequential logic. Flip-flops and latches are fundamental building
blocks of digital electronics systems used in computers, communications, and many other
types of systems.

Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or

"delay”), T ("toggle"), and JK. The behavior of a particular type can be described by
what is termed the characteristic equation, which derives the "next" (i.e., after the next
clock pulse) output, Qnext in terms of the input signal(s) and/or the current output, Q.

The SR Latch – Using NOR Gate Circuit diagram and Truth Table:

Fig. 10.1: Block Diagram, Circuit Diagram and Truth Table of SR Flip
Flop using NOR gate

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The SR Latch – Using NAND Gatecircuit diagram and Truth table

Fig.10.2: Block Diagram, Circuit Diagram and Truth Table of SR Flip

Flop using NAND gate

Clocked SR Latch
The figure shows a NOR-based SR latch with a clock added. The latch is responsive to
inputs S and R only when CLK is high.

Fig. 10.3: Circuit Diagram of Clocked SR Latch

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When CLK is low, the latch retains its current state. Observe that Q changes state −

 When S goes high during positive CLK.

 On leading CLK edge after changes in S & R during CLK low time.
 A positive glitch in S while CLK is high
 When R goes high during positive CLK.

Fig. 10.4: CMOS Diagram of Clocked SR Latch

CMOS AOI implementation of clocked NOR based SR latch is shown in the figure.
When CLK is low, two series terminals in N tree N are open and two parallel transistors
in tree P are ON, thus retaining state in the memory cell.

 When clock is high, the circuit becomes simply a NOR based CMOS latch which
will respond to input S and R.

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Output:
Schematic Diagram:

Fig. 10.5: Schematic Diagram of Clocked SR Latch

Simulation Result:

Fig. 10.6: Simulation waveform of Clocked SR Latch

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Result: We have designed and simulate a SR flip flop using CMOS technology on
symica DE free. Functionality of circuit was verified from waveform.

Discussion:
1. Gated S-R flip-flops are called asynchronous because the output responds
immediately to input changes.
2. Which of the following is not generally associated with flip-flops?
3. Edge-triggered flip-flops must have?
4. What is one disadvantage of an S-R flip-flop?
5. An invalid condition in the operation of an active-HIGH input S-R latch occurs
when ?

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EXPERIMENT-11
AIM: Design and simulate any DRAM cell.

Tools Used: Symica-DE Free

Theory:
Dynamic random-access memory (DRAM) is a type of semiconductor memory that is
typically used for the data or program code needed by a computer processor to
function. DRAM is a common type of random access memory (RAM) that is used in
personal computers (PCs), workstations and servers.

Fig. 11.1: Circuit diagram of DRAM cell

Write Operation of 1T DRAM cell

• The "data write" operation on the 1-T cell is quite straightforward.
• For the write "1“operation, the bit line (D) is raised to logic " 1 " by the write
circuitry, while the selected word line is pulled high by the row address decoder.
• The access transistor Ml turns on, allowing the storage cap. C1 to charge up to a
logic-1 level.
• For the write “0“operation, the bit line (D) is pulled to logic “0" and the word
line is pulled high by the row address decoder.
• In this case, the storage capacitor C discharges through the access transistor,
resulting in a stored “0" bit.

Read Operation of 1T DRAM cell

• For reading of stored data from 1-T DRAM cell, a elaborative read-refresh circuit
is required due to the fact that the "data read" operation need a "destructive readout”. It
means that the stored data must be destroyed or lost during the read operation.
• Typically, the read operation starts with pre-charging the column capacitance C2.
• Then, the word line is pulled high in order to activate the access transistor Ml.
• Charge sharing between C1 and C2occurs and, depending on the amount of stored
charge on C1, the column voltage either increases or decreases slightly. It

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destroys the stored charge on C1. SO, we also have to refresh data every timefor
each "data read" operation.

Output:
Schematic Diagram:

Fig. 11.2: Schematic Diagram of DRAM cell

Simulation Result:

Fig. 11.3: Simulation waveform of DRAM cell

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Result: We have designed a simulate a DRAM cell using Symica DE free.

Discussion:
3. Which memory storage is widely used in PCs and Embedded Systems?
4. Which of the following is more volatile?
5. Which one of the following is a storage element in SRAM?
6. Which of the following memory technology is highly denser?
7. What is the size of a trench capacitor in DRAM?

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Experiment B1

AIM: Design and simulate 16*1 mux using different modeling styles in
VHDL.

Tools Used: Xilinx ISE 14.4, Xilinx Vivado

Theory:
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection
lines and single output line. One of these data inputs will be connected to the output
based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and
ones. So, each combination will select only one data input. Multiplexer is also called
as Mux.
A 16x1 mux can be implemented using 5 4x1 MUX. 4 of these multiplexers can be used
as first stage to mux 4 inputs each with two least significant bits of select lines (S0 and
S1), resulting in 4 intermediate outputs, which, then can be MUX again using a 4:1 mux.

Fig B1.1 Block diagram and Truth Table of 4:1 MUX

VHDL CODE FOR 4:1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
port (i : in std_logic_vector (3 downto 0);
s : in std_logic_vector(1 downto 0);
y: out std_logic);
end mux4;

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architecture Behavioral of mux4 is

begin
process(i,s)
begin
case s is
when "00" => y <= i(0);
when "01" => y <= i(1);
when "10" => y <= i(2);
when others => y <= i(3);
end case;
end process;
end Behavioral;

Fig.B1.2 :16:1 MUX using 4:1 MUX

VHDL CODE FOR 16:1 MUX

library IEEE;
entity mux16 is
port(a:instd_logic_vector(15 downto 0);
s: in std_logic_vector(3 downto 0);
z:out std_logic);
End mux16;

Architecture str of mux16 is

signal x: std_logic_vector(3 downto 0);
component mux4 is
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port (i : in std_logic_vector(3 downto 0);

s : in std_logic_vector(1 downto 0);
y: out std_logic);
End component;
Begin
L0:mux4 port map (a(15 downto 12), s(1 downto 0), x(3));
L1:mux4 port map (a(11 downto 8), s(1 downto 0), x(2));
L2:mux4 port map (a(7 downto 4), s(1 downto 0), x(1));
L3:mux4 port map (a(3 downto 0), s(1 downto 0), x(0));
L4:mux4 port map (x, s(3 downto 2), z);
End str;

Output:
Schematic Diagram:

Fig. B1.3: Schematic Diagram of 16:1 MUX using 4:1 MUX

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Simulation Result:

Fig. B1.4: Simulation Waveform of 16:1 MUX using 4:1 MUX

Result: We have designed VHDL code for 16*1 multiplexer using 4*1 multiplexer
and simulated waveforms have been observed. For this Software and Hardware
realisation is done through Xilinx ISE and NEXYS 4DDR. VHDL code Simulation
results are shown in the form of waveforms. Values are forced through user.
Functionality of circuit is verified through simulation result. Simulation result is verified
on hardware (NEXYS 4DDR kit), where output show in form of LED after applying
particular input on button on NEXYS 4DDR.

Discussion:
1. How is an encoder different from a decoder?
2. For 8-bit input encoder how many combinations are possible?
3. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
4. How many data select lines are required for selecting eight inputs?

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Experiment B2

AIM: Design and simulate S-R Flip flop using VHDL

Tools Used: Xilinx ISE 14.4, Xilinx Vivado

Theory:
S R Flip Flop:

The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic
sequential logic circuit possible. This simple flip-flop is basically a one-bit memory
bistable device that has two inputs, one which will “SET” the device (meaning the output
= “1”), and is labelled S and one which will “RESET” the device (meaning the output =
“0”), labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to
its original state with an output Q that will be either at a logic level “1” or logic “0”
depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back
to its opposing inputs and is commonly used in memory circuits to store a single data bit.
Then the SR flip-flop actually has three inputs, Set, Reset and its current output Q relating
to it’s current state or history. The term “Flip-flop” relates to the actual operation of the
device, as it can be “flipped” into one logic Set state or “flopped” back into the opposing
logic Reset state.

Fig.B2.1: Symbol of S R Flip Flop

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Fig. B2.2 Circuit Diagram of S R Flip Flop

VHDL CODE
library ieee ;
use ieee.std_logic_1164.all;
entity srff is
Port(reset,clock,s,r : in std_logic;
q: out std_logic );
end srff;
architecture behv of srff is
Signal FF: std_logic:=‘0’;
begin
process(clock,reset)
variable sr: std_logic_vector(0 to 1);
begin
If (reset=‘1’) then --negative logic
FF<=‘0’;
-- clock negative edge
elsif (clock=‘0' and clock' event) then
sr := s & r;
case sr is
when "01" => FF <= ’0’;
when "10" => FF <= ’1’;
when "11" => FF <= ’Z’;
when others => FF <= FF;
end case;
end if;
end process;
Q<= FF;
end behv;

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Output:
Schematic Diagram:

Fig. B2.3: Schematic Diagram of SR Flip Flop

Simulation Result:

Fig. B2.4: Simulation Result of SR Flip Flop

Result:We have designed VHDL code for SR flip flop and simulated waveforms have
been observed. For this Software and Hardware realisation is done through Xilinx ISE
and NEXYS 4DDR. VHDL code Simulation results are shown in the form of
waveforms. Values are forced through user. Functionality of circuit is verified through
simulation result. Simulation result is verified on hardware (NEXYS 4DDR kit), where
output show in form of LED after applying particular input on button on NEXYS
4DDR.

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Discussion:
1. When both inputs of a J-K flip-flop cycle, the output will?
2. Which of the following is correct for a gated D-type flip-flop?
3. The logic circuits whose outputs at any instant of time depends only on the present
input but also on the past outputs are called?
4. In S-R flip-flop, if Q = 0 the output is said to be? The output of latches will
remain in set/reset until?

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