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UVM Interview Questions 1705926124

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143 views

UVM Interview Questions 1705926124

Uploaded by

pbmk2105
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Universal Verification

Methodology

Interview Questions
Presenting by
Chanda Prasanthi
UVM ASSIGNMENT
What is mean by TLM Port ? Explain different types of TLM Ports.
What type of Interface is used to connect one component to multiple
component? Explain with a code.
What is the difference between Port, Export, Implementation Port ?
Explain how communication can be established between Producer &
Consumer
When Producer as an Initiator & Consumer act as a target
When Producer as an target & Consumer act as a initiator
When both Producer & Consumer are initiators
When both Producer & Consumer are target, Is it possible to be as a
target both? If not justify it
UVM ASSIGNMENT
What is the difference between create(), new()? Why do we use create() in
UVM ?
Is it necessary to create components, objects using factory register concept?
Explain the advantage of it.
What is the difference between component, object ? and How to register
using factory ?
What is the difference between Instance Override & Global override ? Given
an example with a code.
What are the Virtual methods in UVM ?
What is the need of Reporting Mechanism ?
How can we filter the messages in UVM ?
UVM ASSIGNMENT
What is the method used to perform an action based on severity, based on
report_id ?
What are the default actions for UVM_error, UVM_fatal ?
How can you enable or disable the scoreboard ?
How can you configure the Active agent, Passive agent ?
What are the arguments you need to pass to set a value in the config
database, and get the value from config database ?
What are the different phases in UVM, Explain each.
Which phase refers to the function and which phase is the task?
How can you start a UVM phase?
Can we have a user-defined phase in UVM?
UVM ASSIGNMENT
Explain the data flow & Connection between Sequence, Sequencer, Driver
Explain the different methods involved in the body task of sequence and run
phase of driver
What is the difference between `UVM_do, `UVM_do_with macros
How to set any particular sequence as a default sequence ?
Why do we need Virtual Sequence, Virtual Sequencer ?
What is the difference between m_sequence, p_sequence ?
How can you connect a Virtual Sequencer with a physical sequencer, Explain
an example code.
What is the difference between Adapter, Predictor ?
What contains in Register Map, Draw the register map by considering a
simple design
UVM ASSIGNMENT
What is the difference between Front door access, Back door access ?
What are different Adapter methods ?
What is the difference between peek(), poke(), write(), read() methods.

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