____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________

Confidential
Security C

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ERC Usage

lI
PDKD/TSMC

tia 4 IS
Version1.3 Oct. 2008

en 69 OS
fid 85 I/M 010
on 3 IS /2
/ 0
C
C SC /3
M 10
U
TS

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P.PDKD
P.0 0
____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

What is ERC (Electrical Rule Checking)

TS
M
C
z ERC is a special option for designers. Some errors can be

C
waived, but others may be fatal errors. So, designers MUST

on 3 IS /2
review every error or warning for LVS/ERC report.

fid 85 I/M 010

z Some ERC rules are included in TSMC official LVS command

en 69 OS
SC /3
files.

tia 4
„ Soft connect checking (mainly for nwell or psub)

/
10

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„ Path checking

nf
„ Ptap / ntap checking 0

or
„ MOS s/d power&ground checking

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at
„ Gate directly connecting to power or ground.

IS

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„ Floating gate

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„ Floating well

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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential

Soft-connection and Soft-check Security C

TS
M
z N-well and P-well are high resistor materials

C
C
on 3 IS /2
1. Treat as Short
SigB Sig A connect to Sig B

fid 85 I/M 010

SigA
--> If Sig A is a power line and Sig B connect to a IP power.

en 69 OS
--> The IP get a high resistor power, it means IR drop is very

SC /3
serious.

tia 4
----> ERROR
METAL 1

/
10

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2. Treat as open

nf
Sig A does not connect to Sig B
N-Well --> If Sig A is a power signal and sig B is ground signal
0

or
tndiff --> power and ground short

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--->ERROR

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IS

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¾ There are two methods to solve this problem
ƒ Run two LVS command file, one is “ treat as short”, the other is “treat as open”.
ƒ Use soft connect commands and do soft check!!!

P. 2
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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

TS
What is Soft-connection and Soft-checking

M
C
z Soft-connection definition:

C
on 3 IS /2
„ Passes established connectivity from the upper layer polygons onto the
specified lower layer polygons ( one-directional )

fid 85 I/M 010

< adopt by Calibre tool manual >

en 69 OS
z Soft-check:

SC /3

tia 4
/
„ Help designers to search which contact connects to WELL
10

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nf
z ERC results:
0

or
„ TSMC LVS/ERC command files contain those options and those errors/warnings

m
are reported in <lvs.rep> or <lvs.rep.ext>

at
IS
„ Please confirm every error or warning of those three file <~.rep>/<~.rep.ext>/
<svdb/~.rep>

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„ Give user a warning on the <lvs.rep.ext> file. User can debug this error by

n
“calibre -rve” and open the <svdb/~.softchk> file .

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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

TS
Device Path Check

M
C
C
on 3 IS /2
z Purpose

fid 85 I/M 010

„ Help designers to check if the circuit misses something.

en 69 OS
z Four kinds of path checking

SC /3

tia 4
„ Nodes with a path to power but not ground

/
10
Nodes with a path to ground but not power

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„

nf
„ Nodes without a path to both path and ground
Nodes without a path to pin 0

or
„

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VDD

at
IS

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in out

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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

Pathchk Report (svdb/~.Rep)

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nf
lI
tia 4 IS
en 69 OS
fid 85 I/M 010
on 3 IS /2
/ 0
C
C SC /3
M U 10
TS

55
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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

TS
ERC Steps and Reports

M
C
C
z Get ERC report in LVS stage.

on 3 IS /2
z Calibre :

fid 85 I/M 010

„ % calibre –lvs –spi layout.net calibre_rule_deck

en 69 OS
„ For Calibre, please check the “calibre_erc.db” and “calibre_erc.sum” files.

SC /3

tia 4
„ And please find whether it has soft_check warnings in “<lvs.rep>.ext” report.

/
10

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z Hercules :

nf
„ % hercules hercules_rule_deck
0

or
„ For Hercules, please check the “<Top>.LAYOUT_ERRORS” file.

m
at
z Assura :

IS

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„ %> assura LVS.rsf | tee lvs.log

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„ For Assura, please check the “<Top>.err” file.

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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

PTAP/NTAP/Special MOS Connectivity Check

TS
M
C
z PTAP connects to power or NTAP connects to ground.

C
on 3 IS /2
„ Check ERC errors of “PPVDD49” for PTAP.
„ Check ERC errors of “NPVSS49” for NTAP.

fid 85 I/M 010

z For N /P MOS, one of source/drain connects to POWER and the other

en 69 OS
SC /3
connects to ground.

tia 4
/
„ Check ERC errors “mppg” for PMOS.
10

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„ Check ERC errors “mnpg” for NMOS.

nf
„ We can check MOS types included : CORE/IO/HVD(above 45/65nm), not included
0

or
SRAM/VARACTOR/RF devices.

m
z For Calibre, please check the “calibre_erc.db” and “calibre_erc.sum” files.

at
IS

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VDD
z For Hercules, please check the “<Top>.LAYOUT_ERRORS” file.

n
z For Assura, please check the “<Top>.err” file.

P. 7 VSS
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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

Gate Directly Connect to Power/Ground

TS
M
C
z PMOS gates directly connects to POWER w/o the 2.5v and 3.3v IO

C
devices.

on 3 IS /2
„ For ESD protection, if core or 1.8v PMOS gates directly connects to POWER node, gates will
be damaged.

fid 85 I/M 010

„ Check ERC errors “ppvdd150” for PMOS gates.

en 69 OS
SC /3

tia 4
z NMOS gates directly connects to GROUND w/o the 2.5v and 3.3v IO

/
10

lI
devices.

nf
„ For ESD protection, if core or 1.8v NMOS gates directly connects to GROUND node, gates
will be damaged.
0

or
„ Check ERC errors “npvss150” for NMOS gates.

m
at
z For Calibre, please check the “calibre_erc.db” and “calibre_erc.sum” files.

IS

io
z For Hercules, please check the “<Top>.LAYOUT_ERRORS” file.

n
z For Assura, please check the “<Top>.err” file.

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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

Floating Gate

TS
M
C
C
z Before version 1.3b, we will check floating gate in ERC check

on 3 IS /2
section, but DRM already covered this check rule, after version

fid 85 I/M 010

1.4a we will not support this rule checking any more.

en 69 OS
z Please refer rule “PO.R.8” in N65 DRM document T-N65-LO-DR-

SC /3

tia 4
001 for floating gate types.

/
10

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nf
0

or
m
at
IS

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P. 9
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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

Floating Well

TS
M
C
C
z There is no POWER or GROUND node information connecting to

on 3 IS /2
NWELL or P-SUBSTRATE.

fid 85 I/M 010

„ Check ERC errors “floating.nxwell” for NWELL.

en 69 OS
„ Check ERC errors “floating.psub” for PSUB.

SC /3

tia 4
/
10

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z For Calibre, please check the “calibre_erc.db” and “calibre_erc.sum”

nf
0

or
files.

m
z For Hercules, please check the “<Top>.LAYOUT_ERRORS” file.

at
IS
z For Assura, please check the “<Top>.err” file.

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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential

Layout Example Security C

TS
M
N-IMP

C
C
on 3 IS /2
fid 85 I/M 010
U

en 69 OS
SC /3

tia 4
/
10 NWELL

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nf
DIFF
0

or
~.sum ~.ext

m
---------------------------------------------------------------------------

at
IS
--- RULECHECK RESULTS STATISTICS
WARNING: Stamping conflict in SCONNECT -
---

io
RULECHECK mppg .... TOTAL Result Count = 1 Multiple source nets stamp one target net.

n
RULECHECK mnpg .... TOTAL Result Count = 0 Use LVS REPORT OPTION S or LVS
RULECHECK ppvdd49 ... TOTAL Result Count = 0 SOFTCHK statement to obtain detailed information.
RULECHECK npvss49 ... TOTAL Result Count = 1
----------------------------------------------------------------------------
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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C
Hercules ERC Check Error File

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z Please check the Top.LAYOUT_ERRORS file.

tia 4 IS
en 69 OS
fid 85 I/M 010
on 3 IS /2
/ 0
C
C SC /3
M 10 U
TS

12
12
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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential

Assura ERC Check Error File Security C

TS
M
z Please check the Top.err file.

C
C
z Currently the Assura can not support the net-path check function.

on 3 IS /2
fid 85 I/M 010
U

en 69 OS
SC /3

tia 4
/
10

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nf
0

or
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at
IS

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P. 13
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____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
Confidential
Security C

TS
Summary for ERC checker

M
C
C
z Please confirm every error or warning of these three files

on 3 IS /2
--- “~.rep” “~.rep.ext” “svdb/~.rep” for Calibre.

fid 85 I/M 010

z Please confirm the <Top>.LAYOUT_ERRORS file for Hercules.

en 69 OS
SC /3
z Please confirm the <Top>.err file for Assura.

tia 4
/
10

lI
z Every soft connect error must be fixed.

nf
z Other ERC errors/warnings need to be reviewed by circuit
0

or
designers.

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IS

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P. 14
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