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ASIC

asic

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ramthaku18
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11 views

ASIC

asic

Uploaded by

ramthaku18
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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what are the differences between SIMULATION and SYNTHESIS

Simulation <= verify your design.


synthesis <= Check for your timing
Simulation is used to verify the functionality of the circuit.. a)Functional
Simulation:study of ckt's operation independent of timing parameters and gate
delays. b) Timing Simulation :study including estimated delays, verify setup,hold
and other timing requirements of devices like flip flops are met.
Synthesis:One of the foremost in back end steps where by synthesizing is nothing
but converting VHDL or VERILOG description to a set of primitives(equations as in
CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the
synthesis tools convert the design description into equations or components

Can u tell me the differences between latches & flipflops?

There are 2 types of circuits:


1. Combinational
2. Sequential

Latches and flipflops both come under the category of "sequential circuits", whose
output depends not only on the current inputs, but also on previous inputs and
outputs.

Difference: Latches are level-sensitive, whereas, FF are edge sensitive. By edge


sensitive, I mean O/p changes only when there is a clock transition.( from 1 to 0,
or from 0 to 1)

Example: In a flipflop, inputs have arrived on the input lines at time= 2 seconds.
But, output won't change immediately. At time = 3 seconds, clock transition takes
place. After that, O/P will change.
Flip-flops are of 2 types:
1.Positive edge triggered
2. negative edge triggered

1)fllipflops take twice the nymber of gates as latches


2) so automatically delay is more for flipflops
3)power consumption is also more

latch does not have a clock signal, whereas a flip-flop always does.
What is slack?

The slack is the time delay difference from the expected delay(1/clock) to the
actual delay in a particular path.
Slack may be +ve or -ve.

Equivalence between VHDL and C?

There is concept of understanding in C there is structure.Based upon requirement


structure provide facility to store collection of different data types.

In VHDL we have direct access to memory so instead of using pointer in C (and


member of structure) we can write interface store data in memory and access it.

RTL and Behavioral

Register transfer language means there should be data flow between two registers
and logic is in between them for end registers data should flow.
Behavioral means how hardware behave determine the exact way it works we write
using HDL syntax.For complex projects it is better mixed approach or more
behavioral is used.

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Interview Questions
* Define setup window and hold window ?
* What is the effect of clock skew on setup and hold ?
* In a multicycle path, where do we analyze setup and where do we analyze hold ?
* How many test clock domains are there in a chip ?
* How enables of clock gating cells are taken care at the time of scan ?
* Difference between functional coverage and code coverage ?
* Does 100% code coverage means 100% functional coverage & vice versa?
* What do you mean by useful skew ?
* What is shift miss and capture miss in transition delay faults ?
* What is the structure of clock gating cell ?
* How can you say that placing clock gating cells at synthesis level will reduce
the area of the design ?
* How will you decide to insert the clock gating cell on logic where data enable is
going for n number of flops
* What is the concept of synchronizers ?
* What are lockup latches?
* What is the concept of power islands ?
* What does OCV, Derate and CRPR mean in STA ?
* What is dynamic power estimation ?
* On AHB bus which path would you consider for worst timing ?
* What is the difference between blocking & non-blocking statements in verilog ?
* What are the timing equations for setup and hold, with & without considering
timing skew ?
* Design a XOR gate with 2-input NAND gates
* Design AND gate with 2X1 MUX
* Design OR gate with 2X1 MUX
* Design T-Flip Flop using D-Flip Flop
* In a synchronizer how you can ensure that the second stage flop is getting
stabilized input?
* Design a pulse synchronizer
* Calculate the depth of a buffer whose clock ratio is 4:1 (wr clock is fatser than
read clock)
* Design a circuit that detects the negedge of a signal. The output of this circuit
should get deasserted along with the input signal
* Design a DECODER using DEMUX
* Design a FSM for 10110 pattern recognition
* 80 writes in 100 clock cycles, 8 reads in 10 clock cycles. What is the minimum
depth of FIFO?
* Why APB instead of AHB ?
* case, casex, casez if synthesized what would be the hardware
* Define monitor functions for AHB protocol checker
* What is the use of AHB split, give any application
* Can we synchronize data signals instead of control signals ?

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