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Apb Interview Question

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121 views

Apb Interview Question

Uploaded by

gopi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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APB Protocol

1. Why APB instead of AHB?


The APB is simpler than the AHB. APB is sometimes optimized for reduced
interface complexity andminimal power consumption for supporting
peripheral functions.

2. Difference between APB and AHB


AHB stands for Advanced High-performance Bus and APB sands for
Advanced Peripheral Bus. AHBuses a full duplex parallel communication
whereas the APB uses massive memory-I/O accesses.When comparing the
usage, the APB is simpler than the AHB. APB has no pipelining. The APB
ismainly proposed for connecting to simple peripherals. The APB comes with
a low power peripheral.AHB has a single edge clock protocol, several bus
masters, split transactions, single-cycle bus masterhandover, burst
transfers, large bus widths and non-tristate implementation.In AHB, the
transaction consists of an address phase and a data phase. In case of AHB,
there is onlyone Bus master at a time. But APB is only used for low
bandwidth control accesses. Though the APBhas an address phase and data
phase as like that of the AHB, it comes with a list of low complexitysignal.

Why is there no wait signal on the APB?


Applies to: APB
Answer
The APB has been designed to implement as simple an interface as possible.
Having this simple design makes it much easier to connect new APB
peripherals and makes the analysis of the system performance easier to
calculate.
Although many APB peripherals are slow devices, such as UARTs, they are
normally accessed via control registers. Typically the driver software will first
access a status register to determine that data is available and only then
access the data register. Both of these accesses are possible without the
addition of wait states and therefore the peripheral can easily be accessed as
an APB device.
Peripherals which do require wait states can be designed as AHB slaves and
in the rare case that a design does include a large number of these
peripherals then a secondary stub AHB can be used to reduce the loading on
the main system bus.

For APB usage, Does APB allow connection with different data
width? means Narrow/Wide APB master point connects to
Wide/Narrow APB peripherals.
You can connect APB device with differing data bus widths to a common APB
master, but as the APB protocol does not have any "size" signal, accesses
from the APB master will be accessing the full width of the APB data bus.

So if you had a 32-bit data bus, and a 16-bit APB device, if the registers in
that device were aligned to 2-byte addresses (to match that the peripheral
contains 16-bit registers), an APB access from the master would then read
or write to 2 adjacent registers in that peripheral

Using the latest APB protocol, APB4, this does have a PSTRB signal
that declares which bytes on the data bus are being written to, so that
would ensure only the relevant "narrow" register is being accessed, but
these aren't used for read accesses, so you could accidentally corrupt
read sensitive registers if 2 registers are accessed by one APB
master transfer.

What you can do is align the peripheral registers to addresses that are target
system data bus width aligned, so in my example making the 16-bit
peripheral registers all aligned to 4-byte boundaries. Then one APB transfer
will just access one register in the target device.

But that means the peripheral has to be designed for a specific APB data bus
width, although most APB master designs I have seen are 32-bit designs, so
standardising on that width alignment for registers could be the way to
ensure your peripheral would work in typical applications if you want to mix
different individual peripheral data bus widths.

So it is possible, but care has to be taken to ensure the peripheral registers


are aligned according to the APB data bus width.

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