How to display bold characters?

Using following program bold characters can be displayed. Note that this program takes help
of
UNIX facilities. This may not work on PC based simulators.
module bold;
initial begin
$display ("Normal Text");
$display ("\033[1mBold Text");
$display ("\033[mSwitch back to Normal Text.....");
$display ("\033[7mInverse Text.");
$display ("\033[mSwitch back to Normal Text.....");
$display ("\033[1mBold Text \033[mfollowed by \033[7mInverse text
\033[m");
end
endmodule
Sample Verilog Questions asked in Interviews. Please contribute with your questions.
If
you are looking for answers please refer to website Site FAQ
Differentiate between Inter assignment Delay and Inertial Delay.
What are the different State machine Styles ? Which is better ? Explain
disadvantages and advantages.
What is the difference between the following lines of code ?
• reg1<= #10 reg2 ;
• reg3 = # 10 reg4 ;
What is the value of Var1 after the following assignment ?
reg Var1;
initial begin
Var1<= "-"end
In the below code, Assume that this statement models a flop with async reset. In
this, how does the synthesis tool, figure out which is clock and which is reset. Is the
statements within the always block is necessary to find out this or not ?
1 module which_clock (x,y,q,d);
2 input x,y,d;
3 output q;
4 reg q;
5
6 always @ (posedge x or posedge y)
7 if (x)
8 q <= 1'b0;
9 else
10 q <= d;
11
12 endmodule
What is the output of the two codes below ?
1 module quest_for_out();
2
3 integer i;
4 reg clk;
5
6 initial begin
7 clk = 0;
8 #4 $finish;
9 end
10
11 always #1 clk = ! clk;
12
13 always @ (posedge clk)
14 begin : FOR_OUT
15 for (i=0; i < 8; i = i + 1) begin
16 if (i == 5) begin
17 disable FOR_OUT;
18 end
19 $display ("Current i : ‰g",i);
20 end
21 end
22 endmodule
1 module quest_for_in();
2
3 integer i;
4 reg clk;
5
6 initial begin
7 clk = 0;
8 #4 $finish;
9 end
10
11 always #1 clk = ! clk; 12
13 always @ (posedge clk)
14 begin
15 for (i=0; i < 8; i = i + 1) begin : FOR_IN
16 if (i == 5) begin
17 disable FOR_IN;
18 end
19 $display ("Current i : ‰g",i);
20 end
21 end
22 endmodule
Why cannot initial statement be synthesizeable ?
Consider a 2:1 mux; what will the output F be if the Select (sel) is "X" ?
What is the difference between blocking and nonblocking assignments ?
What is the difference between wire and reg data type ?
Write code for async reset D-Flip-Flop.
Write code for 2:1 MUX using different coding methods.
Write code for a parallel encoder and a priority encoder.
What is the difference between === and == ?
What is defparam used for ?
What is the difference between unary and logical operators ?
What is the difference between tasks and functions ?
What is the difference between transport and inertial delays ?
What is the difference between casex and case statements ?
What is the difference between $monitor and $display ?
What is the difference between compiled, interpreted, event based and cycle based
simulators ?
What is code coverage and what are the different types of code coverage that one
does ?
How do I generate clock in Verilog ?There are many ways to generate
clock in Verilog; you could use one of the following
methods:
Method #1
1 initial begin
2 clk = 0;
3 end
4
5 always begin
6 #5 clk = ~clk;
7
8 end
Method #2
1 initial begin
2 clk = 0;
3 forever begin
4 #5 clk = ~clk;
5 end
6 end
Method #3
1 initial begin
2 clk = 0;
3 end
4
5 always begin
6 #5 clk = 0;
7 #5 clk = 1;
8 end
There are many ways to generate clocks: you may introduce jitter, change duty cycle.
How do I test my design xyz ?
To test or verify or validate any design, you need to have a test bench; writing test
benches is as difficult as designing itself. Please refer to the Verilog tutorial section in
"Art of Writing Test Bench" for more details.
What is the difference between wire and reg ?
Please refer to tidbits section for the difference between wire and reg.
What is the difference between blocking and nonblocking
assignment ?Please refer to tidbits section for difference between blocking and
nonblocking statement.
How do I write a state machine in Verilog ?
Please refer to tidbits section for "writing FSM in Verilog".
How do I avoid Latch in Verilog ?
Latches are always bad (I don't like that statement); latches are caused when all the
possible cases of assignment to variable are not covered. Well this rule applies to
combinational blocks (blocks with edge sensitive lists are sequential blocks); let's
look at
the following example.
Bad Code
1 always @ (b or c)
2 begin
3 if (b) begin
4 a = c;
5 end
6 end
In the code above, value of a is retained, and it gets changed only when b is set to '1'.
This
results in a latch. (Need to phrase it right)
Good Code #1
1 always @ (b or c)
2 begin
3 a = 0;
4 if (b) begin
5 a = c;
6 end
7 end
In the code above, no matter what the value of b is, a gets value of '0' first and if b is
set
to '1' and c is set to '1', only then a gets '1'. This is the best way to avoid latches.
Good Code #2
1 always @ (b or c)
2 begin
3 if (b) begin
4 a = c;
5 end else begin
6 a = 0;
7 end
8 endIn the above code, all the possible cases are covered (i.e. b = 1 and b = 0 case).
How does this xyz code get synthesized ?
Well it is a long story; let me cover that in the synthesis part of Verilog tutorial. You
can
refer to Actel HDL coding Style. One simple logic is: any code inside always blocks
with
edge sensitive sensitivity list, results in flip-flops and assign; inside level sensitive
always
blocks results in combo logic.
How do I implement Memories in Verilog ?
You can implement them by declaring 2-dimension arrays. More details can be found
in
the Verilog tutorial section "Modeling memories and FSM".
How do I read and write from a file ?
To Read from a file we use $readmemh, where h stands for hex decimal. For writing
we
use $writememh, $fdisplay, $fmonitor. You could refer to the Verilog tutorial section
for
more details.
What is this `timescale compiler directive ?
`timescale is used for specifying the reference time unit for the simulator. Syntax of
the
`timescale is as below:
`timescale <reference_time_unit>/<time_precision>
example : `timescale 10ns/1ns
Timescale directive tends to make more sense at gatelevel simulation than at RTL
simulation.
Can we mix blocking and nonblocking in one always block ?
Yes, we can have both blocking and nonblocking code in same always block. Some
things that one should know to use this are:
• Blocking assignments are treated as combinational logic.
•
One should not assign a variable in the same always block with both blocking and
nonblocking assignments.
• Not all synthesis tools support this. (Design compiler supports this).What is the
output of AND gate in the circuit below, when A and B are as in
waveform? Tp is the gate delay of respective gate.
Identify the circuit below, and its limitation.
What is the current through the resistor R1 (Ic) ?Referring to the diagram below,
briefly explain what will happen if the propagation
delay of the clock signal in path B is much too high compared to path A. How do we
solve this problem if the propagation delay in path B can not be reduced ?
What is the function of a D flip-flop, whose inverted output is connected to its
input ?
Design a circuit to divide input frequency by 2.
Design a divide-by-3 sequential circuit with 50% duty cycle.Design a divide-by-5
sequential circuit with 50% duty cycle.
What are the different types of adder implementations ?
Draw a Transmission Gate-based D-Latch.
Give the truth table for a Half Adder. Give a gate level implementation of it.
What is the purpose of the buffer in the circuit below, is it necessary/redundant to
have a buffer ?
What is the output of the circuit below, assuming that value of 'X'

How to model Transport and Inertial Delays in Verilog?

Author : Rajesh Bawankule
Following simple example can illustrate the concept.
module delay(in,transport,inertial);
input in;
output transport;
output inertial;
reg transport;
wire inertial;
// behaviour of delays
always @(in)
begin
transport <= #10 in;
end
assign #10 inertial = in;
endmodule // delay
The timing Diagram for input and outputs
_______ __
in _____| |_____||_______
_______ __
transport _________| |_____||_____
_______
inertial _________| |____________
Non blocking assignment gives you transport delay. Whenever input changes, output is
immediately evaluated and kept in a event queue and assigned to output after specified
"transport" delay.
In Continuous assign statement the latest event overrides the earlier event in the queue.
I am attaching rudimentary testbench and its output. Hope this helps.
module test;
reg in;
wire transport, inertial;
// instantiate delay module
delay my_delay(in,transport,inertial);
// apply inputs
initial
begin
in = 0; #20 in = 1;
#20 in = 0;
#30 in = 1;
#5 in = 0;
#30 in = 1;
#30 $finish;
end
// monitor signals
initial
begin
$monitor($time," in = %b transport = %b inertial = %b",
in,transport, inertial);
end
endmodule // test
log file
Compiling source file "delay.v"
Highest level modules:
test
0 in = 0 transport = x inertial = x
10 in = 0 transport = 0 inertial = 0
20 in = 1 transport = 0 inertial = 0
30 in = 1 transport = 1 inertial = 1
40 in = 0 transport = 1 inertial = 1
50 in = 0 transport = 0 inertial = 0
70 in = 1 transport = 0 inertial = 0
75 in = 0 transport = 0 inertial = 0
80 in = 0 transport = 1 inertial = 0
85 in = 0 transport = 0 inertial = 0
105 in = 1 transport = 0 inertial = 0
115 in = 1 transport = 1 inertial = 1
L35 "delay.v": $finish at simulation time 135
81 simulation events
How to display the system date in $display or $write?
(Answers contributed by Swapnajit Mittra and Noman Hassan)
Support of $system() task in Verilog-XL, NC-Verilog and VCS not only allows you to display
the
system date but also gives you the ability to call any command that you would normally type
on
the UNIX prompt (C executable, script, standard UNIX command etc.), and would make
sense in
executing from within Verilog source code.
$system is not an IEEE Standard(1364-1995), but is supported by both XL and VCS.
You could read back in the output of $system, by writing it to another file and reading it back
in
using $readmemh() as illustrated in following example.
module top;
reg [23:0] today [0:1];initial
begin
$system("date +%m%d%y > date_file");
// output is 073199 for july 31st 1999
$readmemh("date_file", today);
$display("Today is: %x", today[0]);
end
endmodule

Synthesis Interview Questions

 What are the various factors that need to be

considered while choosing a technology library for a
design?

 When stated as 0.13μm CMOS technology, what

does 0.13 represent?
 What is Synthesis?

 What happens when a process neither has

sensitivity list nor a wait statement?

 Where should you declare the index that is used in

a for loop? What is its visibility?

 What are the three weak strength values in IEEE 9

valued logic?

 What is the difference between a transaction and

an event?

 What is a Moore machine? How is it different from a

Mealy machine?

 Assume that variable a is integer and b is natural.

When are the following statements valid?

a := a + b;
b := a + 3;

 What modeling technique will decompose designs

hierarchically?

 Do variables need time queues?

 Does simulation time advance during delta cycles?

 Is it true that synthesis transformations take less

time at the top abstraction levels?

 Is it true that synthesis transformations give refined

results at the top abstraction levels?

 What will a well formed case statement synthesize

to?

 What will happen to a design that is synthesized

without any constraints?

 Explain what role the Synopsys DesignWare

libraries fulfill in the synthesis process.

 What is the difference between a high level

synthesis tool (as represented by Synopsys
behavioral Compiler) versus a logic synthesis tool (as
represented by Synopsys Design Compiler)?

 Explain what it meant for Synopsys DesignWare

component to be ‘inferred’ by a synthesis tool?

 What are different power reduction techniques?

 How do you perform Synthesis activities in Multi vt

libraries?

 What are the advantages of clock gating?

 One circuit will be given to you, where one of the
inputs X have a high toggling rate in the circuit. What
steps you take to reduce the power in that given
circuit?

 You will be told to realize a Boolean equation. The

next question is how efficient usage of power is
achieved in that crcuit?

 Some circuit will be given to you and will be

instructed to set certain timing exceptions commands
on that particular path.

 What is the difference in PT timing analysis during

post and pre layout designs?

 What you mean by FSM States?

 Draw the timing waveforms for the circuit given?

 What is Setup time and hold time effects on the

circuit behavior while providing different situations?

 What is the difference of constraints file in Pre

layout and post layout?

 What is SPEF? Have you used it? How you can

use it?

 What difference you found (or can find) in the netlist

and your timing behavior, while performing timing
analysis in pre layout and post layout?

 What is clock uncertainty, clock skew and clock

jitter?

 What is the reason for skew and jitter?

 What is clock tree synthesis?

 What are the timing related commands with respect

to clock?

 In front end, you set ideal network conditions on

certain pins/clocks etc. Why? In Back end how is it
taken care?

 Which library you have used?

 What difference you (can) find in TSMC and IBM

libraries?

 Draw the LSSD cell structure in TSMC and IBM

libraries?

 Every tool has some drawbacks? What drawbacks

you find in Prime time?

 What are the difference you find when you switch

from 130nm to 90nm?

 Explain the basic ASIC design flow? Where your

work starts from? What is your role?

 What is 90nm technology means?

 What are the issues you faced in your designs?

 Perform the setup and hold check for the given

circuit.

 Why setup and hold required for a flop?

 You had any timing buffer between synthesis and

P&R? How much should be the margin?

 What are the inputs for synthesis and timing

analysis from RTL and P&R team? Whether any
inputs for changing the scripts?

 How will you fix the setup and hold violation?

 What are the constraints you used for the

synthesis? Who decides the constraints?

 What is uncertainty?

 What is false path and multi cycle path? Give

examples? For given example for false path what you
will do for timing analysis?

 What strategies used for the power optimization for

your recent project?
 Why max and min capacitance required?

 You have two different frequency for launch (say

75Mhz) and capture (say 100Mhz).

 What will happen to data? Write the waveform? If

hold problem what you will do?

 What is Metastability? How to overcome

metastability? If metastable condition exists which
frequency you will use as clock- faster or slower?
Why?

 Have you used formality? For a given block what

checks it will do? How it verifies inside the block?

 If you changed the port names during the synthesis

how will you inform Formality?

 Why you use power compiler? What is clock

gating? What are advantage and disadvantages of
clock gating? Write the clock gating circuit? Explain.

 How will you control the clock gating inference for

block of register? Write the command for the same?

 Write the total power equation? What is leakage

power? Write equation for it.

 For clock gated flop and non clock gated flop

outputs connected to a AND gate what problem can
you expect? How to avoid the problem?

 Write the sequence detector state which detects

10? How will optimize? write the verilog code for the
same?

 What is jitter? Why it will come? How to consider?

What is the command for that?

 What is clock latency? How to specify? What is the

command for that?

 What is dynamic timing analysis? What is the

difference with static timing analysis? Which is
accurate? Why it is accurate?

 Give any example for Dynamic timing analysis? Do

you know anything about GCL simulation?

 What is free running clock?

 What type of operating condition you consider for

post layout timing analysis?

 What is one-hot encoding technique? What are

advantages? What are types of encoding?

 Which scripting language you know?

 How will you analysis the timing of different modes

in design? How many modes you had in your design?
What are the clock frequencies?

 What your script contains?

 Write the digital circuit for below condition: "when

ever data changes from one to zero or zero to one the
circuit should generate a pulse of one clock period
length"?

 Have come across any design with latches? What

is the problem in timing analysis if you have latch in
your design?

 Have you come across any multiple clock design?

What are the issues in multiple clock designs?

 What you mean by synthesis strategies?

Synthesis Interview Questions -

v1.0

Synthesis is the stage in the design flow which is concerned with translating the HDL code
into gates - and that's putting it very simply! First of all, the HDL code must be written in a
particular way for the synthesis tool that you are using to infer required hardware. Of course,
a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you
have synthesised that represents the chip which can be fabricated through an ASIC or FPGA
vendor.

Q.1)What value is inferred when multiple

procedural assignments are made to the same
reg variable in an always block?
Answer) When there are multiple non-blocking assignments made to the same reg variable in
a sequential always block, then the last assignment is picked up for logic synthesis. For
example

always @ (posedge clk)

begin

q <= a^b;

q <= a & b;

q <= a|b;

end

Q.2) List out some synthesizable and non-

synthesizable constructs.
Answer)
Synthesizable Non-Synthesizable
Assign Initial block
For loop Delay statements
Gate level primitives Events
Repeat with constant value Real data types
Time data type

Fork, Join

Q.3) What is the hardware that is inferred by the

conditional operator?
Answer) Conditionals in a continuous assignment are specified through the “?:” operator.
Conditionals get inferred into a multiplexor. For example, the following is the code for a simple
multiplexor.

assign y = (s == 1'b1) ? a1 : a0;

Q.4) What logic is inferred when there are

multiple assign statements targeting the same
wire?
Answer) It is illegal to specify multiple assign statements to the same wire in a synthesizable
code that will become an output port of the module. The synthesis tools give a syntax error
that a net is being driven by more than one source. However, it is legal to drive a three-state
wire by multiple assign statements

Q.5) Given two ASICs. one has setup violation

and the other has hold violation. how can they
be made to work together without modifying the
design?
Answer) Slow the clock down on the one with setup violations, as by slowing the clock the
data will reach before the setup time window and will not violate the setup time.

For removing hold violations, add redundant logic in the path where there are hold violations,
as it will slow down the data path, and the data will not change in the hold window, thereby
avoiding hold violation.

Digital Design Interview Questions -

v1.1

Q.1) Implement OR and NOR using 2-to-1

multiplexer.
Answer) OR gate:
Multiplexer equation: Y = I1.(S) + I0.not(S)
I1 => '1' ; I0 => 'B' ; S => 'A'
Y = 1.(A) + B.not(A)
Upon simplifying above equation, Y = A + B

NOR gate:
Multiplexer equation: Y = I1.(S) + I0.not(S)
I1 => '0' ; I0 => 'not(B)' ; S => 'A'
Y = 0.(A) + not(B).not(A)
Upon simplifying above equation, Y = not(A+B)
Q.2) Implement EX-OR and EX-NOR gates using
2-to-1 multiplexer.
Answer) EX-OR gate:

Multiplexer equation: Y = I1.(S) + I0.not(S)

I1 => 'not(B)' ; I0 => 'B' ; S => 'A'
Y = not(B).(A) + B.not(A)

EX-NOR gate:

Multiplexer equation: Y = I1.(S) + I0.not(S)

I1 => 'B' ; I0 => 'not(B)' ; S => 'A'
Y = B.(A) + not(B).not(A)

Q.3) Implement latch using 2-to-1 multiplexer.

Answer) Multiplexer equation: Y = I1.(S) + I0.not(S)
I1 => 'D' ; I0 => 'Q' ; S => 'En'
Y = D.(En) + Q.not(En)

Q.4) Implement D flip-flop using 2-to-1

multiplexer.
Answer) In the below implementation of flip flop, two muxes are used. The flip flop shown
below is a negedge D flip flop.

Q.5) Implement T flip-flip using 2-to-1

multiplexer.
Answer) T flip-flop using D flip-flop :
Digital Design Interview Questions -
v1.2

Q.1) Design a combinational logic circuit

which doubles the frequency of input
clock. (Output clk freq. = 2* input clk
freq.) (Frequency multiplier(*2)).
Answer) To solve these kind of questions, first draw waveforms of
given input and output clocks a nd then try to add one or more
waveforms to input which when applied to a combinational gate will
give the output

Consider the time period of input clock is T. If the input clock is

delayed by T/4 time period and if this delayed clock along with
original input clock is given to a combinational gate then one would
see that only XOR gate fits in, to produce output with double the
frequency of input clock.
Q.2) What kind of circuit is this :
A and B are inputs to an AND gate. AND
gate's output goes to one input of OR
gate. The other input of OR gate comes
from an EX-OR gate. Inputs to the Ex-OR
gate are C and the output of the OR
gate.
A) Combinatorial /Sequential?
B) Synchronous / Asynchronous?

Answer) Combinatorial and Asynchronous

Q.3) What is the function of a D FF
whose complemented output ( Qbar ) is
connected to its input,D. What is the
maximum clock frequency that can be
used for it?
Answer) Suppose that there was some value at the output Q('0') of the flip flop,
so when rising edge of clock comes, it samples the inverted value of output and
retains it until next clock. When next rising edge comes, flop samples inverted
value of output and so on. This behaviour of circuit shows that output will be half
of the clock.

The circuit behaves as a frequency divider(/2).

Q.4) To convert a 2-input NAND gate into inverter.
Answer) Two ways to convert a 2-input NAND gate into inverter :-

a) Short both inputs of NAND gate

b) Tie one of the inputs to ‘1’.

Q.5) If A ? B = C and A?C = B, then what

is the operator "?"
Answer) Starting with OR gate,

A or B = C ; A or C = B

Replacing value of B in first equation,

A or (A or C) =C ----> This is false, hence OR is not the

answer.

AND gate,

A and B = C; A and C = B

Replacing value of B in first equation,

A and (A and C) = C ---> This is again false, hence AND

is not the answer.
XOR gate,

A xor B = C; A xor C = B

Replacing value of B in first equation,

A xor (A xor C) = C,

A xor (A.not(C) + C.not(A)) = C,

A.not(A.not(C) + C.not(A)) + not(A).(A.not(C) + C.not(A))

= C,

A(not(A).not(C) + A.C) + not(A).C = C,

0 + A.C + not(A).C = C,

C = C, -----> This is true, hence XOR is the answer

These type of questions are usually solved using hit and

trial method.

Digital Design Interview Questions -

v1.0

Q.1) Implement inverter using NAND Gate?

Answer) The key to solving such type of questions is, first draw the truth table of the gate
given and then the table for what you want to achieve.
Truth table for AND and INVERTER Gate

From the truth table,

when both inputs => 0, output => 1 (same as inverter)

when both inputs => 1, output => 0 (same as inverter)

Implementation of Inverter using NAND Gate.

Inverter using NAND gate

Another Implementation :

Inverter using NAND gate

NAND Expression : Y = not(A) or not (B)

If B => 1

Y = not(A) or not(1) => Y = not (A) or '0'

Y = not (A) ----> inverter

Q.2) Implement inverter using only NOR gate.

Answer) NOR Expression: Y = not(A) and not(B)

When both inputs => '0' , output => '1'

When both inputs => '1' , output => '0'

Another Implementation:

NOR Expression : Y = not(A) and not(B)

If B => '0'

Y = not(A) and not(0)

Y = not(A) and '1'

Y = not(A) ---> inverter

Inverter using NOR gate

Q.3) Implement inverter using 2-to-1 multiplexer.

Answer) Multiplexer Equation :
Out = S1.S + S0.not(S)
If S1 => '0' ; S0 => '1'
Out = 0.(S) + 1.not(S),
Out= not(S) ---> inverter

Inverter using multiplexer

Q.4) Implement AND gate using 2-to-1

multiplexer.
Answer) Multiplexer Equation :
Out = S1.S + S0.not(S)
If S0 => '0'
Out = S1.S
S1 => 'A'
Out = A.S ---> AND gate

AND gate using multiplexer

Q.5) Implement NAND gate using 2-to-1

multiplexer.
Answer) Multiplexer Equation :
Out = S1.S + S0.not (S)
S0 => '1';
S1 => not(A);
Out = not(A).S + not(S) ---> NAND gate
Simplifying it further,
Out = (not(S) + S)(not(A) + not(S))
Out = 1.(not(A) + not(S))
Out = not(A) + not(S) ----> NAND gate

NAND gate using multiplexer


Verilog Interview Questions - v1.1
Q.1) A task can have arguments of type :
A. Input only.
B. Output only.
C. Both input and output.
D. All input, output and inout.

Answer) D

Q.2) How many flops will be synthesized by the

given code?
always @(posedge clk)
begin
Q1 <= d;
Q2 <= q1;
Q3 <= q2;
end
A. 1
B. 2
C. 3
D. None of the above.

Answer) C

Q.3) Which operator has the highest

precedence in Verilog :
A. Unary
B. Multiplication
C. Addition
D. Conditional

Answer) A

Q.4) In the given code snippet, statement 2 will

be executed at
initial
begin
#5 x = 1'b0; //statement 1
#15 y = 1'b1; //statement 2
end
A. 15
B. 20
C. 5
D. Current simulation time.

Answer) B

Q.5) Variable and signal which will be updated

first?
A. Variable
B. Signal
C. Can't say
D. None of the above.
(Registers represent variables used to store data.)
Answer) C

Q.1) Calculate the setup slack for the below

example :

tclk-q = 300ps ; tsetup = 100ps ; tcombo = 400ps ; tclk = 1000ps

Answer)
From the above waveform, we can derive the following equation :

tclk = tclk-q + tcombo + tsetup + setup-slack

So, setup-slack = tclk – tclk-q – tcombo - tsetup

Hence, setup-slack = 1000 – 300 – 400 -200

= 100ps

Q.2) Calculate the minimum clock cycle time, for

the above example.
Answer) For the minimum clock cycle time, the setup slack is zero.
Hence, tclk = tclk-q + tcombo + tsetup + setup-slack becomes,
tclk (min.) = tclk-q + tcombo + tsetup
tclk (min.) = 300 + 400 + 200
tclk (min.) = 900ps

Q.3) Calculate the hold slack for the above example. ( hold t = 100ps)
Answer)
From the above waveform, the equation for the hold slack comes as :
hold-slack = tclk-q + tcombo – thold

hold-slack = 300 + 400 – 100

= 600ps

Q.4) Explain the worst case hold time scenario.

Answer) The following equation is an analysis of worst case hold time scenarios. In this
case, two FFs are directly connected to each other, i.e. there is no combo delay.

As depicted in the diagram, output Q0 of FF0 is directly connected to D1 of FF1.

Since, for worst case : tcombo = 0

So the equation becomes,

hold-slack = tclk-q – thold

Since, hold-slack > 0 , as to avoid hold violation.

tclk-q – thold > 0

tclk-q > thold

hold-slack = tclk-q + tcombo – thold

CMOS Interview Questions - v1.2

Q.1) Draw the CMOS layout of tristate buffer.

Answer) When En = 0,
The PMOS part of the circuit as well as NMOS part of the circuit doesn't conduct, so
therefore no one drives the output, resulting in high impedance circuit.

When En = 1; In = 0,
The PMOS part of the circuit conducts resulting in '1' at the output.
When En = 1; In = 1,
The NMOS part of the circuit conducts resulting in '0' at the output.

Q.2) Draw the CMOS layout for the following

function :
z = [a.b +c.(d + e)]
Answer) From CMOS Interview Questions - v1.1 post, the key to solving such problems is
that first derive the PMOS part (pullup circuit) and NMOS part (pulldown circuit) circuit and
then draw the complete CMOS layout.

PMOS Part = not([a.b + c.(d+e)]

= not(a.b).not(c.(d+e))
= (not(a) + not(b)).(not(c) + not(d).not(e))

NMOS Part = (a.b + c.(d+e))

Q.3) Explain transmission gate.
Answer) A transmission gate, or analog switch, is defined as an electronic element that will
selectively block or pass a signal level from the input to the output. This switch is comprised
of a pMOS transistor and nMOS transistor. The control gates are biased in a complementary
manner so that both transistors are either on or off.

When the voltage on node X is a '1', the complementary '0' is applied to node active-low X,
allowing both transistors to conduct and pass the signal at A to B. Similarly, when the voltage
on node active-low X is a '0', the complementary '1' is applied to node A, turning both
transistors off and forcing a high-impedance condition on both the A and B nodes.

The labels A and B can be reversed.

Q.4) Draw 2-to-1 mux using transmission gate.
Answer)

Q.5) Draw the layout of XOR gate using

transmission gate.
Answer)
Verilog Interview Questions - v1.3

Q.1) Explain inter-assignment and intra-

assignment delay.
Answer) Inter-assignment delay is used when a delay is specified to the left of a procedural
assignment.

reg a, b;
initial
begin
a = 0;
#10 b = 1;
end

The execution of the procedural assignment is delayed by the number specified by the delay
control. Therefore, the 'b' assignment is delayed by the 10 time units.

Intra-assignment delay is used when a delay is specified to the right of a procedural

assignment.
reg a, b, c;

initial

begin

a = 0; b = 0;

c = #10 a + b;

end

The execution of above statement takes as follows :

Take the value of a and b at the time = 0, evaluate a + b and then wait 10 time units to
assign value to c.

Q.2) What will be the output/effect of the

following statements?
a) a = 4'd12;
$display("Value of a = %b\n", a);
b) b = 3'd2;
$monitor($time, "Value of b = %b\n", b[2:0]);
c) `define SIZE 1024
$display(" Size is %h", SIZE);
Answer)

a) Value of a = 1100

b) 0Value of b = 010

c) Size is 00000400
Q.3) What will be the output of following code?
reg a,b,c;
reg [2:0] d;
initial
begin
a = 1'b0;
$display("Time %t a %b b %b c %c d %d",
$time,a,b,c,d);
b = #10 1'b1;
$display("Time %t a %b b %b c %c d %d",
$time,a,b,c,d);
c = #5 1'b0;
$display("Time %t a %b b %b c %c d %d",
$time,a,b,c,d);
d = #20 {a,b,c};
$display("Time %t a %b b %b c %c d %d",
$time,a,b,c,d);
end
Answer)

Time 0 a 0 b x c x d x

Time 10 a 0 b 1 c x d x

Time 15 a 0 b 1 c 0 d x
Time 35 a 0 b 1 c 0 d 010

Q.4) What will be the output of the below initial

block?
initial
begin
a = 1'b0;
$display("Initial 1 a %b b %b c %b d %b\
n",a,b,c,d);
#0 c = b;
$display("Initial 2 a %b b %b c %b d %b\
n",a,b,c,d);
end
initial
begin
b = 1'b1;
$display("Initial 3 a %b b %b c %b d %b\
n",a,b,c,d);
#0 d = a;
$display("Initial 4 a %b b %b c %b d %b\
n",a,b,c,d);
end
Answer) Initial 1 a 0 b x c x d x

Initial 3 a 0 b 1 c x d x

Initial 2 a 0 b 1 c 1 d x

Initial 4 a 0 b 1 c 1 d 0

Q.5) What is the final value of d?

initial
begin
b = 1'b1; c = 1'b0;
#10 b = 1'b0;
end
initial
begin
d = #25 (b|c);
end
Answer) In the above example, both the initial blocks will be executed at the same time.
Since, in the second initial block, there is an intra assignment delay, so the value of d will be
calculated at 0 time, but will be assigned after 25 time units. So, the final value of d will be 1.


Verilog Interview Questions - v1.4

Q.1) If a net has no driver, it gets the value

A) 0
B) X
C) Z
D) U
Answer) C

Q.2) What is the default value of reg?

A) 0
B) X
C) Z
D) U
Answer) B

Q.3) The task $stop is provided to A) End

simulation B) Suspend simulation C)
Exit simulator D) None of the above
Answer) B

Q.4) If A= 4`1xxz and B= 4`b1xxx, then A= = =B

will return
A) 1
B) X
C) Z
D) 0
Hint

Answer) D

Q.5) Externally, a output port must always

connected to a
A) net only
B) a reg only
C) either net or reg
D) None of the above
Answer) A

Finite State Machine (FSM)

Ways to design clocked sequential circuits :

 Mealy Machine
 Moore Machine

Mealy Machine
In a Mealy machine, the outputs are a function of the present state and the value of inputs.
Due to this, outputs may change asynchronously with change in inputs.
Output = f(Present State, Input)

Moore Machine
In a Moore machine, the outputs depend only on the present state. In the case of Moore
Machine, the next state is calculated using the inputs and the current state. The outputs are
computed by a combinatorial logic circuit whose inputs are the state variables.

Output = f(Present State)

Please go through the excitation table for D - flip flop for better understanding.

Q) Design a circuit that detects three

consecutive '1's using Mealy and Moore FSM.
Answer)
I) Mealy FSM

Mealy FSM
State truth table

Y = In.q1

Q1 = In.q1 + In.q0
Q0 = In.not(q1).not(q0)

Mealy FSM circuit implementation

II) Moore FSM

Moore FSM

State truth table

Output truth table

Y = q0.q1

Q1 = In.q0 + In.q1
Q0 = In.q1 + In.not(q0)

Moore FSM circuit implementation


Synchronous and Asynchronous
resets

Reset
Reset is needed for:

 Forcing the digital circuit into a sane state for simulation

 Initializing hardware, as circuits have no way to initialize themselves.
 For simulation purpose, it is advantageous to have reset applied to all elements that
have states.
Synchronous Resets :
Based on the fact that the reset will be sampled on the active edge of the clock. Reset is
treated as any other input to the state machine.

Synchronous Resets

Advantages :

 As there is no reset pin in the flop, the size is smaller.

 The circuit becomes completely synchronous.
 It provides filtering for the reset line so that it is not affected by glitches, unless they
occur right at clock edge.

Disadvantages :

 Since the reset input is added to combinatorial logic, hence the combinatorial logic
becomes complex.
 May require a pulse stretch circuit to guarantee that a reset pulse is wide enough to
be seen at the rising clock edge.
 Reset buffer tree may be required to ensure that all resets occur in the same clock
cycle.
 Require a free running clock to ensure reset takes place.

Asynchronous Resets :
Based on the fact that the reset has priority over other signals, when asserted, reset occurs.
The main problem when dealing with the asynchronous resets is their removal; the
asynchronous resets need to be de-asserted synchronously.

Asynchronous Resets

Advantages :

 No clock is required for assertion of reset.

 Data path is clear of reset signals.

Disadvantages :

 The flop becomes sensitive to the glitches or noise present in the reset line.
 The deactivation of reset of all flip flops must be synchronous.
Asynchronous Reset Problem
Problems with asynchronous de-assertion of asynchronous reset :

1 Violation of reset recovery time

2 Reset removal happening in different clock cycles for different sequential elements.

Reset Recovery Time :

Reset recovery time refers to the time between when reset is de-asserted and the time that
the clock signal goes high again. Missing a recovery time can cause signal integrity or
metastability problems with the registered data outputs.

Reset removal traversing different clock cycles :

When reset removal is asynchronous to the rising clock edge, slight differences in
propagation delays in either or both the reset signal and the clock signal can cause some
registers or flip-flops to exit the reset state before others.

Reset Synchronizer
Without a reset synchronizer, the usefulness of the asynchronous reset in the final system is
void even if the reset works during simulation.

Reset Synchronizer
An external reset signal asynchronously resets a pair of master reset flip-flops, which then
drives the master reset signal asynchronously through the reset buffer tree to the rest of the
flip flops in the design. The entire design will be asynchronously reset.

Reset removal is done by de-asserting the reset signal, which in turn allows the d-input of the
first master reset flip flop to pass through the reset synchronizer. The reason for using two flip
flops is to remove any metastability that might be caused by the reset signal being removed
asynchronously and too close to the rising clock edge. As two flip flops are used , it typically
takes two active clock edges after reset removal to synchronize removal of master reset.

Timing Parameters related to Asynchronous

Reset :
Recovery time is the minimum amount of time required between the release of an
asynchronous signal from the active state to the next active clock edge.

Removal time specifies the minimum amount of time between an active clock edge and the
release of an asynchronous control signal.
Reset Recovery time and Reset Removal time


Verilog Interview Questions - v1.5

Q.1) If a pure combinational circuit is coded

inside always block, is it necessary to mention
all of the inputs in the sensitivity list?
Answer) Yes, in a pure combinational circuit it is advisable to mention all of the inputs in the
sensitivity list, as not doing so may create different result in pre-synthesis and post-synthesis
simulation, as during the synthesis, the tool considers all the input in the sensitivity list,
whereas, simulation tool only considers the given inputs in the sensitivity list.

Q.2) If in1= 4'b011 and in2= 4'b0011, then the

result of in1**in2 will be A) 6
B) 9
C) 27
D) Invalid expression
Answer) C

Q.3) Give three methods to generate clock in

Verilog.
Answer)

I) initial

begin

clk = 0;

end

always

begin

#(CLK_PERIOD/2) clk = ~clk;

end

II) initial

begin

clk = 0;

forever

begin

#(CLK_PERIOD/2) clk = ~clk;

end

end

III) initial

begin

clk = 0;
end

always

begin

#(CLK_PERIOD/2) clk = 0;

#(CLK_PERIOD/2) clk = 1;

end

Q.4) What will be the output of the following

case statement?
wire [3:0] temp;
always @(...)
begin
case (1'b1)
temp[0] : Block 1;
temp[1] : Block 2;
temp[2] : Block 3;
temp[3] : Block 4;
endcase
end
Answer) The case statement walks down the list of options and executes the first one that
matches. So, for example if, the MSB of temp is the only '1' in temp, then Block 4 statements
will be executed.
Q.5) Why the statement "if (2'b10 & 2'b01)."
doesn't behave as expected, i.e. return true
case?
Answer) This is one of the most common coding error. In this case, the operator that is used
is the bitwise AND(&) operator, whereas the correct operator that should have been used is
the logical AND operator(&&).

Digital Design Interview Questions -

v1.3

Q.1) Explain metastability.

Answer) A flip flop enters into meta-stable state, when the hold or setup window is violated.
At this time, the output of flip flop is unpredictable.

If you want to read more about setup and hold violations, go through this post.

Q.2) What are the probable ways to avoid

metastability?
Answer) Ways to avoid metastability :

 Lowering clock frequency - Gives setup slack

 Lowering data speed - Gives hold slack.
 Faster flip flop - The setup and hold values are very less, hence chances for violation
decreases.

Q.3) In a system with

(a) Insufficient hold time , will slowing the clock
frequency will help?
Answer) No, it doesn't help. Making the data path slower will help with hold time ,but could
violate setup time.

(b) Insufficient setup time ,will slowing the clock

frequency will help?
Answer) Yes, making data path faster will help setup time, but will violate in hold time.

Q.4) Design a clock divider circuit which divides

the clock by an odd number and has 50% duty
cycle. (o/p clk = i/p clk/N, where N is an odd
number).
Answer) We will first examine an example where the input clock is divided by 3. After, which
we will generalize the steps for any odd number.

Step I :

Design a odd number counter (in this case, counter which counts up-to 2)
2-bit counter

Truth table for divide by 3 counter

D0 = q1
D1 = not(q1).not(q0)

From the above simplifications, we can draw the circuit for divide by 3 counter.

Circuit for divide by 3 counter.

Divide by 3 counter waveform

Step II : 50% duty cycle

Now, we have divided the input clock by 3, but the duty cycle is still not 50%. To get 50% duty
cycle, we shift the Q0 output by 90 degrees and add a gate to OR the two flip flops' output.

Divide by 3 with 50% duty cycle

Please note that in above figure, the last flop has negated clock at its clock input terminal.

Divide by 3 with 50% duty cycle waveform

The above method can be extended to other odd larger by divide "N" numbers by following
the same design flow :
 Design a Up or Down divide by "N" counter.
 Add a flip flop to follow one of the flip flops in the counter 1/2 clock cycle.
 OR the output of added flip flop with the one that is driving it to achieve 50% duty
cycle.