I/O InterfaceData Bus Address Bus Control Bus CPU Read I/O Mapped I/O MWe Main Memory COOSd Nv VORead vOwrite r I W/O Port 1 VO Port2| |1/O Port 3 “| Device 1 Device 2 Device 3 Printer Keyboard Mouse1/0 Mapped I/O In /]O Mapped W/O, There are two separate address space for Memory and I/O devices. A memory referencing instruction activates the read and write signals for Main Memory. on the other hand when ever a I/O instruction needs to be executed, read and write signal for I/O devices are activated. In this type of interfacing CPU is connected to pheripherals and main memory with the help of common address and data busses and separate control busses. Since in this configuration, both |/O and memory signals are different therefore I/O also have their own different addresses that's why itis known as I/O Mapped I/O.Data Bus Address Bus coises Memory Mapped I/O CPU te . W/O Port 1 1/0 Port 2 VO Port 3 135 9 [Soy ~~ \" f e038 Device 1 Device 2 Device 3 byiog gq Printer Keyboard Mouse P1010 Main MemoryMemory Mapped I/O In memory mapped I/O, the same address space is used for both memory and I/O. In this case, Computer doesn't distinguishes between main Memory and I/ O devices. /O devices are treated as the memory location in main memory. Since In this configuration, Both main memory and I/O devices have same control bus therefore in order to distinguish I/O devises are treated as the memory location that is why it is known as Memory mapped 1/O.Polling (Programmed 1/0) The CPU asks for service required to each device. CPU polls each device to see if it needs servicing. The CPU checks the status of the device. If the device not ready to read or write the process loops back and checks the status continuously until the device is ready. And After the transfer is completed, CPU checks to see if there is another communication request for a device. Therefore In this method CPU wastes it's time in polling devices. Another problem is that high priority devices not checked untill CPU finished with it's current I/O task, which may have a low priority. MPP ask 1/0 device status Read ‘status’ of /OInterrupt In this method of data transfer, A command is issued to inform the interface to issue an interrupt request signal when the data are available from the device. In the meantime, CPU can proceed to execute another program. The Interface meanwhile keeps monitoring the device. Upon detecting the external interrupt signal, The CPU momentarily stops the current task that it is processing and branches to a service routine to process 1/O transferring process and then returns to the previous task.Data Bus Daisy Chainning Interrupt Interrupt Aknowledgement 3 Priority 5 Signal Device 1 4, | pevice2 }2a| Devices | 5 ee oeDaisy Chainning In this connection, all the external devices are arranged in a series like an array that requests an interrupt. The device with a highest priority is placed in first followed by other devices according to it's priority. The interrupt request line is common to all devices to form a wired logic connection. after executing the current instruction, CPU responds to an interrupt with a interrupt aknowledgment. After getting interrupt aknowledgment devices start to transfer data according to it's service routine specified by the vectored address of the device.PY Parallel Priority Interrupt Vectored pee ‘Address to PU Pater xy|¢ —| LX | 2 Priority Leo. Encoder [a] a oO | | Oo oO | ‘ Ye bl Enable 2 1 3 Interrupt Interrupt ‘AcknowledgementDiagram dekhlo Theory Kudh Bana LenaPriority Encoder Dy D; De Ds Ds Ds Ds D; Highest Priority Lowest Priority ModocWhat is DMA The transfer of data between a fast storage device such as magnetic disk and memory is Often limited by the speed of the CPU. Removing the CPU from the path and letting the pheripheral device manage the memory buses directly would improve the speed of transfer/. This transfer technique is called direct memory access (DMA) During DMA Transfer, thw CPU is idle and has no control of memory buses. A DMA Controller takes over the buses to manage the transfer directly between the /O. device and memory.Parallel Priority Interrupt (DMA) In this configuration computer system can be devided into a memory unit and a number of processors comprised of the CPU and one IOP (Input-Output Processor) Instead of having each interface communicating with CPU, a computer may incorporate one or more external processor and assign them the task of communicating directly with I/O devices. An IOP may be classified as a processor with direct memory access capability that communicates with I/O devices. The IOP is similar to a CPU except that it is designed to handle the details of I/O processing The IOP provides a path for transfer of data between various pheripheral devices and the memory unit.The communication between CPU and IOP may take different forms, depending on thev particular computer considered. CPU Operation Send instruction to |OP If status ok, Start /O Instruction to |OP wv CPU Continues with another program 7 vy Request IOP Status Check Status Word T 1, Continue |_| Transfer Status word to memory location IOP Operation Access Memory for IOP >? | Program Ww Conduct 1/0 transfer using DMA, prepare status report WY VO Transfer completed, Interrupt to CPU Transfer Status word to memory location