SSLDVARSHNEYGROUPOF INSTITUTIONS, ALIGARH

COURSE FILE
DEPARTMENT OF COMPUTER SCIENCE
MR. YOGESH KUMAR
(ASSISTANTPROFESSOR)

BACHELOROFCOMPUTER APPLICATION (BCA-IIISEM)

COMPUTER ORGANISATION AND ARCHITECTURE (COA)
Subject Code: C-303
Session:–2024-2025

Affiliated to
INDEX

S.NO. CONTENTS ENCLOSURE

A
1 ACADEMIC CALENDAR
B
2 SYLLABUS
C
3 COURSE OUTCOMES
D
4 INDIVIDUAL TIME TABLE
E
5 LIST OF STUDENTS
F
LECTURE PLAN
6
G
7 SESSIONAL MARKS & TESTS MARKS
H
8 MONTHLY ATTENDANCE/SHORT ATTENDANCE REPORT
I
9 LIST OF WEEK STUDENTS
J
10 EXTRA CLASS FOR WEEK STUDENTS/MAKEUP CLASSES
K
11 EXTRA TOPIC BEYOND CLASSES
L
12 TUTORIAL & ASSIGNMENTS
M
13 MODEL QUESTION PAPERS & QUIZ/ QUESTION BANK
N
14 SESSIONAL EXAMINATION & UNIVERSITY EXAM QUESTION
PAPERS WITH STANDARD SOLUTIONS
ACADEMICCALENDAR-2024-25

SSLD VARSHNEY INSTITUTE OF ENGINEERING AND MANAGEMENT COLLEGE ALIGARH 13TH KM

STONE,ALIGARH-KANPUR,G.T ROAD N.H-91 ALIGARH U.P 202001
Academic Calender
Dates
S.NO PARTICULAR Odd Semester Even Semester

Commencement of Classes for

1 15th July 2024 6th January 2025
Academic session 2024-25

Last date of fresh admission

and Commencement of
02 20th August 2024
Classes for First YEAR All
courses
Last date of submitting
admission list of students to
03 31st August 2024
university (for newly admitted
students)

Last date of submitting

Enrollment form/Exam Form
for regular & carry over
4 2nd September 2024
examination fee for both
semesters and examination
/carry over examination fee
Last date of submitting 30th September 24th March 2025
05 sessional marks of Theory &
Practical to University.
End Semester Theory 11th November 2024 31st March 2025
06
Examination
15th November 2024
End Semester Practical 5th April2025
07
Examination (PE)

Last date for Submission of PE 18th November 2024 10th April 2025
08
Marks.
31st December 2024
15th April 2025
9 Evaluation of Answer sheets

10 Summer Training/internship 10th February 2025 05th June 2025

Winter Vacations/Summer 1st December 2024

11 05th June 2025
Vacation
Commencement of Classes
12
session 2025-26
SYLLABUS
Computer Organization and Architecture
Subject Code: C-303

UNIT I

Computer Evolution: Brief history of Computer, Classification of Computer, Structure of a Computer

System, Arithmetic Logic Unit, Control Unit, Von Neumann Architecture. Integer Addition and
Subtraction ,Floating point representation., Signed numbers, Binary Arithmetic, 1’s and 2’s Complements ,
Booths Algorithm, Hardware Implementation, IEEE Standards, Floating Point Arithmetic , The accumulator,
Shifts, Carry and Overflow. Instruction Characteristics, CPU with Single BUS, Types of Operands, Types of
Operations, Addressing Modes, Instruction Formats.

UNIT II

Processor Organization: Parallelism and Computer arithmetic, Computer arithmetic associatively. Floating
Point in the 8086, Programmers Model of 8086, Register Organization, 8086 Registers, Instruction Cycles,
Addressing Modes. Micro operations, The Instruction cycle, Control of the CPU, Functional Requirements,
Single, Two, Three bus structure, Execution of a complete instruction, Branching, Sequencing of Control
Signals, Hardwired Control Unit, Micro Programmed Control.

UNIT III

Memory Organization: Characteristics of Memory Systems, Main Memory, Types of Memory,

Memory system considerations, Design of memory subsystem using Static, Dynamic Memory
Chips, Memory interleaving High Speed Memories: Cache Memory, Structure of cache and main
memory, Elements of Cache Design, Mapping functions, Replacement algorithms, External
Memory, Virtual memory

UNIT IV

I/O Organization: Input / Output Module: Need, Techniques, Interrupt Driven I/O, Basic
concepts of an Interrupt , Response of CPU to an Interrupt, Design Issues, Priorities, Interrupt
handling, Types of Interrupts. Data Transfer Techniques, Data Memory Access, Buses, Types of
buses, I/O Interface, Synchronous and Asynchronous Data Transfer, Serial I/O, Input Devices,
Output Devices, Multiprogramming vs. Multiprocessing, Comparison between closely coupled and
loosely coupled Multiprocessor
UNIT-V
Microprogramming: Basic Principles, Features , Hardwired vs. micro programmed computers, Applications
and advantages of microprogramming, Limitations of microprogramming, Computer Clock, Micro
Instructions and its Control Path, Microcode, Machine Instruction. Parallel Organization, Instruction Set
Architecture (ISA), RISC and CISC, Characteristics of CISC, Characteristics of RISC, RISC versus CISC,
Vector Processing Requirements and Characteristics of vector processing.

Suggested Books:

1. Computer Organization & Architecture– by Stallings

2. Computer Organization and Architecture: Designing for Performance by William Stallings
3. Computer Architecture and Organization by John Hayes
Course Outcomes:

Upon completing the course, students will be able to:

 On completion of unit-I, students will know about the Computer and its arithmetic
operations along with IEEE standards and types of buses and their operations.

 On completion of Unit-II, students will get to know more about floating points in
8086 processors and its operations, bus structures, branding and other control units.

 By the end of unit-III, students will know about the memory system it its use along
with the mapping. Overall students will be able to use effective memory system.

 By end of the Unit-IV, students will know about the input/ output modules, responses
and how to handle interruption along with I/O Interface and Synchronous and
Asynchronous data transfer.

 After completion of V unit, students will know about the micro programming
including basic principles features, lock and unlock, machine instructions and more
about RISC and CISC.
INDIVIDUAL TIME TABLE
LIST OF STUDENTS
COURSE: BCA
SEMESTER: IIIrd (ODD)
SUBJECTNAME: Computer Organization and Architecture
SUBJECT CODE: C-303

Father Contact
Student Name Father Name Contact Detail Number

HARSH PUNDHIR DEVENDRA SINGH 8791667567 7078864953

EKTA HARISH CHANDRA 6397524989 6396111783

TANISHA KUSHWAH PUSHPENDRA KUMAR 9897431368 8126773505

NANDINI GAHLOT PRAVEEN KUMAR 9045086762 9045086762

DEEPAK SINGH SANTOSH SINGH 9821248208 9720311099

CHANDRA SHEKHAR SAHAB SINGH 8650203028

PRASHANT KUMAR SINGH LATE MR RAM PRAKASH 9027133702

DIVYANSHU YADAV PREM PAL 9759438540 9520492288

GAUTAM KUMAR SIYARAM 7455866741 9690133241

VEERPAL SINGH OMVEER SINGH 9536840580 9456975604

DEVID SINGH RAJENDRA SINGH 9759745955 9410654720

MANVENDRA PRATAP BHANU PRATAP SINGH 7300699400 7505903243

SATYAM KUMAR DINESH KUMAR 7037681938 9149280907

SUDHANSHU UPADHYAY SANJEEV UPADHYAY 8171352482 8171352482

SSLD VARSHNEY
ENGINEERING COLLEGE
Department of Computer
Science

LECTURE PLAN
PERIODS
(As per EVALUATION SCHEME
SUBJECT SUBJEC University) SUBJECT
PROGRAM SEM CREDIT
NAME T SESSIONAL TOTAL
CODE L T P ESE
CT TA TOTAL
Computer
B.C.A V Organizatio
n and C-303
Architectur 2 1 0 30 20 50 50 100 3
e

Periods(Actual)
Name of Date of Total lectures Date of
Name of Faculty
L T P Subject Commencement planned Conclusion
Coordinator
Yogesh Kumar Yogesh Kumar 10/9/2024 45 --/--/----
6 1 0

Course Overview: This course introduces the structure and functionality of computer systems, covering CPU,
memory, and I/O components, as well as machine-level programming and performance optimization. It provides a
foundational understanding of how hardware and software interact to execute programs efficiently.

Prerequisite: A basic understanding of programming concepts and familiarity with high school mathematics are
essential prerequisites. Knowledge of fundamental computing concepts, such as data types and algorithms, will also
be beneficial.

Course Objective: The course aims to equip students with a comprehensive understanding of computer hardware
components and their interaction with software, focusing on system design, data processing, and performance optimization.
Students will develop the ability to analyze and design efficient computer systems and understand their impact on overall
system performance.
LECTURE PLAN
Computer Organization and Architecture
BCAIII- Semester
Code: -C-303
Preferred Book: Computer Organization & Architecture–
By Stallings

UNIT- I
Above Book Expected
Lecture Delivery
Computer Evolution Referred Page date Remark
s date
No.
Brief history of Computer, L1
10/09/2024
Classification of Computer
Structure of a Computer System, L2 11/09/2024
Arithmetic Logic Unit, Control Unit
Von Neumann Architecture. Integer Addition
L3 12/09/2024
and Subtraction
point representation., Signed numbers, Binary
L4 13/09/2024
Arithmetic, 1’s and 2’s Complements
Booths Algorithm, Hardware L5 14/09/2024
Implementation
IEEE Standards, Floating Point L6 16/09/2024
Arithmetic
The accumulator, Shifts, L7 17/09/2024

Carry and Overflow. Instruction L8

Characteristics 18/09/2024
CPU with Single BUS, Types of L9
Operands, Types of Operations 19/09/2024
Addressing Modes, Instruction L10
Formats. 20/09/2024
Class Test L11
21/09/2024

UNIT- II
Book Expected
Processor Organization Lectures Delivery date Remark
Referred date
Parallelism and Computer arithmetic, L12
Computer arithmetic associatively 23/09/2024
Floating Point in the 8086, L13
Programmers Model of 8086 24/09/2024
Register Organization, 8086 L14
Registers, Instruction Cycles,
Addressing Modes 25/09/2024
Micro operations, The Instruction L15
cycle, Control of the CPU 26/09/2024
Functional Requirements, Single, L16
Two, Three bus structure 27/09/2024
Execution of a complete instruction,
Branching, Sequencing of Control L17
Signals 28/09/2024
Hardwired Control Unit, Micro L18
Programmed Control.
30/09/2024
L19
Class Test
01/10/2024

UNIT- III
Book Expected Delivery
Memory Organization Lectures Referred date date
Remark
Characteristics of Memory Systems,L20
Main Memory, Types of Memory 02/10/2024
Memory system considerations, L21
Design of memory subsystem
using Static Dynamic Memory
Chips 03/10/2024
Dynamic Memory Chips, Memory L22
interleaving High Speed Memories 04/10/2024
Cache Memory, Structure of cache and
L23
main memory 05/10/2024
Elements of Cache Design, L24
Mapping functions 07/10/2024
Replacement algorithms L25
08/10/2024
External Memory, Virtual L26
memory 09/10/2024
L27
Class Test
10/10/2024
UNIT- IV
Book Expected
I/O Organization Lectures Referred date
Delivery date Remark
Input / Output Module: Need, L28
Techniques 11/10/2024
Interrupt Driven I/O, Basic L29
concepts of an Interrupt ,
Response of CPU to an Interrupt 12/10/2024
Design Issues, Priorities, Interrupt L30
handling, Types of Interrupts 14/10/2024
Data Transfer Techniques, Data MemoryL31
Access 15/10/2024
Buses, Types of buses, I/O L32
Interface 16/10/2024
Synchronous and Asynchronous L33 17/10/2024
Data Transfer Serial I/O, Input
Devices, Output Devices
Multiprogramming vs. L34
Multiprocessing 18/10/2024
Comparison between L35
closely coupled and
loosely coupled
Multiprocessor
19/10/2024
L36
Class Test
21/10/2024

UNIT- V
Book Expected
Microprogramming Lectures Referred date
Delivery date Remark
Basic Principles, Features L37
22/10/2024
Hardwired vs. micro programmed L38
computers
23/10/2024
Applications and advantages of L39
microprogramming, Limitations of
microprogramming 24/10/2024
Computer Clock, Micro Instructions L40
and its Control Path 25/10/2024
Microcode, Machine Instruction. L41
Parallel Organization 26/10/2024
Instruction Set Architecture (ISA), L42
RISC and CISC 28/10/2024
Characteristics of CISC, L43
Characteristics of RISC, RISC versus
CISC 29/10/2024
Vector Processing Requirements L44
and Characteristics of vector
processing.
30/10/2024
Class Test L45
31/10/2024
SESSIONAL MARKS REPORT
Sessional 1 Sessional 2 Pre- Aggregate
Student Name Father Name MM : 50 MM : 50 University percentag
test e
HARSH PUNDHIR DEVENDRA SINGH

EKTA HARISH CHANDRA

TANISHA KUSHWAH PUSHPENDRA KUMAR

NANDINI GAHLOT PRAVEEN KUMAR

DEEPAK SINGH SANTOSH SINGH

CHANDRA SHEKHAR SAHAB SINGH

PRASHANT KUMAR
LATE MR RAM PRAKASH
SINGH
DIVYANSHU YADAV PREM PAL

GAUTAM KUMAR SIYARAM

VEERPAL SINGH OMVEER SINGH

DEVID SINGH RAJENDRA SINGH

MANVENDRA PRATAP BHANU PRATAP SINGH

SATYAM KUMAR DINESH KUMAR

SUDHANSHU UPADHYAY SANJEEV UPADHYAY

Monthly Attendence / Short
Attendence Report
List of Weak Students

List of Weak Students

Extra Classes for Weak Students / Makeup
Classes

Extra Classes Timing

Extra Topic Beyond Classes

S.NO Extra Topic Class Timing

Tutorial & Assignments
MODEL QUESTION PAPERS & QUIZ/
QUESTION BANK
Unit I
1. What are the key milestones in the evolution of computers from the early mechanical devices to modern
electronic systems?
2. How are computers classified based on their size and capability? What are the differences between
microcomputers, minicomputers, mainframes, and supercomputers?
3. Can you describe the Von Neumann architecture and explain the role of the Arithmetic Logic Unit (ALU),
Control Unit, and memory in this architecture?
4. How are integer addition and subtraction performed in binary arithmetic, and what are the methods for
representing signed numbers using 1's and 2's complements?
5. What is floating point representation in computers, and how does the IEEE 754 standard define the
representation and operations of floating point numbers?

Unit II
1. How does parallelism enhance the performance of computer arithmetic operations, and what are the main
types of parallelism used in modern processors to improve arithmetic computation?
2. What is the role of floating point arithmetic?How does the 8086 handle floating point operations given its
instruction set and architecture?
3. Describe the key components of the programmes model of the 8086 microprocessor. How do these
components affect the instruction cycle and execution of instructions?

Unit III
1. What are the key characteristics of memory systems that affect their performance and volatility? How do
these characteristics impact overall system performance?
2. What are the different types of memory and their primary use cases?
3. Explain the structure and function of cache memory in a computer system. What are the key elements of
cache design, replacement algorithms?
4. How does virtual memory work, and what role does it play in modern computing systems?

Unit IV
1. What is interrupt-driven I/O, and how does it differ from programmed I/O? Describe the basic concept of an
interrupt and explain the CPU's response to an interrupt.
2. What are the different data transfer techniques used in computer systems? What are the different types of
buses?
3. Compare synchronous and asynchronous data transfer methods. What are the advantages and disadvantages
of each, and in what scenarios might one be preferred over the other?
4. What is the difference between multiprogramming and multiprocessing?
Unit V
1. What are the key differences between hardwired and micro-programmed control units in computers?
Discuss advantages and disadvantages of each approach.
2. What are the main applications and advantages of microprogramming in computer architecture?
3. Compare and contrast Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer
(CISC) architectures. What are the key characteristics of each, and how do they affect instruction execution
and system performance?
4. What are the requirements and characteristics of vector processing? How does vector processing differ from
scalar processing, and in what types of applications is vector processing particularly beneficial?