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8085 - Memory Interfacing Problems

8085_Memory Interfacing Problems

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Sasuke Uchiha
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230 views

8085 - Memory Interfacing Problems

8085_Memory Interfacing Problems

Uploaded by

Sasuke Uchiha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Memory Interfacing Problems

1. https://technobyte.org/external-memory-interfacing-8085-ram-rom-explained/
2. https://www.zseries.in/embedded%20lab/8085%20microprocessor/memory%20mapping.php#.X5MZM
5Lis2y

EXAMPLE-1

Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM
with 8085 processor.

• The memory capacity is 64 Kbytes. i.e


• 2^n = 64 x 1000 bytes where n = address lines.
• So, n = 16.
• In this system the entire 16 address lines of the processor are connected to address input pins of memory
IC in order to address the internal locations of memory.
• The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).
• Since the processor is connected to EPROM, the active low RD pin is connected to active low output
enable pin of EPROM.
• The range of address for EPROM is 0000H to FFFFH.

EXAMPLE-2

Consider a system in which the available 64kb memory space is equally divided between EPROM and RAM.
Interface the EPROM and RAM with 8085 processor.

• Implement 32kb memory capacity of EPROM using single IC 27256.


• 32kb RAM capacity is implemented using single IC 62256.
• The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the processor are
connected to 15 address pins of both EPROM and RAM.
• The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If A15 is 0, it
select EPROM.
• Inverter is used for selecting the memory.
• The memory used is both Ram and EPROM, so the low RD and WR pins of processor are connected to
low WE and OE pins of memory respectively.
• The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 7FFFH to FFFFH.
EXAMPLE-3

Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface
the EPROM and RAM with 8085 processor.

• The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining
two numbers be RAM.
• Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are
connected to 13 address pins of all the memory.
• The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chip select
signals.
• These four chip select signals can be used to select one of the four memory IC at any one time.
• The address line A15 is used as enable for decoder.
• The simplified schematic memory organization is shown.

The address allotted to each memory IC is shown in following table

EXAMPLE-4

Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb memory.
Interface the EPROM and RAM with 8085 processor.

• The total memory capacity is 64Kb. So, let 4 numbers of 8Kb EPROM and 4 numbers of 8Kb RAM.
• Each 8kb memory requires 13 address lines. So the address line A0 - A12 of the processor are
connected to 13address pins of all the memory lCs.
• The address lines A13, A14 and A15 is decoded using a 3-to-8 coder to generate eight chips select
signals. These eight chips select signals can be used to select one of the eight memories at any one time.
• The memory interfacing is shown in following figure.

• The address allocation for Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085 is,

Example 5:

A system requires 8kb EPROM and 8kb RAM. Also the system has 2 numbers of 8155. Draw the Interface
diagram. Allocate addresses to all the devices. The peripheral IC should be I/O mapped.

• The IC 2764 (8k x 8) is selected for EPROM memory and IC 6264 (8k x 8) is selected for RAM
memory. Both the memory IC has time compatibility with 8085 processor.
• The 8kb memory requires 13 address lines. Hence the address lines A0 - A12 are used to select memory
locations.
• The RAM locations of 8155 are selected by address lines A0 to A7.
• 3-to-8 decoder, 74LS138 is used for generating chip select signals by decoding the address lines A13,
A14 and A15.
• Eight bit addresses are allotted to ports of 8l55 and sixteen bit addresses are allotted to RAM memory
locations of 8155.

• The 16 bit address for the memory and IO devices are,

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