15cs34 Module 2 COMPUTER ORGANIZATION

1. ACCESSING I/O DEVICES

 The simple arrangement of connecting set of I/O devices to memory and processor by means of
system bus is as shown in the figure.

Such a arrangement is called as Single Bus Organization.

The single bus organization consists of

 Memory
 Processor
 System bus
 I/O device

The system bus consists of 3 types of buses:

 Address bus (Unidirectional)
 Data bus (Bidirectional)
 Control bus (Bidirectional)

 The system bus enables all the devices connected to it to involve in the data transfer
operation.

 The system bus establishes data communication between I/O device and processor.

Steps for input operation:

 The address bus of system bus holds the address of the input device.
 The control unit of CPU generates IORD Control signal.
 When this control signal is activated the processor reads the data from the input device
(DATAIN) into the CPU register.

Steps for output operation:

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 The address bus of system bus holds the address of the output device.
 The control unit of CPU generates IOWR control signal.
 When this control signal is enabled CPU transfers the data from processor register to
output device(DATAOUT)

There are 2 schemes available to connect I/O devices to CPU

1. Memory mapped I/O:

 In this technique both memory and I/O devices can share the common memory to store the
instruction as well as the operands.
 Memory related instructions are used for data transfer between I/O and processor.
 In case of memory mapped I/O input operation can be implemented as,
MOVE DATAIN , Ro

Source destination

 Similarly output can be implemented as,

MOVE Ro , DATAOUT

Source destination

2. I/O Mapped I/O:

 In this technique CPU separates address space for memory and I/O devices.
 Hence two sets of instruction are used for data transfer.
 One set for memory operations and another set for I/O operations.
 The I/O operation can be implemented as,
IN AL, DX
 This instruction reads one byte of data from the I/P register whose address is strore in DX register
into AL register.

 The O/P operation can be implemented as,

OUT DX, AL
 This instruction transfer the contents of AL register into the O/P register (DATA OUT)
whose address is stored in DX register.

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The hardware arrangement of connecting I/P device to the system bus is as shown in the fig.

This hardware arrangement is called as I/O interface. The I/O interface consists of 3 functional
devices namely:

1) Address Decoder:

 Its function is to decode the address in-order to recognize the input device whose address
is available on the unidirectional address bus.

 The unidirectional address bus of system bus is connected to input of the address decoder
as shown in figure
2) Control Circuit:

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 The control bus of system bus is connected to control circuit as shown in the fig.
 It controls the read write operations with respect to I/O device.

3) Status & Data register:

 It specifies type of operation (either read or write operation) to be performed on I/O
device.
4) Data Register:
 It stores the data to be read from input device to or it holds the data to be written into
output device.
Input and output register:
The various registers used for I/O operations are as follows:

 a)DATAIN register:
The format of DATA IN register is as shown in the fig

 It is part of the input device.

 It is used to store the ASCII value of a character to be read from the keyboard
A) DATAOUT register:

 It is part of the output device.

 t is used to hold the ASCII value of a character to be displayed on the output device.
The format of DATA OUT register is as shown in the fig

B) STATUS register:

The format of STATUS register is as shown in the fig.

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a) SIN flag:
 This control flag is set to 1 when DATA IN register holds the ASCII value of a character
and this flag is part of the input device.
 This flag is set to 0 when the ASCII value of a character is transferred from DATA IN
register to CPU register.
b) SOUT flag
 This flag is part of the output device.
 This flag is set to 1 when DATA OUT register holds the ASCII value of a character, and
the flag is set to 0 when the ASCII value is transferred from DATA OUT register to
output device.
a. KIRQ (Keyboard interrupt request):
 The input device requests the processor to obtain its service by activating this flag to 1.
b. DIRQ (Display Interrupt Request):
 The output device request the CPU or processor to obtain its service for output operation
by activating this control falg to 1.
C) CONTROL register:
The format of CONTROL register is as shown in the fig.

a. KEN (Keyboard enable):

 When this flag is set to 1 it enables input device for the input operation.
b. DEN (Display enable):
 When this flag is set to 1 it enables output device for output operation.

Program Controlled I/O:

 To explain the concept of program controlled I/O consider two operations namely input
operation and output operation.
a) Input operation:
 It is the process of transferring ASCII value of a character from DATA IN register to
CPU register.
b) Output operation:
 It is the process of transferring ASCII value of a character from CPU register to DATA
OUT register.

 Design 2 sets of instruction for input and output operations respectively,

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 These 2 sets of instructions are stored in memory of the CPU.

 Now allow the CPU to execute this program in-order to control the input and output
operation.

“It is the process of controlling the input and output operations by executing 2 sets
of instruction, one set for input operation and the next set for output operation.”

2. Interrupt:
 It is an event which suspends the execution of one program and begins the execution of
another program.

 The arrival of interrupt causes the processor to transfer the execution control from main
program to sub program.
To explain the concept of interrupt, consider the following two programs namely:
(Main Program) (Sub Program)
5000 I1 7000 I1
5004 I2 7004 I2
5008 I3 (Interrupt Instruction) . .
5012 I4 (Next Instruction) . Return
Execution control.

 Most processor uses stack segment memory to store the address of the next
instruction and is also called as return address.

The following steps are takes place when the interrupt related instruction is
executed:

 It suspends the execution of current instruction.

 Transfer the execution control to sub program from main program.
 Increments the content of PC by 4 memory location.
 It decrements SP by 4 memory locations.
 Pushes the contents of PC into the stack segment memory whose address is stored in SP.
 It loads PC with the address of the first instruction of the sub program.
The following steps are takes place when return instruction is executed
1. It transfers the execution control from sub program to main program.
2. It retrieves the content of stack memory location whose address is stored in SP into the PC.
3. After retrieving the return address from stack memory location into the PC it increments the
Content of SP by 4 memory location.

3. Interrupt hardware
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 The external device (I/O device) request the processor by activating one bus line and this
bus line is called as interrupt request line.
 The one end of this interrupt request line is connected to input power supply by means of
pull up register is as shown in the fig.
 The another end of interrupt request line is connected to INTR (Interrupt request) signal
of processor as shown in the fig.

 The I/O device is connected to interrupt request line by means of switch as shown in the
fig.
 When all the switches are open the voltage drop on interrupt request line is equal to the
VDD.
 This state is called as in-active state of the interrupt request line.
 The I/O device interrupts the processor by closing its switch.
 When switch is closed the voltage drop on the interrupt request line is found to be zero.
Therefore INTR=0 and INTR=1.
 The signal on the interrupt request line is logical OR of requests from the several I/O
devices.
Therefore, INTR=INTR1 + INTR2 + ……….+ INTRn

4. Enabling and disabling the interrupts:

There are 3 techniques to enable and disable the interrupts.
 Method No: 1
In this technique the hardware of the CPU should ignore the request from the I/O devices
until the completion of first instruction of interrupt service routine is completed.
The following steps are necessary to enable and disable the interrupts.
 De-activate the request from the I/O devices by executing DI (Disable Interrupt) instruction.
 Allow the CPU to execute the sequence of instruction in the interrupt service routine.
 Activate the request from the I/O devices by means of EI (Enable Interrupt) instruction.
 Transfer the execution control from sup program to main program.

 Method N0:2 (Program status word register)

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In this technique the CPU uses program status word register to enable and disable the
interrupts.
The format of program status word register is as shown in the fig:
D7 D3 D2 D1 D0

I
Interrupt bit = 0 for disable

= 1 for enable

The following steps are necessary to enable and disable the interrupt.

 Design one instruction which sets the interrupt bit of program status word register to 0.
When interrupt bit of program status word register is set to 0 it disables request from the
I/O devices.
 Allow the CPU to execute the interrupt service routine.
 Design one instruction which sets the interrupt bit of program status word register to 1.
When interrupt bit of program status word register is set to 1 it releases request from the I/O
devices.
 Transfer execution control from sub program to main.program

 Method NO:3
 This technique is designed for single interrupt request line.
 The interrupt handling mechanism circuit responds to this interrupt request line only at
the leading edge of the signal and is called as edge triggered signal.
 This signal allows only one request at a time and there is no danger of multiple requests
from the several I/O devices.

The following steps take place when I/O devices interrupts the processor to obtain
the service of the system bus,
 The I/O devices interrupt the processor by activating interrupt request value.
 In response to this signal the CPU starts the execution of the current program and
transfers controls to interrupt service routine.
 The CPU blocks the request from the I/O devices either by executing DI instruction or by
setting interrupt bit of program status word registers to 0.
 Allow the CPU to execute the sequence of instruction in the interrupt service routine.
 The CPU releases the request from the I/O devices either by executing EI instruction or
by setting interrupt bit of program status word registers to 1.
 Transfer the execution control from sub program to main program by means of RET
instruction.
 Define the following terms:
1) interrupt
2) vectored interrupt
3) interrupt nesting
4) an exception and give two examples.

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Solution:

(i) Interrupt:
 It is an event which suspends the execution of one program and begins the execution of
another program.
 The arrival of interrupt causes the processor to transfer its execution control from
main program to sub program.
 The diagrammatic representation of interrupt concept is as shown in the fig:

Main program Sub program

I1
I1 I2
I2 I3
. .
. .
. .
I3 (interrupt) .
I4(Next instruction) I4(RET)
.
.

(ii) Vectored interrupt:

 To reduce the time involved in the polling process, a divice requesting an

interrupt may indentify itself to the processor.
 A device requesting an interrupt may indentify itself by sending a special code to
the processor over the bus.
 Then the processor can immediately transfer its service to interrupt service
routine. Such interrupts are known as vectored interrupts.

(iii)Interrupt nesting
(iv)Exception:
It is defined as any event that causes an interrupt at any instant of time.

Ex(1): I/O interrupts:

The I/O devices interrupt the processor to obtain its service at any instant of time.

Ex(2): Debugging:
It is a kind of exception used as an aid in debugging programs. System software
consists of a program called debugger which helps the programmer to find errors in the program.

Ex(3): Privilege exception:

To protect the operating system of the computer from user
programs, a set of instructions are executed by the processor is in supervisor mode and are
called as “privileged instructions”.
Note: Point (iv) (exceptions) can be the answer for the following question.
“Define exceptions. Explain two kinds of exceptions?”
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14. Explain briefly, with the help of a diagram, the working of daisy chain
with multiple priority levels and multiple devices in each level.
OR.
With a neat block diagram,explain any two methods of handling multiple
I/O devices.
OR.
In the interrupt mechanism, how the simulation arrivals of interrupts from
multiple I/O devices are handled? (10M)

Solution:

1. The daisy chain with multiple priority levels is as shown in the figure.

 The interrupt request line INTR is common to all devices as shown in the fig.

 The interrupt acknowledge line is connected in a daisy fashion as shown in the figure.

 This signal propagates serially from one device to another device.

 The several devices raise an interrupt by activating INTR signal. In response to the signal,
processor transfers its device by activating INTA signal.

 This signal is received by device 1. The device-1 blocks the propagation of INTA signal to
device-2, when it needs processor service.

 The device-1 transfers the INTA signal to next device when it does not require the processor
service.
In daisy chain arrangement device-1 has the highest priority.
2. The second method of handling multiple devices is the multiple devices in each level
as shown in the figure.

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In this technique, devices are organizes in a group and each group is connected to the
processor at a different priority level.
With in a group devices are connected in a daisy chain fashion as shown in the figure.

15. How can the processor obtain the starting address of different interrupt service
routines using Vectored interrupts? (4M)
Solution:

 A device requesting an interrupt can identify itself by sending a special code to the
processor over the bus.

 The code length is in the range of 4 to 8 bits.

 This code enables the processor to recognize the device even if it can share the common
request line.

 The code supplied by the device may represent the starting address of the interrupt service
routine.

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5.Direct Memory Address (DMA):

 It is the process of transferring the block of data at high speed in between main memory and
external device (I/O devices) without continuous intervention of CPU is called as DMA.
 The DMA operation is performed by one control circuit and is part of the I/O interface.
 This control circuit is called DMA controller. Hence DMA transfer operation is performed
by DMA controller.
 To initiate Directed data transfer between main memory and external devices DMA
controller needs parameters from the CPU. These 3 Parameters are:
1). Starting address of the memory block.
2). No of words to be transferred.
3). Type of operation (Read or Write).
 After receiving these 3 parameters from CPU, DMA controller establishes directed data
transfer operation between main memory and external devices without the involvement
of CPU.

Register of DMA Controller:

It consists of 3 type of register:
1). Starting address register:
The format of starting address register is as shown in the fig.

.
It is used to store the starting address of the memory block.
2). Word-Count register:
The format of word count register is as shown in fig.:

It is used to store the no of words to be transferred from main memory to external devices
and vice versa.
3). Status and Controller register:
The format of status and controller register is as shown in fig.:

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a). DONE bit:

 The DMA controller sets this bit to 1 when it completes the direct data transfer between
main memory and external devices.
 This information is informed to CPU by means of DONE bit.

b). R/W (Read or Write):

 This bit is used to differentiate between memory read or memory write operation.
 The R/W = 1 for read operation.
= 0 for write operation.
 When this bit is set to 1, DMA controller transfers the one block of data from external
device to main memory.
 When this bit is set to 0, DMA controller transfers the one block of data from main
memory to external device.

c). IE (Interrupt enable) bit:

 The DMA controller enables the interrupt enable bit after the completion of DMA
operation

d). Interrupt request (IRQ):

 The DMA controller requests the CPU to transfer new block of data from source to
destination by activating this bit.
6.The computer with DMA controller is as shown in the fig.:

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 The DMA controller connects two external devices namely disk 1 and disk 2 to system
bus as shown in the above fig.
 The DMA controller also interconnects high speed network devices to system bus as
shown in the above fig.
 Let us consider direct data transfer operation by means of DMA controller without the
involvement of CPU in between main memory and disk 1 as indicated by dotted lines (in
the fig.).
 To establish direct data transfer operation between main memory and disk 1. DMA
controller request the processor to obtain 3 parameters namely:

1). Starting address of the memory block.

2). No of words to be transferred.
3). Type of operation (Read or Write).

 After receiving these 3 parameters from processor, DMA controller directly transfers
block of data main memory and external devices (disk 1).
 This information is informed to CPU by setting respective bits in the status and controller
register of DMA controller.
These are 2 types of request with respect to system bus
1). CPU request. 2). DMA request.
Highest priority will be given to DMA request.

 Actually the CPU generates memory cycles to perform read and write operations.
The DMA controller steals memory cycles from the CPU to perform read and write
operations. This approach is called as “Cycle stealing”.

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 An exclusive option will be given for DMA controller to transfer block of data from
external devices to main memory and from main memory to external devices. This
technique is called as “Burst mode of operation.”

7.Bus – Arbitration:
 Any device which initiates data transfer operation on bus at any instant of time is called
as Bus-Master.
 When the bus mastership is transferred from one device to another device, the next
device is ready to obtain the bus mastership.
 The bus-mastership is transferred from one device to another device based on the
principle of priority system. There are two types of bus-arbitration technique:

a). Centralized bus arbitration:

In this technique CPU acts as a bus-master or any control unit connected to bus can be
acts as a bus master.

The schematic diagram of centralized bus arbitration is as shown in the fig.:

 The following steps are necessary to transfer the bus mastership from CPU to one of the
DMA controller:). The DMA controller request the processor to obtain the bus mastership by
activating BR (Bus request) signal
 . In response to this signal the CPU transfers the bus mastership to requested devices DMA
controller1 in the form of BG (Bus grant).
 When the bus mastership is obtained from CPU the DMA controller1 blocks the propagation
of bus grant signal from one device to another device.
 The BG signal is connected to DMA controller2 from DMA controller1 in as daisy fashion
style is as shown in the figure.

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 When the DMA controller1 transfers the bus mastership to DMA controller2 by unblocking
bus grant signal.
 . When the DMA controller1 receives the bus grant signal it enables BBSY signal. When
BBSY signal is set to 1 the set of devices connected to system bus doesn’t have any rights to
obtain the bus mastership from the CPU.
b). Distributed bus arbitration:
 In this technique 2 or more devices trying to access system bus at the same time may
participate in bus arbitration process.
 The schematic diagram of distributed bus arbitration is as shown in the figure:

 The external device requests the processor to obtain bus mastership by enabling start
arbitration signal.
 In this technique 4 bit code is assigned to each device to request the CPU in order to
obtain bus mastership.
 Two or more devices request the bus by placing 4 bit code over the system bus.
 The signals on the bus interpret the 4 bit code and produces winner as a result from the
CPU.
 When the input to the one driver = 1, and input to the another driver = 0, on the same bus
line, this state is called as “Low level voltage state of bus”.
 Consider 2 devices namely A & B trying to access bus mastership at the same time.
Let assigned code for devices A & B are 5 (0101) & 6 (0110) respectively.
 The device A sends the pattern (0101) and device B sends its pattern (0110) to master.
The signals on the system bus interpret the 4 bit code for devices A & B produces device
B as a winner.
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Registers: The fastest access is to data held in registers. Hence registers are part of the memory
hierarchy.
More speed, small size and cost per bit is also more.

At the next level of hierarchy, small amount of memory can be directly implemented on the
processor chip.
This memory is called as processor cache. It holds the copy of data and instructions.
There are 2 levels of caches viz level-1 and level-2. Level-1 cache is part of the processor and
level-2 cache is placed in between level-1 cache and main memory.

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The level-2 cache is implemented using SRAM chips.

The next level in the memory hierarchy is called as main memory. It is implemented using
dynamic memory components. The main memory is larger but slower than cache memory. The
access time for main memory is ten times longer than the cache memory

The level next in the memory hierarchy is called as secondary memory. It holds huge amount of
data.

Cache Memory:
It is the fast access time located in between processor and main memory as
shown in the fig. It is designed to reduce the access time.

Processor Cache Memory Main

Memory

The cache memory holds the copy of data and instructions.

The processor needs less access time to read the data and instructions from the cache memory as
compared to main memory.
Hence by incorporating cache memory, in between processor and main memory, it is possible to
enhance the performance of the system.

Mapping functions: There are 3 techniques to map main memory blocks into cache memory.
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1. Direct mapped cache

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The simplest way to determine cache locations in which to store memory blocks is the
direct mapping technique as shown in the figure.
The block 0 , 128 and block 256 are mapped into block-0 cache location.
Similarly blocks 1,129 and 257 from main memory are loaded into cache
block-1.
It is note that contention may arise when more than one memory blocks are loaded into single cache
block, even when the cache is not full.
The main memory block is loaded into cache block by means of memory address. The main memory
address consists of 3 fields as shown in the figure.
Each block consists of 16 words. Hence least significant 4 bits are used to select one of the 16
words.
The 7bits of memory address are used to specify the position of the cache block, location. The most
significant 5 bits of the memory address are stored in the tag bits. The tag bits are used to map one of
25 = 32 blocks into cache block location.
The higher order 5 bits of memory address are compared with the tag bits. If they match, then the
desired word is in that block of the cache.
If there is no match, then the block containing the required word must first be read from the main
memory and loaded into the cache. It is very easy to implement, but not flexible.

2. Associative Mapping:
It is also called as associative mapped cache. It is much more flexible.
In this technique main memory block can be placed into any cache block position.
In this case , 12 tag bits are required to identify a memory block when it is resident of the cache
memory.
The Associative Mapping technique is illustrated as shown in the fig.

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In this technique 12 bits of address generated by the processor are compared with the tag bits of each
block of the cache to see if the desired block is present. This is called as associative mapping
technique.

3.Set Associative Mapping:

It is the combination of direct and associative mapping techniques.

The blocks of cache are divided into several groups. Such a groups are called as sets.

Each set consists of two cache blocks. A memory block is loaded into one of the cache sets.

The main memory address consists of three fields, as shown in the figure.

The lower 4 bits of memory address are used to select a word from a 16 words.

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A cache consists of 64 sets as shown in the figure. Hence 6 bit set field is used to select a cache set

from 64 sets.

The tag field (6 bits) of memory address is compared with the tag fields of each set to determine

whether memory block is available or not.

The following figure clearly describes the working principle of Set Associative Mapping technique

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4.1 Hit rate and Miss Penalty

A successful access to data in a cache is called as „hit‟. The number of hits

given as a fraction of all attempted accesses is called hit rate.

The number of misses stated as a fraction of attempted successes is called as miss rate.
To obtain high performance, hit rates are higher than 0.9.
The extra time needed to bring the desired information from slower memories into the faster
memories is called as “Miss Penalty”.
Let „h‟ be the hit rate,
Tm Miss penalty and
Tc time to access the information from the cache , then the average access time is
given by

Tav = h * Tc + (1 – h) * Tm

Tm Main memory access time.

The hit rate depends on the design of the cache and on the data and instruction access.
Let L1 and L2 are used for data and instructions respectively. Then average access time is given by
Tav = h1 Tc1 + (1 - h1) h2 Tc2 + (1 - h1) (1- h2) Tm
Where, h1 hit rate in L1 cache
h2 hit rate in L2 cache
Tc1 time to access L1 cache
Tc2 time to access L2 cache
Tm time to access main memory

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Ex:1 Consider a cache with 8 word blocks. It takes one clock cycle to send an address to main
memory. The first word is accessed in 8 cycles. Subsequent words are accessed in 4 clock cycles per
word. Calculate the total time needed to load the block into cache using interleaved and non-
interleaved memory.

Solution: Block size = 8 words

Consider a single memory block, the computation is as follows
1 clock cycle needed to send the address
8 clock cycles needed to access the first word
1 clock cycle to send one word to cache memory
4 clock cycles/word to read next 7 words
Hence total time needed to load one memory block into cache memory is
1 + 8 + 1 (4 * 7) = 38 cycles.

Ex:2 Consider a memory with 4 interleaved modules. All four modules start accessing data parallel.
Hence after 8 clock cycles. Each module has one word of data in its data buffer register. These four
data are transferred into cache during next four clock cycles. During this time, the next word is
accessed in each module. In the next four cycles, these words are transferred into cache. Calculate
the total time needed to load the block from interleaved memory into cache.

Solution: Total time = 1 + 8 + 4 + 4 = 17 cycles.

Ex:3 Calculate the total access time if the miss rate is 0.12, miss penalty is 0.015ms and cache access
time is 10ms.

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Solution: miss rate = 0.12

h = hit rate = 1 – 0.12 = 0.88
cache access time = Tc = 10ms
miss penalty Tm = 0.015ms
Hence average access time = h * Tc + (1 – h) * Tm
=( 0.88*10*10-6) + (1-0.88) * 0.015 * 10-3
Therefore, Tav = 10.6ms

Ex:4 A block set associative cache consists of a total of 64 blocks divided into 4 block sets. The main
memory contains 4096 blocks each consisting of 128 words.
1. How many bits are there in main memory address.
2. How many bits are there in each of the TAG ,SET and WORD fields.

Solution: Tag Set Word Main

Memory Address
4 5 7

Main memory address consists of 16 bits.

Word firld consists of 7 bits.
Set field consists of 5 bits.
Tag field consists of 4 bits.
5.0 Virtual memory

In case of modern computers, the address space specified by the processor, is larger than the size of the main
memory.
Ex: If the processor consists of 32 address lines, capable of addressing 232 = 4GB of memory.
The size of the main memory is in the range of hundred megabytes to 1G bytes.

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