Speaker

Video

T3: Fundamentals of Data Converters

Yun Chiu
([email protected])
University of Texas at Dallas
Richardson, TX

Feb 19, 2023

© 2023 IEEE International Solid-State Circuits Conference

Outline Speaker
Video

 Quantization and Sampling

 Overview of Data Converter Architectures
 How To Measure Data Converter Performance?
 Nyquist-Rate ADC and DAC Architectures
 Circuit Building Blocks
 Redundancy
 Digital Correctability and Calibration
 ADC Figure-of-Merits
 Data Converter Papers to See This Year
 References

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© 2023 IEEE International Solid-State Circuits Conference

Data Conversion Speaker
Video
CT, CA DT, DA

A/D

...
   Digitizing   
   Analogizing   

D/A

...
Analog World Digital World

 Data converters bridge analog (physical) world and digital (virtual) world
Y. Chiu T3: Fundamentals of Data Converters 3 of 109

© 2023 IEEE International Solid-State Circuits Conference

Data Conversion Speaker
Video
CT, CA DT, DA

Anti-Aliasing
S/H Quantization
Filter

Reconstruction/
S/H D/A
Smoothing Filter

Analog World Digital World

 Three key functions involved: Filtering, Sampling, Quantization

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Speaker
Video

QUANTIZATION

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A Mathematical View Speaker
Video
Vref bN-1…b0: MSB…LSB Vref

bN-1 bN-1
A/D D/A

...

...
b0 b0
Analog input Digital output Digital input Analog output

 Vin N   Vin  N-1

 V  N
Dout = 2 =  Vout = ∑ bi ⋅ 2i  FSN 
= ∑ b2
i⋅
i

 VFS   Δ  i=0  2  i=1 Δ

Division Multiplication

 N = # of bits, VFS = Full-Scale range, Δ = VFS/2N = 1 LSB, bi = {0, 1}

 Full-Scale range (VFS) is set by reference voltage Vref

Y. Chiu T3: Fundamentals of Data Converters 6 of 109

© 2023 IEEE International Solid-State Circuits Conference

Quantization Error Speaker
Video

Dout ε ε = Dout Δ - Vin

N=3 Assumptions:
7 Δ/2
 N is large (Δ is small)
6 0 Vin
 Vin » Δ and is active
-Δ/2
5 -3Δ -2Δ -Δ 0 Δ 2Δ 3Δ
 ε is uniformly distributed
4
 Spectrum of ε is white
3 Vin Pε Δ Δ
VFS VFS - ≤ε≤
2 2 2 2 2
1 1/Δ Δ/2 2
1 Δ
0 σ ε 2 = ∫ ε 2 ⋅ ⋅ dε =
-3Δ -2Δ -Δ 0 Δ 2Δ 3Δ -Δ/2
Δ 12
ε
-Δ/2 0 Δ/2
Ref. [1]

 "Random" quantization error is usually regarded as quantization noise

Y. Chiu T3: Fundamentals of Data Converters 7 of 109

© 2023 IEEE International Solid-State Circuits Conference

Signal-to-Quantization Noise Ratio (SQNR)
Speaker
Video

 For sinusoidal input with Vpp=VFS N SQNR

(bits) (dB)

VFS / 8 ( 2 Δ ) / 8
2
2 N 8 49.9
2N
SQNR = = = 1.5 × 2 10 62.0
σε 2 Δ2
12 12 74.0
14 86.0
SQNR = 6.02 × N +1.76 [dB] … …

 SQNR depicts the theoretical performance of an ideal converter

 Practical converter performance can be limited by many other factors
 Noise: thermal, 1/f, supply/substrate/coupling, etc.
 Distortion: DC & AC nonlinearities, measured by THD, SFDR, IM3, etc.
 Metastability (ADC): comparator fails to resolve within time limit
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Speaker
Video

SAMPLING

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Sampling (quite some math) Speaker
Video
Continuous Time Discrete Time
ΩT = ω
x(t) x(nT)
x(n)
x(t) Sampling x(n)

0 T 2T 3T 4T t =1
Sample rate: f fss=1/T
T T 0 1 2 3 4 n

1
X ( jω ) = X ( jΩ ) ⊗ ∑ δ ( Ω - kΩ s )
∞ ∞
x ( t )  ∫ x ( t ) e dt = X ( jΩ ) x ( n)  ∑ x (n) z = X ( jω )
FT ZT


-jΩt
T 

-n
k
-∞
 n=-∞ z=e jω
impulse train

X ( jΩ ) X ( jΩ ) ⊗ ∑ δ ( Ω - kΩ s ) Ref. [2]
X ( jω )
k

-ΩN ΩN
Ω Ω fs =
ω

∑ δ (Ω - kΩ )
k
s =
Ω ω
-2Ωs -Ωs 0 Ωs 2Ωs -4π -2π 0 2π 4π
Ω
-2Ωs -Ωs 0 Ωs 2Ωs
No aliasing if fs,min ≥ 2fN  Nyquist-rate sampling
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© 2023 IEEE International Solid-State Circuits Conference

Speaker
Video

OVERVIEW OF DATA CONVERTER

ARCHITECTURES
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Overview of ADC Architectures Speaker
Video
Per-step resolving (Conv. time)
1 word/OSR*Tclk
1 level/Tclk  N bits† (1 step)  fast
Resolution
[Bits] 1 bit/Tclk  Flash
20
Oversampling  Folding
Integrating
Partial word/Tclk  1 level (2N steps)  slowest
 Integration (Serial)
15
 1 bit (N steps)  slow
Pipeline
1 word/Tclk
Subranging  SAR
10 SAR  Algorithmic (Cyclic)
Time
Interleaving
 M bits (N/M steps)  medium
5
Flash  Pipeline
Nyquist-rate
 Subranging
Oversampling
 Others
0
1k 10k 100k 1M 10M 100M 1G 10G 100G  Time interleaving
Sample Rate [Hz]  high-speed ADC array
 Oversampling + NS
SAR, ΔΣM, TI ADC array are popular lately!  ΔΣ modulator

Y. Chiu T3: Fundamentals of Data Converters 12 of 109

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Overview of DAC Architectures Speaker
Video
 Nyquist-rate DACs (oversampling DACs skipped in this tutorial):

Topology Binary-weighted Unit-element Segmented

Technology (B.W.) (U.E.) (S.M.)

Resistive R2R Resistor string N.C.

Capacitive Charge redistribution (can support high speed [3])

High speed &

I-steering N.C. High speed
high resolution

 Some (fun or not so fun) facts about DACs:

 Every ADC has a DAC built in!
 DACs are conceptually straightforward, but tough to design or calibrate at high speed (GS/s+)!

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Speaker
Video

PERFORMANCE MEASUREMENT OF
DATA CONVERTERS
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Data Converter Measurements Speaker
Video

 Static measurement of converter transfer function (TF)

 Differential Non-Linearity (DNL), Integral Non-Linearity (INL)
 Code Density Test (CDT)
 Dynamic frequency- / time-domain measurement of signal quality
 Frequency domain techniques: FFT, SNR, SNDR (SINAD), SFDR, IM3 etc.
 Time-domain techniques: Sine-fit

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Speaker
Video

DNL AND INL

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© 2023 IEEE International Solid-State Circuits Conference

DAC Static Nonlinearity Speaker
Video
Vout Offset Vout Gain Error Vout Nonlinearity
VFS-Δ VFS-Δ VFS-Δ

VFS VFS VFS

2 2 2

Din Din Din

000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111

Segmentation Error (+) Segmentation Error (-) CT Analog Nonlinearity

Vout Vout Vout

VFS-Δ VFS-Δ

VFS VFS
2 2

Din Din Din

000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111

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© 2023 IEEE International Solid-State Circuits Conference

DNL and INL (DAC) Speaker
Video
DNL
Vout 2

1
VFS-Δ

LSB
0
Δi - Δ
INL DNLi = -1

VFS
Δ -2
0 200 400 600 800 1000
INL
2 DNL+1 i 2

INLi = ∑ DNL j 1

j=0

LSB
0

-1
Din -2
000 001 010 011 100 101 110 111 0 200 400 600 800 1000
Code

 DNL: deviation of a conversion step (Vj-Vj-1) from 1 LSB (Δ) – Incremental

 INL: deviation of the output (Vj) from ideal transfer curve – Cumulative

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© 2023 IEEE International Solid-State Circuits Conference

A More Realistic Measurement Speaker
Video
Vout  Can DNL < -1 ?
 DNL of nonmonotonic codes?
VFS-Δ  Measurement procedure:
 Least-square fit transfer curve
VFS  Stretch fitted line to ideal position
2
 Determine DNL and INL
 MATLAB built-in function “detrend”
 Σ(INL) = 0 – why?
Din
000 001 010 011 100 101 110 111

 In practice, endpoints of TF may not end up at 0 and VFS-Δ 

Assumption: Gain error and Offset are of less concern than DNL and INL

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© 2023 IEEE International Solid-State Circuits Conference

ADC Static Nonlinearity Speaker
Video
Dout Missing Code Dout Nonmonotonicity

111 Δi - Δ 111
DNLi =
110 Δ 110
How to
101 101 measure this?
100 100
011 011
010 010 
Can DNL < -1?
001 001 
000 Vin 000 Vin
0 VFS/2 VFS 0 VFS/2 VFS

 ADC static errors also include gain, offset, nonlinearity (DNL and INL), but
 Watch out for missing code and nonmonotonicity!

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© 2023 IEEE International Solid-State Circuits Conference

INL and DNL (ADC) Speaker
Video
Dout  Any code missing? Dout
 Nonmonotonic? 7
111
6
110
Offset-free 5
101
diff. ADC 4
100
3 Vin
011 VFS VFS
2 2 2
010
1
001
0
000 Vin
0 VFS/2 VFS -3Δ -2Δ -Δ 0 Δ 2Δ 3Δ

 Connect midpoints of treads to determine the INL profile (also “detrend”)

 Direct TF measure requires a high-resolution DAC to produce/record the exact
input analog values
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© 2023 IEEE International Solid-State Circuits Conference

Code Density Test Speaker
Video
Vin uniformly distributed over [0, VFS] Vin uniformly distributed over [0, VFS]
Count

Count
DNLi
Δi - Δ
=
n0 n1 n2 n3 n4 n5 n6 n7 Δ
ni - ni n3>Δ
Δ Δ Δ Δ Δ Δ Δ Δ ≈
ni
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Vin Vin
0 VFS 0 VFS

 Apply a linear ramp to ADC input and collect the output code histogram
 Ball-casting problem: # of balls collected proportional to bin size (DNL)
 Missing codes  DNL = -1
 Nonmonotonic codes  all lumped together, very misleading!
 Linear ramp is difficult to generate in practice  use filtered sinewave instead
(but needs to correct the bowl-shaped density curve) Ref. [4]
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© 2023 IEEE International Solid-State Circuits Conference

Speaker
Video

FREQUENCY- & TIME-DOMAIN

MEASUREMENTS
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Spectrum of Quantized Signal Speaker
Video

0 SQNR = 61.93 dB
 N = 10 bits
ENOB = 9.995 bits  fs = 8192, fin = 779
-20
 8192 samples, only [0, fs/2] shown
-40  Normalized to the amplitude of Vin
 Effective # of bits (sinusoidal):
dB

-60

-80
SQNR -1.76 dB
ENOB =
-100
6.02 dB
-120
0 500 1000 1500 2000 2500 3000 3500 4000
Frequency

 FFT requires power-of-two number of samples to compute the spectrum

 fin and fs must be incommensurate, e.g., fin and fs are co-prime
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© 2023 IEEE International Solid-State Circuits Conference

Commensurate fs and fin Speaker
Video

0 fs = 8192 0
fs = 8192
fin = 256 fin = 2048
-20 -20

-40 -40
dB

dB
-60 -60

-80 -80

-100 -100

-120 -120
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
Frequency Frequency

 Repeated/periodic samples lead to periodic quantization errors, manifested as

harmonic distortions

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© 2023 IEEE International Solid-State Circuits Conference

Spectrum Leakage Speaker
Video

0 fs = 8192 0
fs = 8192
fin = 779.3 fin = 779.3
-20 -20

-40 -40 Blackman

window
dB

dB
-60 -60

-80 -80

-100 -100

-120 -120
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
Frequency Frequency

 Samples must include integer # of cycles of input signal

 Windowing can be applied to eliminate spectrum leakage
 Tradeoff b/t main-lobe width and sideband rejection of different windows
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© 2023 IEEE International Solid-State Circuits Conference

Frequency-Domain Performance Eval Speaker
Video
PSD
 Signal-to-noise plus distortion ratio (SNDR)
0 SNDR = 59.2 dB
THD = 63.1 dB  ALL bins except input are noise + disto
-20
SFDR = 64.0 dB  Total harmonic distortion (THD)
ENOB = 9.54 bits  Usually count first 10 HDs
-40
SFDR
 Spurious-free dynamic range (SFDR)
dB

-60
HD3  Effective # of bits (sinusoidal):
Noise -80 HD9
Floor SNDR - 1.76 dB
(NSD) -100 ENOB =
[V/√Hz] 6.02 dB
-120
0 500 1000 1500 2000 2500 3000 3500 4000
Frequency

 High-order harmonics are aliased back, visible in band [0, fs/2]

 E.g., HD3 @ 779x3+1=2338, HD9 @ 8192-9x779+1=1182
 Two-tone/IM3 test is useful for ∑ΔM and DACs, but uncommon for Nyq. ADCs
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© 2023 IEEE International Solid-State Circuits Conference

Sine-Fit: A Time-Domain Method Speaker
Video
PSD T

A
t
SFDR Time domain  Ф
 Freq. domain
HD3
Error sequence
f t
0 fs/2

 Windowing, phase noise of signal/clock generator etc. can make frequency-

domain SNDR measurement quite difficult
 If input is a sinewave, directly fit the measured (or simulated) samples to an
ideal sinewave can yield accurate SNDR measurement (in MATLAB)
 Nonlinear least-square fit by optimizing over (A, ω=2ϖ/T, Ф)

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© 2023 IEEE International Solid-State Circuits Conference

Speaker
Video

NYQUIST ADC ARCHITECTURES

FLASH, SAR, AND PIPELINE

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Flash ADC – Exhaustive Search Speaker
Video
Vi VFS Vi Strobe (fs)
VFS  Massive parallelism
7
 Very fast (N bits/step)
7Δ V2N-1
6  Reference ladder: 2N
6Δ equal-sized resistors
5  Input compared to 2N-1

Encoder
5Δ Vj
Do ref. taps (Vj)
…
…

…
…
…

 Throughput = fs
2Δ
1  Complexity ~2N
Δ V1  Rarely used for more
0
than 6-8 bits
Do 0

2N 2N-1
resistors comparators

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© 2023 IEEE International Solid-State Circuits Conference

Thermometer Code Speaker
Video
VFS Vi Strobe (fs) Thermometer code b2 b1 b0

 Thermometer
0 1 code
111
 1-of-n code
1 0
110
 T2B encoder

…
…
…

…
1 1
010

1 1
001

1-of-n code 000

2N-1
comparators
ROM encoder
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© 2023 IEEE International Solid-State Circuits Conference

Bubble / Sparkle Errors Speaker
Video
Vi 1 1 0
Bubble
 3-input

…
0 boundary det.
 Majority voting
1 0
100
 Gray code
0 1
011

1 0
010
…

Misfired CMP ROM encoder

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© 2023 IEEE International Solid-State Circuits Conference

Quantization – Long Division Speaker
Video

V 
Do =  in 
735
 ÷ 125
 = [
1,0,1]b
 
r 110

Vin LSB QN (Remainder)
∆  Do ( Quotient )
N=3

FS = 1000 1 0 1
Δ = FS/8 500 ) 735 250 ) 235 125 ) 235
= 125 500 0 125
Vin = 735 235 235 110

Step 1: Step 2: Step 3:

1st bit 2nd bit 3rd bit

 The procedure is also known as binary (radix=2) search

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© 2023 IEEE International Solid-State Circuits Conference

Successive-Approximation (SAR) ADC Speaker
Video

Bit cycles
Vi

b0  1 comparator
VDAC  1 DAC
DAC Do  Some digital logic

...
...
bN-1

 Serial architecture (1 bit/step)  NOT built for high speed operation

 Hardware reuse / very efficient, minimal architecture

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© 2023 IEEE International Solid-State Circuits Conference

Binary Search: MSB Cycle Speaker
Video
N = 3, FS = 1 V, Δ = 0.125 V, Vin = 0.735 V
0.735V
VX
Vi VX
1
b0

Sampling
Bit
VDAC 0
cycle
DAC Do

...
...
0.5V 1
MSB
bN-1

 VX = Vi – 0.5V;
 if VX > 0, MSB = 1, keep current VX  VX;
otherwise, MSB = 0, restore VX  VX + 0.5V;

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© 2023 IEEE International Solid-State Circuits Conference

Binary Search: MSB-1 Cycle Speaker
Video
N = 3, FS = 1 V, Δ = 0.125 V, Vin = 0.735 V
0.735V
VX
Vi VX
1 2
b0

Sampling
Bit
VDAC 0
cycle
DAC Do

...
...
0.5V+ 1 0
MSB MSB-1
0.25V bN-1

 VX = VX – 0.25V;
 if VX > 0, MSB-1 = 1, keep current VX  VX;
otherwise, MSB-1 = 0, restore VX  VX + 0.25V;

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© 2023 IEEE International Solid-State Circuits Conference

Binary Search: MSB-2 Cycle Speaker
Video
N = 3, FS = 1 V, Δ = 0.125 V, Vin = 0.735 V
0.735V
VX
Vi VX
1 2 3
b0

Sampling
Bit
VDAC 0
cycle
DAC Do ...

...
...
0.5V+ 1 0 1
MSB MSB-1 MSB-2
0.125V bN-1

 VX = VX – 0.125V;
 if VX > 0, MSB-2 = 1, keep current VX  VX;
otherwise, MSB-2 = 0, restore VX  VX + 0.125V;

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© 2023 IEEE International Solid-State Circuits Conference

Modified Binary Search Speaker
Video

V 
Do =  in 
735
 ÷ 125
 = [
1,0,1]b
 
r 440
 /4
Vin LSB
∆  Do ( Quotient )
QN (Remainder)
N=3

FS = 1000
1 0 1
Δ = FS/8 500 ) 735 500 ) 470 500 ) 940
= 125 500 0 500
Vin = 735 235×2 470×2 440

Step 1: Step 2: Step 3:

1st bit 2nd bit 3rd bit

 Always use the same divisor but amplify the remainder / residue

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© 2023 IEEE International Solid-State Circuits Conference

Algorithmic (Cyclic) ADC Speaker
Video
Voltage TF
Bit cycles Vo
bj=0 bj=1
VX VFS
Vo
Vi 2×

1-b VFS/2
VFS/2 DAC 0 VFS/2 VFS VX
0
 V 
bj Vo = 2 ⋅  VX - b j ⋅ FS 
 2 

 Fixed comparison threshold (VFS/2) + 1b DAC + 2X Residue Gain

 Comparison  if VX < VFS/2, then bj = 0; otherwise, bj = 1
 Residue generation  Vo = 2·(VX – bj·VFS /2)

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© 2023 IEEE International Solid-State Circuits Conference

Pipelined ADC Speaker
Video
n1 bits n2 bits n3 bits nk bits
 Concurrent stage
operation
Vin Stage 1 V1 Stage 2 V2 Stage 3 V3 Vk-1 Stage k
 Latency ~ k/2
(Φ1) (Φ2) (Φ1) (.)
 Throughput ~ fs
 Complexity ~ N
T V1 V2  Scalable to M-bit/stage
S/H 2 n2
(1≤M<N)
Φ1 Φ2 Φ1 Φ2
n2 bits Residue  Power saving possible
two-phase Amp (RA) by stage tapering along
sub- sub-
nonoverlapping pipeline
A/D D/A
clock

 Algorithmic loop unrolled  pipeline enables high conversion throughput

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© 2023 IEEE International Solid-State Circuits Conference

Speaker
Video

NYQUIST DAC ARCHITECTURES

BW, UE, AND SEGMENTED

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© 2023 IEEE International Solid-State Circuits Conference

Binary-Weighted (BW) DAC Speaker
Video
T Cu: unit capacitance Φ1
16Cu N-1
 i VR 
Φ1 Φ2 Φ1 Φ2 CP
Φ2 Vo ≈ ∑ bi ⋅  2 N 
VX Vo i=0  2 
Φ1
A Multiplier
8Cu 4Cu 2Cu Cu

Φ1  
 2N Cu  N-1 V
VR = Vo   ⋅ ∑ bi ⋅  2i NR 
 N Cp + ( 2N+1 - 1) Cu  i=0  2 
 2 Cu + 
b3 b2 b1 b
 A 
0

 Charge redistribution (CR) of a BW capacitor array  very efficient architecture

 N-bit DAC requires N switching elements, w/ direct binary bits passthrough control
 Can be generalized to resistive, R2R and current-steering topologies

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© 2023 IEEE International Solid-State Circuits Conference

Midscale DNL / INL (MSB Transition) Speaker
Video
Vo
Code 0111 Code 1000
+DNL
 C + C 2 + C3   C 
Vo ( 0111)  1
=  ⋅ VR Vo (=
1000 )  4  ⋅ VR
 16Cu   16Cu 
δC > 0

half array other half

0 Di
0111 1000
Assume : C4 − ( C1 + C2 + C3 ) = Cu + δC

V (1000 ) − Vo ( 0111) − 1 LSB Vo

DNL = o
1 LSB
δC -DNL
=  often the largest DNL error δC < 0
Cu

 Architectural efficiency comes at a cost of linearity 0 Di

 Original CR SAR ADC employed this type of DAC 0111 1000

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© 2023 IEEE International Solid-State Circuits Conference

Unit-Element (UE) DAC Speaker
Video
VR UE DAC:
Di
b0 b0 b1 b1 σR
σDNL =
3 R
2N  σR 
σINL ( max ) ≈  
2 2 R 

BW DAC:
1 Vo
σ 
Co σDNL ( max ) ≈ 2N  R 
R 
0
Vo 2N  σR 
σINL ( max ) ≈  
2 R 

 Inherently monotonic  good DNL performance (what about INL?)

 ~2N switching elements  complexity ↑ speed ↓ for large N  typically N≤8 bits
 Needs binary-thermometer decoder
Y. Chiu T3: Fundamentals of Data Converters 44 of 109

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Current-Steering DAC (UE) Speaker
Video
Io
to termination
resistor Io

Φ
I-steering I-steering dj
Sj Sj
cell j-1 cell j
j = 1:2N-1
Φ
dj-1 dj-1 dj dj dj
Binary-to-Thermometer Decoder I

b1 ... bN High-speed

 Fast switching, inherently monotonic → good DNL performance

 ~2N current cells decomposed into a (2N/2×2N/2) matrix of rows and columns

Y. Chiu T3: Fundamentals of Data Converters 45 of 109

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Segmented (SM) DAC Speaker
Video
VFS
L-bit BW
High-speed,
N = M+L L trailing bits
High-resolution L trailing
bits

…
Vo
M M-bit UE
M leading
digital input buffer

leading row B2T decoder bits

bits Io
N-bit
...

input to termination
M resistor
2 0
0 Di 2N-1
UE BW

M σDNL ( max ) ≈ 2L+1σUE

2
column B2T decoder 2N
σINL ( max ) ≈ σUE
2
 A divide-and-conquer approach to tackle complexity of UE DAC
 # of switching elements ~2M+L << 2M+L
Y. Chiu T3: Fundamentals of Data Converters 46 of 109

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Comparison of DAC Architectures Speaker
Video
BW DAC: UE DAC: SM DAC:

σDNL ( max ) ≈ 2N σUE σDNL = σUE σDNL ( max ) ≈ 2L+1σUE

2 N 2N 2N
σINL ( max ) ≈ σUE σINL ( max ) ≈ σUE σINL ( max ) ≈ σUE
2 2 2

Example: N = 12, M = 8, L= 4, σUE = 1%

σINL σDNL
Architecture # of switching elements
[LSB] [LSB]
BW 0.32 0.64 12 (=N)
UE 0.32 0.01 4095 (≈2N)
SM 0.32 0.057 259 (≈2M+L)

Y. Chiu T3: Fundamentals of Data Converters 47 of 109

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Speaker
Video

DATA CONVERTER
CIRCUIT BUILDING BLOCKS
Y. Chiu T3: Fundamentals of Data Converters 48 of 109

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Common Circuit Building Blocks Speaker
Video

 DAC: resistive, capacitive, current types, unit-element, binary-weighted, segmented

architectures – every ADC has a DAC built-in!
 Comparator: decision device, regeneration speed, metastability Covered in
 Sample and Hold (S/H) or Track and Hold (T/H): CT-DT conversion this section

 Residue Amplifier (RA): closed-loop vs. open-loop, static vs. dynamic amplifiers
 Reference and Biasing: BGR, current mirror, on-chip / off-chip bypass
 Clocking Circuits: jitter critical for high-speed ADC and DAC (power consumption)
 Digital Logics: combinatory, sequential, memory, I/O, etc.
 Input and Reference Buffers: peripheral, critical, and power hungry (but often not
included in the converter core)

Y. Chiu T3: Fundamentals of Data Converters 49 of 109

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Speaker
Video

COMPARATOR

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Comparator: Decision-Making Device Speaker
Video
Vo “1”
Φ Ideal TF
Vm- Vo+
Vth
Vi Vi
Vth
Vm+ Vo-
“0”

 From soft to hard decision 

Vth Vm+ Vo+

Vi Vm- Vo-

 Precise gain and linearity unnecessary → simple, open-loop, low-gain, and

wideband Preamplifier (PrA) followed by Latch (positive feedback)
Y. Chiu T3: Fundamentals of Data Converters 51 of 109

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A Simple Comparator Speaker
Video
VDD

PrA track Latch

Φ Latch reset regenerate
Vm-
Vm+ Φ
VDD
Vi+ Vi- Vo + Vo-

Vo+

Vo

Vo-
VSS
VSS
Preamp Latch

 Preamp establishes a seed voltage for latch regeneration  dominates offset

 Usually no return after regeneration starts
Y. Chiu T3: Fundamentals of Data Converters 52 of 109

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Latch Regeneration Speaker
Video

Vo+ Vo- Vo+

-1
1 2 3 4
CL CL Vo+
CL gmVo-
M7 M8 Vo-
Vo-

 Vo + = − Vo − sp = gm / CL Case Vo(t=0) Vo t/(CL/gm)

1 1   Vo + 
 + or   −  = 0 ⇒
 Vo = −gm ⋅ Vo / sCL
−
 1 gm / sCL   Vo  (RHP pole )  100mV 1V 2.3

 10mV 1V 4.6
 gm  CL  Vo ( t )   1mV 1V 6.9
Vo ( t ) = Vo ( t = 0 ) ⋅ exp  t ⋅  or t = ⋅ ln  
 CL  gm V
 o ( t = 0 )   100μV 1V 9.2

Y. Chiu T3: Fundamentals of Data Converters 53 of 109

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Metastability Speaker
Video

T/2 Do
δ δ
 g  ...
Φ
Vo ( t ) = APrA ⋅ Vi ( 0 ) ⋅  t ⋅ m  Error Rate =
1 LSB
 CL 
δ
j
APrA=10× Curve Vi(t=0) t/(CL/gm)
1 2 3 4 Vos
δ
Vo +  10mV 2.3

Vo-
 1mV 4.6 j-1
Vos
 100μV 6.9 ... Vos 1 LSB
Vi
 10μV 9.2 ... Vth,j-1 Vth,j Vth,j+1 ...

 Comparator fails to produce valid logic output for tiny inputs  metastability
 No decision is often worse than a wrong decision! (conversion may halt!)
Y. Chiu T3: Fundamentals of Data Converters 54 of 109

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Dynamic Comparator Speaker
Video

Φ Φ

Vi+ Vi- Vo+ Vo- Vi+ Vi- Vo+ Vo-

Preamp Latch Preamp Latch

 Starting with the static comparator (i.e., preamp + latch)

 First, add a PMOS cross-coupled pair in the latch to fully regenerate logic levels
 Second, turn the static preamp into a dynamic one

Y. Chiu T3: Fundamentals of Data Converters 55 of 109

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Dynamic Comparator Speaker
Video

Φ Φ Φ Φ Φ Φ

Φ
Vo + Vo- Vo+ Vo- Vo + Vo -

Vi+ Vi- Vi+

  Vi- Vi+
  Vi-

Φ Φ Φ

 Third, stack the two together for current reuse (to save power)
 Then, replace the crowbar by conspicuous PMOS reset (high) switches
 Lastly, completely reset ALL internal nodes to remove memory

Y. Chiu T3: Fundamentals of Data Converters 56 of 109

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Strong-Arm Dynamic Comparator Speaker
Video

Φ Φ Φ Φ

 Compact (PrA + latch)

Vo + Vo -  Fully dynamic operation
 low power
 Single-phase clock
(Low reset, high eval.)
 Both nodes  and 
Vi+
  Vi-
start @VDD, end @Gnd
 large CM kickback

Y. Chiu T3: Fundamentals of Data Converters 57 of 109

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Speaker
Video

MOS SAMPLE-AND-HOLD

Y. Chiu T3: Fundamentals of Data Converters 58 of 109

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ZOH, S/H, and T/H Speaker
Video
Ron V(t) ZOH
PMOS
NMOS  A.k.a. S/H
VTp VTn  Zero acq. time
 Not realistic
0 T 2T t
CMOS T

0 Vi VDD V(t) T/H

Ф
 T/2 acq. time
RS
Vo  Practical
H T H T H T H T H T
Vi CS 0 T 2T t
Top-Plate T/2
Sampler

W  MOS technology naturally suitable for implementing T/H

R on
−1
= μCox (VDD − Vth − Vi )
L  Terms S/H and T/H are often used interchangeably
Y. Chiu T3: Fundamentals of Data Converters 59 of 109

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MOS Switch Performance Speaker
Video
RS Ron

ΔQ 1 Qch
Vi C S Vo Charge Inj.: ΔV = ≈ Ф
CS 2 CS

1 μQ Zi
1 L 2
Tracking BW: TBW ≈ = 2 ch Cgs Cgd
Vout
R on = R onCS L CS
W
μCox ( VDD − Vth − Vi ) μQch Vin Qch CS
L
Performance TBW μQch C 2μ
Accuracy tacq ≈ 2 ⋅2 S =
metrics: ΔV L CS Qch L2 ΔQ ( Zi ,CS ,tr /f ...)
0.1% (10b) ≥ 7τ
0.01% (13b) ≥ 9τ

 Tracking bandwidth limited by switch on-resistance Ron (consider clock bootstrapping)

 Clock Feedthrough (CF) and Charge Injection (CI) are network/clock/signal dependent
 Technology scaling improves T/H performance! (a.l.a. leakage allows)
Y. Chiu T3: Fundamentals of Data Converters 60 of 109

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Aperture Error and Bottom-Plate Sampling
Speaker
Video
Ф
RS Ф
Vo CS X
Vi CS Vi
Bottom-Plate
Фe Sampling
VDD
Ф
Vi+Vth(Vi)

Ф
Vth(Vi) Фe Ф
0
Switch on Switch off

 Exact sampling moment (aperture) depends on input in top-plate sampler

 Bottom-plate sampling avoids aperture error and CF+CI distortion by V.G. switching
Y. Chiu T3: Fundamentals of Data Converters 61 of 109

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Aperture Jitter Speaker
Video
140
V(t) Ref. [5] σ = 0.1ps
dV t
120 σ = 1ps
dt t
σ = 10ps
δV t
σ = 100ps
100 t

δt 80

SNR [dB]
Track Hold t 60

40
A 2ω 2σ t 2
δV ( t ) =
2

2 20 A2  A 2ω 2σ t 2  1
SNR =  = 2 2
2  2  ωσ
  t
 Assuming sinewave 0
 Cyclostationary error 10
6
10
7
10
8
10
9

Input Freq [Hz]

 Aperture jitter limits sampler SNR especially at high frequencies

Y. Chiu T3: Fundamentals of Data Converters 62 of 109

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Evaluating T/H Performance Speaker
Video
RS Ron

Sampling
network: Vi C S Vo Vi 2
SNDR = 2 2
A ω 2
R = RS + R on VN2 + σ t + VDISTO 2
2
2
kT/C ∞ 1 kT
VN = ∫
2
noise: 4kTR ⋅ df = Noise Jitter Distortion
0 1+ j2π ⋅ f ⋅ RCS CS

large R
Noise CS 100pF 1pF 10fF
small R
PSD
kT
6.4μV 64μV 640μV
CS
0 f T = 300K
fs 2fs

Y. Chiu T3: Fundamentals of Data Converters 63 of 109

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Clock Bootstrapping Speaker
Video
Φ Φ Charge pump Large cap
(VDD doubler) (battery) VDD
VDD
Φ
In Out M5 M6 M2
M1
M4 M3
Ron C1 C2 C Φ
Φ
Φ
OFF switches
Φ
Out
M1
Φ
Φ ON switches In
VSS
0 Vi VDD Ref. [6]

 Constant gate overdrive VGS = VDD  Ron independent of Vin to the first order
(body effect, charge sharing)  larger tracking BW, better linearity
Y. Chiu T3: Fundamentals of Data Converters 64 of 109

© 2023 IEEE International Solid-State Circuits Conference

Speaker
Video

REDUNDANCY
(NO MULTI-STEP ADC WORKS WITHOUT IT!)

Y. Chiu T3: Fundamentals of Data Converters 65 of 109

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Comparator Offset in Pipelined ADC Speaker
Video
Vo CMP Vos Vo CMP Vos
bj+1=2
bj=0 bj=1 bj=0 bj=1 CMP
VFS VFS
bj+1=1 bj+1=1
CMP CMP
VFS/2 VFS/2
bj+1=0 bj+1=0
CMP
0 VFS/2 VFS Vi 0 VFS/2 VFS Vi
Do Do bj+1=-1

11 11
10 10
10 10 “02” is a
01 01 01 02
01 01 redundant code
00 Vi 00 Vi
0 VFS/2 VFS 0 VFS/2 VFS
 Nearly Zero Tolerance (< 1 LSB) on comparator offset!!
 Architectural Redundancy introduced by over-/under-range comparators
Y. Chiu T3: Fundamentals of Data Converters 66 of 109

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How Exactly Does Redundancy Work? Speaker
Video
Vo
Δbj = -1 b
bj+1=2  Max tolerance of
bj=0 bj=1 CMP comparator offset is ±VFS/4
VFS
 simple comparators
bj+1=1
ΔVo = +VFS CMP
VFS/2  Key to understand
bj+1=0 redundancy:
CMP
VFS ( Vo + ∆Vo )
Vi = (b j + ∆b j ) ⋅
0 VFS/2 VFS Vi
bj+1=-1 +
Do 2 2
VFS ( Vo + VFS )
11 = (b j - 1) ⋅ +
10 2 2
10 V V
01 02 = b j ⋅ FS + o
01 2 2
00 Vi
0 VFS/2 VFS
 Complementary analog and digital errors cancel each other w/ redundancy
Y. Chiu T3: Fundamentals of Data Converters 67 of 109

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From 1-bit To 1.5-bit Architecture Speaker
Video
b=0 b=0.5 b=1 b=0 b=1 b=0 b=0.5 b=1
VR VR VR
-½ bit
VR/2 VR/2 VR/2
-½ VFS
Vo Vo Vo
0 0 0
+½ VFS
-VR/2 +½ bit -VR/2 -VR/2

-VR -VR/4 VR/4 VR -VR -VR/2 VR/2 VR -VR -VR/2 VR/2 VR

Vi Vi Vi

∆Vo 1-bit residue TF ∆Vo

∆b + =0 ∆b + =0
2  no redundancy 2

Y. Chiu T3: Fundamentals of Data Converters 68 of 109

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From 1-bit To 1.5-bit Architecture Speaker
Video
b=0 b=0.5 b=1 b=0 b=0.5 b=1 b=0 b=0.5 b=1
VR VR VR
-½ bit
VR/2 VR/2 VR/2
-½ VFS
Vo Vo Vo
0 0 0
+½ VFS
-VR/2 +½ bit -VR/2 -VR/2

-VR -VR/4 VR/4 VR -VR -VR/4 VR/4 VR -VR -VR/2 VR/2 VR

Vi Vi Vi

 1.5-bit residue TF: 3 decision levels → ENOB = log23 ≈ 1.58

 Max tolerance of comparator offset is ±VR/4
 Also known as Sweeny-Robertson-Tocher (SRT) division algorithm
Y. Chiu T3: Fundamentals of Data Converters 69 of 109

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1.5-bit Multiplier DAC (MDAC) Speaker
Video
T
Φ2 b=0 b=1 b=2
VR
Φ1 Φ2 Φ1 Φ2 Φ1 C1 Vo
Vi VR/2
Φ1 C2
-VR/4 Vi
A Vo 0

VR/4 Φ1e -VR/2

-VR Φ2
0 Decoder -VR -VR/4 VR/4 VR
VR
C1 + C2 C
Vo
= ⋅ Vi + (1- b ) 2 ⋅ VR
C1 C1 Vo = 2 ⋅ Vi + (1- b ) ⋅ VR

 2X gain + 3-level DAC + summation all integrated Ref. [7]

 Can be generalized to n.5-bit architectures

Y. Chiu T3: Fundamentals of Data Converters 70 of 109

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2.5-bit MDAC Speaker
Video
T
Φ2
Vo
Φ1 Φ2 Φ1 Φ2 VR
Φ1 C1 b=0 b=1 b=2 b=3 b=4 b=5 b=6
Vi VR/2
Φ1 C2
Vi
VR1 0
Φ1 C3
...

6
VR -VR/2

6 CMP’s b Φ1 C4
A Vo -VR -5VR/8 -3VR/8 -VR/8 VR/8 3VR/8 5VR/8 VR
-VR Φ2
Φ1e
Φ2
0 Decoder
VR
Φ2 Vo = 4 ⋅ Vi + ( 3 - b ) ⋅ VR

 4X gain + 7-level DAC + summation all integrated

Y. Chiu T3: Fundamentals of Data Converters 71 of 109

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Error-Free Conversion With Redundancy Speaker
Video
Vo Vo
b=-3 b=-2 b=-1 b=0 b=1 b=2 b=3 -3 -2 -1 0 1 2 3
VR VR

overflow redundancy
VR/2 VR/2

0 normal residue range 0

-VR/2 -VR/2

underflow redundancy
Vi Vi
-VR VR1 VR2 VR3 VR4 VR5 VR6 VR -VR VR1 VR2 VR3 VR4 VR5 VR6 VR

Ideal Residue TF A More Realistic Residue TF

 Comparator and residue amplifier offsets absorbed by Internal Redundancy

 Error-free conversion when residue is confined in the range [-VR, +VR]

Y. Chiu T3: Fundamentals of Data Converters 72 of 109

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Pipeline Redundant Bits Assembly Speaker
Video

V1 V2 Vk-1 stage For pipelined ADC,

stage stage
Vin z-½ z-½ z-½
1 2 k
bk-1
Do = W=
Do ∑ w ⋅b j j
b1 b2 bk j

T
b1=2 1 0
z-½
Φ1 Φ2 Φ1 Φ2
b2=0 0 0
z-1 z-½
-1
b3=1 0 1
sample i+1
z-1 z-1 z-½ b4=2 1 0
sample i b5=1 0 1
z-1 z-1 z-1
Do 1 0 1 0 0 1
MSB LSB

Decision Vector: Do = {b1, b2,…,bk}, Scalar Decision: Do = f(Do)

Y. Chiu T3: Fundamentals of Data Converters 73 of 109

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How Does Redundancy Work For SAR? Speaker
Video
16 8 4 2 1 16 10 6 3.5 2 1
Bit cycles
radix 16/8 8/4 4/2 2/1 VX radix 1.6 1.67 1.71 1.75 2
Vi
+VFS 1111 +VFS 1111
1110 b0 1110
1101
5/8 1101
1/2 1100 VDAC 3/8 15/32 3/8 1100
DAC Do

...
...
1011 1011
1/4 3/8 1010 1010
1001 1001
Vin

Vin
0 1000 bN-1 0 1000
0 0111
0 0111
0110 0110
0101 0101
4 bits 0100 w/o redundancy 5 bits 0100

resolved 0011
0010
resolved 0011
0010
0001 w/ redundancy 0001
-VFS 0000 -VFS 0000
MSB LSB MSB LSB
bit cycle bit cycle

Binary search Sub-binary search

Y. Chiu T3: Fundamentals of Data Converters 74 of 109

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Binary Search Revisited Speaker
Video
16 8 4 2 1 16 8 4 2 1 16 8 4 2 1
radix 16/8 8/4 4/2 2/1 radix 2 2 2 2 radix 2 2 2 2
+VFS 1111 +VFS 1111 +VFS 1111
1110 1110 0 1110
1101 1101 0 1101
1/2 1100 1100 1 1100
1011 Input 0
1011 Input 0 1011
1/4 3/8 1010
1 1010
1 1010
1001 1 1001 1 1001
Vin

Vin

Vin
0 1000 1000 1000
0 0 0
0111 1 0111 1 0111
0110 0110 0110
0101 0101 0101
0100 0100 0100
0011 0011 0011
0010 0010 0010
0001 0001 0001
-VFS 0000 -VFS 0000 -VFS 0000
MSB LSB MSB LSB MSB LSB
bit cycle bit cycle bit cycle

 Binary search is efficient, but displays zero error tolerance

Y. Chiu T3: Fundamentals of Data Converters 75 of 109

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Sub-Binary Search ‒ Redundancy Speaker
Video
16 10 6 3.5 2 1 16 10 6 3.5 2 1 16 10 6 3.5 2 1
radix 1.6 1.67 1.71 1.75 2 radix 1.6 1.67 1.71 1.75 2 radix 1.6 1.67 1.71 1.75 2
+VFS 1111 +VFS 1111 +VFS 1111
1110 1110 1110
5/8 1101
0 1101
0 1101
3/8 15/32 3/8 1100 1 0 1 1100 1 0 1 1100
1011 Input 1011 Input 1011
1010 1010 1010
1001 1 1001 1 0 1 1 1001
Vin

Vin

Vin
0 0 1000
0
1000
0 1
1000
0111 0111 0111
0110 0110 0110
0101 0101 0101
0100 0100 0100
0011 0011 0011
0010 0010 0010
0001 0001 0001
-VFS 0000 -VFS 0000 -VFS 0000
MSB LSB MSB LSB MSB LSB
bit cycle bit cycle bit cycle

 Redundancy of sub-binary search can absorb intermediate decision errors

Y. Chiu T3: Fundamentals of Data Converters 76 of 109

© 2023 IEEE International Solid-State Circuits Conference

Sub-Radix-2 Implementations Speaker
Video
16 10 6 3.5 2 1 1.85 1.84 1.83 1.82 1.8 1 16 8 8 4 2 1
radix 1.6 1.67 1.71 1.75 2 radix 1.8 1.8 1.8 1.8 1.8 radix 2 1 2 2 2
+FS 1111 +FS 1111 +FS 1111
1110 1110 1110
1101 1101 1101
1100 1100 1100
1011 1011 1011
1010 1010 1010
1001 1001 1001
Vin

Vin

Vin
1000 1000 1000
0111 0111 0111
0110 0110 0110
0101 0101 0101
0100 0100 0100
0011 0011 0011
0010 0010 0010
Ref. [8] 0001 Ref. [9] 0001 Ref. [10] 0001
-FS 0000 -FS 0000 -FS 0000
MSB LSB MSB LSB MSB LSB
bit cycle bit cycle bit cycle

Nonuniform radix Uniform radix Occasional sub-radix

Y. Chiu T3: Fundamentals of Data Converters 77 of 109

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Uniform Sub-Radix-2 SAR ADC Speaker
Video
For redundant bits, Φ1e VX

C j+1
= radix < 2 SAR
Cj
logic
CN-1 C1 C0 C0
e.g., in a uniform radix SAR D = { bj }
Do

VR
… C0·radix2 C0·radix C0 Φ1 Φ1 Φ1 Φ1
C2 C1 C0 Vi

 Hard-coded radices dependent on the DAC capacitor ratios

 Minimal analog complexity, no additional decoding effort
 Suitable for high-resolution SAR ADC (that requires radix calibration)
Y. Chiu T3: Fundamentals of Data Converters 78 of 109

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SAR Redundant Bits Assembly Speaker
Video
{wj}: bit weights Vi

 Cj 
∑ w ⋅b
N-1
Do ≈∑  b0 Do = W=
Do
 ⋅ b j VDAC
j j

j=0  ∑ C j 
 j

DAC Do

...
...
N-1
e.g., uniform radix 1.8
= ∑ wj ⋅bj VDAC(final)≈Vi
j=0 bN-1 b4=1 1∙1.84
b3=0 0∙1.83
b2=1 1∙1.82
N-1 b2 = 1
∑Q DAC = VR ∑ C j ⋅ b j b1 = 1 b1=1 1∙1.81
j=0 b0 = 0 b0=0 0∙1.80
N-1
= Vi ∑ C j + Noise … C0·radix2 C0·radix C0 Do 15.5
j=0
C2 C1 C0

Decision Vector: Do = {bN-1, bN-2,…,b0}, Scalar Decision: Do = f(Do)

Y. Chiu T3: Fundamentals of Data Converters 79 of 109

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Speaker
Video

DIGITAL CORRECTABILITY AND

CALIBRATION
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Digital Calibration Speaker
Video

Digital
ADC
Post-Processing
Analog Input Digital Output Refs. [11-27]

Digital
DAC
Pre-Processing
Digital Output Analog Input

 Many analog errors in data converters, e.g., offset, gain error, nonlinearity,
can be corrected digitally, which is widely termed Digital Calibration
 Digital calibration (aka digital enhancement, digital assistance, self-healing) is
an opportunity and gift presented by the Moore’s law!
Y. Chiu T3: Fundamentals of Data Converters 81 of 109

© 2023 IEEE International Solid-State Circuits Conference

ADC Digital Correctability Speaker
Video
Multi-stage or Multi-step,
Do w/ built-in redundancy
Do(V1) = Do(V2)
missing codes Do(V1) ≠ Do(V2)
Correctable!

nonmonotonic V1 V2
codes

Do(V3) = Do(V4)
Uncorrectable!
missing decision levels Do(V3) = Do(V4)
0 V3 V4
Vi

 Decision Vector Do reveals more info about input than Scalar Decision Do
 A.l.a Do is unique (even Do is not), a LUT can in theory be found to recover the
input faithfully (i.e., mapping from A  D must be unique, thus, reversible)
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Residue Errors in Pipelined ADC (1.5-b) Speaker
Video
Φ2
 Static errors:
Φ1 C1
 Capacitor mismatch/nonlinearity
Vi
 RA finite gain and nonlinearity
Φ1 C2
 S/H nonlinearity
-VR/4 A Vo
 Dynamic errors:
VR/4 Φ1e
 RA slewing/settling error
 Switch-induced errors
-VR Φ2
0 Decoder  Reference settling error
VR  Memory errors

C1 + C2 C2 Ideal residue TF:

=Vo ⋅ fS/H ( Vi ) + ⋅ (1- b ) ⋅ VR
C1 + C2 C1 + C2 Vo = 2 ⋅ Vi + (1- b ) ⋅ VR
C1 + C1 +
A ( Vo ) A ( Vo )

Y. Chiu T3: Fundamentals of Data Converters 83 of 109

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Residue Errors in Pipelined ADC (1.5-b) Speaker
Video

b=0 b=1 b=2 b=0 b=1 b=2 Do

VR VR
Vo Vo
VR/2 VR/2

Vi Vi
0 0

-VR/2 -VR/2

0
-VR -VR/4 VR/4 VR -VR -VR/4 VR/4 VR -VR Vi VR

 Simple parametric errors (e.g., capacitor mismatch) can be easily corrected

with digital calibration

Y. Chiu T3: Fundamentals of Data Converters 84 of 109

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Residue Errors in Pipelined ADC (1.5-b) Speaker
Video

b=0 b=1 b=2 b=0 b=1 b=2 Do

VR VR
Vo Vo
VR/2 VR/2

Vi Vi
0 0

-VR/2 -VR/2

0
-VR -VR/4 VR/4 VR -VR -VR/4 VR/4 VR -VR Vi VR

 Static nonlinearities (e.g., INL and DNL), dynamic errors (e.g., RA settling
errors [25]), and even memory errors [26] can also be calibrated

Y. Chiu T3: Fundamentals of Data Converters 85 of 109

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Digital Calibration of Pipelined ADC Speaker
Video
Analog pipeline For stage j, we have
C1 + C2 C2
C1 + C2 (
Vi
stage
z-½
V1 stage
z-½
V2 Vk-1 stage
z-½ =Vj ⋅ Vj-1 + ⋅ 1- b j ) ⋅ VR
1 2 k C1 + C2
bk-1
C1 + C1 +
b1 b2 bk A A
D1 Dk-2 stage Dk-1 -½  C1 + C2 
stage stage C
Vj-1  1 +
Do z-½
1
z-½
k-1
z
k =  A  ⋅ Vj +  C2  ⋅ (b -1)
   j
VR  C1 + C2  VR  C1 + C2 
Digital pipeline  
β
α

 Needs to determine coefficients D j-1 = α ⋅ D j + β ⋅ (b j -1)  linear

{ α, β } Ref. [13]
∑α j + β ⋅ ( b j -1)
 Needs to determine coefficients D= ⋅ D m
j-1 m  nonlinear
{ αm, β } Ref. [21] m

 typically, α indicates inter-stage residue gain error while β indicates DAC capacitor mismatch errors

Y. Chiu T3: Fundamentals of Data Converters 86 of 109

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Digital Calibration of SAR ADC Speaker
Video
Φ1e VX

… Cj+1 Cj … SAR
logic
= wj+1·∑C = wj·∑C CN-1 C1 C0 C0
D = { bj }
Do
Key cal. eqn.:
VR
 Cj 
N-1 N-1
Do ≈∑   ⋅ b j = ∑ w j ⋅ b j
Φ1 Φ1 Φ1 Φ1

j=0  ∑ C j 
 j=0
Vi Ref. [9]

 DAC capacitors are subject to random mismatch  need to determine the

exact values of bit weights { wj }

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Speaker
Video

EXPLOITING REDUNDANCY FOR

DIGITAL BACKGROUND CAL.
Y. Chiu T3: Fundamentals of Data Converters 88 of 109

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Residue Gain Cal. (DAC Dither) Speaker
Video
pipeline stage V2
b=1 b=2
VR
V1 α A/D D2

α = 2n Injection zone
Backend VR/2
n n+k ideally T=+1
A/D D/A ADC
bits bits
b
residue V2
... 0 ...
T=-1

2-k
path -VR/
2 Injection zone
T α-1
-VR Ref. [18]
D1 2-k ˆ
D V1
2
 Small dither added to the residue
∫ LMS
path, then subtracted out in the
Digital Processing
digital domain (after correction)
Converge@ 2 ⋅T = 0
D
 In steady state, analog gain (α) and digital gain inverse (α-1) cancel exactly
 2-k ≤ ¼ to avoid overflow, DAC adds 2 bits or more to accommodate dither
Y. Chiu T3: Fundamentals of Data Converters 89 of 109

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Residue Gain Cal. – Comparator Dither Speaker
Video
pipeline stage b=1 b=2
V2 VR
V1 α A/D D2
2-k T=+1
α = 2n Backend VR/2 T=-1
ideally ADC
A/D
n+k
bits
n
bits D/A residue V2
... 0 ...
b path Ref. [15]
-VR/
D1 α-1 2
Injection zone
T -VR
V1
∫ LMS
Digital Processing  Dither forces ADC traverse TWO
redundant conversion paths randomly

Converge@ D1 ⋅ T = 0  Ideally, Do is indep. of conversion path

 In steady state, analog gain (α) and digital gain inverse (α-1) cancel exactly
 Arbitrary dither amplitude a.l.a. no overflow occurs
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SAR Radix Cal. – Sub-Radix Dither Speaker
Video
radix ... 1.8 ... N-1  C  N-1
Cal. D = { bj }
eqn.: o ∑
 ⋅ b j = ∑ w j ⋅ b j
j
+VFS D ≈ 
j=0  ∑ C j 
 j=0 Φ1e
Do
Do W•D
Cj { wj }
bj = 1

1
SAR T
Vin

2 ADC
LMS ∫
bj = 0

2 bj = 1
+VR
bj = 0 1
-VR
Digital
Vin Processing
redundancy
-VFS V2 V1 Vin Converge@ Do ⋅T = 0 Ref. [28]
bit cycle
 Dither forces ADC traverse TWO redundant conversion paths randomly
 In steady state, accurate {wj} is identified s.t. Do is indep. of T
Y. Chiu T3: Fundamentals of Data Converters 91 of 109

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Caveats of Background Cal. Speaker
Video

 Vis-à-vis rule: what you see is what

you get – model coefficients often
depend on input statistics!

 PVT rule: error model coefficients

often depend on P.V.T. variations!

 Complexity, memory, digital power…

 Convergence time (tracking speed)

 After all, solution needs to be

practical and cost-efficient…

Y. Chiu T3: Fundamentals of Data Converters 92 of 109

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Speaker
Video

FIGURE-OF-MERIT (FOM)
WALDEN, SCHREIER AND ALPHA FOMS

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Precision-Speed-Power Tradeoffs Speaker
Video
Vref
 BW: min{fs/2, ERBW}
Vin(t)
A/D Dout(n)  fs: sample rate (Nyquist ADC)

···
Analog Input Digital Output
 ERBW: effective resolution BW (ΔΣ ADC)
fs

Bandwidth Noise Matching

g 1 Id kT 1 1
RA bandwidth  ωu = m  Thermal noise σN  Mismatch σMM  
C C Vov C Area C

 ADC Power ~ Bandwidth or Sample Rate

 A. ADC Power (and Area) ~ Precision2 (4ENOB) for noise- or matching-limited design
B. ADC Power (and Area) ~ Precision (2ENOB) o.w.
 For example, a low-resolution flash ADC’s power and area ~ its # of conversion steps = 2N (≥2ENOB)

Y. Chiu T3: Fundamentals of Data Converters 94 of 109

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Walden vs. Schreier FoM Speaker
Video
Walden FoM Schreier FoM

P  Joule   BW 
FoMW = FoMS SNDR + 10log10 
=  [dB]
fs ⋅ 2ENOB  Conversion Step   P 
Ref. [29] Ref. [30]

 Schreier FoM:
 Implicitly assumes Noise- or Matching-limited ADC of Scenario A
 The dimension of FoMS is dB  Schreier FoM naturally measures SNDR, or
Performance, not just # of effective quantization steps
 Walden FoM:
 Implicitly assumes Nyquist-rate ADC of Scenario B
 The dimension of FoMW is Joule/Conversion-Step  Walden FoM naturally measures
Energy Efficiency

Y. Chiu T3: Fundamentals of Data Converters 95 of 109

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Walden vs. Schreier FoM Speaker
Video
Walden FoM Schreier FoM
190
ISSCC 2022
VLSI 2022

2.E+03 180 ISSCC 1997-2021

VLSI 1997-2021
Envelope
FOMW,hf [fJ/conv-step]

170 ISSCC 2023

2.E+02

FOMS,hf [dB]
160

150
2.E+01

140
ISSCC 2022
VLSI 2022
2.E+00 ISSCC 1997-2021
130
VLSI 1997-2021
Envelope

ENOB missing!
ISSCC2023
120 ENOB missing!
2.E-01 1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 1.E+12
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11
fsnyq [Hz]
fsnyq [Hz]
Ref. [31]
 A complete FoM vs. Performance rendering requires a 3D plot
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But Actually… Speaker
Video
P  BW 
FoMW = FoMS= SNDR − 1.76 + 10log10   + 1.76
fs ⋅ 2ENOB  P 
P  BW 
= =6.02 ⋅ ENOB + 10log10   + 1.76
2 ⋅ BW ⋅ 2ENOB  P 
 BW 
= 10log10 ( 4ENOB ) + 10log10   + 1.76
P  P 
Common
where α =2 - 4  BW ⋅ 4ENOB 
Part: BW ⋅ αENOB = 10log10  + 1.76
P 
 
α = 4 → SNDR (scenario A)
α = 2 → design complexity (scenario B)

 The common part between the two seemingly distinct FoMs is striking!

Y. Chiu T3: Fundamentals of Data Converters 97 of 109

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Alpha FoM Speaker
Video
Define “α” efficiency Also define “α” performance
P
FoMα = where α = 2 - 4 Performance = BW ⋅ αENOB [Hz ⋅ Precision]
BW ⋅ αENOB
 α = 2 → Walden FoM  αENOB indicates "Precision"
 α = 4 → Schreier FoM

P
Efficiency × Performance = ENOB
× BW ⋅ αENOB
= Power
BW ⋅ α

 Performance vs. Efficiency plot gives more info when comparing designs
 Given Power, Performance and Efficiency trade hyperbolically - Alpha law

Y. Chiu T3: Fundamentals of Data Converters 98 of 109

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Performance vs. Efficiency (PE) Chart Speaker
Video
1E+17
Best performance
1E+16

“α” Performance = BW∙αENOB 1E+15

1E+14
[log scale]

1E+13
α= 2-4

Best efficiency
1E+12

1E+11

1E+10

1E+09
1E-18 1E-17 1E-16 [log1E-15
scale] 1E-14 1E-13 1E-12

“α” Efficiency = Power/(BW∙αENOB)

Y. Chiu T3: Fundamentals of Data Converters 99 of 109

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ADC PE Chart (1997-2023) Speaker
Video
1.E+15
VLSI 1997-2022

1.E+14 ISSCC 1997-2022

ISSCC 2023
Performance [Hz∙Precision]
1.E+13

1.E+12
100W
1.E+11
10W
1.E+10 α=3
1W
1.E+09
100mW
1.E+08
10mW
1.E+07
1μW 10μW 100μW 1mW
1.E+06
1.E-18 1.E-17 1.E-16 1.E-15 1.E-14 1.E-13 1.E-12 1.E-11 1.E-10 1.E-09
Efficiency [J/Precision]

Y. Chiu T3: Fundamentals of Data Converters 100 of 109

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ADC PE Chart: α=2–4 Speaker
Video
1.E+17 1.E+17 1.E+17

1.E+16
α=2 1.E+16
α=3 1.E+16
α= 4
1.E+15
Walden 1.E+15 1.E+15
Schreier
1.E+14 1.E+14 1.E+14
Performance [Hz∙Precision]

Performance [Hz∙Precision]

Performance [Hz∙Precision]
1.E+13 1.E+13 1.E+13

1.E+12 1.E+12 1.E+12

1.E+11 1.E+11 1.E+11

1.E+10 1.E+10 1.E+10

1.E+09 1.E+09 1.E+09

1.E+08 1.E+08 1.E+08

1.E+07 1.E+07 1.E+07

1.E+06 1.E+06 1.E+06

1.E+05 1.E+05 1.E+05

1.E+04 1.E+04 1.E+04

1.E-20 1.E-17 1.E-14 1.E-11 1.E-08 1.E-20 1.E-17 1.E-14 1.E-11 1.E-08 1.E-20 1.E-17 1.E-14 1.E-11 1.E-08

Efficiency [J/Precision] Efficiency [J/Precision] Efficiency [J/Precision]

Y. Chiu T3: Fundamentals of Data Converters 101 of 109

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ADC PE Chart (1997-2000) Speaker
Video
1.E+15
VLSI 1997-2000
1.E+14
ISSCC 1997-2000
Performance [Hz∙Precision]
1.E+13

1.E+12
100W
1.E+11
10W
1.E+10 α=3
1W
1.E+09
100mW
1.E+08
10mW
1.E+07
1μW 10μW 100μW 1mW
1.E+06
1.E-18 1.E-17 1.E-16 1.E-15 1.E-14 1.E-13 1.E-12 1.E-11 1.E-10 1.E-09
Efficiency [J/Precision]

Y. Chiu T3: Fundamentals of Data Converters 102 of 109

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ADC PE Chart (1997-2010) Speaker
Video
1.E+15
VLSI 1997-2000
VLSI 2001-2010
Performance [Hz∙Precision] 1.E+14 ISSCC 1997-2000
ISSCC 2001-2010
1.E+13

1.E+12
100W
1.E+11
10W
1.E+10 α=3
1W
1.E+09
100mW
1.E+08
10mW
1.E+07
1μW 10μW 100μW 1mW
1.E+06
1.E-18 1.E-17 1.E-16 1.E-15 1.E-14 1.E-13 1.E-12 1.E-11 1.E-10 1.E-09
Efficiency [J/Precision]

Y. Chiu T3: Fundamentals of Data Converters 103 of 109

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ADC PE Chart (1997-2022) Speaker
Video
1.E+15
VLSI 1997-2000
VLSI 2001-2010
VLSI 2011-2022
1.E+14 ISSCC 1997-2000
ISSCC 2001-2010
Performance [Hz∙Precision]
ISSCC 2011-2022
1.E+13

1.E+12
100W
1.E+11
10W
1.E+10 α=3
1W
1.E+09
100mW
1.E+08
10mW
1.E+07
1μW 10μW 100μW 1mW
1.E+06
1.E-18 1.E-17 1.E-16 1.E-15 1.E-14 1.E-13 1.E-12 1.E-11 1.E-10 1.E-09
Efficiency [J/Precision]

Y. Chiu T3: Fundamentals of Data Converters 104 of 109

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ADC PE Chart (1997-2022) Speaker
Video
1.E+15 Industry VLSI (Academia)
works VLSI (Industry)
1.E+14
ISSCC (Academia)
Performance [Hz∙Precision]
ISSCC (Industry)
1.E+13

1.E+12
100W
1.E+11
10W
1.E+10 α=3
1W
1.E+09
100mW
1.E+08
10mW
1.E+07
1μW 10μW 100μW 1mW
1.E+06
1.E-18 1.E-17 1.E-16 1.E-15 1.E-14 1.E-13 1.E-12 1.E-11 1.E-10 1.E-09
Efficiency [J/Precision]

Y. Chiu T3: Fundamentals of Data Converters 105 of 109

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Converter Papers to See This Year Speaker
Video

 Session 10 - Pipelined and Noise-Shaping ADCs:

 10.1, 10.2 – high-speed pipelined ADCs
 10.4 – high-resolution two-step SAR ADC with predictive level-shifting
 Session 17 - High-Speed Data Converter:
 17.3 –high-speed direct-RF DAC
 17.4, 17.6 – digitally calibrated time-interleaved SAR ADCs
 17.8 – high-speed time-domain ADC

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References Speaker
Video
1. W.R. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., pp. 446-472, Jul. 1948.
2. Oppenheim and Schafer, Discrete-Time Signal Processing, 2nd ed., Prentice Hall, 1998.
3. D. Gruber et al., "A 12b 16GS/s RF-sampling capacitive DAC for multi-band soft-radio base-station applications
with on-chip transmission-line matching network in 16nm FinFET," in ISSCC, 2021.
4. B. Razavi, Principles of Data Conversion System Design, IEEE press, 1995.
5. M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter analysis of high-speed sampling systems," JSSC, no 1,
1990.
6. A.M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC," JSSC, Mar. 1999.
7. S.H. Lewis et al., "A 10-b 20-MS/s analog-to-digital converter," JSSC, Mar. 1992.
8. F. Kuttner, "A 1.2-V 10-b 20-MS/s nonbinary successive approximation ADC in 0.13-μm CMOS," in ISSCC, 2002.
9. W. Liu et al., "A 600MS/s 30mW 0.13μm CMOS ADC array achieving over 60dB SFDR with adaptive digital
equalization," in ISSCC, 2009.
10. C.-C. Liu et al., "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation," in ISSCC, 2010.
11. H.-S. Lee, D.A. Hodges, and P.R. Gray, "A self-calibrating 15 bit CMOS A/D converter," JSSC, no. 6, 1984.
12. S.-U. Kwak, B.-S. Song, and K. Bacrania, "A 15-b 5-Msamples/s low spurious CMOS ADC," JSSC, Dec. 1997.
13. D. Fu et al., "A digital back-ground calibration technique for time-interleaved analog-to-digital converters," in
ISSCC, 1998.
14. P. Kiss et al., "Adaptive digital correction of analog errors in MASH ADC’s—Part II: Correction using test-signal
injection," TCAS-II, Jul. 2000.

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References Speaker
Video
15. J. Li and U.-K. Moon, "Background calibration techniques for multistage pipelined ADC’s with digital
redundancy," TCAS-II, Sept. 2003.
16. X. Wang et al., "A 12-bit 20-MS/s pipelined ADC with nested digital background calibration," in CICC, 2003.
17. Y. Chiu et al., "Least mean square adaptive digital background calibration of pipelined analog-to-digital
converters," TCAS-I, Jan. 2004.
18. E.J. Siragusa and I. Galton, "A digitally enhanced 1.8V 15b 40MS/s CMOS pipelined ADC," in ISSCC, 2004.
19. J. McNeill et al., "Split ADC architecture for deterministic digital background calibration of a 16b 1MS/s ADC," in
ISSCC, 2005.
20. Y.-S. Shu and B.-S. Song, "A 15b linear, 20MS/s, 1.5b/stage pipelined ADC digitally calibrated with signal-
dependent dithering," in VLSI, 2006.
21. B. Murmann and B. Boser, "A 12b 75MS/s pipelined ADC using open-loop residue amplification," in ISSCC,
2003.
22. C. Tsang et al., "Background ADC calibration in digital domain," in CICC, 2008.
23. A. Panigada and I. Galton, "A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic
distortion correction," in ISSCC, 2009.
24. B.D. Sahoo and B. Razavi, "A 12-bit 200-MHz CMOS ADC," JSSC, Sept. 2009.
25. E. Iroaga and B. Murmann, "A 12 b, 75 MS/s pipelined ADC using incomplete settling," in VLSI, 2006.
26. J.P. Keane et al., "Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters",
TCAS-I, Mar. 2006.

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References Speaker
Video
27. A. Ali et al., A 12-b 18-GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and
background calibration," in ISSCC, 2020.
28. W. Liu, P. Huang, and Y. Chiu, "A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration," in
CICC, 2012.
29. R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Select. Areas Comm., Apr. 1999.
30. R. Schreier and G.C. Temes, Understanding Delta-Sigma Data Converters, Wiley, 2005.
31. B. Murmann, "ADC Performance Survey 1997-2022," [Online]: www.stanford.edu/~murmann/adcsurvey.html.

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