A

MAJOR PROJECT REPORT

ON
VEHICLE-TO-GRID TECHNOLOGY IN A MICRO-GRID USING DC FAST CHARGING
ARCHITECTURE
This dissertation Submitted in partial fulfillment of the requirements
For the award of the degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRICAL AND ELECTRONICS ENGINEERING

Submitted by

P.VENKATESH GOUD 18C75A0221

M.HARIN KUMAR 18C75A0230
N.NITHIN REDDY 18C75A0242

Under the guidance of

Mr D PRASADA RAO
Asst.Professor

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

ELLENKI COLLEGE OF ENGINEERING & TECHNOLOGY
PATELGUDA, AMEENPUR, SANGAREDDY DISTRICT - 502319
Affiliated to JNTU, Hyderabad
JUNE-2021
ELLENKI COLLEGE OF ENGINEERING & TECHNOLOGY
PATELGUDA, AMEENPUR, SANGAREDDY DISTRICT – 502319
Affiliated to JNTU, Hyderabad.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

CERTIFICATE

This is to certify that the dissertation entitled “VEHICLE-TO-GRID TECHNOLOGY IN A

MICRO-GRID USING DC FAST CHARGING ARCHITECTURE” being submitted by
P.VENKATESH GOUD (18C75A0221), M.HARIN KUMAR (18C75A0230), N.NITHIN REDDY
(18C75A0242) in partial fulfillment of the requirements for the award of degree of BACHELOR OF
TECHNOLOGY in ELECTRICAL AND ELECTRONICS ENGINEERING, under Jawaharlal Nehru
Technological University, Hyderabad, is a record of bonafide work carried out by them under by guidance
and supervision. The results embodied in this project report have not been submitted to any other university
or institute for the award of any degree.

PROJECT GUIDE HEAD OF THE DEPARTMENT

Mr D PRASADA RAO Mr D PRASADA RAO

Asst.Prof Asst.Prof
Department of EEE Department of EEE

EXTERNAL EXAMINER PRINCIPAL

ACKNOWLEDGEMENT

I am very pleased to present this thesis of my research. This period of my student life has been truly
rewarding a number of people were of immense help to me during the course of my research and the
preparation of my thesis.

I would like to thank Sri E Sadashiva Reddy, Chairman, Ellenki Group of Institutions for
providing us the conducive environment for carrying through my academic schedules and projects with ease.

I express a whole hearted gratitude to Mr. Sambashiva Reddy, Director, Ellenki Group of
Institutions and Director of Research and Development Centre, Ellenki college Of Engineering and
Technology, for providing us the conducive environment for carrying through my academic schedules and
projects with ease.

I would like to thank my guide MR D PRASADA RAO, Department of Electrical and Electronics
Engineering, Ellenki College Of Engineering and Technology, for providing seamless support and
knowledge over the past one year and also for providing right suggestions at every phase of the development
of my project.

I thank to Mr D PRASADA RAO, Head of the Department in Electrical and Electronics

Engineering, Ellenki College of Engineering and Technology, for providing seamless support and
knowledge over the past one year and also for providing right suggestions at every phase of the development
of my project.

I would like to thank Dr. JOHN PAUL, Principal, Ellenki College Of Engineering and
Technology. His insight during course of my research and regular guidance were invaluable to me and also
for providing right suggestions at every phase of the development of my project.

I would like thank all the staff members of Research and Development Centre and Department of
Electrical and Electronics Engineering.

There is definitely a need to thank my friends and parents for their patience and support in always
leading to successful completion of the project.

P.VENKATESHGOUD 18C75A0221
M.HARIN KUMAR 18C75A0230
N.NITHIN REDDY 18C75A0242
CONTENTS
ABSTRACT
LIST OF ABBREVIATIONS
LIST OF FIGURE
LIST OF TABLES

CHAPTER 1 (1-5)
1.1 INTRODUCTION 1-2
1.2 BLOCK DIAGRAM AND EXPLANATION 2-5
1.3 SPECIFICATION OF VARIOUS COMPONENTS 3-4
1.4 CONTROL SYSTEM 4-5
1.5 MICRO GRID TEST SYSTEM CONFIGURATION 5

CHAPTER 2 (6-27)
2.1 SCHEMATIC DIAGRAM 6
2.2 SCHEMATIC DIAGRAM DESCRIPTION 6
2.3 PULSE WIDTH MODULATION TECHNIQUE 7-10
2.4 CLASSIFICATION OF PWM TECHNIQUES 11-27

CHAPTER 3 (28-33)
3.1 PI CONTROLLER 28-29
3.2 ADVANTAGES AND DISADVANTAGES 29
3.3 THE PI ALGORITHM 29-31
3.4 FUNCTION OF INTEGRAL TERM 31-33

CHAPTER 4 (34-45)
4.1 PHASE LOCKED LOOP 34-36
4.2 STRUCTURE AND FUNCTION 36-37
4.3 APPLICATIONS 38-45
CHAPTER 5 (46-65)
INTRODUCTION TO MAT LAB
5.1 EXECUTION PROCEDURE 46-57
5.2 APPLICATIONS OF MATLAB 58-59
5.3 SIMULATION RESULT 60-65

FUTURE SCOPE
CONCLUSION
REFERENCES
ABSTRACT

Electric Vehicle (EV) batteries can be utilized as potential energy storage devices in micro-
grids. They can help in micro-grid energy management by storing energy when there is surplus (Grid-To-
Vehicle, G2V) and supplying energy back to the grid (Vehicle-To-Grid, V2G) when there is demand for it.
Proper infrastructure and control systems have to be developed in order to realize this concept. Architecture
for implementing a V2G-G2V system in a micro-grid using level-3 fast charging of EVs is presented in this
paper. A micro-grid test system is modeled which has a dc fast charging station for interfacing the EVs.
Simulation studies are carried out to demonstrate V2G-G2V power transfer. Test results show active power
regulation in the micro-grid by EV batteries through G2V-V2G modes of operation. The charging station
design ensures minimal harmonic distortion of grid injected current and the controller gives good dynamic
performance in terms of dc bus voltage stability.
LIST OF ABBREVIATION

SYMBOL NAME

EV Electrical vehicle

V2G Vehicle to grid

G2V Grid to vehicle

PWM Pulse width modulation

DSP Digital signal processor

PLD Programming logic device

POD Phase opposition disposition

PI Proportional-integral

VCO Voltage controlled oscillator

APLL Analog phase locked loop

DPLL Digital phase locked loop

LPLL Linear phase locked loop

SPLL Software phase locked loop

ADPLL All digital phase locked loop

PLL Phase locked loop

ECL Emitter coupled logic

TTL Transistor-transistor logic

SOC State of charge

LIST OF FIGURES

S.NO FIGURE FIGURE NAME PAGE NO

NO
1 1.2 Block diagram 2

2 1.4 Off board charger control 4

3 1.4 Inverter control system 5

4 2.1 Schematic diagram 6

5 2.3 Pulse with modulation 8

6 2.4 Wave forms of three phase 12

sinusoidal PWM inverter
7 2.4 Three phase power inverter 22

8 3.1 Block diagram of PI speed 28

controller
9 4.3 Clock distribution 40

10 4.3 Analog phase locked loop 42

11 5.1 Block diagram of mat lab 48

components
12 5.1.1 Simulink library browser 50

13 5.1.2 Diagram of semi power system 57

14 5.2 Basic circuit designing and 59

analyzing of result
15 5.3 Simulation results and wave forms 60
LIST OF TABLES

S.NO SPECIFICATION PAGE NO

1 Switching time table at each sector in SVM 22

2 Phase voltages and output line to line 24

voltages in SVM
Vehicle-To-Grid Technology in a Micro-grid Using DC Fast Charging Architecture

CHAPTER 1

1.1 INTRODUCTION

Up-to-date, the world has undergone a challenge in terms of providing electricity and ensuring global
energy requirements. The challenge is mainly due to the shortage of primary energy resources from
conventional fossil fuels like natural gas, coal and oil [1]. As a result, there is a great tendency to integrate the
renewable energy resources and the use of plug-in electric vehicles (PEVs) on the smart grid in order to
minimize reliance on conventional energy resources, satisfy the energy demands and consequently decreasing
concerns related to global warming effects as well as the ones related to energy crisis [2e5]. The excessive
electricity consumption causes intense surges in demand during peak hour which can cause undesirable
impacts and harm the stability of the existing network. That's why; some researchers are working on ways to
minimize load power variance by using renewable energy sources. In Ref. [6], a stochastic multiobjective
daily volt/var control based on hydro-turbine, fuel cell, wind turbine, and photovoltaic power plants are
investigated. A study in Ref. [7] has developed a new control strategy that involves wind and photovoltaic
generation subsystems. Energy storage systems are important components of a micro-grid as they enable the
integration of intermittent renewable energy sources. Electric vehicle (EV) batteries can be utilized as
effective storage devices in micro-grids when they are plugged-in for charging. Most personal transportation
vehicles sit parked for about 22 hours each day, during which time they represent an idle asset. EVs could
potentially help in micro-grid energy management by storing energy when there is surplus (Grid-To-Vehicle,
G2V) and feeding this energy back to the grid when there is demand for it (Vehicle-To-Grid). V2G applied to
the general power grid faces some challenges such as; it is complicated to control, needs large amount of EVs
and is hard to realize in short term [1]. In this scenario, it is easy to implement V2G system in a micro-grid.
The Society of Automotive Engineers defines three levels of charging for EVs. Level 1 charging uses a plug
to connect to the vehicle’s on-board charger and a standard household (120 V) outlet. This is the slowest form
of charging and works for those who travel less than 60 kilometers a day and have all night to charge. Level 2
charging uses a dedicated Electric Vehicle Supply Equipment (EVSE) at home or at a public station to
provide power at 220 V or 240 V and up to 30 A. The level 3 charging is also referred to as dc fast charging.
DC fast charging stations provide charging power up to 90 kW at 200/450 V, reducing the charging time to
20-30 mins. DC fast charging is preferred for implementing a V2G architecture in micro-grid due to the quick

1
power transfer that is required when EVs are utilized for energy storage. Also the dc bus can be used for
integrating renewable generation sources into the system. In majority of the previous studies, V2G concept
has been applied in the general power grid for services like peak shaving, valley filling, regulation and
spinning reserves [2]. The V2G development in a micro-grid facility to support power generation from
intermittent renewable sources of energy is still at its infancy. Also, level 1 and level 2 ac charging is utilized
for V2G technology in most of the works reported [3]. These ac charging systems are limited by the power
rating of the on-board charger. An additional issue is that the distribution grid has not been designed for bi-
directional energy flow. In this scenario, there is a research need for developing technically viable charging
station architectures to facilitate V2G technology in micro-grids. This work proposes a dc quick charging
station infrastructure with V2G capability in a micro-grid facility. The dc bus used to interface EVs is also
used for integrating a solar photo-voltaic (PV) array into the micro-grid. The proposed architecture allows
high power bi-directional charging for EVs through off-board chargers. Effectiveness of the proposed model
is evaluated based on MATLAB/Simulink simulations for both V2G and G2V modes of operation.

1.2 BLOCK DIAGRAM AND EXPLANATION

DC FAST CHARGING STATION CONFIGURATION FOR V2G
The configuration for dc fast charging station to implement V2G-G2V infrastructure in a micro-grid is
shown in Fig. 1 [4]. EV batteries are connected to the dc bus through off-board chargers. A grid connected
inverter connects the dc bus to the utility grid through an LCL filter and a step-up transformer. The important
components of the charging station are described below.

Block diagram
2
1.3 SPECIFICATION OF VARIOUS COMPONENTS
A. Battery Charger Configuration
For dc fast charging, the chargers are located off-board and are enclosed in an EVSE. A bi directional dc-dc
converter forms the basic building block of an off-board charger with V2G capability. It forms the interface
between EV battery system and the dc distribution grid. The converter configuration is shown in Fig. 2. It
consists of two IGBT/MOSFET switches that are always operated by complimentary control signals.

Fig. 2. Battery charger configuration

1) Buck mode of operation (charging mode):
When the upper switch is operating, the converter acts as a buck converter stepping down the input voltage to
battery charging voltage vehicle (G2V). When the switch is off, the current takes its return path through the
inductor and diode of lower switch and completes the circuit. If is the duty ratio of the upper switch, the
battery voltage is given by:

2) Boost mode of operation (discharging mode):

When the switch is operating, the converter acts as a boost converter stepping up the battery voltage to the dc
bus voltage. When the switch is in on state, current continues to flow through the inductor and completes its
circuit through the anti-parallel diode of the upper switch, and the capacitor. The net power flow in this case
is from the vehicle to the grid (V2G) and the battery operates in the discharge mode. If the capacitor is large
enough to provide a constant dc voltage, the output voltage during boost mode of operation is given by:

Where is the duty cycle of the lower switch.

3
A. Grid Connected Inverter and LCL Filter
The grid connected inverter (GCI) converts the dc bus voltage into a three phase ac voltage and also allows
the reverse flow of current through the anti-parallel diodes of the switches in each leg (Fig. 1). An LCL filter
is connected at the output terminals of the inverter for harmonic reduction and obtaining a pure sinusoidal
voltage and current. The design procedure for determining the LCL filter parameters for this work is adapted
from [4].

1.4 CONTROL SYSTEM

A. Off-Board Charger Control
A constant current control strategy [5] using PI controllers is implemented for charge/discharge control of the
battery charger circuit and is shown in Fig.3. The controller first compares the reference battery current with
zero, in-order to determine the polarity of the current signal, to decide between charging and discharging
modes of operations. Once the mode is selected, the reference current is compared with the measured current
and the error is passed through a PI controller to generate the switching pulses for will be turned off
throughout the charging process and will be turned off throughout the discharging process.

Constant current control strategy for battery charger

B. Inverter Control
A cascade control in synchronous reference frame is proposed for the inverter controller. The conventional
standard vector control using 4 PI controllers in a nested loop is shown in Fig. 4 [4]. The control structure
consists of two outer voltage control loops and two inner current control loops. The d-axis outer loop controls
the dc bus voltage and inner loop controls the active ac current. Similarly, the q-axis outer loop regulates the
ac voltage magnitude by adjusting the reactive current, which is controlled by the q-axis inner current loop.

4
Also, dq decoupling terms L and feed-forward voltage signals are added to improve the performance during
transients.

Inverter control system

MICRO-GRID TEST SYSTEM CONFIGURATION

The micro-grid test system configuration with the dc fast charging station is shown in Fig. 5. A 100 kW wind
turbine (WT) and a 50 kW solar PV array serve as the generation sources in the system. The EV battery
storage system consists of 4 EV batteries connected to a 1.5 kV dc bus of the charging station through off-
board chargers. The solar PV is also connected to this dc bus through a boost converter which has a
maximum power point tracking (MPPT) controller. The utility grid consists of a 25 kV distribution feeder
and a 120 kV equivalent transmission system. The wind turbine driven doubly-fed induction generator is
connected to the micro-grid at the point of common coupling (PCC). Transformers are used to step up the
voltages and connect the respective ac systems to the utility grid.

Proposed microgrid test system configu

5
CHAPTER 2

2.1 SCHEMATIC DIAGRAM

Control scheme diagram

2.2 SCHEMATIC DIAGRAM DESCRIPTION

The charging station design procedure is adapted from [4] and the obtained parameter values are
given in Appendix. The wind turbine is operated at rated speed giving an output maximum
power of 100 kW. The solar PV is operated at standard test conditions (1000W/m2 irradiance
and 25o C temperature) giving the maximum power output of 50 kW. A 150 kW resistive load is
connected to the 480 V ac bus. The reactive current reference to GCI is set to zero for unity pf
operation. The initial state of charge (SOC) of the EV batteries is set at 50%. Once the steady
state conditions are reached, batteries of EV1 and EV2 (Fig. 1) are operated to perform the V2G-
G2V power transfer. The current set-points given to the battery charging circuits of EV1 and
EV2 batteries are shown in Table I and the results are shown in the subsequent figures.

6
2.3 PULSE WIDTH MODULATION TECHNIQUE
Mainly the power electronic converters are operated in the “switched mode”.
Which means the switches within the converter are always in either one of the two states - turned
off (no current flows), or turned on (saturated with only a small voltage drop across the switch).
Any operation in the linear region, other than for the unavoidable transition from conducting to
non conducting, incurs an undesirable loss of efficiency and an unbearable rise in switch
power dissipation. To control the flow of power in the converter, the switches alternate between
these two states (i.e. on and off). This happens rapidly enough that the inductors and capacitors
at the input and output nodes of the converter average or filter the switched signal. The
switched component is attenuated and the desired DC or low frequency AC component is
retained. This process is called Pulse Width Modulation (PWM), since the desired average value
is controlled by modulating the width of the pulses. For maximum attenuation of the switching
component, the switch frequency fc should be high- many times the frequency of the
desired fundamental AC component f1 seen at the input or output terminals. In large
converters, this is in conflict with an upper limit placed on switch frequency by switching losses.
For GTO converters, the ratio of switch frequency to fundamental frequency fc/f1 (= N,
the pulse number) ma y be as low as unity, which is known as square wave switching. Another
application where the pulse number may be low is in converters which are better
described as amplifiers [39], whose upper output fundamental frequency may be relatively
high. These high power switch-mode amplifiers find application in active power filtering
[40], test signal generation [41], servo [42] and audio amplifiers [43]. These low pulse
numbers place the greatest demands on effective modulation to reduce the distortion as
much as possible. The low pulse numbers place the greatest demands on effective modulation to
reduce the distortion as much as possible. In these circumstances, multi -level converters
can reduce the distortion substantially, by staggering the switching instants of the multiple
switches and increasing the apparent pulse number of the overall converter.

PWM Techniques
The fundamental methods of pulse-width modulation (PWM) are divided into the
traditional voltage-source and current -regulated methods. Voltage-source methods more
easily lend themselves to digital signal processor (DSP) or programmable logic device

7
(PLD) implementation. However, current controls typically depend on event scheduling
and are therefore analog implementations which can only be reliably operated up to a
certain power level. In discrete current -regulated methods the harmonic performance is not as
good as that of voltage-source methods. A sample PWM method is described below.

Pulse-width modulation.

Inverter output voltage, VA0= Vdc/2, Whe vcontrol> vtri,and VA0= -Vdc/2, When
vcontrol< vtri .PWM frequency is the same as the frequency of vtri. Amplitude is controlled by
the peak value of vcontrol and Fundamental frequency is controlled by the frequency of vcontrol
.Modulation Index (m) is given by :

Where (VA0)1 is the fundamental frequency component of VA0

8
Voltage-source methods

Voltage-source modulation has taken two major paths; sine triangle modulation
in the time domain and space vector modulation in the q -d stationary reference frame. Sine-
triangle and space vector modulation are exactly equivalent in every way. Adjusting some
parameters in the sine-triangle scheme (such as the triangle shape and sine wave
harmonics) is equivalent to adjusting other parameters in the space vector scheme (such as the
switching sequence and dwell time). The inverter line-to-ground voltage can be directly
controlled through the switching state. For a specific inverter, the switching state is broken out
into transistor signals. However, as a control objective, it is more desirable to regulate the
line -to-neutral voltages of the load. In a three-phase system, the common terms include dc
offset and any triplen harmonics. To narrow the possibilities, the commanded line -to-ground
voltages will be defined herein as:

2
where m is the modulation index which has a range of 0 ≤ m≤ and θc the converter electrical
√3
angle.

In eqn. 3.2, first set of terms on the right hand side define a sinusoidal set of commanded

voltages with controllable amplitude and frequency through m and θc respectively. The
second set of terms on the right hand side is the common -mode terms. In this case, a dc offset is
applied so that the commanded line-to-ground voltages will be within the allowable range of zero
to the dc voltage. The other common-mode term is a third harmonic component which is added
to fully utilize the dc source voltage. The common -mode terms are just the minimum set
and it is possible to command other types of line-to-ground voltages, including discontinuous

9
waveforms, in order to optimize switching frequency or harmonics. Some fundamental
definitions will now be presented for reference when describing the modulation methods.
First, duty cycles are defined by scaling the commanded voltages with modifications to
account for multiple voltage levels. The modified duty cycles are-

Next, a commanded voltage vector is defined by

where the commanded q- and d-axis voltages are related to the a-b-c variables of eqn.3.2

10
2.4 Classification of PWM Techniques

Classification of PWM multilevel converter modulation strategies

Sine-triangle modulation
In sine-triangle method, therein, for n -level inverter the a-phase duty cycle is
compared with (n-1 in general) triangle waveforms. The switching rules are as follows:

In general the sine triangle modulation is discussed here for a 3 -phase inverter

11
Three-phase Sinusoidal PWM inverter

One of the methods of describing voltage-source modulation is to illustrate the

intersection of a modulating signal (duty cycle) with triangle waveforms.

Waveforms of three-phase SPWM inverter.

Let, frequency of v tri= fs= PWM frequency and frequency of v control= f1=
fundamental frequency .In the above figure VAB= VA0– VB0, VBC= VB0– VC0and VCA=
VC0– VA0
Amplitude modulation ratio (ma) is given by

Where, (V A 0)1: fundamental frequency component of V A 0

Frequency modulation ratio (mf) can be expressed as :

12
where, f PWM frequency and f fundamental frequency mf should be an odd integer. If
mf is not an integer, there may exist sub harmonics at output voltage. If mf is not odd, DC
component may exist and even harmonics are present at output voltage. M should be a multiple
of 3 for three-phase PWM inverter.
The carrier-based modulation schemes for multilevel inverters can be generally
classified into two categories: phase -shifted and level -shifted modulations. Both modulation
schemes can be applied to the cascaded H -bridge(CHB) inverters.THD of phase-shifted
modulation is much higher than level-shifted modulation. Therefore we have considered level -
shifted modulation. An m-level CHB inverter using level -shifted multicarrier modulation
scheme requires (m -1) triangular carriers, all having the same frequency and amplitude.
The (m-1) triangular carriers are vertically disposed such that the bands they occupy are
contiguous. There are three alternative PWM strategies with different phase relationships
for the level-shifted multicarrier modulation:
(i) In-phase disposition (IPD), where all carrier waveforms are in phase.
(ii) Phase opposition disposition (POD), where all carrier waveforms above zero reference
are in phase and are 180 out of phase with those below zero.
(iii) Alternate phase disposition (APOD ), where every carrier waveform is in out of phase
with its neighbor carrier by 180.

In Phase Disposition (IPD)

In the present work, in the carrier -based implementation the phase disposition
PWM
scheme is used. Figure 3.4 demonstrates the sine -triangle method for a three –level
inverter. Therein, the a-phase modulation signal is compared with two (n -1 in general)
triangle waveforms. The rules for the in phase disposition method, when the number of level N =
3, are
• The N –1 = 3-1=2 carrier waveforms are arranged so that every carrier is in phase.

13
• The converter is switched to +Vdc/ 2 when the reference is greater than both carrier
waveforms.
• The converter is switched to zero when the reference is greater than the lower carrier
waveform but less than the upper carrier waveform.
• The converter is switched to - Vdc/ 2 when the reference is less than both carrier waveforms.
In the carrier -based implementation, at every instant of time the modulation signals are
compared with the carrier and depending on which is greater, the switching pulses are generated.
As seen from Figure 3.4, the figure illustrates the switching pattern produced by the carrier -
based PWM scheme. In the PWM scheme there are two triangles, the upper triangle ranges from
1 to 0 and the lower triangle ranges from 0 to –1. In the similar way for an N –level inverter, the
(N -1) triangles are used and each has a peak -to-peak value of 2/ (N -1). Hence the upper most
triangle magnitude varies from 1 to (1-2/ (N-1)), second carrier waveform from (1-4/
(N1)), and the bottom most triangle varies from (2 -2/ (N-1)) to –1. In Figure 3.5, simulation
of carrier –based PWM scheme using the in phase disposition (IPD) can be seen. The
switching function for the devices is given by
Ha> Triangle -1 & Triangle -2; Ha3=1, otherwise Ha3=0.
Ha< Triangle -1 & Ha > Triangle -2; Ha2=1, otherwise Ha2=0.
Ha< Triangle -1 & Triangle -2; Ha1=1, otherwise Ha1=0.
It is clear from the figure that during the positive cycle of the modulation signal, when
the modulation is greater than Triangle 1 and Triangle 2, then S1ap and S2ap are turned on and
also during the positive cycle S2ap is completely turned on. When S1ap and S2ap are
turned on, the converter switches to the + Vdc / 2.When S1an and S2ap are on, the converter
switches to zero and hence during the positive cycle S2ap is completely turned on and S1ap and
S1an will be turning on and off and hence the converter switches from + Vdc / 2 to 0.During the
negative half cycle of the modulation signal the converter switches from 0 to - Vdc / 2. The
phase voltage equations for star-connected, balanced three-phase loads expressed in terms
of the existence functions and input nodal voltage V30= Vdc / 2 , V 20= 0 , V10= -Vdc / 2

14
Switching pattern produced using the IPD carrier-based PWM scheme: (a) two triangles and the
modulation signal (b) S1ap (c) S2ap (d) S1an (e) S2an.

Simulation of carrier-based PWM scheme using the in phase disposition (IPD). (a).
Modulation signal and in-phase carrier waveforms (b) Phase “a” output voltage.
Phase Opposition Disposition (POD)

15
For phase opposition disposition (POD) modulation all carrier waveforms above
zero Reference are in phase and are 180out of phase with those below zero. The rules for the
phase opposition disposition method, when the number of level N = 3 are
(i) The N –1 = 2 carrier waveforms are arranged so that all carrier waveforms above zero are
in phase and are 180 out of phase with those below zero.
(ii) The converter is switched to + Vdc / 2 when the reference is greater than both
carrier waveforms.
(iii) The converter is switched to zero when the reference is greater than the lower carrier
waveform but less than the upper carrier waveform.
(iv) The converter is switched to - Vdc / 2 when the reference is less than both carrier
waveforms. As seen from Figure 3.6, the figure illustrates the switching functions
produced by POD carrier-based PWM scheme.
In the PWM scheme there are two triangles, upper triangle magnitude from 1 to 0
and the lower triangle from 0 to –1 and these two triangle waveforms are in out of phase. When
the modulation signal is greater than both the carrier waveforms, S1ap and S2ap are turned on
and the converter switches to positive node voltage and when the reference is less than the upper
carrier waveform but greater than the lower carrier, S2ap and S1an are turned on and the
converter switches to neutral point. When the reference is lower than both carrier
waveforms, S1an and S2an are turned on and the converter switches to negative node
voltage. . Figure 3.7 shows the output voltage waveform of phase “a” and it is clear the
waveform has three steps.

16
Switching pattern produced using the POD carrier -based PWM scheme:
(a) two triangles and the modulation signal (b) S1ap (c) S2ap (d) S1an (e) S2an

Simulation of carrier-based PWM scheme using POD. (a). Modulation signal and phase
carrier waveforms (b) Phase “a” output voltage.
Alternate Phase Opposition Disposition (APOD).
In case of alternate phase disposition (APOD) modulation, every carrier waveform is in
out of phase with its neighbor carrier by 180. Since APOD and POD schemes in case of three

17
level inverter are the same, a five level inverter is considered to discuss about the APOD scheme.
The rules for APOD method, when the number of level N = 5, are
i) The N – 1 = 4 carrier waveforms are arranged so that every carrier waveform is in out of
phase with its neighbor carrier by 180. The converter switches to + Vdc / 2 when the reference is
greater than all the carrier waveforms.
(ii) The converter switches to Vdc / 4 when the reference is less than the uppermost carrier
waveform and greater than all other carriers.
(iii) The converter switches to 0 when the reference is less than the two uppermost carrier
waveform and greater than two lowermost carriers.
(iv) The converter switches to - Vdc / 4 when the reference is greater than the
lowermost carrier waveform and lesser than all other carriers.
(v) The converter switches to -Vdc / 2 when the reference is lesser than all the carrier
waveforms.

Switching pattern produced using the APOD carrier -based PWM scheme for a five level
inverter: (a) Four triangles and the modulation signal (b) S1ap (c) S2ap (d) S3ap (e) S4ap.

18
Simulation of carrier-based PWM scheme using APOD for afive-level inverter. (a) Modulation
signal and carrier waveforms (b) Phase “a” output voltage.
Demonstrates the APOD scheme for a five -level inverter. The figure displays the
switching pattern generated by the comparison of the modulation signals with the four carrier
waveforms. Figure 3.9 shows the output voltage waveform of phase “a” and it is clear
the waveform has five steps.
Space vector modulation
Space vector modulation (SVM) is based on vector selection in the q -d stationary
reference frame. The commanded voltage vector is defined by equation -3.5. The
commanded vector is plotted along with the vectors obtainable by the inverter. The desired
vector V s*qds is shown at some point in time, but will follow the circular path if a three -
phase set of voltages are required on the load. The first step in the SVM scheme is to identify
the three nearest vectors.
(i) Realization of Space Vector PWM
Step -1 Determine Vd, Vq, Vref, and angle ( )
Step -2 Determine time duration T1, T2, T0
Step -3 Determine the switching time of each transistor (S1to S6)

19
Voltage Space Vector and its components in (d, q).

(ii) Coordinate transformation: abc to dq

20
21
22
Three-phase Power inverter

The upper transistors are S1, S3, S5, lower transistors: S4, S6, S2and switching
variable vectors are a, b, c. The switching time of each transistor (S1to S6) is shown below
in Table-1

Output voltages of three-phase inverter

S1through S6are the six power transistors that shape the output voltage. When an
upper switch is turned on (i.e., a, b or c is “1”), the corresponding lower switch is turned off
(i.e., a', b' or c' is “0”).Eight possible combinations of on and off patterns for the three upper

23
transistors (S1, S3, S5)are possible. Line to line voltage vector [Vab Vbc Vca]t. Where voltage
vectors are [a, b, c]

Line to neutral (phase) voltage vector

The eight inverter voltage vectors (V0to V7) are shown below in figure

Inverter voltage vectors

The eight combinations, phase voltages and output line to line voltages are shown below

in table-3.2

24
Principle of Space Vector PWM

a. Treats the sinusoidal voltage as a constant amplitude vector rotating at constant

frequency

b. This PWM technique approximates the reference voltage Vref by a combination of the
eight switching patterns (V0to V7)

c. Coordinate Transformation (abc reference frame to the stationary d-q frame) : A three phase
voltage vector is transformed into a vector in the stationary d -q coordinate frame which
represents the spatial vector sum of the three-phase voltage

d. The vectors (V1to V6) divide the plane into six sectors (each sector: 60 degrees)

e. Vref is generated by two adjacent non -zero vectors and two zero vectors

Basic switching vectors and Sectors

6 active vectors are (V1, V2, V3, V4, V5, V6) .DC link voltage is supplied to the load.
Each sector (1 to 6): 60 degrees. Two zero vectors are (V0, V7). They are located at
origin. No voltage is supplied to the load.

25
Basic switching vectors and sectors.

Current-regulated methods

Although this method directly regulates the currents, it relies on an analog

implementation which is not practical for higher power levels. These schemes provide a digital
implementation, but have lower harmonic performance than the voltage source methods.
The tradeoff between discrete implementation and harmonic performance has been an
issue for current-regulated controls.

Hysteresis control

The hysteresis current-control concept typically employed in two -level drive systems can
be extended to multi-level systems by defining a number of hysteresis bands. The basic operation
of the control involves defining n-1 evenly spaced hysteresis bands on each side of the
commanded current. The voltage level is then increased by one each time the measured current
departs from the commanded value and crosses a hysteresis band. One important detail of this

control is that the voltage level will be at its highest or lowest value when the measured
current crosses the lowermost or uppermost hysteresis band respectively. This ensures that the
current will regulate about the commanded value. This straightforward extension of two -
level current control results in good regulation of the currents and acceptable voltage
level switching. Furthermore, the multi-level hysteresis control handles steps changes in

26
commanded current with a response similar to two-level hysteresis control. The amount of
analog circuitry can be reduced by using a single hysteresis band and increasing or
decreasing the voltage levels each time the current touches the band. This method is then coupled
with timing and a voltage controlled oscillator to drive the current error to zero. An extension to
this method uses two hysteresis bands to provide better dynamic performance, but still utilize a
small amount of analog circuitry for a large number of voltage levels. Three-phase inverter for
hysteresis Current Control is shown below.

Three-phase inverter for hysteresis current control.

Hysteresis Current Controller is shown below.

Hysteresis current controller at Phase “a”.

Characteristics of hysteresis Current Control are discussed below.

Advantages

(i) Excellent dynamic response

27
(ii) Low cost and easy implementation

Drawbacks

(i) Large current ripple in steady-state

(ii) Variation of switching frequency

(iii) No intercommunication between each hysteresis controller of three phases and hence no
strategy to generate zero-voltage vectors. As a result, the switching frequency increases at lower
modulation index and the signal will leave the hysteresis band whenever the zero vector is turned
on.

(iv) The modulation process generates sub harmonic components.

Clocked sigma-delta modulation

Some current-regulated schemes are based on the sigma -delta function. Based
on the hysteresis level h, the per -phase switching state is determined from the current
error. The function can be implemented directly with analog components or it can be
implemented on a DSP based on a fixed clock frequency. In a two-level system, the hysteresis
level is zero and the control reduces to that of standard delta modulation. As with two-level
systems, the switching frequency of the inverter may be less than the clock frequency since the
voltage level may not change every time the control is clocked. The current tracking improves
with increasing clock frequency, and a relatively high frequency is needed for good
performance. This makes the control somewhat undesirable, although digital implementation is
an advantage.The concept behind multilevel delta modulation is illustrated here. As with clocked
sigma delta modulation, the control operates on a per -phase basis and can be implemented on a
DSP. The general scheme functions by increasing or decreasing the voltage level by one at each
clock cycle of the DSP depending on whether the current error is positive or negative respe
ctively. In this control, the hysteresis band does not need to be defined. In the two-level
implementation, the control reduces to that of standard delta modulation.

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CHAPTER 3

3.1 PI CONTROLLER
Like the P-Only controller, the Proportional-Integral (PI) algorithm computes and transmits
a controller output (CO) signal every sample time, T, to the final control element (e.g., valve,
variable speed pump). The computed CO from the PI algorithm is influenced by the controller
tuning parameters and the controller error, e(t).

 PI controllers have two tuning parameters to adjust. While this makes them more
challenging to tune than a P-Only controller, they are not as complex as the three parameter
PID controller.

Integral action enables PI controllers to eliminate offset, a major weakness of a P-only

controller. Thus, PI controllers provide a balance of complexity and capability that makes them
by far the most widely used algorithm in process control applications
The general block diagram of the PI speed controller is shown in Figure 2 [14].

The output Of the speed controller (torque command) at n-th instant is expressed as
follows:Te (n)=Te(n−1)+Kp_ωre(n)+Kiωre(n) (10)Where Te (n) is the torque output of the
controller at the n-th instant, and Kp and Ki theproportional and integral gain constants,
respectively.

A limit of the torque command is imposed as

29
The gains of PI controller shown in (10) can be selected by many methods such as
trialand error method, Ziegler–Nichols method and evolutionary techniques-based searching.
Thenumerical values of these controller gains depend on the ratings of the motor.

3.2 Advantages and disadvantages

 The integral term in a PI controller causes the steady-state error to reduce to zero, which
is not the case for proportional-only control in general.
 The lack of derivative action may make the system more steady in the steady state in the
case of noisy data. This is because derivative action is more sensitive to higher-frequency terms
in the inputs.
 Without derivative action, a PI-controlled system is less responsive to real (non-noise)
and relatively fast alterations in state and so the system will be slower to reach setpoint and
slower to respond to perturbations than a well-tuned PID system may be.

3.3 ThePIAlgorithm
While different vendors cast what is essentially the same algorithm in different forms, here
we explore what is variously described as the dependent, ideal, continuous, position form:

The first two terms to the right of the equal sign are identical to the P-Only controller
referenced at the top of this article.The integral mode of the controller is the last term of the
equation. Its function is to integrate or continually sum the controller error, e(t), over time.

30
Recalling that controller error e(t) = SP – PV, rather than viewing PV and SP as separate
traces as we do above, we can compute and plot e(t) at each point in time t.

Below (click for a large view) is the identical data to that above only it is recast as a plot
of e(t) itself. Notice that in the plot above, PV = SP = 50 for the first 10 min, while in the error
plot below, e(t) = 0 for the same time period.

31
This plot is useful as it helps us visualize how controller error continually changes size
and sign as time passes.

3.4 Function of the Integral Term

While the proportional term considers the current size of e(t) only at the time of the
controller calculation, the integral term considers the history of the error, or how long and how
far the measured process variable has been from the set point over time.

Integration is a continual summing. Integration of error over time means that we sum up
the complete controller error history up to the present time, starting from when the controller was
first switched to automatic.

Controller error is e(t) = SP – PV. In the plot below (click for a large view), the integral
sum of error is computed as the shaded areas between the SP and PV traces.

32
Each box in the plot has an integral sum of 20 (2 high by 10 wide). If we count the
number of boxes (including fractions of boxes) contained in the shaded areas, we can compute
the integral sum of error.

So when the PV first crosses the set point at around t = 32, the integral sum has grown to
about 135. We write the integral term of the PI controller as:

Since it is controller error that drives the calculation, we get a direct view the situation
from a controller error plot as shown below (click for a large view):

33
Note that the integral of each shaded portion has the same sign as the error. Since the
integral sum starts accumulating when the controller is first put in automatic, the total integral
sum grows as long as e(t) is positive and shrinks when it is negative.

At time t = 60 min on the plots, the integral sum is 135 – 34 = 101. The response is largely
settled out at t = 90 min, and the integral sum is then 135 – 34 + 7 = 108.

34
CHAPTER 4
4.1 PHASE LOCKED LOOP

A phase-locked loop or phase lock loop (PLL) is a control system that tries to generate an
output signal whose phase is related to the phase of the input "reference" signal. It is an
electronic circuit consisting of a variable frequency oscillator and a phase detector that compares
the phase of the signal derived from the oscillator to an input signal. The signal from the phase
detector is used to control the oscillator in a feedback loop. The circuit compares the phase of the
input signal with the phase of a signal derived from its output oscillator and adjusts the frequency
of its oscillator to keep the phases matched.

Frequency is the derivative of phase. Keeping the input and output phase in lock step implies
keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can
track an input frequency, or it can generate a frequency that is a multiple of the input frequency.
The former property is used for demodulation, and the latter property is used for indirect
frequency synthesis.

Phase-locked loops are widely used in radio, telecommunications, computers and other
electronic applications. They may generate stable frequencies, recover a signal from a noisy
communication channel, or distribute clock timing pulses in digital logic designs such as
microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop
building block, the technique is widely used in modern electronic devices, with output
frequencies from a fraction of a hertz up to many gigahertz

Practical analogies

Automobile race analogy:

For a practical idea of what is going on, consider an auto race. There are many cars, and
each of them wants to go around the track as fast as possible. Each lap corresponds to a complete
cycle, and each car will complete dozens of laps per hour. The number of laps per hour (a speed)
is a frequency, but the number of laps (a distance) corresponds to a phase. At one instant, car 3
may have gone 37.23 laps.
35
During most of the race, each car is on its own and is trying to beat every other car on the
course. However, if there is an accident, a pace car comes out to set a safe speed. None of the
race cars are permitted to pass the pace car (or the race cars in front of them), but each of the race
cars want to stay as close to the pace car as it can. While it is on the track, the pace car is a
reference, and the race cars become phase-locked loops. Each driver will measure the phase
difference (a distance in laps) between him and the pace car. If the driver is far away, he will
increase his engine speed (the VCO) to close the gap. If he's too close to the pace car, he will
slow down. The result is all the race cars lock on to the phase of the pace car. The cars travel
around the track in a tight group that is a small fraction of a lap.

Clock analogy:

Phase can be proportional to time, so a phase difference can be a time difference. Clocks are,
with varying degrees of accuracy, phase-locked (time-locked) to a master clock.

Left on its own, each clock will mark time at slightly different rates. A wall clock, for example,
might be fast by a few seconds per hour compared to the reference clock at NIST. Over time, that
time difference would become substantial.

To keep his clock in synch, each week the owner compares the time on his wall clock to a more
accurate clock (a phase comparison), and he resets his clock. Left alone, the wall clock will
continue to diverge from the reference clock at the same few seconds per hour rate.

Some clocks have a timing adjustment (a fast-slow control). When the owner compared his wall
clock's time to the reference time, he noticed that his clock was too fast. Consequently, he could
turn the timing adjust a small amount to make the clock run a little slower. If things work out
right, his clock will be more accurate. Over a series of weekly adjustments, the wall clock's
notion of a second would agree with the reference time (within the wall clock's stability).

An early mechanical version of a phase-locked loop was used in 1921 in the Shortt-
Synchronome clock.

36
History:

Automatic synchronization of electronic oscillators was described in 1923. [2] Earliest research
towards what became known as the phase-locked loop goes back to 1932, when British
researchers developed an alternative to Edwin Armstrong's super heterodyne receiver, the
Homodyne or direct-conversion receiver. In the homodyne or synchrodyne system, a local
oscillator was tuned to the desired input frequency and multiplied with the input signal. The
resulting output signal included the original modulation information. The intent was to develop
an alternative receiver circuit that required fewer tuned circuits than the super heterodyne
receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction
signal was applied to the oscillator, maintaining it in the same phase and frequency as the desired
signal.

In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and
vertical sweep circuits are locked to synchronization pulses in the broadcast signal.[6]

When Signe tics introduced a line of monolithic integrated circuits that were complete phase-
locked loop systems on a chip in 1969, [7] applications for the technique multiplied. A few years
later RCA introduced the "CD4046" CMOS Micro power Phase-Locked Loop, which became a
popular integrated circuit.

4.2 Structure and function

Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both
implementations use the same basic structure.

Block diagram of a PLL (without filter)

Both analog and digital PLL circuits include four basic elements:

 Phase detector,
 low-pass filter
 Variable frequency electronic oscillator, and
 feedback path (which may include a frequency divider).
37
Variations

There are several variations of PLLs. Some terms that are used are analog phase-locked
loop (APLL) also referred to as a linear phase-locked loop (LPLL), digital phase-locked loop
(DPLL), all digital phase-locked loop (ADPLL), and software phase-locked loop (SPLL). An
analog PLL uses components that have analog (linear) outputs A digital PLL implies that at least
some of the phase-locked loop components are digital. There may be digital phase detector or a
digital frequency divider, for example, but the VCO may be analog.

Digital PLLs use digital filtering techniques to process the baseband error signal. A time-
to-digital converter is used in place of the analog phase detector to digitize the time arrival
difference between the NCO output and a reference signal. The resulting digital signal is filtered
using signal processing techniques before finally being converted back into the analog domain
(via a digital-to-analog converter) to provide a steering signal to the analog VCO.

The term ADPLL uses all digital components. In place of a voltage-controlled oscillator
(VCO), a DPLL may use a local reference clock and a variable dividing counter under digital
control to create the equivalent oscillator function. The SPLL is an ADPLL implemented in
software. The implementation may be done on a digital signal processor or on a general purpose
computer. Performance parameters

This section requires expansion.

 Loop bandwidth
 Lock range
 Capture range
 Transient response
 Steady-state errors
 Type and order.

38
4.3 Applications:

Phase-locked loops are widely used for synchronization purposes; in space communications for
coherent demodulation and threshold[disambiguation needed] extension, bit synchronization, and symbol
synchronization. Phase-locked loops can also be used to demodulate frequency-modulated
signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple
of a reference frequency, with the same stability as the reference frequency.

Other applications include:

 Demodulation of both FM and AM signals

 Recovery of small signals that otherwise would be lost in noise (lock-in amplifier)
 Recovery of clock timing information from a data stream such as from a disk drive
 Clock multipliers in microprocessors that allow internal processor elements to run faster
than external connections, while maintaining precise timing relationships
 DTMF decoders, modems, and other tone decoders, for remote control and
telecommunications

Clock recovery:

Some data streams, especially high-speed serial data streams (such as the raw stream of
data from the magnetic head of a disk drive), are sent without an accompanying clock. The
receiver generates a clock from an approximate frequency reference, and then phase-aligns to the
transitions in the data stream with a PLL. This process is referred to as clock recovery. In order
for this scheme to work, the data stream must have a transition frequently enough to correct any
drift in the PLL's oscillator. Typically, some sort of redundant encoding is used; 8B10B is very
common.

Desk wing:

If a clock is sent in parallel with data, that clock can be used to sample the data. Because
the clock must be received and amplified before it can drive the flip-flops which sample the data,
there will be a finite, and process-, temperature-, and voltage-dependent delay between the

39
detected clock edge and the received data window. This delay limits the frequency at which data
can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so
that the clock at each data flip-flop is phase-matched to the received clock. In that type of
application, a special form of a PLL called a delay-locked loop (DLL) is frequently used.[10]

Clock generation

Many electronic systems include processors of various sorts that operate at hundreds of
megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs,
which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating
frequency of the processor. The multiplication factor can be quite large in cases where the
operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of
megahertz.

Spread spectrum

All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies
(such as the FCC in the United States) put limits on the emitted energy and any interference
caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating
frequency of the device, and a few harmonics). A system designer can use a spread-spectrum
PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion
of the spectrum. For example, by changing the operating frequency up and down by a small
amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly
over a few megahertz of spectrum, which drastically reduces the amount of noise seen on
broadcast FM radio channels, which have a bandwidth of several tens of kilohertz.

40
Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then
drives the system's clock distribution. The clock distribution is usually balanced so that the clock
arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input.
The function of the PLL is to compare the distributed clock to the incoming reference clock, and
vary the phase and frequency of its output until the reference and feedback clocks are phase and
frequency matched.

PLLs are ubiquitous—they tune clocks in systems several feet across, as well as clocks in
small portions of individual chips. Sometimes the reference clock may not actually be a pure
clock at all, but rather a data stream with enough transitions that the PLL is able to recover a
regular clock from that stream. Sometimes the reference clock is the same frequency as the clock
driven through the clock distribution, other times the distributed clock may be some rational
multiple of the reference.

Jitter and noise reduction

One desirable property of all PLLs is that the reference and feedback clock edges be brought into
very close alignment. The average difference in time between the phases of the two signals when
the PLL has achieved lock is called the static phase offset (also called the steady-state phase
error). The variance between these phases is called tracking jitter. Ideally, the static phase offset
should be zero, and the tracking jitter should be as low as possible.

41
Phase noise is another type of jitter observed in PLLs, and is caused by the oscillator
itself and by elements used in the oscillator's frequency control circuit. Some technologies are
known to perform better than others in this regard. The best digital PLLs are constructed with
emitter-coupled logic (ECL) elements, at the expense of high power consumption. To keep phase
noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor
logic (TTL) or CMOS

Another desirable property of all PLLs is that the phase and frequency of the generated
clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as
well as the voltage of the substrate on which the PLL circuits are fabricated. This is called
substrate and supply noise rejection. The higher the noise rejection, the better.

To further improve the phase noise of the output, an injection locked oscillator can be employed
following the voltage controlled oscillator in the PLL.

Frequency Synthesis

In digital wireless communication systems (GSM, CDMA etc.), PLLs are used to provide the
local oscillator (LO) for up-conversion during transmission and down-conversion during
reception. In most cellular handsets this function has been largely integrated into a single
integrated circuit to reduce the cost and size of the handset. However, due to the high
performance required of base station terminals, the transmission and reception circuits are built
with discrete components to achieve the levels of performance required. GSM LO modules are
typically built with a frequency synthesizer integrated circuit and discrete resonator VCOs.[

Frequency synthesizer manufacturers include Analog Devices, [11] National Semiconductor and
Texas Instruments. VCO manufacturers include Sirenza, Z-Communications, Inc. (Z-COMM).

42
Analog phase-locked loop

A phase detector compares two input signals and produces an error signal which is proportional
to their phase difference. The error signal is then low-pass filtered and used to drive a VCO
which creates an output frequency. The output frequency is fed through an optional frequency
divider back to the input of the system, producing a negative feedback loop. If the output
frequency drifts, the error signal will increase, driving the VCO frequency in the opposite
direction so as to reduce the error. Thus the output is locked to the frequency at the other input.
This input is called the reference.

Analog phase locked loops are generally built with a phase detector, low pass filter and
VCO placed in a negative feedback closed-loop configuration. There may be a frequency divider
in the feedback path or in the reference path, or both, in order to make the PLL's output signal
frequency a rational multiple of the reference. A non integer multiple of the reference frequency
can also be created by replacing the simple divide-by-N counter in the feedback path with a
programmable pulse swallowing counter. This technique is usually referred to as a fractional-N
synthesizer or fractional-N PLL.

The oscillator generates a periodic output signal. Assume that initially the oscillator is at
nearly the same frequency as the reference signal. If the phase from the oscillator falls behind
that of the reference, the phase detector changes the control voltage of the oscillator so that it
speeds up. Likewise, if the phase creeps ahead of the reference, the phase detector changes the
control voltage to slow down the oscillator. Since initially the oscillator may be far from the
reference frequency, practical phase detectors may also respond to frequency differences, so as
to increase the lock-in range of allowable inputs.

43
Depending on the application, either the output of the controlled oscillator, or the control
signal to the oscillator, provides the useful output of the PLL system.

Phase detector

The two inputs of the phase detector are the reference input and the feedback from the voltage
controlled oscillator (VCO). The PD output controls the VCO such that the phase difference
between the two inputs is held constant, making it a negative feedback system. There are several
types of phase detectors in the two main categories of analog and digital.

Different types of phase detectors have different performance characteristics.

For instance, the frequency mixer produces harmonics that adds complexity in applications
where spectral purity of the VCO signal is important. The resulting unwanted (spurious)
sidebands, also called "reference spurs" can dominate the filter requirements and reduce the
capture range and lock time well below the requirements. In these applications the more complex
digital phase detectors are used which do not have as severe a reference spur component on their
output. Also, when in lock, the steady-state phase difference at the inputs using this type of phase
detector is near 90 degrees. The actual difference is determined by the DC loop gain.

A bang-bang charge pump phase detector must always have a dead band where the
phases of inputs are close enough that the detector detects no phase error. For this reason, bang-
bang phase detectors are associated with significant minimum peak-to-peak jitter, because of
drift within the dead band however these types, having outputs consisting of very narrow pulses
at lock, are very useful for applications requiring very low VCO spurious outputs. The narrow
pulses contain very little energy and are easy to filter out of the VCO control voltage. This
results in low VCO control line ripple and therefore low FM sidebands on the VCO.[citation needed]

In PLL applications it is frequently required to know when the loop is out of lock. The
more complex digital phase-frequency detectors usually have an output that allows a reliable
indication of an out of lock condition.

44
Filter

The block commonly called a low pass filter generally has two distinct functions.

The primary function is to determine loop dynamics, also called stability. This is how the loop
responds to disturbances, such as changes in the reference frequency, changes of the feedback
divider, or at startup. Common considerations are the range over which the loop can achieve lock
(pull-in range, lock range or capture range), how fast the loop achieves lock (lock time, lock-up
time or settling time) and damping behavior. Depending on the application, this may require one
or more of the following: a simple proportion (gain or attenuation), an integral (low pass filter)
and/or derivative (high pass filter). Loop parameters commonly examined for this are the loop's
gain margin and phase margin. Common concepts in control theory including the PID controller
are used to design this function.

The second common consideration is limiting the amount of reference frequency energy (ripple)
appearing at the phase detector output that is then applied to the VCO control input. This
frequency modulates the VCO and produces FM sidebands commonly called "reference
spurious". The low pass characteristic of this block can be used to attenuate this energy, but at
times a band reject "notch" may also be needed.[citation needed]

Oscillator

All phase-locked loops employ an oscillator element with variable frequency capability.
This can be an analog voltage controlled oscillator either driven by analog circuitry in the case of
an APLL or driven digitally through the use of a digital-to-analog converter as is the case for
some DPLL designs. Pure digital oscillators such as a numerically-controlled oscillator are used
in ADPLLs.

Feedback path and optional divider

An Example Digital Divider (by 4) for use in the Feedback Path of a Multiplying PLL

PLLs may include a divider between the oscillator and the feedback input to the phase detector to
produce a frequency synthesizer. A programmable divider is particularly useful in radio

45
transmitter applications, since a large number of transmit frequencies can be produced from a
single stable, accurate, but expensive, quartz crystal–controlled reference oscillator.

Some PLLs also include a divider between the reference clock and the reference input to the
phase detector. If the divider in the feedback path divides by N and the reference input divider
divides by M, it allows the PLL to multiply the reference frequency by N / M. It might seem
simpler to just feed the PLL a lower frequency, but in some cases the reference frequency may
be constrained by other issues, and then the reference divider is useful.

46
CHAPTER 5

INTRODUCTION TO MATLAB

5.1 EXECUTION PROCEDURE

Matlab is a high-performance language for technical computing. The name mat lab
stands for matrix laboratory. It integrates computation, visualization, and programming in an
easy-to-use environment where problems and solutions are expressed in familiar mathematical
notation. Typical uses include Math and computation Algorithm development Data acquisition
Modeling, simulation, and prototyping Data analysis, exploration, and visualization Scientific
and engineering graphics Application development, including graphical user interface building.

Matlab is an interactive system whose basic data element is an array that does not require
dimensioning. This allows you to solve many technical computing problems, especially those
with matrix and vector formulations, in a fraction of the time it would take to write a program in
a scalar no interactive language such as C or FORTRAN.

History of Matlab:

Cleve Barry Moler, the chairman of the computer-science department at the University of
New Mexico, he is a mathematician and computer programmer specializing in numerical
analysis. Started developing MATLAB in the late 1970s. He designed it to give his students
access to LINPACK and EISPACK without their having to learn Fortran. It soon spread to other
universities and found a strong audience within the applied mathematics community. Jack Little,
an engineer, was exposed to it during a visit Moler made to Stanford University in 1983.
Recognizing its commercial potential, he joined with Moler and Steve Bangert. They rewrote
MATLAB in C and founded Math Works in 1984 to continue its development. These rewritten
libraries were known as JACKPAC. In 2000, MATLAB was rewritten to use a newer set of
libraries for matrix manipulation, LAPACK.

47
Strengths of Matlab:

 MATLAB is relatively easy to learn.

 MATLAB code is optimized to be relatively quick when performing matrix operations.
 MATLAB may behave like a calculator or as a programming language.
 MATLAB is interpreted, errors are easier to fix.
 Although primarily procedural, MATLAB does have some object-oriented elements.

Other features:

 2-D and 3-D graphics functions for visualizing data

 Tools for building custom graphical user interfaces
 Functions for integrating MATLAB based algorithms with external applications and
languages, such as C, C++, FORTRAN, Java, COM, and Microsoft Excel.

Components of Matlab:

 Workspace
 Current Directory
 Command History
 Command Window

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Block diagram of Mat lab components

MATLAB and engineering:

MATLAB was first adopted by researchers and practitioners in control engineering,

Little's specialty, but quickly spread to many other domains. It is now also used in education, in
particular the teaching of linear algebra and numerical analysis, and is popular amongst scientists
involved in image processing. However, many researchers mostly from Computer Science
background feel that MATLAB should be used only for mathematical analysis necessary in
image processing and not for implementation of image processing software. Moreover,
MATLAB should not be used to simulate computer architectures, systems software and
computer networks unless while solving some numeric problem.

Toolboxes in Matlab:

 Simulink
 Fuzzy
 Genetic algorithm
 Neural network
 Wavelet

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Simulink:

 Introduction:

Simulink is a software add-on to mat lab which is a mathematical tool developed by The
Math works,(http://www.mathworks.com) a company based in Natick. Mat lab is powered by
extensive numerical analysis capability. Simulink is a tool used to visually program a dynamic
system (those governed by Differential equations) and look at results. Any logic circuit, or
control system for a dynamic system can be built by using standard building blocks available in
Simulink Libraries. Various toolboxes for different techniques, such as Fuzzy Logic, Neural
Networks, DSP, Statistics etc. are available with Simulink, which enhance the processing power
of the tool. The main advantage is the availability of templates / building blocks, which avoid the
necessity of typing code for small mathematical processes.

 Concept of signal and logic flow:

In Simulink, data/information from various blocks are sent to another block by lines
connecting the relevant blocks. Signals can be generated and fed into blocks dynamic /
static).Data can be fed into functions. Data can then be dumped into sinks, which could be
scopes, displays or could be saved to a file. Data can be connected from one block to another,
can be branched, multiplexed etc. In simulation, data is processed and transferred only at discrete
times, since all computers are discrete systems. Thus, a simulation time step (otherwise called an
integration time step) is essential, and the selection of that step is determined by the fastest
dynamics in the simulated system.

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Fig 5.1.1 :Simulink library browser

 Connecting blocks:

fig Connectung blocks

To connect blocks, left-click and drag the mouse from the output of one block to the input of
another block.

Sources and sinks:

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The sources library contains the sources of data/signals that one would use in a dynamic
system simulation. One may want to use a constant input, a sinusoidal wave, a step, a repeating
sequence such as a pulse train, a ramp etc. One may want to test disturbance effects, and can use
the random signal generator to simulate noise. The clock may be used to create a time index for
plotting purposes. The ground could be used to connect to any unused port, to avoid warning
messages indicating unconnected ports.

The sinks are blocks where signals are terminated or ultimately used. In most cases, we
would want to store the resulting data in a file, or a matrix of variables. The data could be
displayed or even stored to a file. The stop block could be used to stop the simulation if the input
to that block (the signal being sunk) is non-zero. Figure 3 shows the available blocks in the
sources and sinks libraries. Unused signals must be terminated, to prevent warnings about
unconnected signals.

fig Sources and sinks

 Continuous and discrete systems:

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All dynamic systems can be analyzed as continuous or discrete time systems. Simulink
allows you to represent these systems using transfer functions, integration blocks, delay blocks
etc.

fig continous and descrete systems

 Non-linear operators:

A main advantage of using tools such as Simulink is the ability to simulate non-linear
systems and arrive at results without having to solve analytically. It is very difficult to arrive at
an analytical solution for a system having non-linearities such as saturation, signup function,
limited slew rates etc. In Simulation, since systems are analyzed using iterations, non-linearities

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are not a hindrance. One such could be a saturation block, to indicate a physical limitation on a
parameter, such as a voltage signal to a motor etc. Manual switches are useful when trying
simulations with different cases. Switches are the logical equivalent of if-then statements in
programming.

Fig: simulink blocks

 Mathematical operations:

Mathematical operators such as products, sum, logical operations such as and, or, etc. can
be programmed along with the signal flow. Matrix multiplication becomes easy with the matrix
gain block. Trigonometric functions such as sin or tan inverse (at an) are also available.
Relational operators such as ‘equal to’, ‘greater than’ etc. can also be used in logic circuits.

Fig: Simulink math blocks

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 Signals & data transfer:

In complicated block diagrams, there may arise the need to transfer data from one portion
to another portion of the block. They may be in different subsystems. That signal could be
dumped into a GOTO block, which is used to send signals from one subsystem to another.

Multiplexing helps us remove clutter due to excessive connectors, and makes matrix
(column/row) visualization easier.

fig signals and systems

 Making subsystems:

Drag a subsystem from the Simulink Library Browser and place it in the parent block
where you would like to hide the code. The type of subsystem depends on the purpose of the
block. In general one will use the standard subsystem but other subsystems can be chosen. For
instance, the subsystem can be a triggered block, which is enabled only when a trigger signal is
received.

Open (double click) the subsystem and create input / output PORTS, which transfer
signals into and out of the subsystem. The input and output ports are created by dragging them

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from the Sources and Sinks directories respectively. When ports are created in the subsystem,
they automatically create ports on the external (parent) block. This allows for connecting the
appropriate signals from the parent block to the subsystem.

 Setting simulation parameters:

Running a simulation in the computer always requires a numerical technique to solve a

differential equation. The system can be simulated as a continuous system or a discrete system
based on the blocks inside. The simulation start and stop time can be specified. In case of
variable step size, the smallest and largest step size can be specified. A Fixed step size is
recommended and it allows for indexing time to a precise number of points, thus controlling the
size of the data vector. Simulation step size must be decided based on the dynamics of the
system. A thermal process may warrant a step size of a few seconds, but a DC motor in the
system may be quite fast and may require a step size of a few milliseconds.

Simpower system:

 Introduction:

SimPowerSystems software and other products of the Physical Modeling product family
work together with Simulink software to model electrical, mechanical, and control systems.
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SimPowerSystems software operates in the Simulink environment. Therefore, before
starting this user's guide, make yourself familiar with Simulink documentation. Or, if you
perform signal processing and communications tasks (as opposed to control system design
tasks), see the Signal Processing Block set documentation.

 The Role of Simulation in Design:

Electrical power systems are combinations of electrical circuits and electromechanical

devices like motors and generators. Engineers working in this discipline are constantly
improving the performance of the systems. Requirements for drastically increased efficiency
have forced power system designers to use power electronic devices and sophisticated control
system concepts that tax traditional analysis tools and techniques. Further complicating the
analyst's role is the fact that the system is often so nonlinear that the only way to understand it is
through simulation.

Land-based power generation from hydroelectric, steam, or other devices is not the only
use of power systems. A common attribute of these systems is their use of power electronics and
control systems to achieve their performance objectives.

SimPowerSystems software is a modern design tool that allows scientists and engineers
to rapidly and easily build models that simulate power systems. It uses the Simulink
environment, allowing you to build a model using simple click and drag procedures. Not only
can you draw the circuit topology rapidly, but your analysis of the circuit can include its
interactions with mechanical, thermal, control, and other disciplines. This is possible because all
the electrical parts of the simulation interact with the extensive Simulink modeling library.

Since Simulink uses the MATLAB computational engine, designers can also use
MATLAB toolboxes and Simulink block sets. SimPowerSystems software belongs to the
Physical Modeling product family and uses similar block and connection line interface.

 Sim power systems Libraries:

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SimPowerSystems libraries contain models of typical power equipment such as
transformers, lines, machines, and power electronics. These models are proven ones coming
from textbooks, and their validity is based on the experience of the Power Systems Testing and
Simulation Laboratory of Hydro-Québec, a large North American utility located in Canada, and
also on the experience of École de Technology Supérieure and Université Laval. The capabilities
of SimPowerSystems software for modeling a typical electrical system are illustrated in
demonstration files. And for users who want to refresh their knowledge of power system theory,
there are also self-learning case studies.

The SimPowerSystems main library, powerlib, organizes its blocks into libraries
according to their behavior. The powerlib library window displays the block library icons and
names. Double-click a library icon to open the library and access the blocks. The main powerlib
library window also contains the Powergui block that opens a graphical user interface for the
steady-state analysis of electrical circuits.

 Nonlinear Simulink Blocks for Simpower systems Models:

The nonlinear Simulink blocks of the powerlib library are stored in a special block library
named powerlib models. These masked Simulink models are used by SimPowerSystems
software to build the equivalent Simulink model of your circuit. See Improving Simulation
Performance for a description of the powerlib models library.

Fig 5.1.2 Diagram of simpower system

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5.2 Applications of Matlab:

MATLAB is a data-manipulation software package that allows data to be analyzed and

visualized using existing functions and user-designed programs. MATLAB is a numerical
computing environment and programming language. MATLAB allows easy matrix
manipulation, plotting of functions and data, implementation of algorithms, creation of user
interfaces, and interfacing with programs in other languages. Although it specializes in numerical
computing, an optional toolbox interfaces with the Maple symbolic engine, allowing it to be part
of a full computer algebra system.

Some of the mat lab applications listed are:

 Orthogonal frequency division multiplexing

 Genetic algorithm data mining
 Speech recognition using VQ method
 Channel Estimation and Detection in DS-CDMA
 Analysis of iterative channel estimation and multi-user detection in multi path DS-CDMA
channels
 Time-domain signal detection

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 Time-domain signal detection based on second-order statistics for mimo-OFDM systems
 Space–time block coding
 Space–time block codes for mimo channels
 Blind channel estimation

Basic circuit designing and analyzing of results:

Click on the file and select new model file and a file will be appeared:

Now a block and right click on it, the block will be appearing in the new model file (untitled)

For example consider a sine wave in the source block and in order to obtain or to view
the output place the scope block. Join those two blocks. Now a simple circuit is ready, now set
the simulation time in the tool bar (default it is set to 10.0), simulate the circuit by clicking on the

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simulation icon (PLAY BUTTON). Simulation is completed now by double clicking on the
scope u can view the output, press the auto scale button and o/p will appear clearly.

5.3 SIMULATION RESULTS:

The battery parameters when EV1 is operating in V2G mode and EV2 operating in
G2V mode are shown in Figs. 6 and 7, respectively.

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Voltage, current, and SOC of EV1 battery during V2G operation

Voltage, current, and SOC of EV2 battery during G2V operation

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Active power profile of various components in the system

Variation in dc bus voltage

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Reference current tracking by inverter controller

Grid voltage and grid injected current during V2G-G2V operation

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8. The grid power changes to accommodate the power transferred by the EVs. The negative
polarity of the grid power from 1s to 4s shows that the power is being fed to the grid from the
vehicle. The change in polarity of grid power at 4s shows that the power is supplied by the grid
for charging the vehicle battery. This demonstrates the V2G-G2V operation. Also, the net power
at PCC is zero showing an optimal power balance in the system.

The dc bus voltage is regulated at 1500 V by the outer voltage control loop of the inverter
controller and is shown in Fig. 9. This in turn is achieved by the inner current control loop
tracking the changed d-axis reference current as shown in Fig. 10.

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The grid voltage and current at PCC are shown in Fig. 11. Voltage and current are in phase
during G2V operation and out of phase during V2G operation showing the reverse power flow.

Total harmonic distortion (THD) analysis is done on the grid injected current and the result is
shown in Fig. 12. According to IEEE Std. 1547, harmonic current distortion on power systems
69 kV and below are limited to 5% THD. The THD of grid injected current is obtained as 2.31 %
and is achieved by the judicious design of LCL filter.

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FUTURE SCOPE

Moreover, the feasibility of the smart grid with the V2Gschemes has been explored with the
insight of the recent projects. The low penetration of the electric vehicles embedded with
theV2G functionalities is one of the challenges which hinder to a large extent the EVs adoption
in the energy market. The side effects of the EV technologies like low cost and high efficient
power converters (for EV charger) are among the other factors manifested at the automotive
manufacturers' perspectives. For the effectiveV2G operation with the current battery technology,
the challenge still remains to be battery wearing under frequent charging and discharging cycles.
The researches have shown some promising results for lithium ion (LFP) battery.

Nevertheless, to guarantee high penetration of the EVs, further detailed studies are required that
would take into account various research areas like the strategies to enhance battery lifetime
extension and cost–benefit analysis for their (batteries) deployment in the V2G services. Besides,
the same studies on the other battery technologies like NiMH and various other lithium ion
chemistries are yet to be revealed. This is an important topic as it involves the core technology
for the EV applications especially the V2G services.

However, in the V2G applications, the dynamics of the power system (e.g.
voltage dips) are inevitable. Studies on the V2G that consider weak grid dynamics are quite
important but very few have been reported. Likewise, the integration of the RES into the power
system such as wind and solar energy sources using EVs is one of the good representation
models that require weak grid scenarios to be considered. To foresee the effective and reliable
electric grid operation with the V2G support, a clear understanding of the dynamic behaviors of
the electric grid is indispensable.

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CONCLUSION

Modeling and design of a V2G system in a micro-grid using dc fast charging architecture is
presented in this paper. A dc fast charging station with off-board chargers and a grid connected
inverter is designed to interface EVs to the microgrid. The control system designed for this
power electronic interface allows bi-directional power transfer between EVs and the grid. The
simulation results show a smooth power transfer between the EVs and the grid, and the quality of
grid injected current from the EVs adheres to the relevant standards. The designed controller
gives good dynamic performance in terms of dc bus voltage stability and in tracking the changed
active power reference. Active power regulation aspects of the microgrid are considered in this
work, and the proposed V2G system can be utilized for several other services like reactive power
control and frequency regulation. Design of a supervisory controller which gives command
signals to the individual EV charger controllers is suggested for future research.

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REFERENCES

[1] C. Shumei, L. Xiaofei, T. Dewen, Z. Qianfan, and S. Liwei, “The construction and simulation
of V2G system in micro-grid,” in Proceedings of the International Conference on Electrical
Machines and Systems, ICEMS 2011, 2011, pp. 1–4.

[2] S. Han, S. Han, and K. Sezaki, “Development of an optimal vehicle-togrid aggregator for
frequency regulation,” IEEE Trans. Smart Grid, vol. 1, no. 1, pp. 65–72, 2010.

[3] M. C. Kisacikoglu, M. Kesler, and L. M. Tolbert, “Single-phase on-board bidirectional PEV

charger for V2G reactive power operation,” IEEE Trans. Smart Grid, vol. 6, no. 2, pp. 767–775,
2015.

[4] A. Arancibia and K. Strunz, “Modeling of an electric vehicle charging station for fast DC
charging,” in Proceedings of the IEEE International Electric Vehicle Conference (IEVC), 2012,
pp. 1–6.

[5] K. M. Tan, V. K. Ramachandaramurthy, and J. Y. Yong, “Bidirectional battery charger for

electric vehicle,” in 2014 IEEE Innovative Smart Grid Technologies - Asia, ISGT ASIA 2014,
2014, pp. 406–411.

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