MODULE V

OP-AMP Circuits: Differentiator and Integrator circuits-practical circuits – Design

Comparators: Zero crossing and voltage level detectors, Schmitt trigger. Comparator IC: LM311.
Wave form generation using Op-Amps: Square, triangular and ramp generator circuits using Op-
Amp- Effect of slew rate on waveform generation.
Timer 555IC: Internal diagram of 555IC–Astable and Monostable multi-vibrators using 555 IC.
OP-Amp Integrators and Differentiators

 A circuit that performs the mathematical integration of input signal is

called an integrator.
 The output of an integrator is proportional to the area of the input
waveform over a period of time.
 A circuit that performs the mathematical differentiation of input
signal is called a differentiator.
 The output of a differentiator is proportional to the rate of change of
its input signal.
 The two operations are opposite.
 The two circuits are nearly identical in terms of their
construction.
 Each contains a single OP-amp and an RC circuit.
 The difference in resistor/capacitor placement in the two
circuits causes them to have input/output relationships
that are exact opposites.
 For example, if the input to the integrator is a square wave,
the output will be a triangular wave.
 However, the differentiator will convert a triangular wave
into square wave.
OP-AMP Integrator Circuit

• An integrator is a circuit that performs a

mathematical operation called integration

(process of continuous addition).
• The output of an integrator is proportional to

the area of the input waveform over a period

of time.
• It consists of an OP-amp, input resistor R and

feedback capacitor C.
Analysis

 Rules
 Point A is at virtual ground.
 No current to the inverting input terminal
𝑖 = 𝑖𝑐
𝑣𝑖 −0 𝑑(0−𝑣𝑜 )
=C
𝑅 𝑑𝑡
𝑣𝑖 𝑑𝑣
= −C 𝑜
𝑅 𝑑𝑡
1
𝑑𝑣𝑜 = − 𝑣𝑖 𝑑𝑡
𝑅𝐶
Integrating
1 𝑡 Output is the integral of the input with an
𝑣𝑜 = − ‫׬‬0 𝑣𝑖 𝑑𝑡 inversion and scale multiplier of 1/RC.
𝑅𝐶
26

Sample Input – Output waveform of OP-AMP Integrator

• If a fixed voltage is applied to the input of an

integrator, the output voltage grows over a period of
time, providing a ramp voltage.
• Output voltage ramp (for a fixed input voltage) is
opposite in polarity to the input voltage.
26

Sample Input – Output waveform of OP-AMP Integrator

• The integration of the square wave results in the

triangular wave.
• When the input goes positive, the output will be a
negative ramp. When the input is negative, the output
will be a positive ramp.
26

Sample Input – Output waveform of OP-AMP Integrator

• The integration of the sine wave results in cosine

wave.
Demerits of Opamp Integrator

 For low frequency signals this circuit is very unstable. If the input signal has a low
frequency, the capacitor looks like an open-circuit that disconnects the feedback
path from the circuit. In this situation the circuit behaves like an op-amp in open-
loop. Thus, the output voltage will be in saturation for any input signal.
Practical Integrator

 Feedback resistor Rf provides increased stability.

 All integrators have a critical frequency fc below which they do not
perform proper integration.
 If the input frequency is less than fc, the circuit behaves like a
simple inverting amplifier and no integration occurs.
 Equation to calculate the critical frequency of an integrator:
Problem 1
Problem 2
27

OP-AMP Differentiator

• Its function is to provide an output voltage proportional

to the rate of change of the input voltage.
• It is an inverse mathematical operation to that of an
integrator.
• Differentiator can be obtained by interchanging the
resistor and capacitor of the integrator circuits.
Analysis

 Rules
 Point A is at virtual ground.
 No current to the inverting input terminal
𝑖 = 𝑖𝑐
𝑑(𝑣𝑖 −0) 0−𝑣𝑜
C =
𝑑𝑡 𝑅
𝑑𝑣
𝑣𝑜 = − RC 𝑖
𝑑𝑡

Output is the differentiation of the input with

an inversion and scale multiplier of RC
26

Sample Input – Output waveform of OP-AMP Differentiator

26

Sample Input – Output waveform of OP-AMP Differentiator

26

Sample Input – Output waveform of OP-AMP Differentiator

Demerits of Opamp Differentiator

 At high frequencies the gain of the ideal differentiator is very high. This
high gain makes the circuit unstable.

 Very susceptible to high frequency noise.

Practical Differentiator

 Here Rc and Cc are called as compensating components.

 Addition of the input resistor RC limits the increase in gain at a ratio
of R/RC.
 The circuit now acts like a differentiator amplifier at low
frequencies and an amplifier with resistive feedback at high
frequencies giving much better noise rejection.
 At high frequency, the reactance of Cc is small so high frequency
noise gets bypassed and not appeared at output.
Design procedure for practical differentiator:

Select fa as the highest frequency of input signal.

Assume C and calculate R from the equation

Select fb ≥ 10fa and calculate RC and CC so that RC.C = R.C𝐶

29

Problem 3
• ZERO CROSSING DETECTOR
COMPARATORS • VOLTAGE LEVEL DETECTOR
COMPARATOR

 A comparator is an OP-amp circuit without negative feedback and takes advantage of

very high open-loop voltage gain of OP-amp.
 A comparator has two input voltages (noninverting and inverting) and one output
voltage.
 Because of the high open-loop voltage gain of an OP-amp, a very small difference voltage
between the two inputs drives the amplifier to saturation.
 For example, consider an OP-amp having AOL = 105. A voltage difference of only 0.25 mV
between the inputs will produce an output voltage of (0.25 mV) (105) = 25V. However,
most of OP-amps have output voltages of less than ± 15V because of their d.c. supply
voltages. Therefore, a very small differential input voltage will drive the OP-amp to
saturation. This is the key point in the working of comparator.
27
OP AMP as a Comparator (compares 2 voltages and
produces a signal to indicate which is greater)
Voltage Level Detectors
Voltage Level Detectors

• Figure shows an op-amp comparator circuit.

• A fixed reference voltage Vref is applied to the inverting input terminal and sinusoidal signal is applied
to the non - inverting input terminal.
• When Vin exceeds Vref the output voltage goes to positive saturation because the voltage at the
inverting input is less than non - inverting input.
• On the other hand when Vin is less than Vref output voltage goes to negative saturation.
• Thus output voltage change from one saturation level to the other whenever Vin=Vref.
• At any given time output voltage waveform shows whether Vin is greater or less than Vref.
Hence the name voltage level detector
Zero Crossing Detectors
Zero Crossing Detectors

• It is a voltage level detector with Vref = 0V.

• During the positive half cycle, the input voltage is positive that is above reference voltage. Hence,
the output voltage is +Vsat.
• During the negative half cycle, input voltage is negative that is below the reference voltage, output
is then -Vsat.
• Thus, output voltage switch between +Vsat and –Vsat whenever the input signal crosses the zero
level.
38

SCHMITT Trigger
(Regenerative Comparator)

• The circuit of an op-amp Schmitt Trigger is shown in figure.

• Input voltage Vin is applied to the inverting input terminal and the
feedback voltage goes to the non-inverting terminal. This means the
circuit uses positive voltage feedback.
• It is a bi-stable circuit.
• The input voltage Vi triggers or changes the state of output Vout every
time it exceeds its voltage levels above a certain threshold value
called UTP (Upper Trigger Point) and LTP (Lower Trigger point).
39

SCHMITT Trigger
(Regenerative Comparator)
• The output voltage will remain in the given state until the input voltage Vin exceeds the reference
voltage for that state.
𝑅2
• Let feedback fraction 𝛽 =
𝑅1 +𝑅2
• When output is positively saturated, the reference voltage applied to the non inverting input is
Vref =+𝛽 V𝑠at. The input voltage must be increased slightly above +𝛽𝑉𝑠𝑎𝑡 to switch the
output voltage from positive to negative.
• When the output is negatively saturated the reference voltage is Vref =-𝛽 V𝑠at. The output will
remain there indefinitely until the input voltage becomes more negative than – βVsat. Then the
output switches from negative to positive.
UTP AND LTP

 UTP  LTP
• When Vout = +Vsat, the voltage across R2 is • When Vout = -Vsat, the voltage across R2 is
called Upper Threshold Voltage or Upper called Lower Threshold Voltage or Lower
Trigger Point (UTP). Trigger Point (LTP).
• When the input voltage is less than UTP, the • When the input voltage is less than LTP, the
output voltage Vout is at +Vsat. output voltage Vout is at -Vsat.
• When the input voltage, Vin is slightly more • When the input voltage, Vin is slightly more
positive than UTP, the output Vout switches negative than LTP, the output Vout switches
from +Vsat to -Vsat. from -Vsat to +Vsat.
• UTP= + 𝛽 Vsat • LTP= - 𝛽 Vsat
Characteristics of the Schmitt trigger
Applications

 Schmitt trigger is mostly used to convert a very slowly varying input voltage into an
output having abruptly varying waveform occurring precisely at certain
predetermined value of input voltage.
 Schmitt trigger may be used for all applications for which a general comparator is
used.
 Any type of input voltage can be converted into its corresponding square signal wave.
The only condition is that the input signal must have large enough excursion to carry
the input voltage beyond the limits of the hysteresis range.
COMPARATOR IC - LM311
Pinout Details

 General purpose voltage comparator IC with 8 pins.

 IC LM 311 is operated from dual power supply of ±15 V.
 It can also be operated from single power supply of +5V when pin 4 is grounded.
 Pin1 - externally grounded as a common point for the whole circuit.
 Pin 3 : Inverting terminal, Pin 2 : Non-Inverting terminal, Pin 7 : Output


-
If Vin > Vin+, o/p goes low If Vin- < Vin+, o/p goes high
 The pins 5 and 6 are used to set the balance voltage if you want to manually
adjust the DC-Offset voltage.
Square Wave Generator using OPAMP
 Resistor R is connected between the inverting input terminal of the op-amp and
output of op-amp. So, the resistor R is used in the negative feedback.
 Resistor R2 is connected between the noninverting input terminal of the op-amp and
its output. So, the resistor R2 is used in the positive feedback
 A capacitor C is connected between the inverting input terminal of the op-amp and
ground. So, the voltage across capacitor C will be the input voltage at this inverting
terminal of op-amp.
 Resistor R1 is connected between the non-inverting input terminal of the op-amp and
ground. So, the voltage across resistor R 1 will be the input voltage at this non-
inverting terminal of the op-amp.
 Input voltage at non-inverting terminal, V1 = Reference voltage
= Voltage across R1
𝑹𝟏
= β V0 Here β =
𝑹𝟏 +𝑹𝟐

 V0 can take values +Vsat and -Vsat

 Input voltage at inverting terminal, VC = Voltage across capacitor C
 When VC exceeds V1, switching from +Vsat to –Vsat occurs
 When VC > V1 , V0 = -Vsat When VC < V1 , V0 = +Vsat
OPERATION

 Assume, there is no charge stored in the capacitor initially. Then, the voltage present at the inverting
terminal of the op-amp is zero volts. But, there is some offset voltage at non-inverting terminal of op-amp.
Due to this, the value present at the output of above circuit will be +Vsat.
 Thus, Input voltage at non-inverting terminal, V1 = + β Vsat
 Now, the capacitor C starts charging through a resistor R.
 Charging continues until VC is just greater than + β Vsat.
 At this instant, output will change to −Vsat. Also V1 becomes -β Vsat.
 The capacitor C starts discharging through resistor R
 Discharging continues until VC becomes more negative than - β Vsat.
 At this instant, output will change to +Vsat. Also V1 becomes +β Vsat.
 The cycle repeats.
In short....

 When V0 = +Vsat, C charges from -β Vsat to +β Vsat

 When VC = +β Vsat,V0 switches to –Vsat
 When V0 = -Vsat, C discharges from +β Vsat to -β Vsat
 When VC = -β Vsat,V0 switches to +Vsat
Design for frequency of square waveform

 Write node equation for the second node.

𝑑(0−𝑉𝐶) 𝑉 −𝑉
C = 𝐶 0
𝑑𝑡 𝑅
𝑑𝑉𝐶 −𝑑𝑡
=
𝑉𝐶 −𝑉𝑜 𝑅𝐶
 Integrating
𝑉 (𝒕) 1 𝑡 1
‫𝑉 )𝟎(𝐶 𝑉׬‬ 𝑑𝑉𝐶 = − ‫׬‬0 dt
𝐶 𝐶 −𝑉𝑜 𝑅𝐶

−𝑡
𝒍𝒏 𝑽𝑪(𝒕)– 𝑽𝒐 - 𝒍𝒏 𝑽𝑪(𝟎)– 𝑽𝒐 =
𝑅𝐶
𝑽𝑪(𝒕)– 𝑽𝒐 −𝑡
𝒍𝒏 =
𝑽𝑪(𝟎)– 𝑽𝒐 𝑅𝐶
𝑽𝑪(𝒕)– 𝑽𝒐 −𝑡
=𝒆 𝑅𝐶
𝑽𝑪 𝟎 – 𝑽 𝒐
−𝑡
𝑽𝑪 𝒕 = 𝑽𝒐 + 𝑽𝑪 𝟎 – 𝑽𝒐 𝒆 𝑅𝐶 -------(1)
Refer figure, Consider time period T1
𝑽𝑪 𝟎 = -β Vsat
𝑽𝒐 =+Vsat
At, t = T/2, 𝑽𝑪 𝒕 = +β Vsat
Thus eqn (1) becomes
−𝑇
+β Vsat= + Vsat +(-β Vsat- Vsat) 𝒆 2𝑅𝐶
−𝑇
β = 1-(β + 1)𝒆 2𝑅𝐶

−𝑇
1− β
𝒆 2𝑅𝐶 =
1+ β

−𝑇 1−β
=ln
2𝑅𝐶 1+β
𝑹𝟏
1+𝛽 Here β = 𝟐𝑹𝟏 +𝑹𝟐
T = 2𝑅𝐶 ln 𝑹𝟏 +𝑹𝟐 T = 2𝑅𝐶 ln
1−β 𝑹𝟐

Also, frequency of waveform, f = 1/T

Triangular Wave Generator using OPAMP

Triangular Wave Generator

 The block diagram of a triangular wave generator contains mainly two blocks:
 A square wave generator and an integrator.
 These two blocks are cascaded.
 The output of square wave generator is applied as an input of integrator.
 Integration of a square wave is nothing but a triangular wave.
CIRCUIT DIAGRAM
OPERATION

 Square wave swings between +Vsat and –Vsat with a time period given
by
𝟐𝑹𝟏+𝑹𝟐
T = 2𝑅𝐶 ln
𝑹𝟐

 Triangular wave has same period and frequency as that of square

wave.
 Peak to peak value of triangular wave is given by
𝑽𝒏
𝑉𝑜𝑢𝑡 =
𝟒𝒇𝑹𝒇 𝑪𝒊

 Also output of integrator ill be triangular only if 𝟓𝑹𝒊𝑪𝒊 > 𝟎. 𝟓𝑻

 Also 𝑹𝒇 = 𝟓𝑹𝒊
Another circuit for Triangular Wave
Generator
CIRCUIT OPERATION

 Comparator compares the voltage at point P continuously with respect to the voltage at the inverting input;
which as at ground potential. When the voltage at P goes slightly below zero, the output of A1 will switch to
negative saturation. Assume that the output of comparator A is at +Vsat .
 This forces a constant current +Vsat/R1 through C to give negative going ramp at the output of the integrator.
 Thus one end of the voltage divider is at +Vsat and the other end at the negative going ramp.
 At time t = t1, when the negative going ramp reaches a certain value –Vramp, the effective voltage at point P
becomes slightly below 0V.
 As a result, the output of the comparator A switches from positive saturation to negative saturation -Vsat .
 This forces a reverse constant current -Vsat/R1 through C to give positive going ramp at the output of the
integrator.
 At time t = t2, when the positive going ramp reaches a certain value +Vramp, the effective voltage at point P
becomes slightly above 0V.
 As a result, output of comparator A switches from negative saturation to positive negative saturation +Vsat .
 Sequence repeats to give triangular wave at the output of the integrator.
Waveform
AMPLITUDE AND FREQUENCY CALCULATION
Ramp Wave Generator using OPAMP
OR Saw tooth Wave Generator using OPAMP

 Difference between the triangular and sawtooth waveform:

▪ Rise time of triangular wave is always equal to its fall time while in sawtooth wave generator, rise time may
be much higher than its fall time or vice versa.
 The triangular wave generator can be converted to a sawtooth wave generator by injecting a
variable dc voltage into the noninverting terminal of the integrator.
 This can be done by using a potentiometer R4 as shown in figure.
 When the wiper of the potentiometer is at the centre, the output will be a triangular wave
since the duty cycle is 50%.
 If the wiper moves towards –V, the rise time of the sawtooth becomes longer than the fall
time.
 If the wiper moves towards +V, the fall time becomes more than the rise time.
CIRCUIT DIAGRAM
Waveform
Op amp slew rate basics

 The slew rate of an op amp or any amplifier circuit is the rate of change in the output
voltage caused by a step change on the input.
 It is measured as a voltage change in a given time - typically V / µs or V / ms.
 Low power op-amps may only have figures of a volt per microsecond, whereas there
are fast operational amplifiers capable to providing rates of 1000 V / µsecond.
Effect of slew rate on waveform generation

 The output of an operational amplifier can only change by a certain amount in a given
time. This limit is called the slew rate of the op-amp.
 Operational amplifier slew rate can limit the performance of a circuit if the slew rate
requirement is exceeded. It can distort the waveform and prevent the input signal
being faithfully represented at the output if the slew rate is exceeded.
 If an op amp is operated above its slew rate limit, signals will become distorted.
Effect of slew rate on different waveforms
555 Timer IC

 The 555 Timer IC is a commonly used IC designed to produce a variety of output waveforms
with the addition of an external RC network.
 The basic 555 timer gets its name from the fact that there are three internally connected 5kΩ
resistors which it uses to generate the two comparators reference voltages.
 It is a stable 8-pin device that can be operated either as a very accurate Monostable, Bistable
or Astable Multivibrator to produce a variety of applications such as one-shot or delay timers,
pulse generation, LED and lamp flashers, alarms and tone generation, logic clocks, frequency
division, power supplies and converters etc.
 It consists of some 25 transistors, 2 diodes and about 16 resistors arranged to form two
comparators, a flip-flop and a high current output stage.
Pinout of 555IC
 Pin 1– Ground. It connects the 555 timer to the negative (0v) supply rail.
 Pin 2– Trigger. The negative input to comparator No 1. A negative pulse (with a dc level greater
than Vcc/3 is applied to this terminal).on this pin “sets” the internal Flip-flop when the voltage
drops below 1/3Vcc causing the output to switch from a “LOW” to a “HIGH” state.
 Pin 3 – Output. Output of the timer is available at this pin. There are two ways in which a load can
be connected to the output terminal. One way is to connect between output pin (pin 3) and ground
pin (pin 1) or between pin 3 and supply pin (pin 8). The load connected between output and
ground supply pin is called the normally on load and that connected between output and ground
pin is called the normally off load.
 Pin 4 – Reset. This pin is used to “reset” the internal Flip-flop controlling the state of the output,
pin 3. This is an active-low input and is generally connected to a logic “1” level when not used to
prevent any unwanted resetting of the output.
 Pin 5– Control Voltage. This pin controls the timing of the 555 by overriding the 2/3Vcc level of the
voltage divider network. By applying a voltage to this pin the width of the output signal can be varied
independently of the RC timing network. When not used it is connected to ground via a 10nF
capacitor to eliminate any noise.
 Pin 6– Threshold. The positive input to comparator No 2. This pin is used to reset the Flip-flop when
the voltage applied to it exceeds 2/3Vcc causing the output to switch from “HIGH” to “LOW” state.
This pin connects directly to the RC timing circuit.
 Pin 7– Discharge. The discharge pin is connected directly to the Collector of an internal NPN
transistor which is used to “discharge” the timing capacitor to ground when the output at pin 3
switches “LOW”.
 Pin 8– Supply +Vcc. This is the power supply pin. A supply voltage of + 5 V to + 18 V is applied to this
terminal with respect to ground (pin 1)
Internal diagram of 555IC
 A 555 timer has two comparators, which are basically 2 op-amps, an R-S flip-flop, two transistors and a
resistive network.
 Resistive network consists of three equal resistors and acts as a voltage divider.
 Comparator 1 compares threshold voltage with a reference voltage + 2/3 VCC volts.
 Comparator 2 compares the trigger voltage with a reference voltage + 1/3 VCC volts.
 Output of both the comparators is supplied to the flip-flop. Flip-flop assumes its state according to the
output of the two comparators. One of the two transistors is a discharge transistor of which collector is
connected to pin 7. This transistor saturates or cuts-off according to the output state of the flip-flop. The
saturated transistor provides a discharge path to a capacitor connected externally. Base of another
transistor is connected to a reset terminal. A pulse applied to this terminal resets the whole timer
irrespective of any input.