Memory Mapping in 8085

An 8085 microprocessor has a 16-bit address bus. Each bit can take the
value of either 0 or 1. So, the total number of addresses that can be
generated on a 16-bit address bus will be 256. And each unique address
refers to a memory block containing 8 bits or 1 byte of space.

Thus, we can say that 8085 can support a memory chip of size up to 64 kB.
We can interface a memory chip of size less than that too. Also, we can
interface several memory chips to a single 8085 microprocessor, until and
unless their combined size does not exceed 64 kB. Let us learn how to
achieve all that.
Memory chips of different types and sizes
Memory chips come in a variety of types and with different storage
capacities. A broad classification of memory chips based on their read and
write capability is:

 RAM (Random Access Memory): We can read as well as write data

on this type of memory. The chip of this type has pins for both
memory read and memory write signals.
 ROM (Read Only Memory): As the name suggests, we can only
write data on this type of memory chip. The chip of this type has a pin
only for memory read signal.

Now, you must be wondering what does a microprocessor read from a

ROM if data cannot be written on it.
Data cannot be written on it by a microprocessor when it is connected in
the circuit. But data can be written on it using some special
techniques. This kind of memory is used to store programs, while RAM is
used to store the data.
ROM is also of two types:

 EPROM (Erasable Programmable Read-Only Memory): The

contents of an EPROM are erased by UV rays. Data is written on it
optically.
 EEPROM (Electronically Erasable Programmable Read-Only
Memory): As the name suggests, data is written and removed on this
type of ROM electronically.
Memory chips come in different sizes. The illustration shows below what
these numbers in the specification of a memory chip capacity (size) mean.

Now, let us learn through an example, how external RAM and external
ROM chips can be interfaced with 8085. Let us take up a problem
regarding the interfacing of memory and solve it as we learn the topic.
Memory interfacing – Problem statement
Interface a 1kB EPROM and a 2 kB RAM with microprocessor 8085.
The address allotted to 1 kB EPROM should be 2000H to 22FFH. You
can assign the address range of your choice to the 2 kB RAM.
The first step to solve this problem is to understand the pins of the given
memory chips.
Pin diagram of memory chips

RAM and ROM both have same pins, except for WR pin, which is present
in RAM and is not there in a ROM. Let us understand the pins one by one.
 Data pins: Since each memory location stores eight bits, there are
eight data lines D0-D7 connected to the memory chip.
 Address pins: The number of address pins depends on the size of
the memory. In this case, a memory of size 1 kB x 8 will have
210 different memory locations. Hence, it will have ten address lines
A0 to A9. Similarly, the 2 kB RAM will have 2 11 different memory
locations. So, there are 11 address lines A0-A10.
 CS pin: When this pin is enabled, the memory chip knows that the
microprocessor is talking to it and responds to it accordingly. We
need to generate this signal for each of the chips according to the
range of addresses assigned to them. Basically, we select a chip only
when it is needed. The Chip Select (CS) pin is used for this.
 OE pin: When this active-low output enable pin is enabled, the
memory chip can output the data into the data bus.
 WR pin: Upon activation of this active-low memory write pin, data on
the data bus is written on the memory chip at the location specified
by the address bus.
 VCC and GND pins: These pins serve the purpose of powering the
ICs. For simplicity, we will not show these pins in the diagram.

There are three types of buses in 8085 – Address bus, data bus, and
control bus. Each of these buses will be connected to the memory chip.
Connecting Control Signals

In the memory chips, there are two pins for control signals – OE (Output
Enable) and WR (Memory Write). These will be connected to the control
signals generated using a 3 to 8 decoder. To read about the generation
of control signals, you can read our post on Demultiplexing of Bus and
Generating Control Signals. The circuit for generating control signals is
shown below.
Four control signals are generated when we input the WR, RD and
IO/M signals from the 8085 to the 3:8 decoder
– IOR, IOW, MEMR and MEMW. Since we are dealing with memory, we
will just need MEMR and MEMW signals.
While reading from a memory chip, it’s output should be enabled.
So, MEMR will be connected to the OE pin. Similarly, for writing to a
memory chip, MEMW will be connected to the WR pin of the RAM. After
completing these two connections, we are done with the control signals
except CS. We will deal with that in a bit.
Data Bus interfacing

There are eight lines comprising the data bus of both 8085 and the memory
chips. The interfacing of the data bus is the simplest part. We just connect
corresponding lines (D0-D7 from 8085) to the corresponding pins (D0-D7 of
the memory chip).
Address bus Interfacing

We have a 2kB RAM with 11 address lines. So, the first 11 lines of the
address bus of 8085 will be connected to the corresponding address lines
of the 2kB RAM. Similarly, the first 10 lines of the address bus of 8085 will
be connected to the corresponding lines of 1kB EPROM. The remaining
address lines will be used to generate the chip select (CS) signal.
Generating the chip select signal

This is a little tricky, but it’s the most important part of solving the problem.
Let us proceed step by step and build up an intuition of how to generate the
chip select signal for a memory of given size and given address range.
Let us tabulate the starting and ending address of the 1kB EPROM.
A15 is most significant, and A0 is the least significant bit. The address
range for placing the EPROM is from 2000H to 22FFH (as given in the
question.) Translating these to binary:
2000H = 0011 0000 0000 0000
22FFH = 0011 0011 1111 1111

Address bit number A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Starting address 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0

Ending Address 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1

From the above table, we can observe that ten bits from A0 to A9 are
changing. These ten bits are directly connected to the address lines of the
memory chip.
These ten bits take the value of either 0 or 1 to form addresses. The first
address is 00 0000 0000, and the second address is 00 0000 0001, the
third is 00 0000 0010 and so on. The last address will be 11 1111 1111.
Meanwhile, bits A11 to A15 do not change and don’t have any effect on the
addressing process inside the memory chip. So, we can conclude that the
values of bits A15-A11 (0011 00) given in the above table are in a unique,
unchanging configuration for this memory chip. If even one of these bits
changes, the address won’t belong to this memory chip. So, we can use
these values of A15-A11 to uniquely identify this memory chip, which
is exactly what the CS signal is supposed to do.
We can say that when A15 = A14 = A11 = A10 = 0 and A13 = A12 = 1,
then our memory chip should be selected. Now, we need to design the
logic to generate the CS signal. The resulting Boolean equation of CS will
be:
CS = Complement of (A15* . A14* . A13 . A12 . A11* . A10*)
This equation can be implemented using NAND Gate. The final chip select
logic for 1kB EPROM is illustrated below.
Now, we have to generate a chip select signal for the second memory chip,
which is 2kB RAM. The process is quite similar and differs from the
previous one in two ways:

 The size of the memory is different. So, there are 11 address lines
instead of 10.
 We are not given an address range here. We are given the liberty to
decide on our own.

Similar to the previous case, we connect the first 11 address lines of the
8085 microprocessor to the 11 address lines of the 2kB RAM. These bits
will take values of 0 and 1 and will generate 2 * 1024 different addresses.
The address bits A10-A0 will vary from 000 0000 0000 to 111 1111 1111.
What about the remaining address bits? Well, they don’t have any role in
the addressing of the memory in this 2kB RAM. So, we can fix them to a
certain value without affecting anything. Let’s fix them to 0000 0. Thus, the
address range for this chip becomes 0000 0000 0000 0000 to 0000 0111
1111 1111. In hexadecimal, the address range will be from 0000H to
07FFH.

Address bit number A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Starting address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Ending Address 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

We use a similar technique here. We use the remaining bits A15-A11 to

uniquely identify this chip i.e., to generate chip select signal. So, the
boolean equation will be
CS = Complement of (A15*. A14*. A13*. A12*. A11*)
The implementation of this equation using NAND Gate to generate
the CS signal is shown in the following image.
The final circuit

Since we now have the chip select logic and have decided all the
connections, it’s time to finalize the circuit. The entire external memory
interfacing circuit can be broken up into five different parts:

 8085 microprocessor
 Demultiplexing of address/data bus
 Generation of control signals
 Generation of chip select signals
 Memory chips

The images below show the final circuit with all the five parts listed above
integrated into a single circuit. Just the connections are shown in the first
diagram. In the diagram following it, different subsections of the circuit are
labeled.
The above diagram summarizes the entire process of interfacing the
external memory with the 8085 microprocessor.