MIPS DIRECTIVES

Directive Meaning
.align n Align next datum on 2^n boundary.
.asciiz str Place the null-terminated string str in memory.
.byte b1, …, bn Place the n byte values in memory.
.data Switch to the data segment.
.double d1, …, dn Place the n double-precision values in memory.
.float f1, …, fn Place the n single-precision values in memory.
.global sym The label sym can be referenced in other files.
.half h1, …, hn Place the n half-word values in memory.
.space n Allocates n bytes of space.
.text Switch to the text segment.
.word w1, …, wn Place the n word values in memory.
MIPS INSTRUCTIONS
General format:
<optional label> <operation> <operands>

Example:
loop: addu $t2,$t3,$t4 # instruction with a label
subu $t2,$t3,$t4 # instruction without a label
L2: # a label can appear on a line by itself
# a comment can appear on a line by itself
MIPS INSTRUCTIONS
What does this look like in memory?

.data
nums:
.word 10, 20, 30
.text
.globl main
main:
la $t0, nums
lw $t1, 4($t0)
MIPS INSTRUCTION FORMATS
There are three different formats for MIPS instructions.
• R format
• Used for shifts and instructions that reference only registers.

• I format
• Used for loads, stores, branches, and immediate instructions.

• J format
• Used for jump and call instructions.
MIPS INSTRUCTION FORMATS
Name Fields
Field Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R format op rs rt rd shamt funct
I format op rs rt immed
J format op targaddr

op – instruction opcode. shamt – shift amount.

rs – first register source operand. funct – additional opcodes.
rt – second register source operand. immed – offsets/constants (16 bits).
rd – register destination operand. targaddr – jump/call target (26 bits).
MIPS INSTRUCTION FORMATS
All MIPS instructions are 32 bits – Design principle 1: simplicity favors regularity!

Name Fields
Field Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R format op rs rt rd shamt funct
I format op rs rt immed
J format op targaddr

op – instruction opcode. shamt – shift amount.

rs – first register source operand. funct – additional opcodes.
rt – second register source operand. immed – offsets/constants.
rd – register destination operand. targaddr – jump/call target.
MIPS INSTRUCTION FORMATS
Make simple instructions fast and accomplish other operations as a series of
simple instructions – Design principle 3: make the common case fast!

Name Fields
Field Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R format op rs rt rd shamt funct
I format op rs rt immed
J format op targaddr

op – instruction opcode. shamt – shift amount.

rs – first register source operand. funct – additional opcodes.
rt – second register source operand. immed – offsets/constants.
rd – register destination operand. targaddr – jump/call target.
MIPS R FORMAT
• Used for shift operations and instructions that only reference registers.
• The op field has a value of 0 for all R format instructions.
• The funct field indicates the type of R format instruction to be performed.
• The shamt field is used only for the shift instructions (sll and srl, sra)

Name Fields
Field Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R format op rs rt rd shamt funct

op – instruction opcode. rd – register destination operand.

rs – first register source operand. shamt – shift amount.
rt – second register source operand. funct – additional opcodes.
R FORMAT INSTRUCTION ENCODING EXAMPLE
Consider the following R format instruction:

addu $t2, $t3, $t4

Fields op rs rt rd shamt funct

Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Decimal 0 11 12 10 0 33
Binary 000000 01011 01100 01010 00000 100001
Hexadecimal 0x016c5021
MIPS I FORMAT
• Used for arithmetic/logical immediate instructions, loads, stores, and conditional
branches.
• The op field is used to identify the type of instruction.
• The rs field is the source register.
• The rt field is either the source or destination register, depending on the instruction.
• The immed field is zero-extended if it is a logical operation. Otherwise, it is sign-
extended.

Name Fields
Field Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
I format op rs rt immed
I FORMAT INSTRUCTION ENCODING EXAMPLES

Arithmetic example:
addiu $t0,$t0,1

Fields op rs rt immed
Size 6 bits 5 bits 5 bits 16 bits
Decimal 9 8 8 1
Binary 001001 01000 01000 0000000000000001
Hexadecimal 0x25080001
I FORMAT INSTRUCTION ENCODING EXAMPLES

Memory access example:

lw $s1,100($s2)

Fields op rs rt immed
Size 6 bits 5 bits 5 bits 16 bits
Decimal 35 18 17 100
Binary 100011 10010 10001 0000000001100100
Hexadecimal 0x8e510064
I FORMAT INSTRUCTION ENCODING EXAMPLES
Conditional branch example:
L2:instruction Note: Branch displacement is a signed value in
instruction instructions, not bytes, from the current
instruction. Branches use PC-relative
instruction
addressing.
beq $t6,$t7,L2

Fields op rs rt immed
Size 6 bits 5 bits 5 bits 16 bits
Decimal 4 14 15 -3
Binary 000100 01110 01111 1111111111111101
Hexadecimal 0x11cffffd
ADDRESSING MODES
• Addressing mode – a method for evaluating an operand.
• MIPS Addressing Modes
• Immediate – operand contains signed or unsigned integer constant.
• Register – operand contains a register number that is used to access the register file.
• Base displacement – operand represents a data memory value whose address is the sum of some
signed constant (in bytes) and the register value referenced by the register number.
• PC relative – operand represents an instruction address that is the sum of the PC and some signed
integer constant (in words).
• Pseudo-direct – operand represents an instruction address (in words) that is the field concatenated
with the upper bits of the PC.

PC Relative and Pseudo-direct addressing are actually relative to PC + 4, not PC. The reason for this will
become clearer when we look at the design for the processor, so we’ll ignore it for now.
MEMORY ALIGNMENT REQUIREMENTS
• MIPS requires alignment of memory references to be an integer multiple of the size
of the data being accessed.
• These alignments are enforced by the compiler.
• The processor checks this alignment requirement by inspecting the least significant
bits of the address.

Byte: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Half: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0
Word: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00
Double: XXXXXXXXXXXXXXXXXXXXXXXXXXXXX000
MIPS J FORMAT
• Used for unconditional jumps and function calls.
• The op field is used to identify the type of instruction.
• The targaddr field is used to indicate an absolute target address.

Name Fields
Field Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
J format op targaddr
J FORMAT INSTRUCTION ENCODING EXAMPLE
Jump example: j L1
Assume L1 is at the address 4194340 in decimal, which is 400024 in hexadecimal.
We fill the target field as an address in instructions (0x100009) rather than bytes
(0x400024). Jump uses pseudo-direct addressing to create a 32-bit address.

Fields op target address

Size 6 bits 26 bits
Decimal 2 1048585
Binary 000010 00000100000000000000001001
Hexadecimal 0x08100009
ARITHMETIC/LOGICAL GENERAL FORM
• Most MIPS arithmetic/logical instructions require 3 operands.
• Design principle 1: Simplicity favors regularity.
• Form 1: <operation> <dstreg>, <src1reg>, <src2reg>
Example Meaning Comment
addu $t0, $t1, $t2 $t0 = $t1 + $t2 Addition (without overflow)
subu $t1, $t2, $t3 $t1 = $t2 - $t3 Subtraction (without overflow)

• Form 2: <operation> <dstreg>, <srcreg>, <constant>

Example Meaning Comment
addiu $t1,$t2,1 $t1 = $t2 + 1 Addition immediate (without overflow)
USING MIPS ARITHMETIC INSTRUCTIONS
• Consider the following C++ source code fragment.
unsigned int f,g,h,i,j;
...
f = (g+h)-(i+j);

• Assume the values of f, g, h, i, and j are associated with registers $t2, $t3, $t4, $t5,
and $t6 respectively. Write MIPS assembly code to perform this assignment assuming
$t7 is available.
USING MIPS ARITHMETIC INSTRUCTIONS
Solution (among others):

addu $t2,$t3,$t4 # $t2 = g + h

addu $t7,$t5,$t6 # $t7 = i + j
subu $t2,$t2,$t7 # $t2 = $t2 - $t7
MULTIPLY, DIVIDE, AND MODULUS INSTRUCTIONS
• Integer multiplication, division, and modulus operations can also be performed.
• MIPS provides two extra registers, hi and lo, to support division and modulus
operations.
• hi and lo are not directly addressable, instead must use mfhi and mflo instructions

Example Meaning Comment

mult $t1,$t2 $lo = $t1 * $t2 Multiplication
divu $t2,$t3 $lo = $t2/$t3 Division and Modulus
$hi = $t2%$t3
mflo $t1 $t1 = $lo Move from $lo
mfhi $t1 $t1 = $hi Move from $hi
CALCULATING QUOTIENT AND REMAINDER
• Given the values $t1 and $t2, the following sequence of MIPS instructions assigns the
quotient ($t1/$t2) to $s0 and the remainder ($t1%$t2) to $s1 .

divu $t1,$t2 # perform both division and modulus operations

mflo $s0 # move quotient into $s0
mfhi $s1 # move remainder into $s1
LOGICAL OPERATIONS
• Consist of bitwise Boolean operations and shifting operations.
• Shifting operations can be used to extract or insert fields of bits within a word.

X Y Not X X and Y X or Y X nand Y X nor Y X xor Y

0 0 1 0 0 1 1 0
0 1 1 0 1 1 0 1
1 0 0 0 1 1 0 1
1 1 0 1 1 0 0 0
GENERAL FORM OF MIPS BITWISE INSTRUCTIONS
• Bitwise instructions apply Boolean operations on each of the corresponding pairs of
bits of two values.
Example Meaning Comment
and $t2,$t3,$t4 $t2 = $t3 & $t4 Bitwise and
or $t3,$t4,$t5 $t3 = $t4 | $t5 Bitwise or
nor $t4,$t3,$t6 $t4 = ~($t3 | $t6) Bitwise nor
xor $t7,$t2,$t4 $t7 = $t2 ^ $t4 Bitwise xor
andi $t2,$t3,7 $t2 = $t3 & 7 Bitwise and with immediate
ori $t3,$t4,5 $t3 = $t4 | 5 Bitwise or with immediate
xori $t7,$t2,6 $t7 = $t2 ^ 6 Bitwise xor with immediate
GENERAL FORM OF MIPS SHIFT INSTRUCTIONS
• Shift instructions move the bits in a word to the left or right by a specified amount.
• Shifting left (right) by i is the same as multiplying (dividing) by 2" .
• An arithmetic right shift replicates the most significant bit to fill in the vacant bits.
• A logical right shift fills in the vacant bits with zero.
Example Meaning Comment
sll $t2,$t3,2 $t2 = $t3 << 2 Shift left logical
sllv $t3,$t4,$t5 $t3 = $t4 << $t5 Shift left logical variable
sra $t4,$t3,1 $t4 = $t3 >> 1 Shift right arithmetic (signed)
srav $t7,$t2,$t4 $t7 = $t2 >> $t4 Shift right arithmetic variable (signed)
srl $t2,$t3,7 $t2 = $t3 >> 7 Shift right logical (unsigned)
srlv $t3,$t4,$t6 $t3 = $t4 >> $t6 Shift right logical variable (unsigned)
GLOBAL ADDRESSES AND LARGE CONSTANTS
• The lui instruction can be used to construct large constants or addresses. It loads a 16-bit
value in the 16 most significant bits of a word and clears the 16 least significant bits.
• MIPS immediate is 16 bits

Form Example Meaning Comment

lui <dreg>,<const> lui $t1,12 $t1 = 12 << 16 Load upper immediate

• Example: load 131,071 (or 0x1ffff) into $t2.

lui $t2,1 # put 1 in the upper half of $t2
ori $t2,$t2,0xffff # set all bits in the lower half
• Having all instructions the same size and a reasonable length means having to construct
global addresses and some constants using two instructions.
• Design principle 4: Good design demands good compromise!
DATA TRANSFER GENERAL FORM
• MIPS can only access memory with load and store instructions, unlike x86
• Form: <operation> <reg1>, <constant>(<reg2>)
Example Meaning Comment
lw $t2,8($t3) $t2 = Mem[$t3 + 8] 32-bit load
lh $t3,0($t4) $t3 = Mem[$t4] Signed 16-bit load
lhu $t8,2($t3) $t8 = Mem[$t3 + 2] Unsigned 16-bit load
lb $t4,0($t5) $t4 = Mem[$t5] Signed 8-bit load
lbu $t6,1($t9) $t6 = Mem[$t9 + 1] Unsigned 8-bit load
sw $t5,-4($t2) Mem[$t2-4] = $t5 32-bit store
sh $t6,12($t3) Mem[$t3 + 12] = $t6 16-bit store
sb $t7,1($t3) Mem[$t3 + 1] = $t7 8-bit store
USING DATA TRANSFER INSTRUCTIONS
• Consider the following source code
fragment.
int a, b, c, d;
...
a = b + c - d;
lw $t6,0($t3) # load b into $t6
• Assume the addresses of a, b, c, and d lw $t7,0($t4) # load c into $t7
are in the registers $t2, $t3, $t4, and add $t6,$t6,$t7 # $t6 = $t6 + $t7
$t5, respectively. The following MIPS lw $t7,0($t5) # load d into $t7
assembly code performs this assignment sub $t6,$t6,$t7 # $t6 = $t6 - $t7
assuming $t6 and $t7 are available. sw $t6,0($t2) # store $t6 into a
INDEXING ARRAY ELEMENTS
• Assembly code can be written to access
array elements using a variable index. .data
Consider the following source code fragment. _a: .space 400 # declare space
...
int a[100], i; la $t1, _a # load address of _a
... sll $t2,$t0,2 # determine offset
a[i] = a[i] + 1; add $t2,$t2,$t1 # add offset and _a
lw $t3,0($t2) # load the value
addi $t3,$t3,1 # add 1 to the value
• Assume the value of i is in $t0. The following sw $t3,0($t2) # store the value
MIPS code performs this assignment.
BRANCH INSTRUCTIONS
• Branch instructions can cause the next instruction to be executed to be other than the
next sequential instruction.
• Branches are used to implement control statements in high-level languages.
• Unconditional (goto, break, continue, call, return)
• Conditional (if-then, if-then-else, switch)
• Iterative (while, do, for)
GENERAL FORM OF JUMP AND BRANCH
• MIPS provides direct jumps to support unconditional transfers of control to a
specified location.
• MIPS provides indirect jumps to support returns and switch statements.
• MIPS provides conditional branch instructions to support decision making. MIPS
conditional branches test if the values of two registers are equal or not equal.

General Form Example Meaning Comment

j <label> j L1 goto L1; Direct jump (J)
jr <sreg> jr $ra goto $ra; Indirect jump (R)
beq <s1reg>,<s2reg>,<label> beq $t2, $t3, L1 if($t2 == $t3) goto L1; Branch equal (I)
bne <s1reg>,<s2reg>,<label> bne $t2, $t3, L1 if($t2 != $t3) goto L1; Branch not equal (I)
IF STATEMENT EXAMPLE
• Consider the following source code:

if(i == j)
k = k + i;
• Translate into MIPS instructions assuming the values of i, j, and k are associated with
the registers $t2, $t3, and $t4, respectively.

bne $t2,$t3,L1 # if ($t2 != $t3) goto L1

addu $t4,$t4,$t2 # k = k + i
L1:
GENERAL FORM OF COMPARISON INSTRUCTIONS
• MIPS provides set-less-than instructions that set a register to 1 if the first source
register is less than the value of the second operand. Otherwise, it is set to 0.
• There are versions for performing unsigned comparisons as well.

General Form Example Meaning Comment

slt <dreg>,<s1reg>,<s2reg> slt $t2,$t3,$t4 if($t3<$t4) $t2 = 1; Compare less
else $t2 = 0; than (R)
sltu <dreg>,<s1reg>,<s2reg> sltu $t2,$t3,$t4 if($t3<$t4) $t2 = 1; Compare less
else $t2 = 0; than unsigned (R)
slti <dreg>,<s1reg>,<const> slti $t2,$t3,100 if($t3<100) $t2 = 1; Compare less
else $t2 = 0; than constant (I)
sltiu <dreg>,<s1reg>,<const> sltiu $t2,$t3,100 if($t3<100) $t2 = 1; Compare less than
else $t2 = 0; constant unsigned (I)
TRANSLATING AN IF STATEMENT
• Consider the following source code:
if(a > b)
c = a;

• Translate into MIPS instructions assuming the values of a, b, and c are associated with
the registers $t2, $t3, and $t4 respectively. Assume $t5 is available.

slt $t5,$t3,$t2 # b < a

beq $t5,$zero,L1 # if($t5==0)goto L1
or $t4,$t2,$zero # c = a
L1:
TRANSLATING AN IF-THEN-ELSE STATEMENT
• Consider the following source code:

if(a < b)
c = a;
else
c = b;
• Translate into MIPS instructions assuming the values of a, b, and c are associated with
the registers $t2, $t3, and $t4 respectively. Assume $t5 is available.

slt $t5,$t2,$t3 # a < b

beq $t5,$zero,L1 # if($t5==0)goto L1
move $t4,$t2 # c = a
j L2 # goto L2
L1:move $t4, $t3 # c = b
L2: