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ITLB,Branch Prediction and Hyperthreading

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17 views

ITLB,Branch Prediction and Hyperthreading

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munchingsilver7
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© © All Rights Reserved
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Subject: Microprocessor Semester: IV

Instruction Transaction Look Aside Buffer and Branch Prediction:

The IA-32 Instruction TLB and front-end BTB, shown at the top of Figure 2, steer the front end when
the machine misses the Trace Cache. The ITLB translates the linear instruction pointer addresses given
to it into physical addresses needed to access the L2 cache. The ITLB also
performs page-level protection checking.

There are two main types of branch prediction:


• static prediction
• dynamic prediction.
Static branch prediction is simple, and relies on the assumption that the majority of backwards pointing
branches occur in the context of repetitive loops, where a branch instruction is used to determine
whether or not to repeat the loop again. Most of the time a loop's conditional will evaluate to "taken,"
thereby instructing the machine to repeat the loop's code one more time. This being the case, static
branch prediction merely assumes that all backwards branches are “taken.”
For a branch that points forward to a block of code that comes later in the program, the static predictor
assumes that the branch is "not taken."

P4 uses both static and dynamic branch prediction techniques to prevent mis predicts and delays.
If a branch instruction does not have an entry in the BHT, both processors will use static prediction to
decide which path to take. If the instruction does have a BHT entry, dynamic prediction is used.
The P4's BHT is quite large; at 4K entries, it has enough space to store information on most of the
branches in an average program.
The PIII's branch predictor has a success rate of around 91%, and the P4 allegedly uses an even more
advanced algorithm to predict branches so it should perform even better. The P4 also uses a BTB to
store predicted branch targets. In most of Intel's literature and diagrams, the BTB and BHT are
combined under the label "the front-end BTB."

Hyper threading technology and its use in Pentium 4

Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as


HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve
parallelization of computations (doing multiple tasks at once) performed on x86 microprocessors.
CPU has many different units, or groups of transistors that work together to perform particular
functions. A CPU's execution units are those units that actually perform calculations on data and units
that move data around (to/from memory).
Unfortunately, it's very difficult to keep all of these execution units busy 100% of the time. Because of
the nature of most applications, your CPUs execution units enjoy a horribly low utilization rate -
generally around 35%. Reducing the number of execution units would cut down on costs however we've
ended up with these 7 - 9 execution unit CPUs because of the performance improvements having those
additional units give us in the rare occasion that they are in use.

Prof.Ramya.R.B Dept.of Computer Engineering


Subject: Microprocessor Semester: IV

One of the biggest reasons that around 65% of your CPU's execution resources remain idle is because of
the fact that the CPU can only execute one thread of instructions at a time. Think of a thread as a
collection of instructions related to a single program, for example running spell check in Word would
send a thread of instructions to the CPU to begin checking your document for spelling errors. It turns out
that the instructions within a particular thread mostly use the same execution units over and over again,
leaving the remaining units idle. The idea behind Hyper-Threading is to send multiple threads to the
CPU with the hopes that the idle execution units will be used by different threads. Intel claims that with
HT enabled the utilization of the Pentium 4's execution units can jump to around 50%, not a bad
improvement for such a small modification to the core.

Prof.Ramya.R.B Dept.of Computer Engineering

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