VISVESVARAYATECHNOLOGICAL UNIVERSITY

JNANASANGAMA, BELAGAVI-590018, KARNATAKA

Report on

VLSI Design Workshop using Synopsys Tool

Submitted in partial fulfillment of the requirements for the VII semester
Advanced VLSI [21EC71]
of
Bachelor of Engineering
in
Electronics and Communication Engineering

by

CHETHANA S (1CD21EC038)

Under the Guidance

of Dr. Priya Singh
Assistant Professor
Department of Electronics and Communication Engineering

Department of Electronics and Communication Engineering

CAMBRIDGE INSTITUTE OFTECHNOLOGY, BANGALORE - 560
036 2024-2025
CAMBRIDGE INSTITUTE OF TECHNOLOGY
K.R. Puram, Bangalore-560 036
Table of Contents
1. Introduction
2. Physical Design
3. Design flow using Synopsys tool for physical design
4. What we learned about these tools.
5. Conclusion

1) Introduction
The workshop introduced participants to the essentials of physical design in VLSI, emphasizing key
stages like floorplanning, placement, and routing with Synopsys tools. By navigating the design flow,
they learned to turn logical designs into physical layouts, developing hands-on skills in layout
management and timing verification. This practical experience was invaluable for understanding the
details of physical design and provided a solid foundation for further study in VLSI design.

2) Physical Design
In VLSI design, physical design is a vital phase that involves converting a logical circuit description
into a manufacturable physical layout. This stage includes arranging cell placement, optimizing signal
timing paths, and ensuring compliance with design constraints. Advanced tools and precise methods are
required to transform synthesized netlists into a fabrication-ready layout. The process requires precision
and advanced tools to transform synthesized netlists into a layout ready for fabrication.

3) Design Flow Using Synopsys Tool for Physical Design

The workshop provided hands-on experience with Synopsys tools, following a structured design flow:

I. Floorplanning: This step involved determining the arrangement and size of the
different functional blocks within the chip, considering performance and area
constraints.
II. Placement:
 Global Placement: In this phase, components were roughly positioned based on the
floorplan, ensuring a high-level fit within the design area.
 Detailed Placement: Further refinement of component positions to minimize signal delay
and meet timing requirements.

III. Routing: This stage connected the placed cells with wires, ensuring signal paths met timing
constraints and avoided congestion. Global routing established rough paths, while detailed
routing finalized wire routes with exact geometries.

Design Flow Overview

The workshop outlined the following main stages in the VLSI design flow:

 Simulation: Initial RTL verification to ensure functional correctness.

 Synthesis: Conversion of RTLinto a gate-level netlist.
 Physical Design: Involves floorplanning, placement, and routing to transform the netlist into
a physical layout.

4) What we learnt about these tools

I. Logic Synthesis: Logic synthesis is the process of converting a high-level description of circuit
behavior, typically in a hardware description language (HDL) such as Verilog, into a gate-level
representation. Using tools like Synopsys' Design Compiler, logic synthesis transforms HDL
into a netlist that details the logical components and connections of the design.
II. Netlist Conversion and GDSII: The netlist, representing the design's logical structure, is
ultimately converted into GDSII format (Graphic Data System II), which is a standard format
for physical design data used in IC fabrication. The IC Compiler software plays a crucial role in
this conversion, enabling the mapping of logic to physical layout, especially at the 32nm
technology node (SAED32_EDK).
III. Technology Specifications and Models:
 RVT and LVT: RVT (Regular Voltage Threshold) and LVT (Low Voltage Threshold)
are different transistor threshold voltage options that offer trade-offs between power and
performance.
 Non-Linear Delay Model (NLDM): This model describes the delay of gates under
varying load and transition conditions, essential for accurate timing analysis.
IV. Essential Files for Design Compilation:To facilitate synthesis, several key files are required:
 Technology File: Provides detailed information on the manufacturing process
technology.
 Top-Level Verilog Code (.v or .sdc): Describes the design functionality.
 Netlist File: Generated after synthesis, showing the interconnections between logic
gates.
 Standard Parasitic Exchange Format (SPEF): Contains parasitic data, crucial for
timing analysis.
V. Design and Timing Constraints:
 Slack and Timing Violations: Slack indicates the difference between required and
actual arrival times for a signal, where negative slack highlights timing violations.
 Setup Time and Violation Paths: Setup time is the minimum time before a clock edge
that data should be stable, and violations indicate timing issues that must be addressed to
meet design criteria.
VI. RTL and Circuit Simulation: The workshop included a practical session on simulating a First- In-
First-Out (FIFO) buffer circuit. Using a pre-written RTL file, participants loaded the design in
a Linux command terminal, illustrating the synthesis and simulation flow from code to
functional verification.
VII. Physical Design and Placement:
 Global and Detailed Placement: Placement assigns cells to physical locations on the
chip, initially positioning them roughly (global placement) and then refining their
positions (detailed placement).
 Milkyway Reference and .TCL Scripting: The Milkyway reference database aids in
layout data management, and .tcl scripts automate steps within the design environment.
VIII. Design Checks and Verification:
 Logic Equivalence Check (LEC): Ensures that the synthesized netlist matches the
functional intent of the RTL.
 Layout vs. Schematic (LVS) and Design Rule Check (DRC): LVS checks for
consistency between the layout and schematic, while DRC verifies adherence to
manufacturing constraints.
5) Conclusion
Participants gained a thorough introduction to physical design in VLSI, with a focus on floor
planning, placement, and routing using Synopsys tools. By working through the design flow,
they learned to convert logical designs into physical layouts, developing practical skills in layout
management and timing verification. This hands-on experience was crucial for understanding
the nuances of physical design and set the stage for deeper exploration in VLSI design.