Data Types

System Verilog introduces new data types with the following

benefits.
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays: reduced memory
usage, built-in support for searching and sorting
• Classes and structures: support for abstract data structures
• Unions and packed structures: allow multiple views of the
same data
• Strings: built-in string support
• Enumerated types: code is easier to write and understand.
Built-In Data Types
Two basic data types: variables and nets, both which hold
4-state values: 0, I, Z and X.
• RTL code uses variables to store combinational and sequential values.
• Variables can be unsigned single or multi-bit (reg [7: 0] m),
signed 32-bit variables (integer)
unsigned 64-bit variables (time)
floating point numbers (real)
• Variables can be grouped together into arrays that have a fixed size.
• All storage is static, meaning that all variables are alive for the entire
simulation
• A net is used to connect parts of a design such as gate primitives
and module instances.

• Nets come in many flavors, but most designers use scalar and
vector wires to connect together the ports of design blocks.

• System Verilog adds many new data types to help both hardware
designers and verification engineers.
The Logic Type
A logic signal can be used anywhere a net is used, except
that a logic variable cannot be driven by multiple structural
drivers, such as when you are modeling a bidirectional bus.

In this case, the variable needs to be a net-type such as wire

so that System Verilog can resolve the multiple values to
determine the final value.
State Data Types
System Verilog introduces several 2-state data types to improve
simulator performance and reduce memory usage, compared with
variables declared as 4-state types.

The simplest type is the bit , which is always unsigned.

There are four signed 2-state types: byte, shortint, int, and longint
Fixed-Size Arrays
Declaring and Initializing Fixed-Size Arrays
Verilog requires that the low and high array limits must be given in the
declaration.
Since almost all arrays use a low index of 0, System Verilog lets you use the
shortcut of just giving the array size, which is similar to C's style.
The Array Literal
How to initialize an array using an array literal, which is an apostrophe followed by the
values in curly braces.

You can set some or all elements at once.

You are able to replicate values by putting a count before the curly braces.
Lastly, you might specify a default value for any element that does not have an explicit
value.
Basic Array Operations - for and for each
The most common way to manipulate an array is with a for- or for
each-Ioop. In Sample 2.8, the variable i is declared local to the for-
loop.

• The System Verilog function $size returns the size of the array.

• In the for each-Ioop, you specify the array name and an index in
square brackets, and System Verilog automatically steps through all
the elements of the array.

• The index variable is automatically declared for you and is local to

the loop.
Basic Array Operations - Copy and Compare

You can perform aggregate

compare and copy of arrays
without loops.

(An aggregate operation

works on the entire array as
opposed to working on just
an individual element)

Comparisons are limited to

just equality and inequality.
Bit and Array Subscripts, Together at Last
A common annoyance in verilog-1995 is that you cannot use array and bit
subscripts together, verilog-2001 removes this restriction for fixed-size arrays,
prints the first array element (binary 101), its lowest bit (1), and the next two
higher bits (binary 10).
Packed Arrays
The packed bit and array dimensions are specified as part of the type, before
the variable name. These dimensions must be specified in the [msb : lsb]
format, not[size] Sample shows the variable bytes, a packed array of four bytes
that are stored in a single 32-bit word as shown in Figure 2-2.
You can mix packed and unpacked dimensions. You may want to
make an array that represents a memory that can be accessed as bits,
bytes, or long words.
Dynamic Arrays
• A dynamic array is declared with empty word subscripts [ ].

• This means that you do not specify the array size at compile
time; instead, you give it at run-time.

• The array is initially empty, and so you must call the new [ ]
constructor to allocate space, passing in the number of entries
in the square brackets.

• If you pass the name of an array to the new [ ] constructor, the

values are copied into the new elements, as shown in Sample.
Queues
SystemVerilog introduces a new data type, the queue, which
combines the best of an linked list and array.

Like a linked list, you can add or remove elements anywhere in a

queue, without the performance hit of a dynamic array that has to
allocate a new array and copy the entire contents.

Like an array, you can directly access any element with an index,
without linked list's overhead of stepping through the preceding
elements.
A queue is declared with word subscripts containing a dollar
sign: [$].

The elements of a queue are numbered from 0 to $.

Sample shows how you can add and remove values from a
queue using methods.

Note that queue literals only have curly braces, and are
missing the initial apostrophe of array literals.
The System Verilog queue is similar to the Standard Template
Library's deque data type.

You create a queue by adding elements. SystemVerilog typically

allocates extra space so that you can quickly insert additional
elements.
If you add enough elements that the queue runs out of that extra
space, System Verilog automatically allocates more.

As a result, you can grow and shrink a queue without the

performance penalty of a dynamic array, and SystemVerilog keeps
track of the free space for you.
Note that you never call the new [ ] constructor for a queue.
You can use word subscripts and concatenation instead of methods.
As a shortcut, if you put a $ on the left side of a range, such as [$: 2]
, the $ stands for the minimum value, [0: 2] , A $ on the right side,
as in [1: $], stands for the maximum value, [1: 2] , in first line of the
initial block of Sample 2.20.
• The queue elements are stored in contiguous locations, and so it
is efficient to push and pop elements from the front and back.

• This takes a fixed amount of time no matter how large the queue.

• Adding and deleting elements in the middle of a queue requires

shifting the existing data to make room.

• The time to do this grows linearly with the size of the queue.

• You can copy the contents ofa fixed or dynamic array into a
queue.
Associative Arrays
• SystemVerilog offers associative arrays that store entries in a
sparse matrix.

• This means that while you can address a very large address
space, SystemVerilog only allocates memory for an element
when you write to it.

• In the following picture, the associative array holds the values

0:3, 42, 1,000, 4,521, and 200,000.

• The memory used to store these is far less than would be

needed to store a fixed or dynamic array with 200,000 entries.
An associative array can be stored by the simulator as a tree or
hash table. This additional overhead is acceptable when you
need to store arrays with widely separated index values, such as
packets indexed with 32-bit addresses or 64-bit data values.
Array Methods
There are many array methods that you can use on any
unpacked array types:

fixed, dynamic, queue, and associative.

These routines can be as simple as giving the current array

size or as complex as sorting the elements. The parentheses
are optional if there are no arguments.
In a with clause, the name item is called the iterator argument and
represents a single element of the array.
Sample 2.28 shows various ways to total up a subset of the values in the
array. The first total compares the item with 7. This relational returns a 1
(true) or 0 (false) and multiplies this with the array. So the sum of
{9,0,8,0,0,0} is 17. The second total is computed using the? : conditional
operator.
Array Sorting and Ordering
SystemVerilog has several methods for changing the order of elements in an
array. You can sort the elements, reverse their order or shuffle the order as
shown
Building a Scoreboard with Array Locator Methods
The array locator methods can be used to build a scoreboard. Sample 2.31 defines the
Packet structure, then creates a scoreboard made from a queue of these structures.
Choosing a Storage Type

Here are some guidelines for choosing the right storage type based on

 flexibility,

 memory usage,

 speed, and sorting.

These are just rules of thumb, and results may vary between
simulators.
Flexibility
• Use a fixed-size or dynamic array if it is accessed with consecutive
positive integer indices: 0, 1, 2, 3…

• Choose a fixed-size array if the array size is known at compile time

•
• choose a dynamic array if the size is not known until run-time.

• If you are writing routines to manipulate arrays, consider using just

dynamic arrays, as one routine will works for any size dynamic array as
long as the element type (int, string, etc.) matches.
• Associative arrays can also be passed regardless of size.

• Associative arrays can also be used to model content-addressable

memories.

• Queues are a good way to store data where the number of

elements grows and shrinks a lot during simulation, such as a
scoreboard that holds expected values. Lastly, queues are great
for searching and sorting.
Memory usage
• If you want to reduce the simulation memory usage, use two- state
elements.
• You should choose data sizes that are multiples of 32 bits to avoid wasted
space.
• For arrays that hold up to a thousand elements, the type of array that you
choose does not make a big difference in memory usage
• Queues are slightly less efficient to access than fixed-size or dynamic arrays
because of additional pointers.
• Modeling memories larger than a few megabytes should be done with an
associative array.
• Note that each element in an associative array can take several times more
memory than a fixed-size or dynamic memory because of pointer overhead
Speed
• Choose your array type based on how many times it is accessed per clock
cycle.

• For only a few reads and writes, you could use any type, as the overhead is
minor compared with the DUT.

• Fixed-size and dynamic arrays are stored in contiguous memory, so any

element can be found in the same amount of time, regardless of array size.
• If you need to insert new elements into a large queue, your test bench
may slow down, so consider changing how you store new elements.

• When reading and writing associative arrays, the simulator must search
for the element in memory.

• Popular ways are hash tables and trees, these requires more computation
than other arrays, and therefore associative arrays are the slowest.
Sorting
• System Verilog can sort any single-dimension array (fixed- size, dynamic, and
associative arrays plus queues), you should pick based on how often the data
is added to the array.

• If the data is received all at once, choose a fixed-size or dynamic array so

that you only have to allocate the array once.

• If the data slowly dribbles in, choose a queue, as adding new elements to the
head or tail is very efficient.

• Using the routines first, next, and prev, you can search an associative array
for a value and find successive values.
Choosing the best data structure
Here are some suggestions on choosing a data structure

• Network packets.
Properties: fixed size, accessed sequentially.
Use a fixed-size or dynamic array for fixed- or variable-size packets.

• Scoreboard of expected values.

Properties: Sizes are not known until run time, accessed by value, and
a constantly changing size.
Use queue, since continually adding and deleting elements during
simulation.
• Sorted structures. Use a queue if the data comes out in a predictable
order or an associative array if the order is unspecified.

• Modelling very large memories, greater than a million entries. If you do

not need every location, use an associative array as a sparse memory.

• Command names and values from a file.

Property: lookup by string, Read the strings from the file, and then look
up the commands in an associative array using the command as a string
index
Creating New Types with typedef
You can create new types using the typedef statement.
Creating User-Defined Structures
• In SystemVerilog you can create a structure using the struct
statement, similar to what is available in C.

• But a struct is a degenerate class, so use a class instead, A typedef

just groups data fields together. Without the code that manipulates
the data, you are only creating half of the solution.

• There are several places where a typedef is useful: creating simple

user defined types, unions, and enumerated types and virtual
interfaces.
Creating a struct and a new type
You can combine several variables into a structure.
Example : creates a structure called pixel that has three unsigned bytes for red, green, and blue.
Making a union of several types
In hardware, the interpretation of a set of bits in a register may depend
on the value of other bits.

Use the suffix “_u” when declaring a union

Unions are useful when you frequently need to read and write a
register in several different formats.
Type Conversion
• The proliferation of data types in Systemverilog means that you
will need to convert between them.

• If the layout of the bits between the source and destination

variables are the same, such as an integer and enumerated type,
cast between the two values.

• If the bit layouts differ, such as an array of bytes and words, use
the streaming operators to rearrange the bits.
The Static Cast
The static cast operation converts between two types with no
checking of values.
You specify the destination type, an apostrophe, and the
expression to be converted as shown
The Dynamic Cast

The dynamic cast, $cast, allows you to check for out-of-bounds values.

Streaming Operators :
• When used on the right side of an assignment, the streaming
operators « and» take an expression, structure, or array, and packs
it into a stream of bits.

• The » operator streams data from left to right while « streams

from right to left, as shown in Sample
Enumerated Types
An enumeration creates a strong variable type that is limited to a
set of specified names, such as the instruction opcodes or state
machine values.

For example, the names ADD, MOVE, or ROTW make your code
easier to write and maintain than if you had used literals such as
8'h01 or macros.

Another alternative for defining constants is a parameter.

These are fine for individual values, but an enumerated type

automatically gives a unique value to every name in the list.
The simplest enumerated type declaration contains a list of constant names
and one or more variables as shown in Sample 2.45.

This creates an anonymous enumerated type, but it cannot be used for any
other variables than the ones in this declaration.

Sample :A simple enumerated type

enum {RED, BLUE, GREEN} color;

In general you want to create a named enumerated type to easily declare

multiple variables, especially if these are used as routine arguments or
module ports.

You first create the enumerated type, and then the variables of this type.
Constants
• There are several types of constants in System verilog.
•
• The classic verilog way to create a constant is with a text macro.

• On the plus side, macros have global scope and can be used for bit
field definitions and type definitions.

• On the negative side, macros are global, so that they can cause
conflicts if you just need a local constant.

• Lastly, a macro requires the - character so that it is recognized and

expanded by the compiler.
System verilog also supports the const modifier that allows you
to make a variable that can be initialized in the declaration but
not written by procedural code.

Sample 2.52 Declaring a const variable

initial begin
const byte colon = “ : ” ;
…
end

The value of colon is initialized when the initial block is entered.

Strings
• If you have ever tried to use a verilog reg variable to hold a string of
characters, your suffering is over.

• The System Verilog string type holds variable-length strings.

• An individual character is of type byte.

• The elements of a string of length N are numbered 0 to N-1.

• Note that, unlike C, there is no null character at the end of a string, and
any attempt to use the character "\0" is ignored.

• Memory for strings is dynamically allocated, so you do not have to

worry about running out of space to store the string.
Sample 2.53 shows various string operations.

The function getc(N) returns the byte at location N, while toupper

returns an upper-case copy of the string and tolower returns a
lowercase copy.

The curly braces { } are used for concatenation.

The task putc(M, C) writes a byte c into a string at location M, which

must be between 0 and the length as given by len.

The substr(start, end) function extracts characters from location

start to end.
Expression Width
• A prime source for unexpected behavior in Verilog has been the width of
expressions.

• Sample 2.54 adds 1 + 1 using four different styles.

• Addition A uses two 1-bit variables, and so with this precision 1 + 1 =0.

• Addition Buses 8-bit precision because there is an 8-bit variable on the left
side of the assignment. In this case, 1 + 1 =2.

• Addition C uses a dummy constant to force System Veri log to use 2-bit
precision.
• Lastly, in addition D, the first value is cast to be a 2-bit value with the cast
operator, and so 1 + 1 =2.
There are several tricks you can use to avoid this problem.

First, avoid situations where the overflow is lost, as in addition A.

Use a temporary, such as b8, with the desired width, Or, you can
add another value to force the minimum precision, such as 2' b0.

Lastly, in SystemVerilog, you can cast one of the variables to the

desired precision.