Q-1) With a neat diagram, explain the basic operation concept of

computer

The basic operation concept of a computer is based on the input-process-output

cycle. This cycle involves three key stages:

1. Input: Data is entered into the computer via input devices (keyboard,
mouse, etc.).
2. Process: The central processing unit (CPU) processes the input data based
on instructions from software.
3. Output: The processed data is then presented to the user through output
devices (monitor, printer, etc.).
Q-2 ) What is performance measurement? Explain the basic performance
equation.

Performance Measurement

Performance measurement in computing refers to the process of evaluating the

efficiency of a system, typically in terms of how well it performs tasks or
operations. This involves assessing the system's speed, capacity, and reliability
when executing different types of workloads. Key factors often measured
include:

● Execution time: How long it takes to complete a task.

● Throughput: The amount of work done in a given time frame (e.g.,
transactions per second).
● Response time: How quickly a system responds to a request.
● Efficiency: How well resources like CPU and memory are utilized.
Q-3) Explain BIG-Endian and LITTLE-Endian methods of byte addressing
with proper examples.

The terms Big Endian and Little Endian refer to how multi-byte data (e.g.,
integers) is stored in memory. Computers can represent numbers in multiple
bytes, and the ordering of these bytes determines the system's endianness.
Q-4) Explain basic instruction types with examples.

Basic Instruction Types

Instructions are commands given to a computer to perform specific

operations. These are executed by the CPU as part of the
Fetch-Decode-Execute cycle.

1. Data Transfer Instructions

These instructions transfer data between different parts of the computer

system without altering the data.

● Examples:
○ MOV (Move data between registers or memory).
○ LOAD (Load data from memory to a register).
○ STORE (Store data from a register to memory).
● Example for C ← A + B:
○ LOAD R1, A (Load value of A into register R1).
○ LOAD R2, B (Load value of B into register R2).

2. Arithmetic Instructions

These instructions perform arithmetic operations like addition, subtraction,

multiplication, and division.

● Examples:
○ ADD (Add two operands).
○ SUB (Subtract one operand from another).
○ MUL (Multiply two operands).
● Example for C ← A + B:
○ ADD R3, R1, R2 (Add values in R1 and R2, store the result in R3).
3. Logical Instructions

These instructions perform logical operations like AND, OR, XOR, and NOT.

● Examples:
○ AND (Logical AND).
○ OR (Logical OR).
○ NOT (Logical NOT).
● Usage in a Context: Logical instructions could be used to validate or
set flags before performing C ← A + B.

4. Control Flow Instructions

These instructions control the sequence of execution in a program. They

include branching, looping, and subroutine calls.

● Examples:
○ JMP (Jump to a specific instruction).
○ BEQ (Branch if equal).
○ CALL (Call a subroutine).
● Example for C ← A + B:
○ If a branch condition is required:
■ BEQ LABEL (Branch to LABEL if a condition is met).

5. Input/Output Instructions

These instructions are used to transfer data between the processor and I/O
devices.

● Examples:
○ IN (Input data from an I/O device).
○ OUT (Output data to an I/O device).
● Usage in Context: The result C can be stored in memory or sent to an
output device.
Q-5) Explain instruction execution straight-line sequencing and
Branching sequencing.

Instruction Execution

Instruction execution is the process by which the CPU fetches, decodes,

and executes an instruction. The execution of an instruction follows a
series of steps, commonly known as the Fetch-Decode-Execute cycle,
which is the fundamental process in every computer system.

Here’s how instruction execution typically works:

1. Fetch:
○ The Program Counter (PC) holds the memory address of the
next instruction to be executed.
○ The CPU fetches the instruction from the memory location
specified by the PC.
○ The fetched instruction is stored in the Instruction Register
(IR).
2. Decode:
○ The instruction in the IR is decoded to determine what
operation needs to be performed.
○ The Control Unit (CU) decodes the opcode (operation code) to
identify the type of instruction (e.g., arithmetic, logical, data
transfer).
○ The operands (if any) are extracted from the instruction.
3. Execute:
○ The CPU performs the operation specified by the decoded
instruction (e.g., arithmetic operation, data transfer).
○ If the instruction requires the use of registers or memory, the
CPU accesses those resources.
○ Once the execution is complete, the result is either stored in a
register or written back to memory.
4. Update PC:
○ The Program Counter (PC) is updated to point to the next
instruction to be fetched.
○ This may be incremented by the length of the current
instruction (often 1 word or byte).

This cycle continues for each instruction in the program, repeating as long
as there are instructions to execute.

Straight-Line Sequencing

Straight-line sequencing refers to a scenario where instructions are

executed sequentially without any deviation or branching. In this case,
the Program Counter simply increments after each instruction to fetch the
next one.

● Flow of Control: The program executes instructions one after

another, in the order they are stored in memory.

Branching sequencing allows the program’s execution to jump to different

locations depending on certain conditions. This is usually done with
branch instructions or conditional jumps, where the Program Counter is
changed to a different address based on specific conditions or results of
operations.

Types of Branch Instructions:

1. Unconditional Branch: The program always jumps to the specified

memory address.
○ Example: JUMP 500 (jump to address 500).
2. Conditional Branch: The program jumps to the specified address
only if a certain condition is met (e.g., a comparison result is true).
○ Examples:
■ BEQ label: If the equality flag is set (meaning values
compared are equal), jump to label.
■ BNE label: If the values are not equal, jump to label.
■ BLT label: If the first value is less than the second, jump
to label.

Q-6) Define addressing mode, and explain the

following addressing with an example.

a. Index addressing mode

b. Indirect addressing mode

c. Relative addressing mode

Addressing Mode

Addressing mode refers to the way in which the operand (data) for an
instruction is specified. It determines how the address of the operand is
calculated and accessed. Addressing modes allow flexibility in programming by
enabling different ways to reference data.

a. Index Addressing Mode

In Index Addressing Mode, the effective address of the operand is calculated by

adding a constant value (known as the index or offset) to the contents of a
register (called the index register).

● Formula:
Effective Address = Base Address + (Index Register)
● Example: Suppose we have an array stored in memory and we want to
access its elements using an index:
Q-8) What is DMA? Explain the use of a DMA controller in a computer
system, with a neat diagram.

Direct Memory Access (DMA)

Direct Memory Access (DMA) is a technique used in computer systems to allow

peripherals (such as hard drives, sound cards, or network adapters) to directly
transfer data to or from memory without involving the CPU. This enables faster
data transfer and reduces the CPU's workload, allowing it to perform other tasks
while data is being transferred.
DMA Controller

The DMA controller is a hardware component that manages the direct data
transfer between peripherals and memory. It acts as an intermediary between
the system’s memory and I/O devices, taking over control of the data bus to
transfer data without requiring CPU involvement. The DMA controller uses
system buses (address bus, data bus, and control bus) to facilitate this transfer.

Q-9) What is an interrupt? With example illustrates the concept of

interrupts and handling multiple device interrupts.

Interrupts

An interrupt is a mechanism that allows a computer's processor to stop its

current execution and temporarily divert its attention to a different task. This is
typically done in response to an event, such as input from a keyboard or mouse,
or a hardware failure. Once the interrupt has been handled, the processor can
resume its previous task.

Example of Interrupts

Consider the scenario where you are typing on a keyboard and running a
program that’s calculating something. The keyboard can generate interrupts to
signal that a key has been pressed. The CPU will stop its current work, read the
keypress (interrupt handling), and then continue the calculation.

Example of a Keyboard Interrupt:

1. The CPU is executing a program (say, adding numbers).

2. The user presses a key on the keyboard.
3. The keyboard generates an interrupt, sending an interrupt request to the
CPU.
4. The CPU stops its current work and jumps to the interrupt service routine
(ISR) for handling the keyboard input.
5. The ISR processes the keypress (e.g., stores it in a buffer).
6. After processing the interrupt, the CPU returns to the addition operation it
was performing.

Example of Handling Multiple Device Interrupts

Imagine a system with two devices:

● Device 1: A keyboard (low priority interrupt).

● Device 2: A timer (high priority interrupt).

Sequence of Events:

1. The CPU is executing a program.

2. Device 2 (Timer) sends a high-priority interrupt (e.g., every 1 millisecond).
3. The CPU acknowledges the interrupt, stops the program, and jumps to the
Timer ISR to handle the event (e.g., update a clock or perform time-based
actions).
4. While the CPU is processing the Timer ISR, Device 1 (Keyboard) generates
a low-priority interrupt (a key is pressed).
5. The CPU finishes the Timer ISR, and since the keyboard interrupt has
lower priority, it processes the keyboard interrupt next, jumping to the
Keyboard ISR.
6. After both interrupts are handled, the CPU resumes the program it was
executing.

Q-10 ) Explain the mapping function. Write a note on Direct Mapping,

Associative mapping, and Set-associative mapping.

A Mapping function is used to decide where data should be stored in the cache
memory. Cache memory is much faster than main memory, but it is smaller in
size, so only a portion of the data from main memory is stored in the cache. The
mapping function determines how the data from the main memory is
transferred to the cache and how it is retrieved.

When a CPU accesses data, the mapping function decides the location of the
data in the cache based on the address of the data in the main memory. The
objective of the mapping function is to efficiently utilize cache space and
improve data access speed.

1. Direct Mapping

In Direct Mapping, each block of main memory is mapped to exactly one cache
line. The mapping function uses the memory address to determine which cache
line a specific memory block will go into.

Structure of Direct Mapping:

● Memory Block: The block of data in the main memory.

● Cache Line: A unit of cache storage.
● Mapping: A specific memory block can only map to one cache line, and
this relationship is fixed.

2. Associative Mapping

In Associative Mapping, any block of memory can be placed in any cache line.
There is no fixed mapping between memory blocks and cache lines. When a
memory block is accessed, the cache is searched to check if it is already loaded
in any cache line.

How it Works:

● The memory address is divided into two parts:

○ Tag: Identifies the memory block.
○ Block offset: Specifies the location within the block.
● The Tag is compared with the tags stored in all cache lines, and if there is
a match, it is a cache hit. If no match is found, the data is fetched from
memory, and one of the cache lines is replaced.

3. Set-Associative Mapping

Set-Associative Mapping is a hybrid between direct mapping and associative

mapping. The cache is divided into multiple sets, and each set contains several
cache lines. A block of memory can be mapped to any line within a specific set,
not just a single cache line.

How it Works:

● The memory address is divided into three parts:

○ Tag: Identifies the memory block.
○ Set index: Specifies which set the block is mapped to.
○ Block offset: Specifies the location within the block.
● The Set index part of the address is used to select a set, and then the
cache lines within that set are searched to find a match. If no match is
found, the block is fetched from memory and placed in one of the lines
within the selected set.

Q-11) Explain single-Bus organization of data path inside a

processor with neat diagram

Execution Sequence in a Single-Bus Organization

In a single-bus organization, all components of the processor (registers, ALU,

memory) are connected via a single data bus. This architecture is simple and
cost-effective, but only one data transfer can occur at a time, making it
slower compared to multi-bus systems.
Q-12) Explain the complete set of operations involved in executing the instruction
Add (R3), R1 along with the control sequence

Executing the Instruction ADD (R3), R1

The instruction ADD (R3), R1 represents an add operation in assembly language

where the content of the memory address specified by R3 is added to the content
of R1 and the result is stored in R1. This instruction involves indirect addressing,
where the contents of R3 are used as a memory address pointing to the operand.

Assumptions:

● R1 is a register that holds one operand.

● R3 holds the memory address (pointer) of the second operand.
● M[Address] refers to memory at the given address.
● The instruction is executed in a simple 3-stage pipeline: Fetch, Decode,
Execute.