EE6580: VLSI DATA CONVERSION CIRCUITS

ASSIGNMENT 5
SUNDARAIAH GURINDAGUNTA
EE10M086

For all simulation I use ELDO LEVEL 3

1)
Clock evaluation

Program to generate the clocks as per given in question

.model notgate logic vhi=1.8 vlo=0 vth=0.9
.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9

vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)

INV#a 1 2 notgate
Delbuf1 2 3 0.1e-7
Delbuf2 1 l 4e-9
INV#b l lb notgate
and1 2 3 lc andgate
nor1 l 3 lr norgate

Following are clocks for both lathes

The differential input is evaluated as below

A)
First latch

The output is taken from the two terminals which is the

differential signal.In the graphs VPO is the
defferential output which is the difference between the
two outputs Program for first latch to find dynamic
offset in ELDO
*first latch without capacitance
.model notgate logic vhi=1.8 vlo=0 vth=0.9
.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9

.MODEL nmost NMOS level=3

.MODEL pmost PMOS level=3

vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)

INV#a 1 2 notgate
Delbuf1 2 3 0.1e-7
Delbuf2 1 l 4e-9
INV#b l lb notgate
and1 2 3 lc andgate
nor1 l 3 lr norgate

vinput input 0 pwl(0 -0.36 36e-6 0.36)

*vinput input 0 SIN 0 0.18 10K
vd1 vdd 0 dc 1.8
vd2 vcm 0 dc 0.9
E1 inp vcm input 0 0.5
E2 inm vcm input 0 -0.5

*Ylcp VSWITCH inp ip lc 0 //only used at initial stage

*Ylcm VSWITCH inm im lc 0
Mnp inp lc ip 0 nmost W=0.27u L=0.18u
*Mpp ip ln inp vdd pmost W=0.27u L=0.18u

Mnm inm lc im 0 nmost W=0.27u L=0.18u

*Mpm im ln inm vdd pmost W=0.27u L=0.18u

*Yl VSWITCH vdd out3 l 0

Ml out3 lb vdd vdd pmost W=0.27u L=0.18u
*Ylb VSWITCH out4 0 l 0
Mlb out4 l 0 0 nmost W=0.27u L=0.18u

M1 ip im out3 vdd pmost W=0.27u L=0.18u

M4 im ip out3 vdd pmost W=0.27u L=0.18u
M2 ip im out4 0 nmost W=0.27u L=0.18u
M3 im ip out4 0 nmost W=0.27u L=0.18u

*Ylr VSWITCH ip im lr 0
Mlr im lr ip 0 nmost W=0.27u L=0.18u

E3 opo 0 ip im 1
.plot v(1) v(2) v(3) v(lc) v(lr) v(l) v(lb) v(input)
v(inm) v(inp) v(ip) v(im) v(out3) v(out4) v(opo)
.tran 0.01p 36u
.end
The transient response of output which is combining the
differential signal using opamp adder.
In the figure the change from –ve to +ve(flip) occurs
at 18usec.At this time the input is 0v,since we know
that the input signal is varying from -0.36 to +0.36
with the slope 2mv/1clock cycle, where 1 clock
cycle=0.1usec hence the result
Result: zero(0) volts offset
Latch b

The output is taken from the two terminals which is the

differential signal.In the graphs VPO is the
defferential output which is the difference between the
two outputs

Program for second latch to find dynamic offset in ELDO

*second latch without capacitance

.model notgate logic vhi=1.8 vlo=0 vth=0.9
.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9
.MODEL nmost NMOS level=3
.MODEL pmost PMOS level=3

vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)

INV#a 1 2 notgate
Delbuf1 2 3 0.1e-7
Delbuf2 1 l 4e-9
INV#b l lb notgate
and1 2 3 lc andgate
nor1 l 3 lr norgate

vinput input 0 pwl(0 -0.36 36e-6 0.36)

*vinput input 0 SIN 0 0.18 10K
vd1 vdd 0 dc 1.8
vd2 vcm 0 dc 0.9
E1 ip vcm input 0 0.5
E2 im vcm input 0 -0.5

M1 inm inp vdd vdd pmost W=0.27u L=0.18u

M11 inm ip vdd vdd pmost W=0.27u L=0.18u
M4 inp inm vdd vdd pmost W=0.27u L=0.18u
M41 inp im vdd vdd pmost W=0.27u L=0.18u
M2 out1 out2 0 0 nmost W=0.27u L=0.18u
M3 out2 out1 0 0 nmost W=0.27u L=0.18u
M21 out1 lb 0 0 nmost W=0.27u L=0.18u
M31 out2 lb 0 0 nmost W=0.27u L=0.18u

M22 inm l out1 out1 nmost W=0.27u L=0.18u

M32 inp l out2 out2 nmost W=0.27u L=0.18u

E3 opo 0 inp inm 1

.plot v(1) v(2) v(3) v(lc) v(lr) v(l) v(lb) v(input)
v(inm) v(inp) v(ip) v(im) v(out1) v(out2) v(opo)
.tran 0.01p 36e-6
.end
In the figure the change from –ve to +ve(flip) occurs
at 18usec.At this time the input is 0v,since we know
that the input signal is varying from -0.36 to +0.36
with the slope 2mv/1clock cycle, where 1 clock
cycle=0.1usec hence the result
Result: zero(0) volts offset
B) Program for first latch to find dynamic offset in
ELDO with capacitor
*first latch with capacitance
.model notgate logic vhi=1.8 vlo=0 vth=0.9
.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9

.MODEL nmost NMOS level=3

.MODEL pmost PMOS level=3

vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)

INV#a 1 2 notgate
Delbuf1 2 3 0.1e-7
Delbuf2 1 l 4e-9
INV#b l lb notgate
and1 2 3 lc andgate
nor1 l 3 lr norgate

vinput input 0 pwl(0 -0.36 36e-6 0.36)

*vinput input 0 SIN 0 0.18 10K
vd1 vdd 0 dc 1.8
vd2 vcm 0 dc 0.9
E1 inp vcm input 0 0.5
E2 inm vcm input 0 -0.5
*Ylcp VSWITCH inp ip lc 0 //only used at initial stage
*Ylcm VSWITCH inm im lc 0
Mnp inp lc ip 0 nmost W=0.27u L=0.18u
*Mpp ip ln inp vdd pmost W=0.27u L=0.18u

Mnm inm lc im 0 nmost W=0.27u L=0.18u

*Mpm im ln inm vdd pmost W=0.27u L=0.18u

*Yl VSWITCH vdd out3 l 0

Ml out3 lb vdd vdd pmost W=0.27u L=0.18u
*Ylb VSWITCH out4 0 l 0
Mlb out4 l 0 0 nmost W=0.27u L=0.18u

M1 ip im out3 vdd pmost W=0.27u L=0.18u

M4 im ip out3 vdd pmost W=0.27u L=0.18u
M2 ip im out4 0 nmost W=0.27u L=0.18u
M3 im ip out4 0 nmost W=0.27u L=0.18u
C1 ip 0 0.5e-15

*Ylr VSWITCH ip im lr 0
Mlr im lr ip 0 nmost W=0.27u L=0.18u

E3 opo 0 ip im 1

.plot v(1) v(2) v(3) v(lc) v(lr) v(l) v(lb) v(input)

v(inm) v(inp) v(ip) v(im) v(out3) v(out4) v(opo)
.tran 0.01p 36u
.end

In the figure the change from –ve to +ve(flip) occurs

at 18.2usec. Since we know that the input signal is
varying from -0.36 to +0.36 with the slope 2mv/1clock
cycle, where 1 clock cycle=0.1usec,
hence the input at that flip=(18.2-18)e-6*2e-3/1e-7=4mv
Result: offset= 4mvolts

Program for second latch to find dynamic offset in ELDO

*second latch with capacitance

.model notgate logic vhi=1.8 vlo=0 vth=0.9
.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9

.MODEL nmost NMOS level=3

.MODEL pmost PMOS level=3

vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)

INV#a 1 2 notgate
Delbuf1 2 3 0.1e-7
Delbuf2 1 l 4e-9
INV#b l lb notgate
and1 2 3 lc andgate
nor1 l 3 lr norgate

vinput input 0 pwl(0 -0.36 36e-6 0.36)

*vinput input 0 SIN 0 0.18 10K
vd1 vdd 0 dc 1.8
vd2 vcm 0 dc 0.9
E1 ip vcm input 0 0.5
E2 im vcm input 0 -0.5

M1 inm inp vdd vdd pmost W=0.27u L=0.18u

M11 inm ip vdd vdd pmost W=0.27u L=0.18u
M4 inp inm vdd vdd pmost W=0.27u L=0.18u
M41 inp im vdd vdd pmost W=0.27u L=0.18u

M2 out1 out2 0 0 nmost W=0.27u L=0.18u

M3 out2 out1 0 0 nmost W=0.27u L=0.18u
M21 out1 lb 0 0 nmost W=0.27u L=0.18u
M31 out2 lb 0 0 nmost W=0.27u L=0.18u

M22 inm l out1 out1 nmost W=0.27u L=0.18u

M32 inp l out2 out2 nmost W=0.27u L=0.18u
C1 inm 0 0.5e-15
E3 opo 0 inp inm 1
.plot v(1) v(2) v(3) v(lc) v(lr) v(l) v(lb) v(input)
v(inm) v(inp) v(ip) v(im) v(out1) v(out2) v(opo)
.tran 0.01p 36e-6
.end
In the figure the change from –ve to +ve(flip) occurs
at 21.8usec. Since we know that the input signal is
varying from -0.36 to +0.36 with the slope 2mv/1clock
cycle, where 1 clock cycle=0.1usec,
hence the input at that flip=(21.8-18)e-6*2e-3/1e-
7=76mv
Result: offset= 76mvolts

Dynamic offset results due to:

Imbalanced CI and CF
Imbalanced load capacitance
Mismatch between differential pair transistors
And Clock routing
The increased offset in the second latch is due to the
large common mode jump in the outputs than in the first
latch. In the first latch the common mode jump is just
nearly Vcm which result in high CMRR,where as in the
second latch the jump almost double than the first
because Charge injection and clock feed through
introduce large CM jump in Vo+ and Vo-.,hence the
decrease in CMRR results in large offset.
And finally we conclude that the first latch is the
static latch in which the output connects to input in
some particular phase hence small CM jump,where as the
second latch is dynamic latch in which the input is
always connected to output in some manner(situation is
not same in all phases) results large CM jump hence the
large offset.
2)
a)Operation of Latch
on the +ve side(left side)
During overlap of L and La phase the coupling capacitor
cb tries to charged to Vrefp-Vcm(looking from input
side)(Vcm-Vrefp if we talk the gate of PMOS),finally at
the end L phase the voltage across capacitor is Vrefp-
Vcm. During Lc phase the input is coupled to the latch
through the coupling capacitor and the parasitic of
PMOS transistors gets charged to Vip+Vcm-Vrefp i.e.,
the falling edge of Lc is the sampling instant ,the
value at the gate at this instant will stored into the
MOS capacitances and the voltage at the gate PMOS is
constant during non-Lc phase. And during L phase again
the reference is restored into the capacitor as well
the regeneration takes place in the latch.
Similar arguments is applicable for the –ve side(right
side) and explained as follows, During overlap of L and
La phase the capacitor cb tries to charged to Vrefm-
Vcm(looking from input side)(Vcm-Vrefm if we talk the
gate of PMOS),finally at the end L phase the voltage
across capacitor is Vrefm-Vcm. During Lc phase the
input is coupled to the latch through the coupling
capacitor the parasitic of PMOS transistors gets
charged to Vim+Vcm-Vrefm i.e., the falling edge of Lc
is the sampling instant ,the value at the gate at this
instant will stored into the MOS capacitances and the
voltage at the gate PMOS is constant during non-Lc
phase. And during L phase again the reference is
restored into the capacitor as well the regeneration
takes place in the latch.
Therefore at the end Lc phase the voltage at gate of
left PMOS is Vip+Vcm-Vrefp and right side PMOS is
Vim+Vcm-Vrefm.In L phase the regeneration takes place
according to the values.The output is high when
Vip+Vcm-Vrefp is greater than Vim+Vcm-Vrefm, and the
output is low when Vim+Vcm-Vrefm is greater than
Vip+Vcm-Vrefp. In the Ld phase the ouput is taken out
from the latch.In the regeneration the La has to be
turned OFF first than L otherwise signal dependent
charge gets injected into capacitor hence change in
thresholds in simply La has to be turned OFF first to
prevent signal dependent charge injection.
b)
The capacitance seen from the input terminal is the
parallel combination of the parasitic capacitance
formed by the switch connecting Vref and the series of
Cb with parasitics formed with by the switch connecting
the Vcm in parallel with the parasitic capacitance of
PMOS transistors in Latch. The parasitic capacitances
PMOS includes Cgb,Cgs,Cgd,where as Cgd and Cgs are
overlap capacitance. Equivalently for the input looking
the series combination of Cp and Cb.
Therefore the equivalent capacitance=CpCb/(Cb+Cp)
c)
Typical values for MOS transistor in LEVEL 3 is given
below(data collected from
http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.2.ht
m)
NMOS PMOS
CCBD 2.06E-15 1.71E-14
CBS 4.45E-15 1.71E-14
CGSOV 1.80E-15 2.88E-15
CGDOV 1.80E-15 2.88E-15
CGBOV 2.00E-16 2.01E-16
CGS 0.00E+00 1.10E-14
CGD 0.00E+00 1.10E-14
CGB 3.88E-15
0.00E+00
Since the devices are chosen to be minimum size the
parasitcs are bound to be in the order of few tens of
femto Farads at the maximum.
Since the parasitics in the LEVEL 3 is in the order
femto farads, the Cp is in the several orders of femto
farads.
If Cb is too small then there is charge injection
problem and High thermal noise
If Cb is too large then It takes long time to charge
and as well the capacitance looking into input is large
and chance of large bottom plate capacitance.
So choose moderate value which gives the small charge
injection and thermal noise and small time constant.
Reasonable is 10-40 times of Cp.
Since the the parasitic capacitance is in the orders of
femto farads the reasonable value of Cb is 50fF.
d)
Clock generation

ELDO program for Clock generation

*[email protected]
.model notgate logic vhi=1.8 vlo=0 vth=0.9
.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9
*clock generation
vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)
INV#a 1 2 notgate
delbuf1 2 3 0.1e-7
and1 2 3 lcs andgate
delbuf2 1 ls 4e-9
delbuf3 ls l1 0.9e-7
andla ls l1 las andgate
delbuf4 ls l2 0.1e-7
andld las l2 lds andgate
INV#b ls lbs notgate

.plot v(1) v(2) v(3) v(lcs) v(ls) v(lbs) v(lds) v(las)

.tran 0.1p 36e-6
.end
Clocks
Ladder circuit
Selection of Rladder
In L phase the capacitor has to charge Vcm-Vref with
time constant of (Rladdereqv+Rextra)(Cb+Cextra) where
Rextra includes the resistance of switches and Cextra
includes the parasitic of switches as well.
Here Rladdereqv is the resistance looking from latch
into ladder and the worst Rladdereqv=4Rladder
Let those are small compared to Rladdereqv,then Rladder
can be choosen such that this time constant is several
times smaller than L phase time period.Where L phase
time period is 0.1microsec
∗ ≪ 0.1 − 6
Rladder=10kOhms
This Rladder must allow very little charge discharge
for every clock cycle.
Digital backend
Transition detector
1 to N code to Binary converter(Encoder)
Flash converter(converts Analog input to thermometer
code)
Simulation program for the Single comparator in ELDO
*[email protected]
.model notgate logic vhi=1.8 vlo=0 vth=0
.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9
*clock generation
vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)
INV#a 1 2 notgate
del1 2 3 0.1e-7
and1 2 3 lcs andgate
del2 1 ls 4e-9
del3 ls l1 0.9e-7
andla ls l1 las andgate
del4 ls l2 0.1e-7
andld las l2 lds andgate
INV#b ls lbs notgate

.MODEL nmost NMOS level=3

.MODEL pmost PMOS level=3

vinput input 0 pwl(0 -0.36 36e-6 0.36)

*vinput ims 0 SIN 0 0.18 10K
vd1 vdds 0 dc 1.8
vd2 vcms 0 dc 0.9
*E1 ips vcms input 0 0.5
*E2 ims vcms input 0 -0.5

E1 ips 0 input 0 0.5

E2 ims 0 input 0 -0.5

.connect vrefp 0
.connect gnds 0
.connect vrefm 0

.connect gnds 0
.connect vrefps 0
.connect vrefms 0

Ylc1p VSWITCH ips lcrefp lcs gnds

Ylc1m VSWITCH ims lcrefm lcs gnds

Ylp VSWITCH vrefps lcrefp ls gnds

Ylm VSWITCH vrefms lcrefm ls gnds

cb1 lcrefp lcmp 15f

cb2 lcrefm lcmm 15f

Ylap VSWITCH vcms lcmp las gnds

Ylam VSWITCH vcms lcmm las gnds
Ylc2p VSWITCH lcmp lcp lcs gnds
Ylc2m VSWITCH lcmm lcm lcs gnds

M1 dlc1 dlc2 vdds vdds pmost W=0.27u L=0.18u

Mlc1 dlc1 lcp vdds vdds pmost W=0.27u L=0.18u

M4 dlc2 dlc1 vdds vdds pmost W=0.27u L=0.18u

Mlc2 dlc2 lcm vdds vdds pmost W=0.27u L=0.18u

M2 dlb1 dlb2 gnds gnds nmost W=0.27u L=0.18u

Mlb1 dlb1 lbs gnds gnds nmost W=0.27u L=0.18u

M3 dlb2 dlb1 gnds gnds nmost W=0.27u L=0.18u

M31 dlb2 lbs gnds gnds nmost W=0.27u L=0.18u

Ml1 dlc1 ls dlb1 dlb1 nmost W=0.27u L=0.18u

M32 dlc2 ls dlb2 dlb2 nmost W=0.27u L=0.18u

Ylc1p1 VSWITCH dlc1 ldm lds gnds

Ylc1p2 VSWITCH dlc2 ldp lds gnds

INVld1 ldm oms notgate

INVld2 ldp ops notgate
Eopo outputs gnds oms ops 1
.plot v(1) v(2) v(3) v(lcs) v(lrs) v(ls) v(lbs) v(lds)
v(las) v(input) v(0) v(outputs) v(0) v(oms) v(ops)
.tran 0.1p 36e-6
.end

Simulation program for the flash ADC in ELDO

.model notgate logic vhi=1.8 vlo=0 vth=0.9

.model andgate logic vhi=1.8 vlo=0 vth=0.9
.model norgate logic vhi=1.8 vlo=0 vth=0.9
.model orgate logic vhi=1.8 vlo=0 vth=0.9
*clock generation
vl 1 0 pulse(0 1.8 1p 1p 1p 0.5e-7 1e-7)
INV#a 1 2 notgate
del1 2 3 0.1e-7
and1 2 3 lc andgate
del2 1 l 4e-9
del3 l l1 0.9e-7
andla l l1 la andgate
del4 l l2 0.1e-7
andld la l2 ld andgate
INV#b l lb notgate

.MODEL nmost NMOS level=3

.MODEL pmost PMOS level=3

*vinput input 0 pwl(0 -0.36 36e-6 0.36)

vinput input 0 SIN 0 3 10K
vd1 vdd 0 dc 1.8
vd2 vcm 0 dc 0.9
*E1 ip vcms input 0 0.5
*E2 ims vcms input 0 -0.5

E1 ip 0 input 0 0.5
E2 im 0 input 0 -0.5

Vref1 ref1 0 dc 1.65

Vref2 ref2 0 dc 0.15
Rladderp1 ref1 refp15 10k
Rladderp2 refp15 refp14 10k
Rladderp3 refp14 refp13 10k
Rladderp4 refp13 refp12 10k
Rladderp5 refp12 refp11 10k
Rladderp6 refp11 refp10 10k
Rladderp7 refp10 refp9 10k
Rladderp8 refp9 refp8 10k
Rladderp9 refp8 refp7 10k
Rladderp10 refp7 refp6 10k
Rladderp11 refp6 refp5 10k
Rladderp12 refp5 refp4 10k
Rladderp13 refp4 refp3 10k
Rladderp14 refp3 refp2 10k
Rladderp15 refp2 refp1 10k
Rladderp16 refp1 ref2 10k

Rladderm1 ref2 refm15 10k

Rladderm2 refm15 refm14 10k
Rladderm3 refm14 refm13 10k
Rladderm4 refm13 refm12 10k
Rladderm5 refm12 refm11 10k
Rladderm6 refm11 refm10 10k
Rladderm7 refm10 refm9 10k
Rladderm8 refm9 refm8 10k
Rladderm9 refm8 refm7 10k
Rladderm10 refm7 refm6 10k
Rladderm11 refm6 refm5 10k
Rladderm12 refm5 refm4 10k
Rladderm13 refm4 refm3 10k
Rladderm14 refm3 refm2 10k
Rladderm15 refm2 refm1 10k
Rladderm16 refm1 ref1 10k

*comparator subckt definition

.subckt fcomparator ips ims outputs vrefps vrefms vcms
ls lcs lbs lds las vdds gnds

Ylc1p VSWITCH ips lcrefp lcs gnds

Ylc1m VSWITCH ims lcrefm lcs gnds

Ylp VSWITCH vrefps lcrefp ls gnds

Ylm VSWITCH vrefms lcrefm ls gnds

c1 lcrefp lcmp 50f

c2 lcrefm lcmm 50f

Ylap VSWITCH vcms lcmp las gnds

Ylam VSWITCH vcms lcmm las gnds

Ylc2p VSWITCH lcmp lcp lcs gnds

Ylc2m VSWITCH lcmm lcm lcs gnds
M1 dlc1 dlc2 vdds vdds pmost W=0.27u L=0.18u
Mlc1 dlc1 lcp vdds vdds pmost W=0.27u L=0.18u

M4 dlc2 dlc1 vdds vdds pmost W=0.27u L=0.18u

Mlc2 dlc2 lcm vdds vdds pmost W=0.27u L=0.18u

M2 dlb1 dlb2 gnds gnds nmost W=0.27u L=0.18u

Mlb1 dlb1 lbs gnds gnds nmost W=0.27u L=0.18u

M3 dlb2 dlb1 gnds gnds nmost W=0.27u L=0.18u

M31 dlb2 lbs gnds gnds nmost W=0.27u L=0.18u

Ml1 dlc1 ls dlb1 dlb1 nmost W=0.27u L=0.18u

M32 dlc2 ls dlb2 dlb2 nmost W=0.27u L=0.18u

Ylc1p1 VSWITCH dlc1 ldm lds gnds

Ylc1p2 VSWITCH dlc2 ldp lds gnds

INVld1 ldm oms notgate

INVld2 ldp ops notgate

Eopo outputs gnds oms ops 1

.ends fcomparator
*COMPARATOR ARRAY

Xcomp1 ip im t1 vrefp1 vrefm1 vcm l lc lb ld la vdd 0

fcomparator
Xcomp2 ip im t2 vrefp2 vrefm2 vcm l lc lb ld la vdd 0
fcomparator
Xcomp3 ip im t3 vrefp3 vrefm3 vcm l lc lb ld la vdd 0
fcomparator
Xcomp4 ip im t4 vrefp4 vrefm4 vcm l lc lb ld la vdd 0
fcomparator
Xcomp5 ip im t5 vrefp5 vrefm5 vcm l lc lb ld la vdd 0
fcomparator
Xcomp6 ip im t6 vrefp6 vrefm6 vcm l lc lb ld la vdd 0
fcomparator
Xcomp7 ip im t7 vrefp7 vrefm7 vcm l lc lb ld la vdd 0
fcomparator
Xcomp8 ip im t8 vrefp8 vrefm8 vcm l lc lb ld la vdd 0
fcomparator
Xcomp9 ip im t9 vrefp9 vrefm9 vcm l lc lb ld la vdd 0
fcomparator
Xcomp10 ip im t10 vrefp10 vrefm10 vcm l lc lb ld la vdd
0 fcomparator
Xcomp11 ip im t11 vrefp11 vrefm11 vcm l lc lb ld la vdd
0 fcomparator
Xcomp12 ip im t12 vrefp12 vrefm12 vcm l lc lb ld la vdd
0 fcomparator
Xcomp13 ip im t13 vrefp13 vrefm13 vcm l lc lb ld la vdd
0 fcomparator
Xcomp14 ip im t14 vrefp14 vrefm14 vcm l lc lb ld la vdd
0 fcomparator
Xcomp15 ip im t15 vrefp15 vrefm15 vcm l lc lb ld la vdd
0 fcomparator
*THERMOMETER TO 1 TO N CODE

nott1 t1 tc1 notgate

nott2 t2 tc2 notgate
nott3 t3 tc3 notgate
nott4 t4 tc4 notgate
nott5 t5 tc5 notgate
nott6 t6 tc6 notgate
nott7 t7 tc7 notgate
nott8 t8 tc8 notgate
nott9 t9 tc9 notgate
nott10 t10 tc10 notgate
nott11 t11 tc11 notgate
nott12 t12 tc12 notgate
nott13 t13 tc13 notgate
nott14 t14 tc14 notgate
nott15 t15 tc15 notgate

andt1 vdd tc1 i1 andgate

andt2 t1 tc2 i2 andgate
andt3 t2 tc3 i3 andgate
andt4 t3 tc4 i4 andgate
andt5 t4 tc5 i5 andgate
andt6 t5 tc6 i6 andgate
andt7 t6 tc7 i7 andgate
andt8 t7 tc8 i8 andgate
andt9 t8 tc9 i9 andgate
andt10 t9 tc10 i10 andgate
andt11 t10 tc11 i11 andgate
andt12 t11 tc12 i12 andgate
andt13 t12 tc13 i13 andgate
andt14 t13 tc14 i14 andgate
andt15 t14 tc15 i15 andgate
andt16 t15 vdd i16 andgate

*ENCODER

or#1 i8 i9 i10 i11 i12 i13 i14 i15 BIT3 orgate

or#2 i4 i5 i6 i7 i12 i13 i14 i15 BIT2 orgate
or#3 i2 i3 i6 i7 i10 i12 i14 i15 BIT1 orgate
or#4 i1 i3 i5 i7 i9 i11 i13 i15 BIT0 orgate

.plot v(BIT0) v(BIT1) v(BIT2) v(BIT3)

.tran 0.1p 4e-7
.end