EXPERIMENT -1

Aim: Implementing various logic gates.

Materials required: Software LogiSim installed on a PC.

Theory:

Logic Gates: Logic gates are the basic building blocks of any digital system. It is an
electronic circuit having one or more than one input and only one output. The relationship
between the input and the output is based on a certain logic. Based on this, logic gates are
named as AND gate, OR gate, NOT gate etc.

1. AND Gate

An AND gate has a single output and two or more inputs.

 When all of the inputs are 1, the output of this gate is 1.
 The AND gate‟s Boolean logic is Y=A.B if there are two inputs A and B.

An AND gate‟s symbol and truth table are as follows:

Logic diagram

Truth Table

2. OR Gate:

Two or more inputs and one output can be used in an OR gate.

 The logic of this gate is that if at least one of the inputs is 1, the output will be 1.
 The OR gate‟s output will be given by the following mathematical procedure if
there are two inputs A and B: Y=A+B

An OR gate‟s symbol and truth table are as follows:

Logic diagram

Truth Table

3. NOT Gate:
The NOT gate is a basic one-input, one-output gate.
 When the input is 1, the output is 0, and vice versa. A NOT gate is sometimes called
an inverter because of its feature.
 If there is only one input A, the output may be calculated using the Boolean equation
Y=A‟.

A NOT gate‟s symbol and truth table are as follows:

Logic diagram:

Truth Table:
Universal Logic Gates
4. NOR Gate
A NOR gate, sometimes known as a “NOT-OR” gate, consists of an OR gate followed by a
NOT gate.
 This gate‟s output is 1 only when all of its inputs are 0. Alternatively, when all of the
inputs are low, the output is high.
 The Boolean statement for the NOR gate is Y=(A+B)‟ if there are two inputs A and
B.
A NOR gate‟s symbol and truth table are as follows:

Logic diagram:

Truth Table:

5. NAND Gate:
A NAND gate, sometimes known as a „NOT-AND‟ gate, is essentially a Not gate followed
by an AND gate.
 This gate‟s output is 0 only if none of the inputs is 0. Alternatively, when all of the
inputs are not high and at least one is low, the output is high.
 If there are two inputs A and B, the Boolean expression for the NAND gate is
Y=(A.B)‟
A NAND gate‟s symbol and truth table are as follows:
Logic diagram:

Truth Table:

6. XOR Gate

The Exclusive-OR or „Ex-OR‟ gate is a digital logic gate that accepts more than two inputs
but only outputs one value.
 If any of the inputs is „High,‟ the output of the XOR Gate is „High.‟ If both inputs are
„High,‟ the output is „Low.‟ If both inputs are „Low,‟ the output is „Low.‟
 The Boolean equation for the XOR gate is Y=A‟.B+A.B‟ if there are two inputs A
and B.

Logic diagram

Truth Table
7. XNOR Gate:

The Exclusive-NOR or ‘EX-NOR’ gate is a digital logic gate that accepts

more than two inputs but only outputs one.
1. If both inputs are ‘High,’ the output of the XNOR Gate is ‘High.’ If both
inputs are ‘Low,’ the output is ‘High.’ If one of the inputs is ‘Low,’ the
output is ‘Low.’
2. If there are two inputs A and B, then the XNOR gate’s Boolean equation
is: Y=A.B+A’B’.

Logic diagram:

Truth Table:

Result: Study of various logic gates and their implementation has been done. Their truth
table‟s are also verified.
EXPERI MENT-2

Aim: Implementing Binary-to Gray and Gray-to Binary code conversions.

Materials required: Software LogiSim installed on a PC.

Theory:

Binary to Gray code conversion:

The Binary to Gray code converter is a logical circuit that is used to convert the binary code
into its equivalent Gray code.
This conversion can be done by applying the following rules:
1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the
given binary code.
2. Other bits of the output gray code can be obtained by XORing binary code bit at that
index and previous index.

Example:

The following circuit is used to convert the 4-bit Binary code to Gray code .
Gray to binary conversion:

The Gray to Binary code converter is a logical circuit that is used to convert the gray code
into its equivalent binary code.

This conversion can be done by applying the following rules:

1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the
given gray code.

2. Other bits of the output binary code can be obtained by checking the gray code bit at
that index. If the current gray code bit is 0, then copy the previous binary code bit,
else copy the invert of the previous binary code bit.

Example:

The following circuit is used to convert the 4-bit Gray code to Binary code.

Result: Binary-to Gray and Gray-to Binary code convertors has been studied and
implemented.
EXPERIMENT -3

Aim: Implementing Half Adder and Full Adder

Materials required: Software LogiSim installed on a PC.

Theory:

A half adder is a digital logic circuit that performs binary addition of two single-bit binary
numbers. It has two inputs, A and B, and two outputs, SUM and CARRY. The SUM output is
the least significant bit (LSB) of the result, while the CARRY output is the most significant
bit (MSB) of the result

Block diagram:

Truth Table:

Logical Expression:

 Sum = A XOR B
 Carry = A AND B

Half-Adder logical circuit:

Full Adder:

The half adder is used to add only two numbers. To overcome this problem, the full adder
was developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C.
The full adder has three input states and two output states i.e., sum and carry.

Block diagram:

Truth Table:

Logical Expression:

 Sum = A XOR B XOR C

 Carry = AB+BC+CA
Or
AB+(A XOR B)C
Full-Adder logical circuit:

Result: The Half Adder and Full Adder are implemented successfully and their truth
tables are also verified.
EXPERIMENT -4

Aim: Implementing Half Subtractor and Full Subtractor

Materials required: Software LogiSim installed on a PC.

Theory:

Half Subtractor

The half subtractor is also a building block for subtracting two binary numbers. It has two
inputs and two outputs. This circuit is used to subtract two single bit binary numbers A and
B. The 'diff' and 'borrow' are two output states of the half subtractor.

Block diagram

Truth Table:

Logical Expression:

 Diff= A'B+AB'
 Borrow = A'B

Half-Subtractor logical circuit:

Full Subtractor:

The Half Subtractor is used to subtract only two numbers. To overcome this problem, a full
subtractor was designed. The full subtractor is used to subtract three 1-bit numbers A, B, and
C, which are minuend, subtrahend, and borrow, respectively. The full subtractor has three
input states and two output states i.e., diff and borrow.

Block diagram:

Truth Table:

Logical Expression:

 Diff= A XOR B XOR C

 Borrow = BBin+ A'B+ A'Bin
Full-Subtractor logical circuit:

Result: The Half Subtractor and Full Subtractor are implemented successfully and
their truth tables are also verified.
EXPERIMENT -5

Aim: Implementing 4:1 and 8:1 MUX.

Materials required: Software LogiSim installed on a PC.

Theory:

Multiplexer is a combinational circuit that has maximum of 2n data inputs, „n‟ selection lines
and single output line. One of these data inputs will be connected to the output based on the
values of selection lines. Multiplexer is also called as MUX.

4x1 Multiplexer:

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines S1 & S0 and one output
Y.

Block Diagram:

Truth Table:

Boolean Expression:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Circuit Diagram:

8x1 Multiplexer:

8x1 Multiplexer has eight data inputs I7, I6, I5, I4, I3, I2, I1 & I0, three selection lines S2 ,S1 &
S0 and one output Y.

Block Diagram:

Truth Table:
Boolean Expression:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2

.A6+S0.S1.S2.A7

Circuit Diagram:

Result: 4x1 and 8x1 MUX has been implemented and their truth tables are also verified.
EXPERIMENT -6

Aim: Implementing 1:4 and 1:8 DEMUX.

Materials required: Software LogiSim installed on a PC.

Theory:

A De-multiplexer is a combinational circuit that has only 1 input line and 2n output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The
information is received from the single input lines and directed to the output line. On the
basis of the values of the selection lines, the input will be connected to one of these outputs.
De-multiplexer is opposite to the multiplexer.

De-multiplexer is also treated as DEMUX.

1x4 De-Multiplexer:

A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and four
outputs (Y0 to Y3). The input data goes to any one of the four outputs at a given time for a
particular combination of select lines.

Block Diagram:

Truth Table:
Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 Din

0 1 0 0 Din 0

1 0 0 Din 0 0

1 1 Din 0 0 0
Boolean Expression:

Y0=S1' S0' Din

y1=S1' S0 Din
y2=S1 S0' Din
y3=S1 S0 Din

Logic Circuit Diagram:

1x8 De-Multiplexer:

1-to-8 demultiplexer that consists of single input D, three select inputs S2, S1 and S0 and
eight outputs from Y0 to Y7. It distributes one input line to one of 8 output lines depending
on the combination of select inputs.
Block Diagram:

Truth Table:

Selection
Outputs
Inputs

s2 s1 s0 Y 7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 Din

0 0 1 0 0 0 0 0 0 Din 0

0 1 0 0 0 0 0 0 Din 0 0

0 1 1 0 0 0 0 Din 0 0 0

1 0 0 0 0 0 Din 0 0 0 0

1 0 1 0 0 Din 0 0 0 0 0

1 1 0 0 Din 0 0 0 0 0 0

1 1 1 Din 0 0 0 0 0 0 0

Boolean Expressions:

Y0=S0'.S1'.S2'.Din
Y1=S0.S1'.S2'. Din
Y2=S0'.S1.S2'. Din
Y3=S0.S1.S2'. Din
Y4=S0'.S1'.S2 Din
Y5=S0.S1'.S2 Din
Y6=S0'.S1.S2 Din
Y7=S0.S1.S3. Din

Logic Circuit:

Result: 1x4 and 1x8 DE-MUX has been implemented and their truth tables are also
verified.
EXPERIMENT -6

Aim: Implementing 3:8 Decoder.

Materials required: Software LogiSim installed on a PC.

Theory:

The combinational circuit that change the binary information into 2N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines
define the 2N-bit code for the binary information. In simple words, the Decoder performs the
reverse operation of the Encoder.

3 to 8 line decoder:

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder,
there are eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three inputs, i.e., A0,
A1, and A2. This circuit has an enable input 'E'. When enable 'E' is set to 1, one of these four
outputs will be 1.

Block Diagram:
Truth Table:

Logical expression:

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit:
E

Result: 3:8 Decoder has been implemented and truth table is also verified
EXPERIMENT -8

Aim: Implementing 2-bit by 2-bit array multiplier..

Materials required: Software LogiSim installed on a PC.

Theory:

An array multiplier is a digital combinational circuit used for multiplying two binary numbers
by employing an array of full adders and half adders. This array is used for the nearly
simultaneous addition of the various product terms involved. To form the various product
terms, an array of AND gates is used before the Adder array.

2-bit by 2-bit array: For implementation of array multiplier with a combinational circuit,
consider the multiplication of two 2-bit numbers as shown in figure. The multiplicand bits are
b1 and b0, the multiplier bits are a1 and a0, and the product is c3c2c1c0

For the above multiplication, an array of four AND gates is required to form the
various product terms like a0b0 etc. and then an adder array is required to calculate
the sums involving the various product terms and carry combinations mentioned in the
above equations in order to get the final Product bits.
1. The first partial product is formed by multiplying a0 by b1, b0. The multiplication
of two bits such as a0 and b0 produces a 1 if both bits are 1; otherwise, it produces
0. This is identical to an AND operation and can be implemented with an AND
gate.
2. The first partial product is formed by means of two AND gates.
3. The second partial product is formed by multiplying a1 by b1b0 and is shifted one
position to the left.
4. The above two partial products are added with two half-adder(HA) circuits.
Usually there are more bits in the partial products and it will be necessary to use
full-adders to produce the sum.
5. Note that the least significant bit of the product does not have to go through an
adder since it is formed by the output of the first AND gate.

Circuit Diagram:
Result: 2-bit by 2-bit array multiplier has been successfully studies and
implemented.
EXPERIMENT -9

Aim: Implementing 4-bit Arithmetic Logic Unit.

Materials required: Software LogiSim installed on a PC.

Theory:

ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like AND, OR, XOR, NAND,
NOR etc.

Block Diagram: A simple block diagram of a 4 bit ALU for operations AND, OR, XOR and
Add is shown here:

 1-bit ALU

 4-bit ALU

The 4-bit ALU block is combined using four 1-bit ALU block.
Circuit functionality of a 1 bit ALU: Depending upon the control signal S1 and S0 the
circuit operates as follows:
 for Control signal S1 = 0 , S0 = 0, the output is A AND B,
 for Control signal S1 = 0 , S0 = 1, the output is A OR B,
 for Control signal S1 = 1 , S0 = 0, the output is A XOR B,
 for Control signal S1 = 1 , S0 = 1, the output is A ADD B.

Result: 4-bit ALU has been successfully studied and implemented.