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25 views11 pages

Model Question

Uploaded by

sunnymanuka0
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Birla Institute of Technology & Science, Pilani

Work Integrated Learning Programmes Division


B.Sc Design and Computing at HCL Technologies
2nd Semester 2023-2024

Mid-Semester Test
(EC-2 Regular)

Course No. : BSDCHZC215


Course Title : Digital Design
Nature of Exam : Open Book
Weightage : 30% No. of Pages = 3
Duration : 2 Hours No. of Questions = 6
Date of Exam : 1st June 2024 ; 9a.m.
Note to Students:
1. Please follow all the Instructions to Candidates given on the cover page of the answer book.
2. All parts of a question should be answered consecutively. Each answer should start from a fresh page.
3. Assumptions made if any, should be stated clearly at the beginning of your answer.

Q.1 Set. (A) [2+3+2] Marks


The combinational circuit shown in the figure is a function of four variables A,B,C,D
a) Find its Boolean expression
b) Minimize the Boolean expression found in (a) using Karnaugh Map
c) Draw the resultant circuit
Q.1 Set. (B) [2+3+2] Marks
The combinational circuit shown in the figure is a function of four variables A,B,C,D
d) Find its Boolean expression
e) Minimize the Boolean expression found in (a) using Karnaugh Map
f) Draw the resultant circuit
Q.2 Set. (A) [5] Marks
Implement a three input combinational circuit f(A,B,C),where A is the MSB and C is
the LSB, that gives an output one when two or more number of inputs are high
a. Write the Truth Table. [2.5]
b. Implement with minimum number of logic gates (only equation reqrd.) [2.5]
Q.2 Set. (B) [5] Marks
Implement a three input combinational circuit f(A,B,C),where A is the MSB and C is
the LSB, that gives an output one following the conditions that at-least one input is high
and gives the output Zero when all three inputs are high.
a. Write the Truth Table. [2.5]
b. Implement with minimum number of logic gates (only equation reqrd.) [2.5]
Q.3 Set. (A) [2.5+2.5] Marks
a. Obtain the SOP equation of the circuit shown and give the NAND- NAND
realization of it
U1
A'
B' AND2

U2 U3
B y=f(A,B,C)
C' AND2 OR3
U4
B'
C
AND2
b. Convert the SOP expression obtained in (a) to standard POS

Q.3 Set. (B) [2.5+2.5] Marks


a. Obtain the SOP equation of the circuit shown and give the NAND- NAND
realization of it
.
U1
c'
B' AND2

U2 U3
B y=f(A,B,C)
C
AND2 OR3
U4
B'
A
AND2
b. Convert the SOP expression obtained in (a) to standard POS

Q.4 Set. (A) 5 Marks


Show the two-level NOR gates implementation of the given function
. F (w,x,y,z)= w’x + yz + w’xz
Q.4 Set. (B) 5 Marks
Show the two-level NOR gates implementation of the given function
. F (w,x,y,z)= wx’ + yz +w xy’
Q.5 Set. (A) [2+1+1] Marks
a) Using 2’s complement method, find the result of subtraction of numbers given in
base 10 to show the result in binary. (5)10 - (12)10= (?)2

b) What is the range of decimal numbers in 2’s complement 5 bit representation?

c) Represent (456)10 as ( ? )16 =( ? )8


Q.5 Set. (B) [ 2+1+1] Marks
a) Using 2’s complement method, find the result of subtraction of numbers given in
base 10 to show the result in binary. (7)10 - (11)10= (?)2

b) What is the range of decimal numbers in 2’s complement 6 bit representation?

c) Represent (456)10 as ( ? )16 =( ? )8

d)

Q.6 Set. (A)


Apply Boolean Algebra to reduce F = (x + y)(x + y’) to a minimum number of literals. [4]
Q.6 Set. (B)
Apply Boolean Algebra to reduce F = xy + x’z + yz to a minimum number of literals. [4]

xy + x’z + yz(x + x’) = xy + x’z + xyz + x’yz


= xy(1 + z) + x’z(1 + y)
= xy + x’z.

=====All the best====

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