FIRST SET OF QUESTIONS

1. What is the different kind of faults model you have worked on?
Ans:
 Stuck-at, Transition, Path-delay, IDDQ, Hold-Time, Bridging.

2. What is the difference in the hold time delay fault model other than all delay faults model?(give
the details algorithm wise)
Ans:
 Hold Timing: Take all best corner (short/min) delay paths in to ATPG for pattern
generation and analyze coverage.

3. What is the flow to generate the different delay fault model? What are the inputs and from
where it’s generated?
Ans:
 Hold Timing: Take all best corner (short/min) delay paths from STA in to ATPG for
pattern generation and analyze coverage.
 Path Delay : worst corner (critical/max) delay paths from STA in to ATPG for ATPG
 Stuck-at : No timing model involved here. Single Pulse based.
o Switch add_fault model –stuck_at
 Transition: At-speed edge to edge timing based pattern generated.
o Switch add_fault model –transition
 IDDq – Measure leakage current , once after switching is done.
o Switch add_fault model –IDDq

4. What are the different kind of the TR delay fault model?

Ans:
 Path – Delay(Max) & Hold Timing (Min)

5. What is the difference between LOC,LOS and LOES.(With advantage/disadvantage of each)

Ans:
 LOC : Launch & Capture is generated inside design after complete shifting is done.
Enough Time for SE settling down.
 LOS : Launch is generated by last shift & capture is produced in design. High speed
ASSERT/DE_ASSER – SE is required.
 LOES : Enhanced shift generation is produced to replicate LOS & Launch.

6. What are the different kind of the MBIST tool you have worked on?
Ans :
 MBIST Architect & Logic Vision Tessent MBIST & Synopsys – STAR MEMORY SYSTEM

7. Describe the flow of the Tessent MBIST flow?(With detail of each steps)
Ans :
 ET Checker : Check DRC in terms of Clock/Port/PIN-Mapping/design checks.
 ET Planner : Configure Memory BIST in terms of ( Grouping/Controller Decision
making/Clocking/Collar Insertion/Redundancy Allocation )
 ET Assembler : Creates RTL & Synthesize & Inserts BIST in to Design
 ET Verifier : Stand-Alone BIST Testing & Memory<->Controller at IP Level
 ET Sign-Off : BIST Simulation from Design Top.

8. What is the architecture of the tessent MBIST?

Ans:
 TAP --> WTAP --> MBIST Controller --> Memory Interface --> Memory

9. How you will apply the grouping on the different Memory.(On which criteria you will decide the
grouping of the memory)
Ans:
 Clock (Frequency) & Physical Placement File & Memory Type & Memory Structure
10. What is the difference between single port memory and 2 port memory? How you will do DFT
for that?
Ans :
 1 Port would have single WRDE/RDE/CLK/ME/CLK/CS/ADDE/DI/DO.
 2 Port would have two WRDEA/RDEA/CLKA/MEA/CLKA/CSA/ADDEA/DIA/DOA &&
WRDEB/RDEB/CLKB/MEB/CLKB/CSB/ADDEB/DAB.
 1 port doesn’t have any partition & 2 port would have center decoder and divided
memory banks in to two, where enabling can be done easily.
 DFT : 1 port is grouping in to separate memory controller (can either read/write at a
time ) & 2 port in term of separate memory controller.( can read and write individually
in to their partitions & connected by same clock source )

11. What is the difference between dual port memory and 2 port memory? How you will do DFT for
that?
Ans :
 Dual port is similar to 2 port, except CLKA & CLKB will be connected to different clock source
for operation.

12. Can we group two memory which have a different frequency in same group? Yes then why? No
then why?
Ans:
 No. BIST can run memory at-speed testing in to single frequency at a time.

13. Can we group two different memory in same group? Yes then why? No then why?
Ans: Yes. Controller is sufficient enough to take care memory interface w.r.t to different address
size & data bus width port mapping of different memories.

14. Can we group 1P memory and 2P memory in same group? Yes then why? No then why?
Ans : Yes we can.

15. Give basic structure of LBIST.

Ans :

16. How you used iJtag in your design?

Ans : IJTAG sits in a ring, where we can easily access different 1500 wrapped cores with high
flexibility.
17. How you access Ijtag while doing the simulation.
Ans: IJTAG is the first single bit register where we can check signals from top tap instructions
provided or not. Once it is activated only then we can check for remaining all signals related to
design periphery is set to its mode value.

18. How ICL language works? what is the three inside ICL file?
Ans: Related to IJTAG.

19. How you use the iJTAG for post silicon debug?
Ans: Same as 17th ans.

20. How much type of simulation you have performed?

Ans : Stuck-at/Transition ( Timing & No-timing – with different PVT enabled corners ).

21. what is the difference between unit delay and zero delay simulation?
Ans :
 Cells are characterized in to zero delay from input to output and perform simulation. (Switch
is set to zero delay)
 Cells are characterized in to Unit delay from input to output and perform simulation. (Switch
is set to Unit delay)

OTHER SET OF QUESTIONS

1. Introduction
1. Good morning/Evening. My name is <name>.I am working at eInfochips as DFT
Engineer since around <num> years.

2. On how much project you have performed ATPG/MBIST/Scan Insertion/LBIST?

1. On x projects I have performed ATPG.
2. On x project I have learned MBIST/SCAN insertion flow.
3. On x project I have learned LBIST insertion flow.

3. What method you are using for TR, LOC & LOS? Why so?
1. In our project we were using LOC (Launch on capture) method.
2. We didn’t insert SE high speed circuit to have SE faster toggle which we do in LOS.
3. We implemented LOES to achieve same.

4. How do you handle different IPs in your design?

Ans :
 Mode 1 : We created different test mode decoder (Sequential/Combinational) circuit at
design top to target analog/digital/custom – IP in design.
 Mode 2 : We created AMS wrapper with help of SHS to wrap the IP in to core and target
it from TAP with different

5. How do you insert MBIST controller in your design?

Ans :
 Decide no.of memories in design & partition it
o Characterize memory: (w.r.t to clock/frequency & partition & type &
structure & redundancy modes & Placement).
 Group based on above terminology and configure MBIST
o Characterize memory : ( w.r.t to frequency/BIST & algorithm &
redundancy allocation & pipeline mechanism & Signature/ID code
generation & Insertion instance location & Timing Exceptions on
Constraints )
 Generate RTL & Insert MBIST & Synthesize it & check LEC/Formality on same.

6. Which tool you are using for IEEE 1149.1 Insertion?

Ans: BSD Compiler

7. Difference you've face with respect to DFT from 65 nm to 16 nm?

Ans:
 At lower technology nodes, faced the power related issues when generating patterns.
 The capture power was increasing due to the circuit complexity at lower nodes.
Additional care needed to handle the clock-gating of the entire chips to reduce the
overall capture/shift power.

8. In Path Delay Test, from where you are getting path definition? How many no. of paths you are
taking?
1. In our project, from STA team we were getting the path definitions for path-delay test.
2. We were targeting around 1000 paths.

9. Have you tried N-detect technique?? Will N-detect help more in detection of defects?
Ans:
 N-Detect: Target single fault with more than one pattern is n-detect. Mainly with
respect to tester , if particular type or set of patterns are discarded , then we would
be in a position to deliver patterns that increase control/observe.

10. How do you write out test_setup procedure for tool?

1. In our project, we had client utility that was taking the TAP constraints required for
test_setup from the input files and converting them into test_setup procedure.

11. How do you tell tool that I need to get shifting of 1000 pulse?
1. For TETRAMAX tool, we can use below command to tell tool to generate shifting of 1000
pulses.
2. Command : set_drc dft_max_shift_cycles 1000

12. How do you define/write shift procedure? what is in that procedure?

1. In the shift procedure we are pulsing the clock and also we are keeping the value of the
Si and So to # which states that tool generated scan vectors will be applied here.

13. How load_unload procedure is different than shift procedure?

1. In the load_unload procedure we define the constraints required to do the shift like
scna en, reset also we will keep bidirectional signals to Z. And shift procedure is also
defined in the load unload.
2. while in the shift procedure we are pulsing the clock and also we are keeping the value
of the Si and So to # which states that tool generated scan vectors will be applied here.

14. For TR, How do you generate double pulse? what changes have been made in spf file?
1. If there is OCC in the design than thru that double pulse is generated, And in the SPF we
will declare the output of the OCC as the internal clock in the clock structure block.
Hence tool will take these signals as the clock while using the clock constraint.
And in the clocking procedure pulse the internal clocks.
2. If there is no OCC in the design than, thru the waveform table we can define the two
clock pulses.
3. In the SPF define the reference clocks as the reference attribute in the clokc structure
block. And also define them in the every WFT.

15. How do you tell tool to get capture clocks from OCC in TR?
1. Define the output of the OCC as the internal clock in the clock structure and also pulse
the internal clock in the clocking procedure. From the clock structure, tool will be able
to get that it needs to take the capture clock from the OCC.
16. What kind of issues you've faced in simulation?
1. I have faced x-mismatches failure which was coming because clock was becoming X.
After back-tracing clock X source found that one constraint needs to be fixed.
17. Which tool you are using for simulation as well as waveform viewer?
1. Simulation : VCS, NCSim.
2. Waveform viewer : Verdi, Simvision
18. What is difference between Unit delay simulation & zero delay simulation?
1. Zero Delay : Node and the path delays are considered as the zero and simulation is
done. It is used to check the design without considering the any timing related
discrepancy.
2. unit Delay: When we want to perform the gate level simulation but SDF is not yet ready
than unit delay simulation is performed where all the structural delays are taken the
unit time value.
The nonzero structural and continuous assignment delay expressions are substituted by a delay
of 1 timescale unit,
19. Which simulation you used to do? What is simulation flow?
1. In the VCS, simulation flow is compilation, elobration and pattern simulation
Compilation: Tool will analyze the source code mainly for the syntax error, expansion of
the macro and will generate the intermediate file for the later use.
Elobration: A tool would stitch things (design components, verification components,
and/or both) together. In this phase, the tool reports unresolved elements, if any. The
intermediate files created in the analyze phase are further processes and a new set of
intermediate files are creates (sometimes called object files).

20. What are the timing cases you are taking while doing timing simulation?
Ans : Best case for Hold & Worst case for setup.

21. What is inside .sdf file? What information it consists?

1. SDF containts the timing information of all the cells and the interconnects for all the
timingcases. Also it contains the setup and hold for rise and fall

22. If zero delay simulation is passing and .sdf (timing) simulation is failing? what could be
common cause? what would be your approach?
1. Common cause of failure is the timing issue. If it is X mismatch than check for the setup
or hold time violation on particular node using the waveform viewr and confirm with thr
SDF file. If it is 0-1 mismatch than there could be the clock related issue- clock defined in
the SDC and in the ATPG are not matched. If clock defined is not proper or data late or
early condition is there.

23. Simulation mismatch Occurs where flop1 & flop2 are clocked by clock1 & clcok2 respectively.
What should be the solution?
Ans :
Ask Interviewer: Is it chain / capture test (Stuck-at / Transition)
Ask Interviewer: Is it STA / DTA
Cross check Exceptions & ask Interviewer frequency of clock1 & clock2
Ask Interviewer: Relation between clock1-flop1 & clock2-flop2.

24. Suppose in same scan chain, flop1 & flop2 are clocked by clock1 & clock2 respectively. Clock2 is
faster than clock1 & there is no lockup latch between them. Will it create mismatch?
Ans :
 Clock2 expects data faster, where before data is sampled at flop1 (considering
clock1 is slower).
 Clock2 is waiting for Data1 to come out. & Shift-Out is opposite to Shift-In with
difference in intervals. Still data are captured.

25. How do you get the list of Multi Cycle Path & False Path?
Ans: STA

26. Have you faced ever timing simulation failure due to HOLD violation?
Ans : Yes. We faced it. Data is lost in chain test and we observed hold timing is not closed in
simulation.

27. How many corners are you using for timing simulation?
Ans: Best case, Worst case, typical case, BCMIN, BCMAX, BCHMIN, BCHMAX, WCC, WCMAX,
WCMIN.

28. How would you come to know from simulation that it is HOLD violation or setup violation?
Ans :
 In our project, we performed timing simulation in all the corners. The best case and
typical case simulations were passing but the worst case sim. Was failing. Possible
reason for worst case sim failure is HOLD time violation. So we reduce the freq. and then
worst case simulation was passing.

29. What kind of issue you've faced in netlist check? Before starting ATPG, there is some model
issue. How do you verify it?
Ans: Before pattern generation, tool has BUILD mode (design optimization) , where it catches
netlist & .v (library) binding errors .

30. How do you confirm that there is lockup latch is correctly inserted in netlist or not?
Ans : We can check in scan-cell report & pt session.

31. There is scan part & non-scan part in netlist, What kind of logic should not be part of non-scan
part?
Ans : Clock generator & RST Generator & Functionally Don’t touch & Async logic & Metastable
areas.

32. Which kind of reset you are using in your design? Synchronous reset or asynchronous
reset?
Ans: We were using Asynchronous reset in our design.

33. Have you made any kind of script to check netlist quality?
Ans: No.
We were getting scan-inserted netlist to do ATPG. We do netlist-check using ATPG tool only.

34. How TMAX is able to handle OCC?

Ans: TMAX takes, the OCC information from SPF(clock structure).

35. How P1500 is being used in your design?

Ans: P1500 was used in our design to easily assess the embedded cores.

36. How do you access the P1500 chain in your design?

Ans : TAP
Third Set of Questrions

Q2. How to debug Simulation failure?

Ans – Ask Interviewer for mismatch scenario

1) Capture time mismatch in timing simulation.

- If there are X mismatch then it is due to setup and hold time violations. So, need to analyze
setup and hold for failing flops.
2) 0/1 mismatch in timing simulations.
- Need to analyze timing of failing flops and report STA for timing is not close properly.
3) Simulation and ATPG model mismatch issue.

Q3. Have you work on any Tester?

Ans. - Verigy 93000 PS1600

Q4. How to debug silicon failure?

Ans – First we get error log file from tester team then we convert it into TMAX compatible log file. Using
this log file we run diagnosis in TMAX and find out failing points.
Q5. Have you done any pattern translation?

Ans – I have done pattern translation from stil to binl file.

Q6. On Which pattern format you work on?

Ans – I have worked on STIL pattern format.

Q7. Which tool you use for simulation?

Ans – For simulation I have use VCS.

Q8. Diagnosis flow?

Ans – First we got silicon failure log file from tester team. Then we convert that log file into TMAX
compatible log file. Then first run tmax up to DRC. Then read patterns which is failing and then using
run_diagnosis command and failure log file we can run diagnosis and find out failing points.

Another set of questions

1. How test pin partition?

 If there isn’t Dft_pad available then we can share the functional pins. If we have
Dft_pad available we can directly use it.

2. Test mode control modes?

 Below are the test control modes :
i. Scan
ii. MBIST
iii. Analog
iv. Boundary Scan

3. Jtag insertion? Internal tools

 Tessent Bscan

4. Scan insertion? Mentor tool

 DFT Advisor
5. Compression technique? EDT
 TestKompress.
6. DRC rules? K19, K20 violations, EDT boundaries

7. How make sure don’t mess up edt boundary?
 Put it into specific modules or hierarchy and apply don’t_touch attribute.
8. SE constraint?
 SE is Scan Enable constraint required to differentiate Scan shift and capture
operation in Scan.
9. Edt update?
 Edt update is a signal required to update mask registers in Edt logic to perfrom X-
masking.
10. Dedicated edt clock?
 It is required for clocking Edt logic registers.
11. How to generate edt clock?
 We can provide directly Edt clock from Top.
12. Pattern generation? TK tool
 Yes.
13. How to do PD?
 We get the critical timing paths from STA team. We add those paths to target during
ATPG. Tool generates pattern by sensitizing the critical path and captures responses.
14. Diff between pd and tr?
 Path-delay fault targets entire paths to check weather it is Slow-to-Rise/Fall.
 TR fault model targets particular Gate/node.
15. Multiple clk domain faults?
 It is Intra-clock domain ATPG technique, in which we launch at clock1 and capture at
clock2 to test the logic present in-between.
16. Margin issue?
 Tester : It is a window where we have our all vectors working without any failures.
Usually Test Engineer sets the margin. For exa : NVNF (V100->100ns) , V90 to V110
17. Synpsys dft compiler? Pipe lined scan

18. Mentor lv mbist flow?
 MBIST using LV flow :
i. ETChecker :
1. Run ETChecker in genTemplate mode
2. Run ETChecker in clockInfo mode.
3. Run ETChecker in ruleCheck mode
4. Handoff files to ETPlanner step.

ETPlanner :

1. Run ETPlanner in genPlan mode,

2. Run ETPlanner in checkPlan mode,
3. Run ETPlanner in genLVWS mode,

Run ETPlanner in UpdateETCheckerInfo mode,

5. Handoff files to ETAssemble step.

19. Bscan insertion flow?


20. Block level tap? Wtap? Top level tap?
 In our project, we had Top level tap and block-level Wtap.
21. How many flops driven by pipe line?
 2-3
22. Functional sdc for atpg?
 We are not using functional SDC during ATPG.
23. Timing for at speed test?
 Yes.
24. What type Mbist architecture – which algo for ram developed for mbist? Rom?
 Read-only algorithm
25. What algorithm for burning test of memory?
 Not worked.
26. Yeild/fault diagnostics tool?
 I have used TETRAMAX tool to diagnose the tester pattern failures.
27. Ir drop failures? – power
 In one of our project, the SAF patterns were failing on tester due to capture power.
 We came up with different solutions to limit power constraints for different blocks in
entire chip.
28. Lbist flow?

29. 4 partition? How defects for partition?

30. Segment faults- scan segments?

31. Ddr2, ddr io stich in bscan? How stich?
 Plug-n-Play
32. How to work on tessent incentia? Netlist editing?

33. Commands for fanin –fanout?
 get/report/add
34. Coverage gap?
 Analyze AU/ND faults.
 Perform no_faulting on mem/IPs/macros.
35. Comfortable with perl/tcl?
 Yes.
36. Test point insertion?
 To increase controllability and observability.
 To solve DRCs.
37. Coverage loss due to mem and anlog blk?
 Yes. We faced coverage loss due to memories. We added those memory faults into
no_fault list to increase the coverage since we had separate test to test the memories.
38. Timing simulations?
 Yes.
39. Currently work with einfo or infotech?
 einfochips
Another set of questions :

1) roles and reposibilities on the recent project

Ans – Pattern generation in compress mode/Uncompress mode. Pattern simulation,
Patterns Translation. Check all DRC, Clean all patterns simulation and also clean all results of
post silicon.
2) atpg tools used
Ans – Tetramax, TestKompress

3) atpg issues faced during project

Ans. – 1) Undefine module in netlist
2) S1 Violations (scan chain blockage )
3) C1 ( unstable scan cells, when clocks are off ), C39 ( non—logical clock connected
to scan cells ) Violations

4) pattern count and atpg runtime

a. Ans – For 1 block it is around 50k and to generate full coverage patterns run time is
around 5-6 Days.

5) compression ratio achieved

Ans. – around 250X

6) what was the tester used

Ans. – Verigy 93000 PS1600

7) post silicon issues faced and how it was resolved

Ans. – 1) Netlist mismatch issue
2) SDC Issue – After fixing SDC and regenerate patterns it was resolve.

8) Mentor tools that you have worked

Ans. – TestKomperss, LV MBIST1

9) how was the boundary scan inserted

BSD Compiler
10) mbist tools worked
Ans : LV-Tessent MBIST / SMS (synopsys) / MBIST – Architect

11) mbist fault injection flow

Ans : Get x & y co-ordinates of memory to identify address location and model AND/XOR/
structure type in fault injection file and provide it to controller.

12) Have you worked on mentor bist tool

Yes.
13) scan insertion issues faced
DRC related to clock/set/reset & chain balancing & compression achieving & 100% scan
conversion & clock based chain stitching (edge mix/not mix ) & optimization cells (right cells
during synthesis of compressor rtl ).

14) tool used for scan insertion

Ans. – DFT Compiler, Design Craft

Another set of questions

1. Customer name?

 It is confidential, but I can share their application i.e. IoT, Communication devices
(Repeaters/Router), Mobile computing, Sensors

2. MBIST tool name?

 MG: Tessent LV MBIST and Synopsys: Start Memory System

3. Which Algorithms used for MBIST?

 As per the requirement we can select tool specific algorithm i.e. March based algorithm for
SRAM/RF and Read Only algorithm for ROM. Also we can create user defined algorithm
based on fault model requirement given by foundry.

4. How to do fault injection in the flow?

 If the memory supports error injection module then the MBIST controller will able to inject
fault into the memory. Hence we can create fault injection pattern and load it into MBIST
controller

5. Boundary Scan tool name?

 Synopsys: BSD compiler and MG: Tessent Boundary Scan

6. Have worked on Mentor? Are you familiar with EDT flow?

 Yes, EDT is embedded deterministic testing logic inserted to support

compression/decompression logic for coverage improvement and X masking

7. Have you done scan insertion? What DRC you faced?

 First we consider the input channels available for scan insertion.

 Then we define scan i/o, scan enable, scan clock and scan reset.
 We need to check all the DRC to achieve full scan design. DRC with respect to all the flops
clock/set/reset
 Analyze and apply compression if required to reduce test time & test data volume. DRC with
respect to compression logic.

8. How do you take care of OCC? Is it Synopsys tool?

 Yes. It is synopsys tool

 We need to define proper control signals related to OCC i.e. reference clock, ATE clock,
pll_bypass, test_se, test_mode, and occ_reset.
 Then tool will insert occ with respect to configuration we have applied during insert_dft. We
need to clean OCC related DRC if observed.
 During ATPG we need to define proper capture procedures and clock information of OCC to
generate double pulse (at-speed) from OCC during ATPG.

9. How comfortable to work on DFT compiler? How to debug DFT-DRC in DFT Compiler?

 Good enough.
 Lets take example of scan chain blockage. We need to select the DRC i.e. S1-1 and then it
will show the scan chain flop where the scan chain is blocked.
 Then put the design configuration into test_setup mode or shit mode to trace the SI where the
scan chain is getting X. Nail down the issue by applying constraints or changing logic.

10. Any experience on LV flow?

 Yes. MBIST insertion and validation done for several types of memories using LV flow.

11. Have you done STA?

 Yes. We use to create DFT mode SDCs and provide them to PnR team.
 Then as per the feedback from PnR team we need to update constraints to smooth timing
related issues.
 Also we need to validate all the SDCs using PT and then deliver SDCs. Generate top level
MBIST SDCs by combining block level constraints.
 If timing violations are observed during DFT pattern simulation we need to check the timing
of failing flop and then report them to PnR team if they missed any constraints

12. What is the compression you used? Have you used EDT compression?

 Compression depends upon the block level and top level channels available for scan purpose.
 We need to analyze the compression ratio generated from tool and select best possible value
w.r.t coverage number, pattern count and test data volume.
 Yes, I have used EDT compression

13. You know Perl, TCL or Shell.. rate 0..10?

 8 out of 10
14. What consideration you take for Boundary scan insertion

 We need to consider pin mapping for all the pads before boundary scan insertion
 Then we should know the functionality of each pad and accordingly we need to define BS
cells.
 All the test need to be performed to test functionality to pads.

15. How you decide that you need Boundary scan and how you plan?

 If the die have digital pads or analog pads and if we need to test the interconnection between
die and package or between two package then we can go with Boundary scan.
 According to functionality of each pads we will decide which Boundary scan cell we will
insert and test pads.