Unit-2: Operating System (OS) of Raspberry Pi

2.1. Benefits of Raspberry Pi Operating system:

Raspberry Pi OS (formerly Raspbian) is the official operating system developed by the
Raspberry Pi Foundation. It offers numerous benefits, especially for users and developers
working with Raspberry Pi devices. Here are the key advantages:
1. Optimized for Raspberry Pi Hardware
 Specifically designed to run efficiently on Raspberry Pi models.
 Lightweight and tailored to work well with the Pi's limited resources.
 Offers robust support for Raspberry Pi-specific features like GPIO pins, cameras, and
HAT (Hardware attached on Top).
2. Ease of Use
 Comes with a user-friendly desktop environment that is intuitive for beginners.
 Includes pre-installed tools and software, such as a web browser, text editor, and
terminal, for immediate productivity.
3. Educational Focus
 Preloaded with programming tools like Python, Scratch, and Thonny IDE to support
learning.
 Perfect for teaching coding, electronics, and other STEM (science, technology,
engineering, and mathematics) concepts.
 Backed by extensive tutorials and educational resources from the Raspberry Pi
Foundation.
4. Wide Software Compatibility
 Access to the vast library of Debian-compatible software.
 Includes pre-installed applications for general use, such as VLC Media Player and
Libre Office.
 Compatible with third-party tools and frameworks for various projects (e.g., IoT, web
servers, gaming).
5. Community Support
 A large, active community of Raspberry Pi enthusiasts and developers.
 Comprehensive documentation, forums, and online guides available for
troubleshooting and project ideas.
6. Stability and Reliability
 Based on Debian Linux, known for its stability and security.
 Regular updates from the Raspberry Pi Foundation ensure consistent performance and
bug fixes.
 Long-term support, making it reliable for critical projects.
7. Excellent for Learning Linux
 Beginner-friendly introduction to Linux while retaining the flexibility for advanced
users.
 Includes a terminal and essential commands, encouraging users to learn and
experiment with Linux systems.
8. Energy-Efficient and Low Resource Usage
 Designed to work efficiently with Raspberry Pi's low-power hardware.
 Minimal resource consumption ensures smooth operation even on older models.

Different types of OS:

1. Raspberry Pi OS (formerly Raspbian)
Description: The official OS developed and maintained by the Raspberry Pi Foundation.
Features:
a. Based on Debian Linux.
b. Comes in multiple versions: Lite (minimal), Desktop (GUI), and Full (includes
additional software).
c. Optimized for performance on Raspberry Pi hardware.
Best For: General-purpose use, education, and projects requiring a stable and supported OS.
2. Ubuntu
Variants:
a. Ubuntu Desktop: For a full desktop experience.
b. Ubuntu Server: For server and headless applications.(headless means a Linux
operating system that runs without a monitor, keyboard, or mouse )
c. Ubuntu Core: For IoT and containerized applications.
Features:
d. Rich package ecosystem.
e. LTS (Long-Term Support) releases for stability.
Best For: Developers and users familiar with Ubuntu.
3. Kali Linux
 Description: A security-focused distribution designed for penetration testing (Used
to simulate cyberattacks on networks and systems to identify and address
vulnerabilities) and cyber security tasks.
 Features:
o Preloaded with tools like Metasploit, Wireshark, and Nmap.
o Lightweight version available for Raspberry Pi.
 Best For: Cyber security professionals and ethical hackers.
4. RetroPie
Description: A platform for retro gaming on Raspberry Pi.
Features:
a. Emulation of classic consoles like NES (Nintendo Entertainment System),
SNES(Super Nintendo Entertainment System super Nintendo Entertainment
System), Sega Genesis.
b. Customizable game controllers and UI.
Best For: Gaming enthusiasts
5. Libre ELEC (Libre Embedded Linux Entertainment Center) and OSMC
(Open Source Media Center)
Description: Media center-focused distributions.
Features:
a. Libre ELEC: A minimal OS for running Kodi.
b. OSMC: More user-friendly with extended features.
Best For: Home theater and media playback.
6. Twister OS
 Description: A desktop-focused OS offering a Windows or mac OS -like interface.
 Features:
o Enhanced GUI with pre-installed apps.
o Themes mimicking popular OSes.
 Best For: Users seeking a polished desktop experience.

7. DietPi

 Description: An ultra-lightweight OS optimized for minimal resource usage.

 Features:
o Custom installation options for applications.
o Suitable for headless setups.
 Best For: Lightweight and resource-efficient applications.

8. Other Specialized OSes

 Batocera: For gaming emulation.
 Fedora IoT: For IoT projects.
 Windows 10 IoT Core: A stripped-down Windows for IoT use cases.
 Arch Linux ARM: For advanced users who want to customize their OS from scratch.

How to Choose:

 Beginner or General Use: Raspberry Pi OS.

 Desktop Experience: Ubuntu or Twister OS.
 Media Center: LibreELEC or OSMC.
 Gaming: RetroPie or Batocera.
 IoT or Minimal: DietPi or Fedora IoT.
 Advanced Users: Arch Linux ARM.

2.3 Block diagram of Raspberry Pi :

Raspberry Pi is a small single-board computer (SBC). It is a credit card-sized computer that
can be plugged into a monitor. It is developed by the Raspberry pi foundation, based in the
U.K. The block diagram of Raspberry pi is shown in the figure below.
Block Diagram Components:

1. Central Processing Unit (CPU) and Graphics Processing Unit (GPU)

 CPU: ARM-based processor
 GPU: Broadcom Video Core
 Handles video decoding, 3D rendering, and multimedia tasks.
2. Memory (RAM)
 Connected directly to the CPU/GPU.
 SDRAM in varying capacities (512 MB,1GB, 2GB, 4GB, 8GB for Raspberry Pi 4).
3. Input/ Output Interfaces
 GPIO Pins:
o 40-pin General Purpose Input/Output header for connecting peripherals like
sensors, LEDs, and other hardware.
 USB Ports:
o USB 2.0 and/or USB 3.0 (depending on the model).
 Ethernet Port:
o For wired network connectivity.
 HDMI Port(s):
o Output for audio and video
 Audio Jack:
o For analog audio output.
 Camera Serial Interface (CSI):
o Connects to compatible camera modules.
 Display Serial Interface (DSI):
o For connecting touchscreen displays.
4. Storage
 MicroSD Card Slot:
o Main storage medium for the operating system and user data.
5. Networking
 Wi-Fi Module:
o Supports 2.4 GHz and 5 GHz bands (on models with built-in Wi-Fi).
 Bluetooth Module:
o For wireless communication with peripherals.
6. Power Supply
 Micro-USB or USB-C connector (depending on the model) supplies power to the
board.
7. Peripheral Controllers
 USB Controller: Manages data transfer for USB devices.
 Ethernet Controller: Handles wired network connectivity.
8. System-on-Chip (SoC)
 Combines the CPU, GPU, and other critical components into a single integrated chip,
usually from Broadcom.

2.4 COMPARISON BETWEEN BCM 2835,BCM 2836,BCM 2837

Block Diagram of ARM1176JZF-S

Block Diagram of ARM1176JZF-S

ARM11J6JZF-S (ARM11 Family)
● ARMv6 Architecture
● Single Core
● 32-Bit RISC
● 700 MHz Clock Rate
● 8 Pipeline Stages
● Branch Prediction
The ARM1176JZF-S processor is a highly integrated, efficient, and high-performance CPU
architecture designed by ARM. Below is an explanation of its block diagram and its primary
components.

1. Core Pipeline

 Fetch Stage: Fetches instructions from memory.

 Decode Stage: Decodes instructions into executable signals.
 Execute Stage: Executes instructions, performing arithmetic, logical, and memory
access operations.
 The pipeline improves performance by allowing multiple instructions to be
processed simultaneously.

2. Cache System

 L1 Cache (Instruction and Data):

o Split cache architecture with separate instruction and data caches.
o Helps reduce latency by storing frequently used instructions and data close to
the processor.
 Optional L2 Cache Support: Extends caching capabilities for higher performance.

3. MMU (Memory Management Unit)

 Manages virtual-to-physical memory translations.
 Supports memory protection and virtual memory functionalities.
 Essential for running modern operating systems like Linux.

4. Jazelle Technology
1. Provides hardware acceleration for Java bytecode execution.
2. Optimizes performance for Java-based applications by reducing interpretation
overhead.
5. Vector Floating Point (VFP) Coprocessor
 A specialized hardware unit for floating-point arithmetic operations.
 Enhances performance in applications requiring mathematical computations, such
as multimedia and scientific processing.
6. Trust Zone Security Extensions
 A security architecture that creates two execution environments:
 Secure World: For trusted operations like secure key storage.
 Normal World: For regular operations.
 Ensures data integrity and confidentiality, especially for embedded and mobile
devices.
7. AMBA Bus Interface
 The Advanced Microcontroller Bus Architecture (AMBA) connects the CPU
core with other system components like memory, peripherals, and coprocessors.
 Ensures efficient communication and data transfer across the system.
8. Debugging and Trace Units
 Embedded Trace Module (ETM): Enables real-time debugging and
performance analysis.
 JTAG Interface: Provides hardware debugging capabilities.
9. Clock and Power Management
 Includes mechanisms to optimize power consumption.
 Dynamically scales performance and power usage based on workload
requirements.
10. Interrupt Controller
 Manages hardware interrupts for efficient task switching.
 Supports both standard and fast interrupts for low-latency response.

ARM11: ARM11 family of processor cores

 The 1176 is one of the more advanced cores in this series, offering features
like support for multimedia processing and a floating-point unit (FPU).
 J:
Stands for Jazelle technology, a feature enabling hardware acceleration of
Java bytecode execution.
 Z:
Indicates the inclusion of Trust Zone technology. Trust Zone provides a
secure execution environment, enabling trusted operations alongside normal
system operations, commonly used for secure payments, DRM, and sensitive
data protection.

 F:
Denotes the presence of a Floating-Point Unit (FPU). The FPU accelerates
mathematical calculations, particularly those involving decimal points,
making the core suitable for multimedia and signal processing tasks.
 S:
Refers to the synthesizable nature of the core. A synthesizable core can be
customized and implemented in a variety of chip designs, providing
flexibility to chip manufacturers.

Pipelining in ARM :

 A Pipelining is the mechanism used by RISC (Reduced instruction set computer) processors
to execute instructions, by speeding up the execution by fetching the instruction, while other
instructions are being decoded and executed simultaneously, which in turn allows the
memory system and processor to work continuously.

 The pipeline design for each ARM family is different. Pipelining is a design technique or a
process which plays an important role in increasing the efficiency of data processing in the
processor of a computer and microcontroller. By keeping the processor in a continuous
process of fetching, decoding and executing called (F&E cycle). ARM devices need
pipelining because of RISC as it emphasizes on compiler complexity. Each stage is
equivalent to 1 cycle, that is n stages = n cycles.

Pipeline:
3 stage pipelining:

 Fetch loads an instruction from memory.

 Decode identifies the instruction to be executed.

 Execute processes the instruction and writes the result back to the register.

 By over lapping the above stages of execution of different instructions, the speed of
execution is increased.

 The pipelining allows the core to execute an instruction every cycle, which results in
increased throughput.

ARM pipeline characteristics:

 The ARM pipeline doesn‘t process an instruction until it passes completely through the
execution stage.

 In the execution stage, the PC always points to the instruction address + 8 bytes.

 When the processor is in thumb state, PC always points to the instruction address + 4 bytes.
 While executing branch instructions or branching by direct modification of PC causes the
ARM core to flush it‘s pipeline.

 As instruction in the execution stage will complete its execution even though an interrupt
has been raised.

ARM 7 –

 It has 3 stages pipelining as shown in the figure.

 It can complete it‘s process in 3 cycles.

 It has the basic F&E cycle leading to optimum throughput.

 This is why the ARM 7 has the lowest throughput as compared to that of its other family
members.

 It processes 32bit data.

ARM 9 –

 Pipelining in ARM 9 is similar to ARM 7 but with 5 stages.

 It takes 5 cycles to complete the process

5 stage pipelining:

 Fetch- It will fetch instructions from memory.

 Decode- It decodes the instructions that were fetched in the first cycle.

 ALU – It executes the instruction that has been decoded in the previous stage.

 LS1 (Memory) Loads/Stores the data specified by load or store instructions.

 LS2 (Write) Extracts (zero or sign) extends the data loaded by byte or half word load
instruction.
 Because of an increase in stages and efficiency, the throughput is 10%-13% higher than
ARM 7.
 Core frequency of ARM 9 is slightly higher than that of ARM 7

ARM 10
 It is a six stage pipeline, which in turn takes 6 cycles to complete the process.
 Same as that of ARM 9 but with an issue stage which checks whether the instruction is
ready to get decoded in the current stage or not.
 It nearly doubles the throughput than that of ARM 7.
 The core frequency is higher than that of ARM 9.
Pipeline stages used by ARM1176JZF-S: CPU Pipeline

Execution flow for ALU operations

Execution flow for Multiply Operations

Execution flow for Load/Store Operations

1. Fetch Stage – fetches instr’s from a cahe memory, ideally one/cycle
2. Decode Stage – reveals instr function to be performed and identifies the resources
needed. Resources include registers, buses, Functional Units…
3. Issue Stage – reserves resources, operands are read from registers
4. Execute Stage – instr’s are executed in one or several execute stages.
5. Writeback - stage is used to write results into registers.

Cache Organization

A fast buffer lies between the main memory (RAM) and the CPU called the CPU Cache. The
main purpose of this model is to cut down the latency associated with the fetching process
from main memory to the CPU register. Two main categories of CPU caches exist: I
(Instruction)-Cache and D (data)-Cache.

One Level Memory System

 Cache replacement policies are Pseudo-Random or Round Robin, which is controlled by
the RR bit in CP15 register c1
 MicroTLB (TLB) (Translation Look aside Buffer) determines if cache lines are write-back
or write-through
 Contain both secure and non-secure data in cache lines
 Each cache is implemented as a four-way set associative cache of configurable size.
 The caches are virtually indexed and physically tagged. One can configure the cache
sizes in the range of 4 to 64KB.
 Cache is Harvard implementation (simultaneous access to data memory and program
memory)
 Each cache way is architecturally limited to 16KB in size, because of the limitations
of the virtually indexed, physically tagged implementation. The number of cache
ways is fixed at four, but the cache way size can vary between 1KB and 16KB in
powers of 2.
 Write operations must occur after the Tag RAM reads and associated address
comparisons are complete. A three-entry Write Buffer is included in the cache to
enable the written words to be held until they can be written to cache.
 The addresses of these outstanding writes provide an additional input to the Tag
RAM comparison for reads.
 To avoid a critical path from the Tag RAM comparison to the enable signals for the
data RAMs, there is a minimum of one cycle of latency between the determination of
a hit to a particular way, and the start of writing to the data RAM of that way.
 This requires the Data Cache Write Buffer to hold three entries, for back-to-back
writes.
 The other main operations performed by the cache are cache line refills and Write-
Back. These occur to particular cache ways that are determined at the point of the
detection of the cache miss by the user selection logic.
 To reduce overall power consumption, the number of full cache reads is reduced by
the sequential nature of many cache operations, especially on the instruction side. On
a cache read that is sequential to the previous cache read
 Only the data RAM set that was previously read is accessed, if the read is within the
same cache line. The Tag RAM is not accessed at all during this sequential operation.
To reduce unnecessary power consumption additionally, only the addressed words
within a cache line are read at any time. With the required 64-bit read interface, this is
achieved by disabling half of the RAMs on occasions when only a 32-bit value is
required.
 The implementation uses two 32-bit wide RAMs to implement the cache data RAM.
This means that cache refills can take several cycles, depending on the cache line
lengths. The cache line length is eight words. The control of the level one memory
system and the associated functionality, together with other system wide control
attributes are handled through the system control coprocessor.

GPU Overview
 Broadcom Videocore IV GPU
 Tile-based renderer (TBR) that use up to four cores
 40 nm technology
 Integrated graphics card so shared memory
 Capable of Blu-Ray quality of 1080p with H.264 at 40Mb/s
 Graphics performance is similar to the Xbox 1
 24 GFLOPS of general purpose computational power
 Has texture filtering and DMA infrastructure
 OpenGL ES 1.1, OpenGL ES 2.0, hardware accelerated OpenVG 1.1, Open EGL,
and OpenMAX
Questions:
1. What are the benefits of Raspberry pi operating system ? (4M)
2. Write a note on different types of operating systems and their applications that
are used in Raspberry Pi.(4M)
3. Draw and explain block diagram of Raspberry Pi in detail (8M)
4. Give the comparison between BCM 2835/BCM 2836/BCM 2837 (4M/8M)
5. State the characteristics of Broadcom processor BCM 2835/BCM 2836/BCM
2837.
6. Draw and explain block diagram of ARM1176JZF-S (8M)
7. What is mean pipelining in ARM? Explain 3 stage pipelining in ARM(4M).
8. What is mean pipelining in ARM? Explain 5 stage pipelining in ARM (4M).
9. With the help of diagram explain cache organization in Raspberry pi(8M)
10. Draw the diagram for Pipeline stages used by ARM1176JZF-S: CPU Pipeline
1. Execution flow for ALU operations
2. Execution flow for Multiply operations
3. Execution flow for Load/Store operations