CD54HC283, CD74HC283, CD54HCT283, CD74HCT283

SCHS176E – NOVEMBER 1997 – REVISED JULY 2022

High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry

1 Features 2 Description
• Adds two binary numbers The CDx4HC283 and CDx4HCT283 contain 4-bit
• Full internal lookahead binary adders. The HCT device has TTL-voltage
• Fast ripple carry for economical expansion compatible inputs.
• Operates with both positive and negative logic
Device Information
• Fanout (over temperature range) (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Standard outputs 10 LSTTL loads
CD54HC283 J (CDIP, 16) 24.38 mm × 6.92 mm
– Bus driver outputs 15 LSTTL loads
• Wide operating temperature range: –55℃ to 125℃ CD74HC283CD74H D (SOIC, 16) 9.90 mm × 3.90 mm
C283
• Balanced propagation delay and transition times N (PDIP, 16) 19.31 mm × 6.35 mm
• Significant power reduction compared to LSTTL CD74HCT283CD74 D (SOIC, 16) 9.90 mm × 3.90 mm
Logic ICs HCT283
N (PDIP, 16) 19.31 mm × 6.35 mm
• HC types
– 2 V to 6 V operation (1) For all packages see the orderable addendum at the end of
the datasheet.
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
• HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility,
VIL = 0.8 V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 µA at VOL, VOH

Functional Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
SCHS176E – NOVEMBER 1997 – REVISED JULY 2022 www.ti.com

Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram........................................... 9
2 Description.......................................................................1 7.3 Feature Description.....................................................9
3 Revision History.............................................................. 2 8 Power Supply Recommendations................................10
4 Pin Configuration and Functions...................................3 9 Layout.............................................................................10
5 Specifications.................................................................. 4 9.1 Layout Guidelines..................................................... 10
5.1 Absolute Maximum Ratings(1) .................................... 4 10 Device and Documentation Support..........................11
5.2 Recommended Operating Conditions ........................4 10.1 Receiving Notification of Documentation Updates.. 11
5.3 Thermal Information....................................................4 10.2 Support Resources................................................. 11
5.4 Electrical Characteristics.............................................5 10.3 Trademarks............................................................. 11
5.5 Switching Characteristics ...........................................6 10.4 Electrostatic Discharge Caution.............................. 11
6 Parameter Measurement Information............................ 8 10.5 Glossary.................................................................. 11
7 Detailed Description........................................................9 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 9 Information.................................................................... 11

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2003) to Revision E (July 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1

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4 Pin Configuration and Functions

J, N, or D package
16-Pin CDIP, PDIP, or SOIC
Top View

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5 Specifications
5.1 Absolute Maximum Ratings(1)
MIN MAX UNIT
VCC Supply voltage – 0.5 7 V
IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA
IO Drain current, per output For –0.5 V < VO < VCC + 0.5 V ±25 mA
IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature range – 65 150 °C
Lead temperature (Soldering 10s)(SOIC - lead tips only) 300 °C

(1) Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.

5.2 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage range HC types 2 6 V
VI, VO DC input or output voltage 0 VCC V
2V 1000
Input rise and fall time 4.5 V 500 ns
6V 400
TA Temperature range –55 125 V

5.3 Thermal Information

D (SOIC) N (PDIP)
THERMAL METRIC 16 PINS 16 PINS UNIT
(1)
RθJA Junction-to-ambient thermal resistance 73 67 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.4 Electrical Characteristics

TEST VCC 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER UNIT
CONDITIONS(2) (V) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 1.5 1.5 1.5
High level input
VIH 4.5 3.15 3.15 3.15 V
voltage
6 4.2 4.2 4.2
2 0.5 0.5 0.5
Low level input
VIL 4.5 1.35 1.35 1.35 V
voltage
6 1.8 1.8 1.8
IOH = –20 μA 2 1.9 1.9 1.9
IOH = –20 μA 4.5 4.4 4.4 4.4 V
High level output
VOH IOH = –20 μA 6 5.9 5.9 5.9
voltage
IOH = –4 mA 4.5 3.98 3.84 3.7
V
IOH = –5.2 mA 6 6 5.34 5.2
IOL = 20 μA 2 0.1 0.1 0.1
IOL = 20 μA 4.5 0.1 0.1 0.1 V
Low level output
VOL IOL = 20 μA 6 0.1 0.1 0.1
voltage
IOL = 4 mA 4.5 0.26 0.33 0.4
V
IOL = 5.2 mA 6 0.26 0.33 0.4
Input leakage
II VCC or GND 6 ±0.1 ±1 ±1 µA
current
ICC Supply current VCC or GND 6 8 80 160 µA
HCT Types
High level input 4.5 to
VIH 2 2 2 V
voltage 5.5
Low level input 4.5 to
VIL 0.8 0.8 0.8 V
voltage 5.5
VOH High level output IOH = – 20 μA 4.5 4.4 4.4 4.4 V
VOH voltage IOH = – 4 mA 4.5 3.98 3.84 3.7 V
VOL Low level output IOL = 20 μA 4.5 0.1 0.1 0.1 V
VOL voltage IOL = 4 mA 4.5 0.26 0.33 0.4 V
Input leakage
II VCC to GND 5.5 ±0.1 ±1 ±1 µA
current
ICC Supply current VCC or GND 5.5 8 80 160 µA
CIN input held at 4.5 to
100 540 675 735 µA
VCC – 2.1 5.5
B1, A1, A0 inputs 4.5 to
100 360 450 490 µA
held at VCC – 2.1 5.5
(1) Additional supply
ΔICC B0 input held at 4.5 to
current per input pin 100 144 180 196 µA
VCC – 2.1 5.5
B3, A3, A2, B2
4.5 to
inputs held at VCC – 100 180 225 245 µA
5.5
2.1

(1) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
(2) VI = VIH or VIL, unless otherwise noted.

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5.5 Switching Characteristics

TEST 25℃ –40 to 85℃ –55℃ to 125℃
PARAMETER VCC (V) UNIT
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 160 200 240
CL = 50 pF
tPLH, Propagation delay 4.5 32 40 45
ns
tPHL CIN to S0 CL = 15 pF 5 13
CL = 50 pF 6 27 34 41
2 180 225 270
CL = 50 pF
tPLH, 4.5 36 45 54
CIN to S1 ns
tPHL CL = 15 pF 5 15
CL = 50 pF 6 31 38 46
2 195 245 295
CL = 50 pF
tPLH, 4.5 39 49 59
CIN to S2, CIN to COUT ns
tPHL CL = 15 pF 5 16
CL = 50 pF 6 33 42 50
2 230 290 345
CL = 50 pF
tPLH, 4.5 46 58 69
CIN to S3 ns
tPHL CL = 15 pF 5 19
CL = 50 pF 6 39 49 59
2 195 245 295
CL = 50 pF
tPLH, 4.5 39 49 59
An, Bn to COUT ns
tPHL CL = 15 pF 5 16
CL = 50 pF 6 33 42 50
2 210 265 315
CL = 5 0pF
tPLH, 4.5 42 53 63
An, Bn to Sn ns
tPHL CL = 15 pF 5 18
CL = 50 pF 6 36 45 54
2 75 95 110
tTLH,
Output transition time CL = 50 pF 4.5 15 19 22 ns
tTHL
6 13 16 19
CIN Input capacitance CL = 50 pF - 10 10 10 pF
Power dissipation
CPD 5 70 pF
capacitance(1) (2)
HCT TYPES

tPLH, Propagation delay CL = 15 pF 5 13

ns
tPHL CIN to S0 CL = 50 pF 4.5 31 39 47

tPLH, CL = 15 pF 5 18
CIN to S1 ns
tPHL CL = 50 pF 4.5 43 54 65

tPLH, CL = 15 pF 5 19
CIN to S2, CIN to COUT ns
tPHL CL = 50 pF 4.5 46 58 69

tPLH, CL = 15 pF 5 22
CIN to S3 ns
tPHL CL = 50 pF 4.5 53 66 80

tPLH, CL = 15 pF 5 20
An, Bn to COUT ns
tPHL CL = 50 pF 4.5 48 60 72

tPLH, CL = 15 pF 5 21
An, Bn to Sn ns
tPHL CL = 50 pF 4.5 49 61 74

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5.5 Switching Characteristics (continued)

TEST 25℃ –40 to 85℃ –55℃ to 125℃
PARAMETER VCC (V) UNIT
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
tTLH,
Output transition time CL = 50 pF 4.5 15 19 22 ns
tTHL
CIN Input capacitance 10 10 10 pF
Power dissipation
CPD 5 82 pF
capacitance(1) (2)

(1) CPD is used to determine the dynamic power consumption, per package.
(2) PD = VCC 2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

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6 Parameter Measurement Information

Test
Point

From Output
Under Test
CL(1)

1. Includes probe and test-fixture capacitance.

Figure 6-1. Load Circuit for Push-Pull Output

Figure 6-2. HC and HCT Transition Times and

Propagation Delay Times, Combination Logic

Figure 6-3. HCT Transition Times and Propagation Delay Times, Combination Logic

1. The greater between tr and tf is the same as tt.

2. The greater between tplh and tphl is the same as tpd.

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7 Detailed Description
7.1 Overview
The ’HC283 and ’HCT283 binary full adders add two 4-bit binary numbers and generate a carry-out bit if the sum
exceeds 15.
Because of the symmetry of the add function, this device can be used with either all active-high operands
(positive logic) or with all active-low operands (negative logic). When using positive logic the carry-in input must
be tied low if there is no carry-in.
7.2 Functional Block Diagram

7.3 Feature Description

• Balanced CMOS Push-Pull Outputs
• Clamp Diode Structure

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8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8976501EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8976501EA Samples
& Green CD54HC283F3A
CD54HC283F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8976501EA Samples
& Green CD54HC283F3A
CD54HCT283F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HCT283F3A Samples
& Green
CD74HC283E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC283E Samples

CD74HC283M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC283M Samples

CD74HCT283E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT283E Samples

CD74HCT283M OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 HCT283M

CD74HCT283M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HCT283M Samples

CD74HCT283MT OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 HCT283M

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC283, CD54HCT283, CD74HC283, CD74HCT283 :

• Catalog : CD74HC283, CD74HCT283

• Military : CD54HC283, CD54HCT283

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 1-Nov-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC283M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT283M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT283M96 SOIC D 16 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 1-Nov-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC283M96 SOIC D 16 2500 356.0 356.0 35.0
CD74HCT283M96 SOIC D 16 2500 356.0 356.0 35.0
CD74HCT283M96 SOIC D 16 2500 366.0 364.0 50.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 1-Nov-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC283E N PDIP 16 25 506 13.97 11230 4.32
CD74HC283E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT283E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT283E N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
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