Computer Organization and Architecture

UNIT 1
SYLLABUS:
Introduction: Functional units of digital system and their interconnections, buses, bus architecture, types
of buses and bus arbitration. Register, bus and memory transfer. Processor organization, general
registers organization, stack organization and addressing modes.

Computer Organization and Architecture

Computer Organization and Architecture is used to design computer systems.

Computer Architecture is considered to be those attributes of a system that are visible to the user like
addressing techniques, instruction sets, and bits used for data, and have a direct impact on the logic
execution of a program, It defines the system in an abstract manner, It deals with What does the system do.

Computer Organization is the way in which a system has to structure and It is operational units and the
interconnections between them that achieve the architectural specifications, It is the realization of the
abstract model, and It deals with How to implement the system.

Computer Architecture VS Computer Organization

Computer Architecture Computer Organization

Computer Architecture is concerned with the way Computer Organization is concerned with the
hardware components are connected together to form a structure and behaviour of a computer system as
computer system. seen by the user.

It acts as the interface between hardware and software. It deals with the components of a connection in a
system.

Computer Architecture helps us to understand the Computer Organization tells us how exactly all the
functionalities of a system. units in the system are arranged and interconnected.

A programmer can view architecture in terms of Whereas Organization expresses the realization of
instructions, addressing modes and registers. architecture.

While designing a computer system architecture is An organization is done on the basis of architecture.
considered first.
Computer Architecture deals with high-level design Computer Organization deals with low-level design
issues. issues.

Architecture involves Logic (Instruction sets, Addressing Organization involves Physical Components (Circuit
modes, Data types, Cache optimization) design, Adders, Signals, Peripherals)

Digital Computers
A Digital computer can be considered as a digital system that performs various computational tasks.

The first electronic digital computer was developed in the late 1940s and was used primarily for numerical
computations.

By convention, the digital computers use the binary number system, which has two digits: 0 and 1. A binary
digit is called a bit.

A computer system is subdivided into two functional entities: Hardware and Software.

The hardware consists of all the electronic components and electromechanical devices that comprise the
physical entity of the device.

The software of the computer consists of the instructions and data that the computer manipulates to
perform various data-processing tasks.

o The Central Processing Unit (CPU) contains an arithmetic and logic unit for manipulating data, a
number of registers for storing data, and a control circuit for fetching and executing instructions.
o The memory unit of a digital computer contains storage for instructions and data.
o The Random Access Memory (RAM) for real-time processing of the data.
o The Input-Output devices for generating inputs from the user and displaying the final results to the
user.
o The Input-Output devices connected to the computer include the keyboard, mouse, terminals,
magnetic disk drives, and other communication devices.

Basic Operational Concepts

o The primary function of a computer system is to execute a program, sequence of instructions. These
instructions are stored in computer memory.
o These instructions are executed to process data which are already loaded in the computer memory
through some input devices.
o After processing the data, the result is either stored in the memory for further reference, or it is
sent to the outside world through some output port.
o To perform the execution of an instruction, in addition to the arithmetic logic unit, and control unit,
the processor contains a number of registers used for temporary storage of data and some special
function registers.
o The special function registers include program counters (PC), instruction registers (IR), memory
address registers (MAR) and memory and memory data registers (MDR).
o The Program counter is one of the most critical registers in CPU.
o The Program counter monitors the execution of instructions. It keeps track on which instruction is
being executed and what the next instruction will be.
o The instruction register IR is used to hold the instruction that is currently being executed.
o The contents of IR are available to the control unit, which generate the timing signals that control,
the various processing elements involved in executing the instruction.
o The two registers MAR and MDR are used to handle the data transfer between the main memory
and the processor.
o The MAR holds the address of the main memory to or from which data is to be transferred.
o The MDR contains the data to be written into or read from the addressed word of the main
memory.
o Whenever the processor is asked to communicate with devices, we say that the processor is
servicing the devices. The processor can service these devices in one of the two ways.
o One way is to use the polling routine, and the other way is to use an interrupt.
o Polling enables the processor software to check each of the input and output devices frequently.
During this check, the processor tests to see if any devices need servicing or not.
o Interrupt method provides an external asynchronous input that informs the processor that it should
complete whatever instruction that is currently being executed and fetch a new routine that will
service the requesting device.
Buses

A bus is a set of wires. The elements of the computer are linked to the buses. It can transfer data from one
element to another, the source element outputs data onto the bus. The destination element then inputs this
information from the bus. As the complexity of a computer system improves, it becomes more effective (in
methods of minimizing connections) at using buses instead of a direct connection between each pair of devices.

It outputs this address to the memory bus, memory inputs this address from the address bus and uses it to
access the suitable memory location. Each I/O device including a keyboard, monitor, or disk drive, has a specific
address as well.

When accessing an I/O device, the CPU locates the address of the device on the address bus. Each device can
read the address off of the bus and specify whether it is the device being accessed by the CPU.

Data is shared via the data bus. When the CPU fetches information from memory, it first outputs the memory
address on its address bus. Therefore memory outputs the data onto the data bus, the CPU can read the
information from the data bus. When writing data to memory, the CPU first outputs the address onto the
address bus, therefore outputs the data onto the data bus.

The control bus is different from the other two buses. The address bus includes n lines, which associate to
transit one n-bit address value. The lines of the data bus work simultaneously to send a single, multi-bit value.

In contrast, the control bus is a collection of individual control signals. These signals indicate whether data is to
be read into or written out of the CPU, whether the CPU is accessing memory or an I/O device, and whether the
I/O device or memory is read to transfer data.

Although this bus is shown in the figure, it is a set of unidirectional signals. These signals are output from the
CPU to the memory and I/O subsystems, even though a few are output by these subsystems to the CPU. A
system can have an order of buses. For instance, it can use its address, data, and control buses to access
memory and an I/O controller. The I/O controller can access all I/O devices using a second bus known as the I/O
bus or a local bus.

Bus Structure
A system bus has typically from fifty to hundreds of distinct lines where each line is meant for a
certain function. These lines can be categorized into three functional groups i.e., data lines,
address lines, and control lines. Let us discuss them one by one each.

1. Data Lines

Data lines coordinate in transferring the data among the system components. The data lines
are collectively called data bus. A data bus may have 32 lines, 64 lines, 128 lines, or even more
lines. The number of lines present in the data bus defines the width of the data bus.

Each data line is able to transfer only one bit at a time. So the number of data lines in a data
bus determines how many bits it can transfer at a time. The performance of the system also
depends on the width of the data bus.

2. Address Lines

The content of the address lines of the bus determines the source or destination of the data
present on the data bus. The number of address lines together is referred to as the address
bus. The number of address lines in the address bus determines its width.
The width of the address bus determines the memory capacity of the system. The content of
address lines is also used for addressing I/O ports. The higher-order bits determine the bus
module, and the lower-ordered bits determine the address of memory locations or I/O ports.

3. Control Lines

The address lines and data lines are shared by all the components of the system, so there must
be some means to control the use and access of data and address lines. The control signals
placed on the control lines control the use and access to the address and data lines of the bus.
The control signal consists of the command and timing information. Here the command in the
control signal specifies the operation that has to be performed. And the timing information
over the control signals specifies when the data and address information is valid.

The control lines include the lines for:

• Memory Write: This command causes the data on the data bus to be placed over the
addressed memory location.
• Memory Read: This command causes the data on the addressed memory location to be
placed on the data bus.
• I/O Write: The command over this control line causes the data on the data bus to be
placed over the addressed I/O port.
• I/O Read: The command over this control line causes the data from the addressed I/O
port to be placed over the data bus.
• Transfer ACK: This control line indicates the data has been received from the data bus or
is placed over the data bus.
• Bus Request: This control line indicates that the component has requested control over
the bus.
• Bus Grant: This control line indicates that the bus has been granted to the requesting
component.
• Interrupt Request: This control line indicates that interrupts are pending.
• Interrupt ACK: This control line acknowledges when the pending interrupt is serviced.
• Clock: This control line is used to synchronize the operations.
• Reset: The bit information over this control line initializes all the modules.

Timing in Bus
As we have seen, the bus’s control lines also provide timing information along with the
command. Well, the way of deriving the timing information over the control line can be
categorized in two ways:
1. Synchronous Bus

With the synchronous bus scheme, all the devices or components connected to the bus derive
timing information over the control line referred to as the bus clock. Over the bus clock line, the
clock transmits an alternating sequence of 1s and 0s at regular intervals. A single 1-0
transmission is considered a clock or bus cycle.

2. Asynchronous Bus

The clock does not synchronise the transmitter and receiver components in this asynchronous
bus scheme. Instead, the data transfer is controlled using a handshake protocol between the
master component and the slave component.

In this way, the occurrence of one event on the bus is followed by and depends on the
occurrence of a previous event.

I/O Interface of Input Device Connected to Bus

In the section ahead, we will discuss how these three things over the bus are decoded by the
I/O interface.

Each I/O device interface has a set of registers with unique addresses. Whenever the processor
puts an address over the address line of the bus, it is examined by all the devices connected to
the bus. Whichever device recognizes this address responds to the control operations issued on
the control lines of the bus.

The processor issues read/write operation over the control lines of the bus, and the data
corresponding to the read and write operation is transmitted over the data lines of the bus.
Consider that we have an input device keyboard, and some data from the keyboard has to be
issued to the processor; the machine instruction for the same is:

Bus Arbitration
Bus Arbitration is the procedure by which the active bus master accesses the bus, relinquishes control of it,
and then transfers it to a different bus-seeking processor unit. A bus master is a controller that can access
the bus for a given instance.

A conflict could occur if multiple DMA controllers, other controllers, or processors attempt to access the
common bus simultaneously, yet only one is permitted to access. Bus master status can only be held by one
processor or controller at once. By coordinating the actions of all devices seeking memory transfers, the
Bus Arbitration method is used to resolve these disputes.

Two approaches are followed for the bus Arbitration:

1. Centralized Bus Arbitration - In which the necessary arbitration is carried out by a lone bus arbitrator.
2. Distributive Bus Arbitration - In which every device takes part in choosing the new bus master. A 4bit
identification number is allocated to each device on the bus. The created ID will decide the device's priority.

Centralized Bus Arbitration Methodologies

There are three methods of Centralized Bus Arbitration, which are listed below:

1. Daily Chaining Method - All bus masters work on the same line to make bus requests in this
straightforward and less expensive approach. Up until it comes across the first master who is making a
request for access to the bus, the bus grant signal travels serially through each master. Any other seeking
module will not receive the grant signal and hence be unable to access the bus since this master prevents
the bus grant signal from propagating.

Any device linked to the bus, such as the processor or any DMA controller unit, may act as the bus master
throughout any bus cycle.

Its Advantages:

o It is scalable and provides simplicity

o The user is free to add multiple devices to a predefined number of maximum devices wherever he wants
along the chain.

Its Disadvantages:

o A device's priority value is determined by the location of the master bus.

o Using this strategy results in propagation delay.
o The entire system will cease to function if one gadget malfunctions.
3. Rotating or Polling Priority Method - The address lines needed depend on how many connected
masters are in the system. The controller is utilized to produce the unique priority for the master (or
address). A series of master addresses are generated by the controller. The bus is used once the
asking master knows its address and activates the busy line.

Its Advantages:

o This approach is neutral in terms of processor and device preferences.

o The process is also straightforward.

Its Disadvantages:

o It is challenging to add bus masters since it increases the circuit's address line count.
o The system will continue to function even if one device malfunctions.

3. Independent Request or Fixed Priority Method - A unique pair of bus requests and bus grant lines are
provided to each master, and each pair is given a priority. The controller's built-in priority decoder chooses
the utmost priority request and then asserts the matching bus grant signal.

Its Advantage:

o This technique produces a quick response.

Its Disadvantage:

o A significant number of control lines are needed, which raises the cost of the hardware.

Computer Registers
Registers are a type of computer memory used to quickly accept, store, and transfer data and instructions
that are being used immediately by the CPU. The registers used by the CPU are often termed as Processor
registers.

A processor register may hold an instruction, a storage address, or any data (such as bit sequence or
individual characters).

The computer needs processor registers for manipulating data and a register for holding a memory
address. The register holding the memory location is used to calculate the address of the next instruction
after the execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic computer:

Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

The following image shows the register and memory configuration for a basic computer.

Backward Skip 10sPlay VideoForward Skip 10s

o The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the memory location.
o The Memory Address Register (MAR) contains 12 bits which hold the address for the memory location.
o The Program Counter (PC) also contains 12 bits which hold the address of the next instruction to be read
from memory after the current instruction is executed.
o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register (IR).
o The Temporary Register (TR) is used for holding the temporary data during the processing.
o The Input Registers (IR) holds the input characters given by the user.
o The Output Registers (OR) holds the output after processing the input data.

Register Transfer Language

A digital computer system exhibits an interconnection of digital modules such as registers, decoders,
arithmetic elements, and Control logic.

These digital modules are interconnected with some common data and control paths to form a complete
digital system.

Moreover, digital modules are best defined by the registers and the operations that are performed on the
data stored in them.

The operations performed on the data stored in registers are called Micro-operations.

The internal hardware organization of a digital system is best defined by specifying:

o The set of registers and the flow of data between them.

o The sequence of micro-operations performed on the data which are stored in the registers.
o The control paths that initiates the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations used to specify the sequence of
micro-operations.

In a computer system, data transfer takes place between processor registers and memory and between
processor registers and input-output systems. These data transfer can be represented by standard
notations given below:

o Notations R0, R1, R2..., and so on represent processor registers.

o The addresses of memory locations are represented by names such as LOC, PLACE, MEM, etc.
o Input-output registers are represented by names such as DATA IN, DATA OUT and so on.
o The content of register or memory location is denoted by placing square brackets around the name
of the register or memory location.

Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits that can perform a given
micro-operation and transfer the result of the operation to the same or another register.

Most of the standard notations used for specifying operations on various registers are stated below.

o The memory address register is designated by MAR.

o Program Counter PC holds the next instruction's address.
o Instruction Register IR holds the instruction being executed.
o R1 (Processor Register).
o We can also indicate individual bits by placing them in parenthesis. For instance, PC (8-15), R2 (5),
etc.
o Data Transfer from one register to another register is represented in symbolic form by means of
replacement operator. For instance, the following statement denotes a transfer of the data of
register R1 into register R2.

1. R2 ← R1

o Typically, most of the users want the transfer to occur only in a predetermined control condition.
This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
o It is more convenient to specify a control function (P) by separating the control variables from the
register transfer operation. For instance, the following statement defines the data transfer
operation under a specific control function (P).

1. P: R2 ← R1

The following image shows the block diagram that depicts the transfer of data from R1 to R2.
Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register R1 are
connected to the 'n' inputs of register R2.

A load input is activated by the control variable 'P' which is transferred to the register R2.

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information from one
register to another. The number of wires connecting all of the registers will be excessive if separate lines
are used between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information between registers in a
multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary information is
transferred one at a time. Control signals determine which register is selected by the bus during a particular
register transfer.

The following block diagram shows a Bus system for four registers. It is constructed with the help of four 4
* 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the input-output configuration of a
Bus system for four registers. For instance, output 1 of register A is connected to input 0 of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The
selection lines choose the four bits of one register and transfer them into the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four multiplexers are
selected and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive the
content of register A since the outputs of this register are connected to the 0 data inputs of the
multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by
register B.

The following function table shows the register that is selected by the bus for each of the four possible
binary values of the Selection lines.
Note: The number of multiplexers needed to construct the bus is equal to the number of bits in each register.
The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines. For instance, a common bus for
eight registers of 16 bits each requires 16 multiplexers, one for each line in the bus. Each multiplexer must
have eight data input lines and three selection lines to multiplex one significant bit in the eight registers.

A bus system can also be constructed using three-state gates instead of multiplexers.

The three state gates can be considered as a digital circuit that has three gates, two of which are signals
equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance
state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.
o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will communicate with the bus
line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point of time.

Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated below.

o The transfer of information from a memory unit to the user end is called a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from the memory word (M)
selected by the address register (AR).

And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory word (M) selected by
address register (AR).
General Register Organization
A set of flip-flops forms a register. A register is a unique high-speed storage area in the CPU. They include
combinational circuits that implement data processing. The information is always defined in a register before
processing. The registers speed up the implementation of programs.

Registers implement two important functions in the CPU operation are as follows −

• It can support a temporary storage location for data. This supports the directly implementing programs
to have fast access to the data if required.
• It can save the status of the CPU and data about the directly implementing program.

Example − Address of the next program instruction, signals get from the external devices and error messages,
and including different data is saved in the registers.

If a CPU includes some registers, therefore a common bus can link these registers. A general organization of
seven CPU registers is displayed in the figure.
The CPU bus system is managed by the control unit. The control unit explicit the data flow through the ALU by
choosing the function of the ALU and components of the system.

Consider R1 ← R2 + R3, the following are the functions implemented within the CPU −

MUX A Selector (SELA) − It can place R2 into bus A.

MUX B Selector (SELB) − It can place R3 into bus B.

ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).

Decoder Destination Selector (SELD) − It can transfers the result into R1.

The multiplexers of 3-state gates are performed with the buses. The state of 14 binary selection inputs
determines the control word. The 14-bit control word defines a micro-operation.

The encoding of register selection fields is specified in the table.

Encoding of Register Selection Field

Binary Code SELA SELB SELD

000 Input Input None

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7

There are several micro-operations are implemented by the ALU. Few of the operations implemented by the
ALU are displayed in the table.
Encoding of ALU Operations

OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 ADD A and B AND

01010 OR A and B OR

01100 XOR A and B XOR

01110 Complement A COMA

10000 Shift right A SHRA

11000 Shift left A SHLA

There are some ALU micro-operations are shown in the table.

ALU Micro-Operations

Micro-operation SELA SELB SELD OPR Control Word

R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010

R6 ← R6 + R1 - R6 R1 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 – None TSFA 010 000 000 00000

Output ← Input Input - None TSFA 000 000 000 00000

R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100