EXPERIMENT - 1

Aim:-
Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of
the data sheet, concept of Vcc and ground, verification of the truth tables of logic gates
using TTL ICs.

Apparatus Required:-
Digital lab kit, single strand wires, breadboard, TTL IC’s

Gates IC NO.

AND 7408

OR 7432

NAND 7400

NOR 7402

NOT 7404

XOR 74136

Theory:-
Logic gates are idealized or physical devices implementing a Boolean function, which it
performs a logical operation on one or more logical inputs and produce a single output.
Depending on the context, the term may refer to an ideal logic gate, one that has for
instance zero rise time and unlimited fan out or it may refer to anon-ideal physical device.

The main hierarchy is as follows:-

1. Basic Gates

2. Universal Gates

3. Advanced Gates
Basic Gates
1. AND gate: - Function of AND gate is to give the output true when both the inputs
are true. In all the other remaining cases output becomes false. Following table
justifies the statement:-

Input A Input B Output

1 1 1

1 0 0

0 1 0

0 0 0

IC 7408

2. OR gate: - Function of OR gate is to give output true when one of the either inputs
are true .In the remaining case output becomes false. Following table justify the
statement:-

Input A Input B Output

0 0 0

0 1 1

1 0 1

1 1 1
IC 7432

3. NOT gate: -Function of NOR gate is to reverse the nature of the input .It
converts true input to false and vice versa. Following table justifies the statement :-

Input Output

1 0

0 1

IC 7404
Universal Gates
1. NAND gate: -Function of NAND gate is to give true output when one of the
two provided input are false. In the remaining output is true case .Following table
justifies the statement :-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 1

IC 7400

2. NOR gate: - NOR gate gives the output true when both the two provided input
are false. In all the other cases output remains false. Following table justifies the
statement :-

Input A Input B Output

1 1 0

1 0 0

0 1 0

0 0 1
IC 7402

Advanced Gates
1. XOR gate: - The function of XOR gate is to give output true only when both the
inputs are true. Following table explain this:-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 0

IC 74136
Experiment No. 2
Procedure:-
 Place the breadboard gently on the observation table.
 Fix the IC which is under observation between the half shadow line of
breadboard, so there is no shortage of voltage.
 Connect the wire to the main voltage source (Vcc) whose other end is connected
to last pin of the IC (14 place from the notch).
 Connect the ground of IC (7th place from the notch) to the ground terminal
provided on the digital lab kit.
 Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using
connecting wires.(In accordance to IC provided).

 Connect output pins to the led on digital lab kit.

 Switch on the power supply.

 If led glows red then output is true, if it glows green output is false, which is
numerically denoted as 1 and 0 respectively. The Color can change based on the
IC manufacturer it’s just verification of the Truth Table not the color change.

Result:-
All gates are verified. Observed output matches theoretical concepts.

Precautions:-
 All connections should be made neat and tight.
 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires.

Aim: -Verification of state tables of

1. R-S flip-flop
2. J - K flip-flop
3. T Flip-Flop
4. D Flip-Flop

Using NAND and NOR gates.

Apparatus:- IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate).

Theory: -In case of sequential circuits the effect of all previous inputs on the
outputs is represented by a state of the circuit. Thus, the output of the circuit at any time
depends upon its current state and the input. These also determine the next state
of the circuit. The relationship that exists among the inputs, outputs, present states
and next states can be specified by either the state table or the state diagram.

State Table: -The state table representation of a sequential circuit consists of

three sections labelledpresent state next stateand output. T he p r e sen t s t a t e
d e s i gn a t e s t h e s t a t e o f f l i p - f l op s be f o re t h e occurrence of a clock
pulse. The next state shows the states of flip-flops after the clock pulse, and the
output section lists the value of the output variables during the present state.

Flip-Flop:-The basic one bit digital memory circuit is known as flip-flop.It can store
either 0or 1. Flip-flops are classifieds according to the number of inputs.

R-S Flip-Flop:- The circuit is similar to SR latch except enable signal is replaced by
clock pulse.
Logic Diagram

Characteristic table for S-R flip flop

D Flip-Flop:-The modified clocked SR flip-flop is known as D-flip-flop.From the truth
tableof SR flip-flop we see that the output of the SR flip-flop is in unpredictable state
when the inputsare same and high. In many practical applications, these input conditions
are not required. These inputconditions can be avoided by making then complement of
each other.

Logic Diagram

Characteristic table for D flip flop

J-K Flip-Flop:- In a RS flip-flop the input R=S=1 leads to an indeterminate output.

The RSflip-flop circuit may be re-joined if both inputs are 1 than also the outputs are
complement of each other.

Logic Diagram

Characteristic table for J-K flip flop

T Flip-Flop:-T flip-flop is known as toggle flip-flop. The T flip-flop is modification of
the J-K f l i p - f l op . Bot h t h e J K i np ut s of t h e J K f l i p - f l o p a r e h e l
d at
l o gic 1 an d t h e c l oc k s i gn a l continuous to change.

Logic Diagram

Characteristic table for T flip flop

Procedure:-
1. Co nn e c t i o n s a r e m a d e as p er ci rc ui t di a gr a m.
2. Verify truth-tables for various combinations of input .

RESULT: -Study and verified truth-tables of various flip-flops.

Precaution:- Experiment No. 3
1. All the IC’s should be checked before use the apparatus.
2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc
5. The circuit should be off before change the connections.6.After
completing the experiment switch off the supply to apparatus.

Aim: -Implementation and verification of decoder, de-multiplexer and encoder, using

logic gates.

Apparatus: -Digital trainer kit, 7432 IC, 7404 IC, 7411 IC and Connecting wires.

Theory:-

Decoder:-A decoder is a multi-inputand multi output combinational logic circuit which

converts coded input into coded outputs, where the input and output coded are different.

Logic Diagram of 2 to 4 decoder

Truth table of 2 to 4 decoder

Procedure:-
 Connect the supply from the trainer kit through patch cords; also connect circuit as
per circuit diagram.
 Give the input to A, B and EN trough switch.
 Observe the output Y0 to Y3 on the trainer kit through LEDs.
For different combinations of inputs observe the outputs and match them with truth
table.

ENCODER:-An encoder is a combinational logic circuit .It is the reverse of a decoder

function. It has 2 to the power n input and n output lines. An encoder accepts an active
level on one of its inputs representing a digit such as a decimal /octal digit and it convert
to coded output.

Encoder is used at the starting stage to encode the message into a unique code.
Encoder encodes different types of messages into various forms. In Digital Circuits it
encodes a decimal value into a binary word. The encoded binary word has number of bits
associated with it. The number of bits depends upon the decimal value which is being
encoded. For example in case of decimal values ranging from 0 to 7 the number of bits
required to encode these values is 3.

Logic diagram of encoder

Truth trable of encoder

Procedure:-

1. Connect the supply from the trainer kit through patch chords; also connect circuit as
per circuit diagram.

2. Givetheinputconnectionsto I0 , I 1 , I 2 a n d I 3 .

3. Observe the output Y0, Y1 on the trainer kit through LED’s

4. For different combinations of inputs observe the output and match the truth table

De- multiplexers:-.A demultiplexer sometimes abbreviated d-mux, is a circuit that has one
input and more than one output. It is used when a circuit wishes to send a signal to one of many
devices. This description sounds similar to the description given for a decoder, but a decoder is
used to select among many devices while a demultiplexer is used to send a signal among many
devices.

Logic diagram of demultiplexer

Truth table of demultiplexer

Procedure:-

1. Connect the supply from the trainer kit through patch chords, also connect
circuit as per circuit diagram

2. Give input connections at I, and at selection line.

3. Observe the output D0,D1 on the trainer kit through LED’s.

4. For different combinations of inputs observe the output and match the truth table
RESULT:-Truth tables of Encoder,de-multiplexers and decoder are verified

Precautions:-
 All connections should be made neat and tight.
 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires.
Experiment No. 4
Aim:-Implementation of 4x1 multiplexer, using logic gates.

Apparatus: -Digital trainer kit, AND-7411, OR-7432, NOT-7404 Gate IC, Connecting
wires.

Theory:-

MULTIPLEXER: -A multiplexer (MUX) is a device that accepts data from one of many
inputsources for transmission over a common shared line. To achieve this MUX
has severaldata lines and a single output along with data-select inputs, which permit
digital data onany of the inputs to be switched to the output line. The
logic symbol for a 1 to 4 dataselector/multiplexer is shown in Figure

Block diagram of multiplexer

The selection lines decide the number of inputs lines of particular multiplexer. If
the number of n inputs lines is equal to 2m, then m select lines are required to
select one of the n input line.

Note that if a binary zero appears on the data-select lines then data on input line D0
willappear on the output. Thus, data output Y is equal to D0 if and only if S1=0 and S0=0.

Y=D0.S1’.S0’Similarly, the data output is equal to D1, D2 and D3 for y=C1.S1’.S0’

,Y=C2.S0’. S1 and Y=C3.S0.S1 respectively. Thus the total multiplexer logic expression,
formed from ORing terms i

The implementation of this equation is as shown in figure:

Logic diagram of multiplexer

DATA SELECT INPUT INPUT

S1 S0
SELECTE

0 0 D0
0 1 D1
1 0 D2
1 1 D3

Truth table of mux

PROCEDURE:-
1. Connections are made as per circuit diagram.
2. Verify the truth table.

3. Also connect Vcc and Ground then performed experiment.

Result:-Study of 4×1 multiplexer and verified its truth table.
Precautions:-
1. All ICs should be checked before starting the experiment.
2. All the connection should be tight.
3. Always connect ground first and then connect Vcc.
4. Suitable type wire should be used for different types of circuit.
5. The kit should be off before change the connections.
6. After completed the experiments switch off the supply of the apparatus
Experiment No. 5

Objectives:

 To understand the operation of half-adders

 To understand the operation of full-adder
 To use Boolean simplification methods to reduce the number of gates in
the design
 To develop digital circuit building and troubleshooting skills

Text References:

Tocci Chapter 6 Sections 6-9 through 6-11

Components Needed:

 Two 7400 IC - quad two input NAND gate

Equipment Needed:

 Knight electronics ML-2001 logic trainer

 Logic Probe

Discussion:

This experiment will examine a method to add two binary numbers. The
technique uses two circuits, a half-adder and a full adder, to accomplish the
addition. When two (A and B) numbers (decimal, binary or any other number
base) are added the results is a SUM
(S) and possibly a CARRY (C). The half-adder performs this function at the bit
level with two inputs (Ax and Bx) and two outputs (SUMx and CARRYx) where x
is the bit number. The full-adder needs to be used when there is a carry bit
since the half-adder only has two inputs. The carry bit would be the third
input.

There is more than one logic design for the half- and full-adders. In this
experiment a truth table for the outputs of both adders will be created. K-
map simplification will be done and the simplified Boolean equation will be
converted to a NAND logic and built.
Procedure:

1. Half-Adder
1.1. Create the truth table for the SUM (S) and the CARRY (Cout) bit.
The inputs are A and B.

Inputs Theoretical Outputs Experimental Outputs

A B S Cout S Cout

Table 1
1.2. Read the Boolean equations from the truth table. It should be in SOP
form.
1.3. Draw the logic diagrams for the simplified Boolean equations S
and Cout.
1.4. Convert the logic diagrams for S and Cout to a NAND logic.
1.5. Build the circuits and test. Record the results on Table 1.

1.6. Compare and comment on the Table 1 results.

2. Full-Adder
2.1. Create the truth table for the SUM (S) and the CARRY (Cout) bit.
The inputs are A, B and Cin.
Inputs Theoretical Simulated Outputs
Outputs
A B Cin S Cout S Cout
Table 2
2.2. Create two K-maps for outputs S and Cout and derive the
simplified Boolean equations (if possible).

2.3. Draw the logic diagrams for the simplified Boolean equations S and
Cout.
EXPERIMENT-6

Aim: -Implementation of 4-bit parallel adder, using 7483 IC.

Apparatus:-

1. Digital Trainer Kit.

2. IC 7483

3. Connecting Wires

Theory:-

Adder: -An adder is a logic circuit which adds two or three bits at a time and give sum and
carry as the result.

Parallel Adder:-
A n-bit parallel adder can be constructed using number of full adders circuit connected in
parallel the carry output of each is connected to the carry input of the next higher-order
adder. Since all the bits of the augends and addend are fed into the adder circuits
simultaneously and the additions in each position are known as parallel adder.
A3 A2 A1 A0 → Augends bits
B3 B2 B1 B0 → Addend bits
S3 S2 S1 S0 → Sum bits
LOGIC DIAGRAM OF BCD ADDER

Pin diagram of IC 7483

Procedure:-
1 .Connect ground and Vcc to 7483 IC from trainer kit through patch cords.
2. Connect inputs A0, A1, A2, A3 and B0, B1, B2, B3 to logic input switches.
3. Connect carry in from pin no.13 to ground so that carry input (CY1) will be logic
‘0’state.

4. Connect S0, S1, S2, S3 and carry out (CY0) from pin nos. 9, 6, 2, 15 and 14 to
the outputdisplay.5.Verify truth tables for different combinations of inputs.
TRUTH TABLE:-
The Truth table operation of the 4-bit Parallel Adder is shown below:

INPUTS OUTPUTS

A0 A1 A2 A3 B0 B1 B2 B3 CY1 S0 S1 S2 S3 CY0
0 0 0 1 0 1 0 1 1 1 1 0 0 1
1 0 0 0 1 1 1 0 0 0 0 0 0 1

Result:-

For various combinations of selected input lines, observed the LED output and verified the
truth table.
Precautions:-
1. All ICs should be checked before starting the experiment.
2. All the connection should be tight.
3. Always connect ground first and then connect Vcc.
4. Suitable type wire should be used for different types of circuit.
5. The kit should be off before change the connections.
6. After completed the experiments switch off the supply of the apparatus.

1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Experiment No:7

AIM: To verify the truth table of 4- bit adder and 2's compliment subtractor circuit using a 4-bit adder
IC(7483) are verified
Apparatus: Logic trainer kit, 4-bit adder (IC 7483), X-OR gates (IC 7486), wires

Theory: IC 7483 is a 4 bit adder. In binary, subtraction can be performed by using 2's complement
method. In this method negative number is converted into its 2's complement and it is added to
the other number. The result of this addition is the subtraction of origin numbers.
If we modify the adder circuit, such that 2's complement and simple representation are presented, we
can perform addition subtraction as required. X-OR gate is used as a controlled inverter/ buffer
for this purpose. Use it as buffer for addition and inverter for subtraction.

Procedure:
1. Connect the IC 7483 and IC 7486 as per diagram.
2. Connect all A's and all B's to logic sources, S's to logic indicators.
3. Connect Cin to logic 0, this will set the circuit for addition.
4. Give various input combinations, verify adder operation. Here Cout is MSB of addition.
5. Connect Cin to logic 1, this will set the circuit for subtraction by 2's complement method.
6. Give various input combinations and observe outputs. Here Cout is neglected (2's
complement subtraction)
7. Switch off power supply

Precautions: All the connections should be made properly.

Result: The truth table of 4- bit adder, 2's compliment subtractor circuit using a 4-bit adder IC are
verified.
Experiment No. 8
Aim:- Design, and verify the 4-bit synchronous counter.

Apparatus:-

S.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 4 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35
Theory:-
Synchronous counter: -A simple way of implementing the logic for each bit of an
ascending counter (which is what is depicted in the image to the right) is for each bit to
toggle when all of the less significant bits are at a logic high state. For example, bit 1
toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3
toggles when bit 2, bit 1 and bit 0 are all high; and so on.
Synchronous counters can also be implemented with hardware finite state machines.Which
are more complex but allow for smoother, more stable transitions?
Hardware-based counters are of this type and they can be implemented using the IC 7476

PIN DIAGRAM FOR IC 7476:

TRUTH TABLE:-
Input PresentState NextState A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X

0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 1

0 0 1 0 0 0 1 0 X X 1 1 X

0 0 0 1 0 0 0 0 X 0 X X 1

1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1
TRUTH TABLE OF 4 BIT SYNCHRONOUS COUNTERS

LOGIC DIAGRAM

State diagram
Procedure:-
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

Result: -Study of 4 bit synchronous counters and verified its truth table.

Precautions:-
1. All ICs should be checked before starting the experiment.

2. All the connection should be tight.

3. Always connect ground first and then connect Vcc.

4. Suitable type wire should be used for different types of circuit.

5. The kit should be off before change the connections.

6. After completed the experiments switch off the supply of the apparatus
Experiment No. 9

AIM: - To design and verify 4 bit ripple (asynchronous counter).

APPARATUS REQUIRED:-

S.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2

2. NAND GATE IC 7400 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 30

THEORY:-
A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter.
There are two types of counter, synchronous and asynchronous. In synchronous common
clock is given to all flip flop and in asynchronous first flip flop is clocked by external
pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A
soon the clock of second stage is triggered by output of first stage. Because of inherent
propagation delay time all flip flops are not activated at same time which results in
asynchronous operation.
PIN DIAGRAM FOR IC 7476:
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:-
CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1
Procedure:-
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

Result: -
Study of 4 bit synchronous counter and verified its truth table

Precautions:-

1. All ICs should be checked before starting the experiment.

2. All the connection should be tight.
3. Always connect ground first and then connect Vcc.
4. Suitable type wire should be used for different types of circuit.
5. The kit should be off before change the connections.
6. After completed the experiments switch off the supply of the apparatus