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Pochi ReddyGenus Attribute Reference
Product Version 23.1
March 2025
© 2025 Cadence Design Systems, Inc.
Printed in the United States of America.
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Genus Attribute Reference
Table of Contents
Contents
About This Manual 112
Additional References 112
Reporting Problems or Errors in Manuals 113
Customer Support 113
Cadence Online Support 113
Other Support Offerings 114
Supported User Interfaces 114
Message Details 115
Man Pages 116
Command-Line Help 116
Getting the Syntax for a Command 116
Getting Attribute Help 117
Searching For Commands When You Are Unsure of the Name 117
Documentation Conventions 118
Text Command Syntax 118
New Attributes 118
New in 23.14 119
New in 23.13 120
New in 23.12 121
New in 23.11 121
1 123
Introduction 123
More on Attributes and Objects 123
Setting and Getting Attribute Values 123
actual_scan_chain Attributes 124
actual_scan_segment Attributes 125
analysis_view Attributes 125
constraint_mode Attributes 125
delay_corner Attributes 126
design Attributes 126
hinst Attributes 127
inst Attributes 127
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library_domain Attributes 127
library_set Attributes 128
mode Attributes 128
module Attributes 128
rc_corner Attributes 129
root Attributes 129
timing_condition Attributes 129
2 130
General 130
attribute Attributes 130
additional_help 131
category 131
check_function 132
compute_function 132
data_type 132
default_value 133
help 133
indices 133
is_computed 133
is_hidden 134
is_obsolete 134
is_saved 134
is_settable 134
is_user_defined 135
possible_values 135
set_function 135
skip_in_db 135
units 136
base_cell Attributes 136
drive_strength 136
logic_function 136
voltage_threshold_group 136
command Attributes 136
category 137
help 137
tcl_defined 137
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usage 137
version 138
command_option Attributes 138
command 138
data_type 138
help 138
is_list 139
required 139
3 140
Tcl User Interface 140
all Attributes in TUI 141
accept_user_defined_attributes 141
base_name 142
escaped_name 142
max_print 142
name 143
obj_type 143
screen_max_print 144
attribute_path 144
attributes 145
beta_feature 145
145
categories 145
cmd_file 145
command_log 146
commands 146
common_ui 146
continue_on_error 146
cpu_runtime 146
design Attributes in TUI 147
obsolete_state 147
state 147
state_ignore_cdn_exception_buff 148
dont_report_library 148
dont_report_operating_conditions 149
elapsed_runtime 149
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enable_ui_precision 149
fail_on_error_mesg 149
floorplan_default_blockage_name_prefix 150
150
get_db_display_limit 150
heartbeat 150
heartbeat_print_date 150
information_level 151
init_ground_nets 151
init_lib_search_path 152
init_min_dbu_per_micron 152
init_oa_abstract_views 153
init_oa_default_rule 153
init_oa_foundry_rule 153
init_oa_layout_views 154
init_oa_ref_libs 154
init_oa_search_libs 154
init_oa_special_rule 154
init_physical_only 154
init_power_nets 155
init_state 155
155
limited_access_feature 156
load_average 156
156
log_command_error 156
log_file 157
memory_usage 157
mesg_severity_downgrade 157
message Attributes 158
count 158
help 158
help_always_visible 159
id 159
print_count 160
priority 161
screen_print_count 161
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severity 162
truncate 162
type 163
messages 170
obj_types 170
path 171
peak_memory 171
physical_memory_usage 172
platform_wordsize 172
print_error_info 172
program_major_version 172
program_name 173
program_short_name 173
program_version 173
prompt_print_cwd 173
173
real_runtime 174
report_library_message_summary 174
report_tcl_command_error 175
restore_history_file 175
save_history_file 176
script_search_path 176
set_db_verbose 177
show_report_options 177
source_suspend_on_error 178
source_verbose 178
source_verbose_info 178
source_verbose_proc 179
startup_license 179
stdout_log 179
179
support_ui_units 180
tcl_partial_cmd_argument_matching 180
tcl_return_display_length_limit 180
tinfo_include_load 180
tinfo_tstamp_file 181
trigger_post_time_info 181
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ui_precision 181
ui_precision_capacitance 182
ui_precision_derating 182
ui_precision_power 183
ui_precision_sensitivities 184
ui_precision_timing 184
ui_units_capacitance 185
185
ui_units_timing 186
xm_protect_version 186
4 188
Unified Metrics 188
metric_advanced_url_endpoint 188
metric_capture_3d_hotspots 188
metric_capture_depth 188
metric_capture_design_image 189
metric_capture_design_image_blockages 189
metric_capture_design_image_blockages_threshold 189
metric_capture_design_image_power_intent 189
metric_capture_design_image_route_drc 190
metric_capture_max_drc_markers 190
metric_capture_min_count 190
metric_capture_overwrite 190
metric_capture_pba_tns_histogram 190
metric_capture_per_view 190
metric_capture_reg2reg_metrics 191
metric_capture_timing_analysis_mode 191
metric_capture_timing_path_groups 191
metric_capture_timing_paths 192
metric_capture_tns_histogram 192
metric_capture_tns_histogram_buckets 192
metric_capture_tns_histogram_max_slack 192
metric_capture_tns_histogram_paths 192
metric_capture_vth_metrics 192
metric_capture_vth_per_power_domain 193
metric_category_default 193
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metric_current_run_id 193
metric_enable 193
metric_summary_metrics 193
5 194
Flow Attributes 194
flow Attributes for Flows 194
feature_values 194
features 194
owner 195
run_count 195
skip_metric 195
steps 195
tool 195
tool_options 196
flow_step Attributes for Flows 196
begin_tcl 196
body_tcl 197
categories 197
check_tcl 197
end_tcl 197
exclude_time_metric 198
feature_values 198
features 198
owner 198
quiet 198
run_count 198
skip_db 198
skip_metric 199
status 199
root attributes for Flows 199
design_flow_effort 200
flow_branch 200
flow_caller_data 201
flow_db_directory 201
flow_error_errorinfo 201
flow_error_message 201
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flow_error_write_db 201
flow_exclude_time_for_init_flow 201
flow_exit_when_done 202
flow_feature_values 202
flow_features 202
flow_footer_tcl 202
flow_header_tcl 203
flow_hier_path 203
flow_history 203
flow_log_directory 203
flow_log_prefix_generator 203
flow_mail_on_error 204
flow_mail_to 204
flow_metrics_file 205
flow_metrics_snapshot_parent_uuid 205
flow_metrics_snapshot_uuid 205
flow_overwrite_db 205
flow_plugin_names 206
flow_plugin_steps 206
flow_post_db_overwrite 206
flow_remark 207
flow_report_directory 207
flow_run_tag 207
flow_schedule 207
flow_starting_db 207
flow_startup_directory 208
flow_status_file 208
flow_step_begin_tcl 208
flow_step_canonical_current 208
flow_step_check_tcl 208
flow_step_current 209
flow_step_end_tcl 209
flow_step_last 209
flow_step_last_msg 209
flow_step_last_status 209
flow_step_next 209
flow_steps 210
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flow_summary_tcl 210
flow_template_feature_definition 210
flow_template_tools 210
flow_template_type 210
flow_template_version 210
flow_top 211
flow_user_templates 211
flow_verbose 211
flow_working_directory 211
flow_write_db_snapshot 211
flow_write_db_snapshot_exclude_time 212
flow_yamllint_exec 212
flows 212
flowtool_exit_timeout 213
flowtool_extra_arguments 213
flowtool_metrics_qor_excel 213
flowtool_metrics_qor_html 214
flowtool_metrics_qor_text 214
flowtool_metrics_qor_vivid 215
flowtool_predict_full_names 215
flowtool_schedule_flow_immediate 216
flowtool_summary_tcl 216
6 217
Hierarchical Flow 217
assemble_design_generic_hier 217
217
ilm_filter_internal_path 218
ilm_keep_async 218
218
is_ilm 219
7 220
Design for Manufacturing 220
yield 220
8 222
Elaboration and Synthesis 222
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All Attributes in Elab-N-Synth 222
blackbox 222
cross_probe_frc_value 223
encrypted 223
group 224
hdl_convert_onebit_vector_to_scalar 225
hdl_convert_onebit_vector_wire_to_scalar 226
hdl_preserve_signals 227
227
hdl_proc_name 227
227
instances 228
228
ungroup 229
design Attributes for Elab-n-Synth 229
arch_filename 229
arch_name 230
embedded_script 230
entity_filename 231
entity_name 231
hdl_all_filelist 232
hdl_config_name 233
hdl_cw_list 233
hdl_elab_command_params 234
hdl_filelist 234
hdl_parameters 235
hdl_user_name 236
hdl_vdp_list 236
language 237
library_name 237
logic_abstract 238
hdl_subprogram Attributes for Elab-n-Synth 238
map_to_module 238
map_to_operator 239
return_port 239
hnet Attributes for Elab-n-Synth 239
constant 239
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dont_touch 240
hpin Attributes for Elab-n-Synth 240
cap_violation 240
cap_violation_by_mode 241
constant 241
dont_touch 241
fo_violation 242
fo_violation_by_mode 242
iopt_avoid_tiecell_replacement 242
lssd_master_clock 242
prune_unused_logic 243
trans_violation 243
trans_violation_by_mode 243
hport Attributes for Elab-n-Synth 243
constant 243
iopt_avoid_tiecell_replacement 244
lssd_master_clock 244
net Attributes for Elab-n-Synth 244
dont_touch 245
pg_pin Attributes for Elab-n-Synth 245
constant 245
pin Attributes for Elab-n-Synth 246
cap_violation 246
cap_violation_by_mode 246
constant 246
dont_touch 247
fo_violation 247
fo_violation_by_mode 248
iopt_avoid_tiecell_replacement 248
lssd_master_clock 248
trans_violation 248
trans_violation_by_mode 248
port Attributes for Elab-n-Synth 249
cap_violation 249
cap_violation_by_mode 249
constant 249
fo_violation 250
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fo_violation_by_mode 250
ignore_external_driver_drc 250
iopt_avoid_tiecell_replacement 250
lssd_master_clock 251
trans_violation 251
trans_violation_by_mode 251
root Attributes for Elab-n-Synth 251
dp_ungroup_separator 252
frc_treat_modules_as_leaf_insts 253
hdl_allow_inout_const_port_connect 253
hdl_allow_instance_name_conflict 253
hdl_allow_positional_connections_for_pg_inst 254
hdl_append_generic_ports 254
hdl_array_naming_style 255
hdl_async_set_reset 256
hdl_auto_async_set_reset 256
hdl_auto_exec_sdc_scripts 257
hdl_auto_sync_set_reset 258
hdl_bidirectional_assign 258
hdl_bidirectional_wand_wor_assign 259
hdl_bus_wire_naming_style 260
hdl_case_mux_threshold 260
hdl_case_sensitive_instances 261
hdl_cdfg_early_redundancy_removal 261
hdl_create_label_for_unlabeled_generate 262
hdl_decimal_parameter_name 262
hdl_delete_transparent_latch 263
hdl_enable_proc_name 263
hdl_enable_real_support 264
hdl_error_on_blackbox 264
hdl_error_on_latch 264
hdl_error_on_logic_abstract 265
hdl_error_on_negedge 265
hdl_exclude_params_in_cell_search 266
hdl_ff_keep_explicit_feedback 266
hdl_ff_keep_feedback 267
hdl_flatten_complex_port 268
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hdl_flatten_complex_port_in_bottom_up_flow 268
hdl_generate_index_style 269
hdl_generate_separator 269
hdl_ignore_pragma_names 270
hdl_index_mux_threshold 270
hdl_instance_array_naming_style 271
hdl_interface_separator 271
hdl_keep_first_module_definition 271
hdl_language 272
hdl_latch_keep_feedback 272
hdl_libraries 273
273
hdl_link_from_any_lib 273
hdl_max_loop_limit 274
hdl_max_map_to_mux_control_width 274
hdl_max_memory_address_range 275
hdl_max_recursion_limit 275
hdl_module_definition_resolution 275
hdl_nc_compatible_module_linking 276
hdl_new_bidirectional_assign 277
hdl_overwrite_command_line_macros 277
hdl_parameter_naming_style 278
hdl_parameterize_module_name 279
hdl_preserve_async_sr_priority_logic 279
hdl_preserve_dangling_output_nets 279
hdl_preserve_supply_nets 280
hdl_preserve_sync_ctrl_logic 281
hdl_preserve_sync_set_reset 281
hdl_preserve_unused_flop 282
hdl_preserve_unused_latch 283
hdl_preserve_unused_registers 285
hdl_primitive_input_multibit 287
hdl_record_naming_style 287
hdl_reg_array_naming_style 288
hdl_reg_naming_style 288
hdl_reg_record_naming_style 288
hdl_rename_cdn_flop_pins 289
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hdl_rename_cdn_latch_pins 289
hdl_report_case_info 290
hdl_resolve_instance_with_libcell 290
hdl_resolve_parameterized_instance_with_structural_module 291
hdl_sv_module_wrapper 293
hdl_sync_set_reset 293
hdl_track_filename_row_col 294
hdl_track_module_elab_memory_and_runtime 294
hdl_unconnected_value 295
hdl_use_block_prefix 301
hdl_use_case_generate_prefix 301
hdl_use_current_dir_before_hdl_search_path 301
hdl_use_cw_first 302
hdl_use_default_parameter_values_in_name 302
hdl_use_for_generate_prefix 303
hdl_use_if_generate_prefix 303
hdl_use_port_default_value 304
hdl_verilog_defines 304
hdl_vhdl_assign_width_mismatch 305
hdl_vhdl_case 305
hdl_vhdl_environment 306
hdl_vhdl_lrm_compliance 306
hdl_vhdl_preferred_architecture 307
hdl_vhdl_range_opto 307
hdl_vhdl_read_version 308
hdl_zero_replicate_is_null 308
init_blackbox_for_undefined 309
init_hdl_search_path 310
input_assert_one_cold_pragma 310
input_assert_one_hot_pragma 311
input_asynchro_reset_blk_pragma 311
input_asynchro_reset_pragma 312
input_case_cover_pragma 312
input_case_decode_pragma 312
input_map_to_mux_pragma 313
input_pragma_keyword 313
input_synchro_enable_blk_pragma 314
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input_synchro_enable_pragma 314
input_synchro_reset_blk_pragma 315
input_synchro_reset_pragma 315
proto_hdl 316
script_begin 316
script_end 316
synthesis_off_command 317
synthesis_on_command 317
9 319
GUI 319
gui_auto_update 319
gui_enabled 320
gui_hv_phys_threshold 321
gui_hv_threshold 321
gui_pv_highlight_hier_instances_show_legend 322
gui_show_old_legend 323
gui_sv_threshold 323
gui_sv_update 324
gui_visible 325
imm_block_view_brightness 326
win_fp_inst_threshold 326
10 328
ChipWare 328
avoid 329
bit_width 330
candidate_impls 331
constraint 332
cw_library_version 333
cwd_setup_file 333
designware_compatibility 334
formula 334
hdl_parameter 335
legal 336
obsolete 336
operator 337
param_association 337
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parameters 338
permutable_group 339
pin_association 340
pre_elab_script 340
preferred_comp 341
preferred_impl 342
preserve_techelts 344
report_as_datapath 345
selected_impl 346
signed 347
speed_grade 347
sub_arch 348
technology 349
unbound_oper_pin 349
user_speed_grade 350
user_sub_arch 351
11 352
Library Attributes 352
Additional Attributes for Library 352
All Attributes for Library 352
constraint_high 353
corresponding_q_or_qn_pin 353
dont_merge_multibit 353
dont_split_multibit 354
is_auto_library_domain 354
is_synchronizer 354
is_usable 355
355
leakage_power_scale_in_nW 355
355
lib_cell 356
356
library_domain 356
356
library_side_file 358
merge_multibit 358
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power_library 359
sync_enable_pins 359
timing_model_reason 359
tristate 360
unusable_reason 360
via_variation_file 360
voltage 361
base_cell_set Attributes for Library 362
base_cells 362
orig_base_cells 362
base_cell Attributes for Library 362
area 363
base_class 364
base_pins 364
bottom_padding 364
class 364
dont_touch 364
dont_use 364
integrated_clock_gating_type 365
is_always_on 365
is_black_box 365
is_combinational 365
is_eeq_cell 366
is_fall_edge_triggered 366
is_inferred_macro 366
is_interface_timing 366
is_iso_nor 366
is_macro 367
is_master_slave_flop 367
is_master_slave_lssd_flop 367
is_memory 367
is_negative_level_sensitive 367
is_pad 368
is_physical_defined 368
is_pll 368
is_positive_level_sensitive 368
is_power_on_bottom 368
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is_power_switch 369
is_rise_edge_triggered 369
is_sequential 369
is_timing_defined 369
is_timing_model 369
is_tristate 370
left_padding 370
level_shifter_type 370
lib_cells 370
library_set 370
master_physical_variant_cell 371
num_base_pins 371
pg_base_pins 371
physical_variant_cells 371
right_padding 372
symmetry 372
timing_model_type 372
top_padding 372
base_pin Attributes for Library 372
base_cell 373
is_always_on 373
is_analog 373
is_async 373
is_isolated 374
is_isolation_cell_clock 374
is_isolation_cell_data 374
is_isolation_cell_enable 374
is_level_shifter_enable 375
is_power_switch_enable 375
is_retention_cell_enable 375
is_unconnected 375
pg_type 376
related_ground_pin 376
related_power_pin 376
restore_action 376
restore_edge_type 376
save_action 376
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tied_to 377
use 377
internal_power 377
377
is_backside 378
378
level_shifter_group Attributes for Library 378
ground_direction 379
level_shifter_cells 379
max_ground_input_voltage 379
max_ground_output_voltage 379
max_input_voltage 380
max_output_voltage 380
min_ground_input_voltage 380
min_ground_output_voltage 381
min_input_voltage 381
min_output_voltage 381
valid_location 381
lib_arc Attributes for Library 382
drive_resistance_fall 382
drive_resistance_rise 382
enabled 382
from_lib_pin 383
is_disabled 383
liberty_attributes 383
mode 383
real_enabled 383
sdf_cond 384
sdf_conf 384
sense 384
timing_type 384
to_lib_pin 384
when 384
lib_cell Attributes for Library 384
area 387
area_multiplier 387
async_clear_pins 387
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async_preset_pins 387
backup_power_pins 388
base_cell 388
bottom_padding 388
cell_delay_multiplier 388
cell_min_delay_multiplier 388
class 389
clock_pins 389
combinational 389
congestion_avoid 389
constraint_multiplier 390
data_pins 390
dont_touch 390
dont_use 390
failure_probability 390
has_lvf 391
has_non_seq_setup_arc 391
height 391
integrated_clock_gating_type 391
is_adder 391
is_always_on 391
is_black_box 392
is_clock_isolation_cell 392
is_combinational 392
is_dummy_scmr_iw_cell 392
is_eeq_cell 392
is_fall_edge_triggered 392
is_inferred_macro 393
is_interface_timing 393
is_isolation_cell 393
is_macro 393
is_master_slave_flop 394
is_master_slave_lssd_flop 394
is_memory 394
is_negative_level_sensitive 394
is_pad 394
is_pll 395
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is_positive_level_sensitive 395
is_power_switch 395
is_retention_cell 395
is_rise_edge_triggered 395
is_sequential 396
is_timing_model 396
is_tristate 396
keep_as_physical 396
latch_enable 396
latch_enable_pins 397
leakage_scale_factor 397
lef_inconsistent 397
left_padding 397
level_shifter_direction 398
level_shifter_type 398
level_shifter_valid_location 398
lib_arcs 398
lib_pins 398
liberty_attributes 398
library 399
master_physical_variant_cell 399
max_ground_input_voltage 399
max_ground_output_voltage 400
max_input_voltage 400
max_output_voltage 400
min_ground_input_voltage 401
min_ground_output_voltage 401
min_input_voltage 401
min_output_voltage 401
mode_definition 402
non_seq_setup_arc 402
num_base_pins 402
pg_lib_pins 402
physical_variant_cells 402
power_gating_cell 403
power_gating_cell_type 403
preserve_avoid 403
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primary_power 404
required_condition 404
right_padding 404
scan_enable_pins 404
scan_in 404
scan_in_pins 404
scan_out 405
scan_out_pins 405
seq_functions 405
sequential 405
short 405
std_cell_main_rail_pin 405
switch_off_enables 406
switched_power 406
symmetry 406
sync_clear_pins 406
sync_preset_pins 406
timing_model_type 406
top_padding 407
tristate 407
type_changed_pin_names 407
usable_flop 407
usable_latch 407
width 407
lib_pin Attributes for Library 408
alive_during_partial_power_down 410
alive_during_power_up 410
all_q_pin_of_d_pin 410
all_qb_pin_of_d_pin 410
async_clear_polarity 410
async_preset_polarity 411
base_pin 411
bundle 411
capacitance 411
capacitance_max_fall 412
capacitance_max_rise 412
capacitance_min_fall 412
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capacitance_min_rise 412
capacitance_rf 413
clock_polarity 413
drive_resistance 413
driver_type 413
fanout_load 414
from_lib_arcs 414
function 414
function_type 414
higher_drive_pin 415
is_always_on 415
is_analog 415
is_async 415
is_clock 416
is_data 416
is_generated_clock 416
is_ground 417
is_inverted 417
is_iq_function 417
is_iqn_function 417
is_isolated 418
is_isolation_cell_clock 418
is_isolation_cell_data 418
is_isolation_cell_enable 418
is_level_shifter_enable 419
is_pad 419
is_power 419
is_power_switch_enable 419
is_retention_cell_enable 419
is_scan_out 420
is_scan_out_inverted 420
is_std_cell_main_rail 420
is_tristate 420
is_unconnected 420
isolation_enable_condition 421
isolation_enable_phase 421
latch_enable_polarity 421
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Table of Contents
liberty_attributes 421
lower_drive_pin 422
min_capacitance 422
min_fanout 422
min_transition 422
mother_power 423
non_seq_setup_arc 423
pg_function 423
pg_type 423
physical_connection 423
power_gating_class 424
power_gating_pin_phase 424
power_gating_polarity 424
pulse_clock 425
rail_connection 425
related_bias_pin 425
related_ground_pin 425
related_power_pin 426
restore_action 426
restore_edge_type 426
save_action 426
scan_enable_polarity 426
scan_in_polarity 426
signal_level 427
slew_threshold_percent_fall_high 427
slew_threshold_percent_fall_low 427
slew_threshold_percent_rise_high 427
slew_threshold_percent_rise_low 427
stack_via_list 427
stack_via_required 427
switch_off_enable_polarity 428
sync_clear_polarity 428
sync_enable_polarity 428
sync_preset_polarity 428
tied_to 428
to_lib_arcs 429
tristate 429
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Table of Contents
use 429
user_function 429
voltage_name 430
voltage_value 430
x_offset 430
y_offset 430
library Attributes for Library 430
cap_scale_in_ff 431
default_opcond 431
default_power_rail 431
default_wireload 432
files 432
has_cells_having_power_ground_pins 432
input_threshold_pct_fall 432
input_threshold_pct_rise 432
lib_cells 432
liberty_attributes 433
library_type 433
max_operating_voltage 433
min_operating_voltage 433
nominal_process 434
nominal_temperature 434
nominal_voltage 434
operating_conditions 434
output_threshold_pct_fall 434
output_threshold_pct_rise 434
power_rails 435
slew_derate_from_library 435
slew_lower_threshold_pct_fall 435
slew_lower_threshold_pct_rise 435
slew_upper_threshold_pct_fall 436
slew_upper_threshold_pct_rise 436
time_scale_in_ps 436
usable_comb_cells 436
usable_seq_cells 437
usable_timing_models 437
version 437
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Table of Contents
wireload_models 437
wireload_selections 437
operating_condition Attributes for Library 437
liberty_attributes 437
library 438
process 438
temperature 438
tree_type 438
pg_base_pin Attributes for Library 438
base_cell 439
pg_type 439
tied_to 439
pg_lib_pin Attributes for Library 439
all_q_pin_of_d_pin 441
async_clear_polarity 441
async_preset_polarity 442
base_pin 442
bundle 442
capacitance 442
capacitance_max_fall 442
capacitance_max_rise 443
capacitance_min_fall 443
capacitance_min_rise 443
capacitance_rf 443
clock_polarity 444
drive_resistance 444
driver_type 444
fanout_load 444
from_lib_arcs 445
function 445
function_type 445
higher_drive_pin 445
is_always_on 446
is_async 446
is_data 446
is_generated_clock 446
is_ground 447
March 2025 28 Product Version 23.1
Genus Attribute Reference
Table of Contents
is_inverted 447
is_iq_function 447
is_iqn_function 447
is_isolated 447
is_isolation_cell_clock 448
is_isolation_cell_enable 448
is_level_shifter_enable 448
is_pad 448
is_power 448
is_scan_out 449
is_scan_out_inverted 449
is_std_cell_main_rail 449
is_tristate 449
is_unconnected 449
isolation_enable_condition 450
isolation_enable_phase 450
latch_enable_polarity 450
liberty_attributes 450
lower_drive_pin 451
min_capacitance 451
min_fanout 451
min_transition 452
mother_power 452
non_seq_setup_arc 452
permit_power_down 452
pg_function 452
pg_type 453
physical_connection 453
power_gating_class 453
power_gating_pin_phase 453
power_gating_polarity 454
pulse_clock 454
rail_connection 454
related_bias_pin 455
scan_enable_polarity 455
scan_in_polarity 455
signal_level 455
March 2025 29 Product Version 23.1
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Table of Contents
stack_via_list 455
stack_via_required 456
sync_clear_polarity 456
sync_enable_polarity 456
sync_preset_polarity 456
tied_to 456
to_lib_arcs 457
tristate 457
use 457
user_function 457
voltage_name 458
voltage_value 458
x_offset 458
y_offset 458
pin Attribute for Library 458
is_isolation_cell_data 458
root Attributes for Library 459
active_operating_conditions 460
allow_invalid_primary_power_pins_libcell 460
allow_multiple_sync_ctrls 461
aocv_library 461
auto_library_domain 462
auto_library_domain_threshold 462
bank_based_multibit_inferencing 462
base_cell_sets 463
base_cells 463
bussed_pin_of_single_bitwidth_as_pin 464
case_analysis_propagation_for_icg 464
case_analysis_sequential_propagation 464
change_cap_precision 465
convert_rising_falling_arcs_to_combo_arcs 465
disable_when_checks 466
dummy_scmr_iw_cell_in_all_lds 466
enable_library_pins_sorting_in_mmmc 466
establish_library_during_lef_loading 466
exact_match_seq_sync_ctrls 467
force_merge_combos_into_multibit_cells 467
March 2025 30 Product Version 23.1
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Table of Contents
force_merge_isos_into_multibit_cells 468
force_merge_seqs_into_multibit_cells 469
hide_mmmc_lib_clones 469
honor_valid_location 470
ignore_attribute_check_during_pin_conversion 470
ignore_pin_error_in_test_cell_function 470
ignore_scan_combinational_arcs 471
ignore_sigma_arc_inconsistency 471
init_design_mmmc_skip_inactive 472
init_mmmc_version 472
large_cell_arc_threshold 472
lbr_convert_n_piece_cap_to_2_piece 472
lbr_convert_nochange_arcs 473
lbr_ignore_disable_libarc 473
lbr_infer_cap_range_from_c1cn_dynamic_pincap_model 473
lbr_infer_cap_range_from_dynamic_pincap_model 474
lbr_mmmc_enable_init_design_speedup 474
lbr_respect_async_controls_priority 474
lbr_seq_in_out_phase_opto 475
lbr_timing_library_optimize_table_data 476
lbr_use_test_cell_seq 476
level_shifter_groups 476
lib_avoid_existing_eeq_cell 477
libraries 477
library 478
library_domains 478
library_sets 479
library_setup_lightweight 479
limit_lbr_messages 480
link_library 480
load_libraries_of_inactive_views 481
map_to_master_slave_lssd 481
mark_async_pin_using_timing_arcs 482
mark_inconsistent_cells_as_dont_use 482
mark_macro_as_power_switch_cell 482
mark_valid_lp_cell_as_usable 483
multibit_allow_async_phase_map 483
March 2025 31 Product Version 23.1
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Table of Contents
multibit_auto_exclude_registers_with_exceptions 484
multibit_cells_from_different_busses 485
multibit_combo_name_concat_string 485
multibit_prefix_string 486
multibit_preserve_inferred_instances 487
multibit_preserved_net_check 487
multibit_seqs_instance_naming_style 488
multibit_seqs_members_naming_style 489
multibit_seqs_name_concat_string 489
multibit_short_prefix_string 490
multibit_split_string 491
opconds 492
operating_conditions 492
override_library_max_drc 492
parse_lib_moments_table 493
rc_corners 493
reload_when_for_macro_cell 494
socv_library 494
speed_up_read_socv 494
speedup_library_establishment 494
support_3Dtable_power_arc 495
support_aae_lib_path_change 495
support_appending_libs 496
support_combo_clock 496
support_internal_pg_pins 496
support_master_slave_flop 497
support_multi_seq_elements 497
support_multi_seq_scan_latch 497
support_serial_scanin_multibit_cell 498
support_tlatch_group 498
suppress_syntech_messages 498
target_library 498
timing_analysis_socv 499
timing_conditions 499
timing_enable_sr_latch_preset_clear_arcs 500
timing_library_lookup_drv_per_frequency 500
timing_nsigma_multiplier 501
March 2025 32 Product Version 23.1
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Table of Contents
timing_socv_view_based_nsigma_multiplier_mode 502
treat_non_seq_arc_cell_as_unusable 502
turbo_lib_loading 502
use_area_from_lef 503
use_compatibility_based_grouping 503
use_default_related_pg_pin_for_aon 504
use_main_cell_output_function_for_test_cell 504
use_multibit_cells 504
use_multibit_combo_cells 505
use_multibit_iso_cells 505
use_multibit_seq_and_tristate_cells 506
use_nextstate_type_only_to_assign_sync_ctrls 507
use_scan_seqs_for_non_dft 507
wireload_mode 508
wireload_selection 508
seq_function Attribute for Library 509
d_function 509
wireload_selection Attribute for Library 509
library 509
wireload Attributes for Library 510
fanout_cap 510
liberty_attributes 510
library 511
12 512
Input and Output (IO) 512
hdl_architecture Attribute for IO 512
hdl_flatten_complex_port_in_bottom_up_flow 512
hdl_component Attribute for IO 512
sim_model 512
hdl_parameter Attribute for IO 514
current_value 514
13 515
Physical 515
All Attributes for Physical 515
index 516
is_fixed_mask 517
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Table of Contents
is_no_flop 517
is_spare 518
layer 518
location 518
location_x 520
location_y 521
orient 522
place_status 522
skip_in_write_def 524
base_cell Attributes for Physical 525
keep_as_physical 525
site 525
blockage Attributes for Physical 525
component 526
def_name 526
density 526
has_fills 526
has_slots 526
is_exceptpgnet 527
is_exclude_flops 527
is_partial 527
is_pushdown 527
is_soft 527
mask 528
max_layer 528
min_layer 528
polygons 528
properties 529
rects 529
spacing 529
user_created 529
user_name 530
visible 530
width 530
bump Attributes for Physical 530
base_cell 530
center 530
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Table of Contents
def_name 531
model 531
net 531
orient 531
port 531
properties 531
urx 532
ury 532
weight 532
def_pin Attributes for Physical 532
layers 532
net_expr 533
net_name 533
orientation 533
placement_status 533
polygons 534
ports 534
properties 534
special 535
use 535
vias 535
visible 535
design Attributes for Physical 535
aspect_ratio 536
avoid_no_row_libcell 536
bbox 537
blockages 537
boundary 538
bumps 538
def_component_mask_shift 538
def_extension 539
def_file 539
def_history 540
def_technology 540
def_version 540
die_area 541
floorplan_default_row_pattern_site 541
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Table of Contents
floorplan_first_row_site_index 542
floorplan_last_row_site_index 542
gcells 542
groups 543
num_phys_insts 543
obstruction_routing_layer 544
pcells 544
phys_ignore_nets 545
phys_ignore_special_nets 545
phys_insts 545
phys_skip_and_copy_special_nets 546
regions 546
rows 547
sdp_files 547
sdp_groups 547
sdp_type 548
small_blocked_box_count 548
track_count 549
utilization 549
utilization_threshold 549
fill Attributes for Physical 550
mask 550
opc 550
polygons 551
properties 551
rects 551
via 551
via_mask 552
via_opc 552
via_points 552
gcell_grid Attribute for Physical 552
num_grids 552
gcell Attributes for Physical 552
demand 553
horizontal_demand 553
horizontal_remaining 553
horizontal_supply 553
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Table of Contents
instance_count 553
pin_count 553
pin_density 554
rect 554
remaining 554
supply 554
utilization 554
vertical_demand 555
vertical_remaining 555
vertical_supply 555
group Attributes for Physical 555
components 555
constraint_type 555
def_name 556
is_floating 556
members 556
properties 556
region 556
user_created 557
Ispatial Flow 557
innovus_executable 557
invs_add_io_buffers 558
invs_add_io_buffers_base_name 558
invs_add_io_buffers_exclude_clock_net 558
invs_add_io_buffers_exclude_nets 558
invs_add_io_buffers_honor_dont_touch 558
invs_add_io_buffers_in_cells 558
invs_add_io_buffers_include_nets 559
invs_add_io_buffers_out_cells 559
invs_add_io_buffers_port 559
invs_add_io_buffers_pre_place 559
invs_add_io_buffers_skip_refine_place 559
invs_add_io_buffers_status 559
invs_add_io_buffers_suffix 559
invs_assign_buffer 559
invs_assign_removal 559
invs_clk_gate_recloning 559
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Table of Contents
invs_enable_useful_skew 560
invs_init_core_row 560
invs_launch_servers 560
invs_memory_usage 561
invs_opt_leakage 561
invs_opt_leakage_options 561
invs_place_opt_design 561
invs_postexport_report_script 561
invs_postload_script 561
invs_power_library_flow 562
invs_pre_place_opt 562
invs_preload_script 562
invs_scanreorder_keepport 562
invs_set_lib_unit 563
invs_spatial_place_connected 563
invs_temp_dir 563
invs_timing_driven_place 563
invs_to_genus_colorized_lef_path 564
invs_write_path_groups 564
invs_write_scandef_options 564
layer Attributes for Physical 564
area 565
cap_multiplier 565
cap_table_name 565
capacitance 566
color 566
eol_keepout 566
eol_spacing 566
first_column_cut_spacing 566
layer_index 566
mask 567
max_adjacent_spacing 567
max_cut_spacing 567
max_width 567
min_spacing 567
min_width 567
offset 567
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Table of Contents
offset_x 567
offset_y 568
pitch 568
pitch_x 568
pitch_y 568
resistance 568
route_index 568
same_mask_spacing 569
smallest_min_spacing 569
used 569
utilization 569
via_length 569
via_width 569
visible 570
width 570
net Attributes for Physical 570
annotated_capacitance_max 570
physical_cap 570
pcell Attributes for Physical 570
def_name 571
height 571
is_spare 571
model 571
orient 571
orientation 571
placement_status 572
properties 572
urx 572
ury 572
weight 573
width 573
pdomain Attributes for Physical 573
boundary 573
cutouts 573
mingap 574
rects 574
rsext 574
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Table of Contents
place_blockage Attributes for Physical 574
def_name 574
properties 575
pnet Attributes for Physical 575
capacitance 575
components 575
def_name 576
fixedbump 576
frequency 576
original_name 576
path_count 576
path_index 577
path_value 577
pattern 577
properties 577
rc_name 578
route_rule 578
shieldnet 578
source 578
use 578
visible 579
weight 579
xtalk 579
power_domain Attributes for Physical 579
disjoint_hinst_box_list 580
ext_bottom 580
ext_edges 580
ext_left 580
ext_right 580
ext_top 580
extend_power_bottom 581
extend_power_left 581
extend_power_right 581
extend_power_top 581
first_row_site_index 581
gap_bottom 581
gap_edges 581
March 2025 40 Product Version 23.1
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Table of Contents
gap_left 581
gap_right 582
gap_top 582
last_row_site_index 582
min_gaps 582
rects 582
row_pattern_site 582
row_space_type 582
row_spacing 582
rs_exts 582
region Attributes for Physical 583
def_name 583
derived_from_power_domain 583
properties 583
rects 583
user_created 584
root Attributes for Physical 584
cap_table_file 585
congestion_effort 585
db_units 585
def_output_escape_multibit 585
def_output_version 586
delaycal_enable_high_fanout 586
design_bottom_routing_layer 586
design_process_node 587
design_top_routing_layer 587
extract_rc_lef_tech_file_map 587
force_via_resistance 588
highlighted 588
init_lef_files 588
init_lib_phys_consistency_checks 588
interconnect_mode 589
layers 589
lef_library 589
lef_manufacturing_grid 590
lef_stop_on_error 590
lef_units 590
March 2025 41 Product Version 23.1
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Table of Contents
oa_def_file 590
590
opt_spatial_common_db 591
opt_spatial_early_clock 591
opt_spatial_merge_flops 591
opt_spatial_useful_skew 591
phys_annotate_ndr_nets 591
phys_assume_met_fill 591
phys_checkout_innovus_license 592
phys_density_based_balancing_max_area_ratio 592
phys_density_based_balancing_min_area_ratio 592
phys_extra_vias_length_factor 592
phys_fix_multi_height_cells 592
phys_flow_effort 593
phys_pre_place_iopt 593
phys_premorph_density 593
phys_read_script_large_file_source 593
phys_refresh_power_intent_1801 594
phys_scan_def_file 594
phys_summary_table_print_negative_tns 594
phys_update_preannotation_script 594
physical_aware_multibit_mapping 594
physical_force_predict_floorplan 595
pqos_ignore_msv 595
pqos_ignore_scan_chains 595
pqos_placement_effort 595
predict_floorplan_allow_core_reshape 596
predict_floorplan_allow_illegal_macro 596
predict_floorplan_constraints 596
predict_floorplan_enable_cpg 597
predict_floorplan_invs_post_resize_script 597
predict_floorplan_keep_fences 597
predict_floorplan_keep_fixed_macros 597
predict_floorplan_script 598
predict_floorplan_skip_propagate_activity 598
predict_floorplan_use_innovus 598
qos_report_power 598
March 2025 42 Product Version 23.1
Genus Attribute Reference
Table of Contents
qrc_tech_file 599
read_def_fuzzy_name_match 599
read_def_keep_net_property 599
read_def_libcell_mismatch_error 600
read_qrc_tech_file_rc_corner 600
report_logic_levels_histogram_fixed_depth 600
report_ndr_min_layer_count 600
route_early_global_horizontal_supply_scale_factor 600
route_early_global_num_tracks_per_clock_wire 600
route_early_global_secondary_pg 601
route_early_global_vertical_supply_scale_factor 601
route_rules 601
scale_of_cap_per_unit_length 601
scale_of_res_per_unit_length 602
selected 602
shrink_factor 603
sites 603
source_of_via_resistance 604
via_resistance 604
vias 604
604
route_blockage Attributes for Physical 604
def_name 604
properties 605
route_rule Attributes for Physical 605
from_lef 605
hardspacing 605
layers 605
mincuts 606
properties 606
viarules 606
vias 606
route_type Attributes for Physical 606
bottom_mask_layer_num 607
bottom_one_side_layer_num 607
bottom_preferred_layer 607
driver_use_multi_cut_via 607
March 2025 43 Product Version 23.1
Genus Attribute Reference
Table of Contents
em_route_rule 607
em_route_rule_distance 608
input_stack_via_rule 608
mask 608
min_stack_layer 608
non_default_rule 608
output_stack_via_rule 608
preferred_routing_layer_effort 608
shield_net 608
shield_side 609
stack_distance 609
top_mask_layer_num 609
top_one_side_layer_num 609
top_preferred_layer 609
row Attributes for Physical 609
height 610
is_horizontal 610
macro 610
num_x 610
num_y 610
orientation 611
selectable 611
site 611
step_x 611
step_y 611
user_created 611
visible 611
width 612
sdp_column Attributes for Physical 612
flip 612
justify_by 612
orient 613
sdp_group 613
sdp_instances 613
sdp_row 613
sdp_rows 613
size_same 613
March 2025 44 Product Version 23.1
Genus Attribute Reference
Table of Contents
skip_value 614
sdp_group Attributes for Physical 614
hier_path 614
orient 614
origin 614
sdp_columns 615
sdp_rows 615
sdp_instance Attributes for Physical 615
flip 615
instance 615
justify_by 615
orient 616
sdp_column 616
sdp_row 616
size_fixed 616
skip_value 616
sdp_row Attributes for Physical 616
flip 617
justify_by 617
orient 617
sdp_column 617
sdp_columns 618
sdp_group 618
sdp_instances 618
size_same 618
skip_value 618
site Attributes for Physical 618
class 618
height 619
row_pattern 619
size 619
symmetry 619
width 619
slot Attributes for Physical 619
polygons 620
rects 620
specialnet Attributes for Physical 620
March 2025 45 Product Version 23.1
Genus Attribute Reference
Table of Contents
components 621
def_name 621
fixedbump 621
original_name 621
path_count 621
path_index 622
path_value 622
pattern 622
polygons 622
properties 622
rc_name 623
rectangles 623
source 623
style 623
use 623
weight 624
style Attributes for Physical 624
polygon 624
track_pattern Attributes for Physical 624
num_tracks 624
properties 625
track Attributes for Physical 625
count 625
is_horizontal 625
is_used 625
layer 626
layer_number 626
macro 626
mask 626
multiple 626
same_mask 626
start 627
step 627
via Attributes for Physical 627
bottom_layer 628
cut_cols 628
cut_layer 628
March 2025 46 Product Version 23.1
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Table of Contents
cut_pattern 628
cut_rows 629
height 629
lef_name 629
min_route_layer 629
polygons 629
properties 629
rects 630
top_layer 630
viarule_name 630
width 630
xbottom_enclosure 631
xbottom_offset 631
xcut_size 631
xcut_spacing 631
xorigin_offset 632
xtop_enclosure 632
xtop_offset 632
ybottom_enclosure 632
ybottom_offset 633
ycut_size 633
ycut_spacing 633
yorigin_offset 633
ytop_enclosure 634
ytop_offset 634
14 635
Formal Verification 635
clp_enable_1801_hierarchical_bbox 635
clp_ignore_ls_high_to_low 635
clp_treat_errors_as_warnings 636
lec_executable 636
sim_model 637
637
verification_directory 638
verification_directory_naming_style 638
wcdc_clock_dom_comb_propagation 639
March 2025 47 Product Version 23.1
Genus Attribute Reference
Table of Contents
wcdc_synchronizer_type 640
wclp_lib_statetable 640
wlec_add_noblack_box_retime_subdesign 641
wlec_analyze_abort 641
wlec_analyze_setup 642
wlec_auto_analyze 643
wlec_black_box_ilm_modules 643
wlec_compare_threads 644
wlec_composite_compare 644
wlec_dft_constraint_file 645
wlec_gzip_fv_json 645
wlec_hier_append_string 646
wlec_hier_comp_threshold 646
wlec_hier_compare_string 647
wlec_hier_prepend_string 647
wlec_lib_statetable 648
wlec_low_power_analysis 648
wlec_multithread_license_list 649
wlec_no_dft_constraints 649
wlec_parallel_threads 650
wlec_post_add_notranslate_modules 650
wlec_run_hier_check_noneq 650
wlec_set_cdn_synth_root 651
wlec_uniquify 651
wlec_use_lec_model 652
wlec_use_smart_lec 653
wlec_verbose 653
write_verification_files 654
15 655
Netlist Export 655
error_on_lib_lef_pin_inconsistency 655
gen_module_prefix 655
hdl_keep_wand_wor_type 656
lef_add_logical_pins 656
lef_add_power_and_ground_pins 657
use_power_ground_pin_from_lef 657
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Table of Contents
write_sv_port_wrapper 657
write_vlog_bit_blast_bus_connections 659
write_vlog_bit_blast_constants 660
write_vlog_bit_blast_mapped_ports 662
write_vlog_bit_blast_tech_cell 664
write_vlog_convert_onebit_vector_to_scalar 667
write_vlog_declare_wires 668
write_vlog_empty_module_for_black_box 670
write_vlog_empty_module_for_logic_abstract 671
write_vlog_empty_module_for_subdesign 673
write_vlog_generic_gate_define 674
write_vlog_line_wrap_limit 675
write_vlog_no_negative_index 676
write_vlog_port_association_style 677
write_vlog_preserve_net_name 678
write_vlog_simplify_constant 679
write_vlog_skip_ilm_modules 680
write_vlog_skip_subdesign 680
write_vlog_top_module_first 681
write_vlog_unconnected_port_style 683
write_vlog_wor_wand 685
16 688
Constraints 688
arc Attributes for Constraints 688
from_pin 688
is_cellarc 688
to_pin 689
clock Attributes for Constraints 689
active_clock 690
comment 691
hold_uncertainty 691
ideal_transition_max_fall 692
ideal_transition_max_rise 692
ideal_transition_min_fall 692
ideal_transition_min_rise 693
inverted_sources 693
March 2025 49 Product Version 23.1
Genus Attribute Reference
Table of Contents
is_combinational_source_path 694
max_capacitance_clock_path_fall 694
max_capacitance_clock_path_rise 694
max_capacitance_data_path_fall 694
max_capacitance_data_path_rise 694
max_transition_clock_path_fall 694
max_transition_clock_path_rise 695
max_transition_data_path_fall 695
max_transition_data_path_rise 695
min_capacitance_clock_path_fall 695
min_capacitance_clock_path_rise 695
min_capacitance_data_path_fall 696
min_capacitance_data_path_rise 696
min_transition_clock_path_fall 696
min_transition_clock_path_rise 696
min_transition_data_path_fall 696
min_transition_data_path_rise 696
network_latency_fall_max 697
network_latency_fall_min 697
network_latency_rise_max 698
network_latency_rise_min 699
non_inverted_sources 700
setup_uncertainty 700
source_latency_early_fall_max 701
source_latency_early_fall_min 702
source_latency_early_rise_max 703
source_latency_early_rise_min 704
source_latency_late_fall_max 705
source_latency_late_fall_min 706
source_latency_late_rise_max 707
source_latency_late_rise_min 708
cost_group Attribute for Constraints 709
weight 709
exception Attributes for Constraints 709
comment 710
cost_group 710
max 711
March 2025 50 Product Version 23.1
Genus Attribute Reference
Table of Contents
no_compress 711
user_priority 711
external_delay Attributes for Constraints 712
clock_network_latency_included 712
clock_source_latency_included 712
delay 712
hnet Attributes for Constraints 713
hdl_type 713
resistance 713
hpin Attributes for Constraints 714
break_timing_paths 715
from_arcs 716
hold_uncertainty 716
ideal_driver 717
ideal_network 717
is_ideal_network 718
network_latency_fall_max 719
network_latency_fall_min 720
network_latency_rise_max 721
network_latency_rise_min 722
setup_uncertainty 723
slew_max_fall 724
slew_max_rise 724
slew_min_fall 724
slew_min_rise 724
source_latency_early_fall_max 725
source_latency_early_fall_min 726
source_latency_early_rise_max 726
source_latency_early_rise_min 727
source_latency_late_fall_max 728
source_latency_late_fall_min 729
source_latency_late_rise_max 730
source_latency_late_rise_min 731
timing_case_logic_value 732
to_arcs 733
net Attribute for Constraints 733
resistance 733
March 2025 51 Product Version 23.1
Genus Attribute Reference
Table of Contents
pin Attributes for Constraints 734
break_timing_paths 735
from_arcs 736
hold_uncertainty 736
ideal_driver 737
ideal_network 738
is_ideal_network 739
network_latency_fall_max 740
network_latency_fall_min 741
network_latency_rise_max 742
network_latency_rise_min 743
setup_uncertainty 744
slew_max_fall 744
slew_max_rise 745
slew_min_fall 745
slew_min_rise 745
source_latency_early_fall_max 745
source_latency_early_fall_min 746
source_latency_early_rise_max 747
source_latency_early_rise_min 748
source_latency_late_fall_max 749
source_latency_late_fall_min 750
source_latency_late_rise_max 751
source_latency_late_rise_min 752
timing_case_logic_value 753
to_arcs 754
port Attributes for Constraints 754
break_timing_paths 756
drive_resistance_fall_max 758
drive_resistance_fall_min 758
drive_resistance_rise_max 758
drive_resistance_rise_min 758
driver_from_pin_fall_max 759
driver_from_pin_fall_min 759
driver_from_pin_rise_max 759
driver_from_pin_rise_min 759
driver_ignore_drc 759
March 2025 52 Product Version 23.1
Genus Attribute Reference
Table of Contents
driver_ignore_drc_by_mode 760
driver_input_slew_fall_to_fall_max 760
driver_input_slew_fall_to_fall_min 760
driver_input_slew_fall_to_rise_max 760
driver_input_slew_fall_to_rise_min 760
driver_input_slew_rise_to_fall_max 761
driver_input_slew_rise_to_fall_min 761
driver_input_slew_rise_to_rise_max 761
driver_input_slew_rise_to_rise_min 761
driver_pin_fall_max 762
driver_pin_fall_min 762
driver_pin_rise_max 762
driver_pin_rise_min 763
external_capacitance_max 763
external_capacitance_min 763
external_driven_pin_fall 763
external_driven_pin_rise 764
external_fanout_load 764
external_pin_cap 764
external_resistance 765
external_wire_cap 765
external_wire_res 766
external_wireload_fanout 766
external_wireload_model 767
from_arcs 767
hold_uncertainty 768
ideal_driver 768
ideal_network 769
input_slew_max_fall 770
input_slew_max_rise 770
input_slew_min_fall 770
input_slew_min_rise 771
is_ideal_network 771
min_capacitance 772
network_latency_fall_max 772
network_latency_fall_min 773
network_latency_rise_max 774
March 2025 53 Product Version 23.1
Genus Attribute Reference
Table of Contents
network_latency_rise_min 775
setup_uncertainty 776
slew_max_fall 777
slew_max_rise 777
slew_min_fall 777
slew_min_rise 777
source_latency_early_fall_max 777
source_latency_early_fall_min 778
source_latency_early_rise_max 779
source_latency_early_rise_min 780
source_latency_late_fall_max 781
source_latency_late_fall_min 782
source_latency_late_rise_max 783
source_latency_late_rise_min 784
timing_case_logic_value 785
to_arcs 786
17 787
Multi-Mode Multi-Corner (MMMC) Flow 787
analysis_view Attributes for MMMC Flow 787
constraint_mode 788
delay_corner 788
design 788
is_active 789
is_dynamic 789
is_hold 789
is_hold_default 790
is_leakage 790
is_setup 790
is_setup_default 790
latency_file 791
path_adjust_file 791
constraint_mode Attributes for MMMC Flow 791
design 792
ilm_sdc_files 792
is_active 792
is_dynamic 793
March 2025 54 Product Version 23.1
Genus Attribute Reference
Table of Contents
is_hold 793
is_leakage 793
is_setup 793
sdc_files 794
tcl_vars 794
delay_corner Attributes for MMMC Flow 794
design 795
early_irdrop_files 795
early_rc_corner 796
early_temperature_files 796
early_timing_condition 797
early_timing_condition_string 797
is_dynamic 798
is_hold 798
is_leakage 798
is_setup 798
is_si_enabled 799
late_irdrop_files 799
late_rc_corner 799
late_temperature_files 800
late_timing_condition 800
late_timing_condition_string 801
mmmc_design 801
library_set Attributes for MMMC Flow 801
aocv_files 802
libraries 802
library_files 802
si_files 803
socv_files 803
opcond Attributes for MMMC Flow 804
is_hold 804
is_setup 804
is_virtual 804
library_file 804
process 805
temperature 805
tree_type 805
March 2025 55 Product Version 23.1
Genus Attribute Reference
Table of Contents
rc_corner Attributes for MMMC Flow 806
post_route_cap 806
post_route_clock_cap 807
post_route_clock_cross_cap 808
post_route_clock_res 808
post_route_cross_cap 809
post_route_res 809
pre_route_cap 810
pre_route_clock_cap 810
pre_route_clock_res 811
pre_route_res 811
qrc_tech_file 812
temperature 812
timing_condition Attributes for MMMC Flow 813
library_sets 813
opcond 813
opcond_library 814
18 815
Clock Gating 815
clock_gate_enable_pin 815
clock_gate_enable_polarity 816
clock_gating_integrated_cell 816
is_clock_gate_clock 817
is_clock_gate_enable 817
is_clock_gate_obs 818
is_clock_gate_out 818
is_clock_gate_reset 819
is_clock_gate_test 819
is_integrated_clock_gating 820
is_synthesis_clock_gate 820
lp_clock_gating_method 820
lp_clock_gating_add_obs_port 821
lp_clock_gating_auto_cost_group_initial_target 821
lp_clock_gating_auto_cost_grouping 822
lp_clock_gating_auto_path_adjust 822
lp_clock_gating_auto_path_adjust_fixed_delay 823
March 2025 56 Product Version 23.1
Genus Attribute Reference
Table of Contents
lp_clock_gating_auto_path_adjust_modes 824
lp_clock_gating_auto_path_adjust_multiplier 824
lp_clock_gating_cell 825
lp_clock_gating_connect_test_clock_gate_types 826
lp_clock_gating_connect_test_consider_constant_enabled_as_connected 827
lp_clock_gating_control_point 827
lp_clock_gating_coverage_effort 828
lp_clock_gating_exceptions_aware 828
lp_clock_gating_exclude 829
lp_clock_gating_extract_common_enable 830
lp_clock_gating_gated_clock_gates 830
lp_clock_gating_gated_flops 831
lp_clock_gating_hierarchical 831
lp_clock_gating_infer_enable 832
lp_clock_gating_is_flop_rc_gated 832
lp_clock_gating_is_flop_user_gated 833
lp_clock_gating_is_leaf_clock_gate 833
lp_clock_gating_max_flops 833
lp_clock_gating_min_flops 834
lp_clock_gating_module 835
lp_clock_gating_prefix 835
lp_clock_gating_stage 836
lp_clock_gating_style 836
lp_clock_gating_test_signal 837
lp_insert_clock_gating 838
report_clock_from_different_views 838
lp_clock_gating_exclude_signal 839
19 840
Conformal Constraint Designer (CCD) 840
ccd_executable 840
wccd_threshold_percentage 840
20 842
Timing 842
adjust_derate 843
arrival 843
box_has_aocv_derate 844
March 2025 57 Product Version 23.1
Genus Attribute Reference
Table of Contents
box_has_ocv_derate 844
case_analysis_multi_driver_propagation 844
causes_ideal_net 845
845
define_clock_with_new_cost_group 846
delay 846
delay_corner_pd_at_tc_no_timing_derate 847
delaycal_equivalent_waveform_model 847
847
delaycal_library_interpolation_mode 848
848
delaycal_socv_lvf_mode 848
848
delaycal_socv_use_lvf_tables 849
849
design Attributes in Timing 849
analysis_views 850
arcs 850
average_net_length 850
constraint_modes 850
cost_groups 850
delay_corners 850
dynamic_power_view 851
dynamic_power_view_in_setup 851
early_fall_cell_check_derate_factor 851
early_fall_clk_cell_derate_factor 851
early_fall_clk_check_derate_factor 851
early_fall_clk_net_delta_derate_factor 851
early_fall_clk_net_derate_factor 851
early_fall_data_cell_derate_factor 852
early_fall_data_net_delta_derate_factor 852
early_fall_data_net_derate_factor 852
early_rise_cell_check_derate_factor 852
early_rise_clk_cell_derate_factor 853
early_rise_clk_check_derate_factor 853
early_rise_clk_net_delta_derate_factor 853
early_rise_clk_net_derate_factor 853
March 2025 58 Product Version 23.1
Genus Attribute Reference
Table of Contents
early_rise_data_cell_derate_factor 853
early_rise_data_net_delta_derate_factor 853
early_rise_data_net_derate_factor 854
early_socv_inter_rc_variation_factor 854
external_delays 854
fep 855
force_wireload 855
hold_views 855
ideal_seq_async_pins 856
latch_borrow 856
latch_max_borrow 857
latch_max_borrow_interface 857
857
late_fall_cell_check_derate_factor 858
late_fall_clk_cell_derate_factor 858
late_fall_clk_check_derate_factor 858
late_fall_clk_net_delta_derate_factor 858
late_fall_clk_net_derate_factor 858
late_fall_data_cell_derate_factor 859
late_fall_data_net_delta_derate_factor 859
late_fall_data_net_derate_factor 859
late_rise_cell_check_derate_factor 859
late_rise_clk_cell_derate_factor 859
late_rise_clk_check_derate_factor 860
late_rise_clk_net_delta_derate_factor 860
late_rise_clk_net_derate_factor 860
late_rise_data_cell_derate_factor 860
late_rise_data_net_delta_derate_factor 860
late_rise_data_net_derate_factor 861
late_socv_inter_rc_variation_factor 861
leakage_power_view 861
leakage_power_view_in_setup 861
lp_default_toggle_percentage 861
multi_cycles 862
nl_has_aocv_derate 862
path_adjusts 862
path_delays 862
March 2025 59 Product Version 23.1
Genus Attribute Reference
Table of Contents
path_disables 862
path_groups 863
setup_views 863
slack 863
slack_max 864
timing_disable_internal_inout_net_arcs 864
timing_paths 864
tns 865
total_net_length 865
tps 865
tslk 865
wireload 865
detailed_sdc_messages 866
866
disabled_arcs 868
dont_break_combo_loops_thr_c_to_q 869
dont_break_combo_loops_thr_c_to_q_macro 869
dont_break_combo_loops_thr_en_to_q 869
dont_retime 870
870
early_estimated_worst_irdrop_factor 870
early_fall_cell_check_sigma_derate_factor 871
early_fall_clk_cell_sigma_derate_factor 871
early_fall_clk_check_sigma_derate_factor 871
early_fall_data_cell_sigma_derate_factor 871
early_irdrop_data 871
early_rise_cell_check_sigma_derate_factor 872
early_rise_clk_cell_sigma_derate_factor 872
early_rise_clk_check_sigma_derate_factor 872
early_rise_data_cell_sigma_derate_factor 872
enable_break_timing_paths_by_mode 872
enable_data_check 873
exceptions 874
external_non_tristate_drivers 874
free_global_vars_set_by_read_sdc 875
875
hierarchical_name 875
March 2025 60 Product Version 23.1
Genus Attribute Reference
Table of Contents
init_prototype_design 875
init_timing_enabled 876
is_hierarchical 876
is_negative_level_sensitive 876
is_positive_level_sensitive 876
late_estimated_worst_irdrop_factor 876
late_fall_cell_check_sigma_derate_factor 877
late_fall_clk_cell_sigma_derate_factor 877
late_fall_clk_check_sigma_derate_factor 877
late_fall_data_cell_sigma_derate_factor 877
late_irdrop_data 878
late_rise_cell_check_sigma_derate_factor 878
late_rise_clk_cell_sigma_derate_factor 878
late_rise_clk_check_sigma_derate_factor 878
late_rise_data_cell_sigma_derate_factor 878
legacy_preserve_sdc_object_name 879
mark_retention_pin_ideal 879
min_pulse_width 879
min_timing_arcs 880
ocv_mode 880
phys_socv 880
preserve_sdc_annotated_comb_insts 881
retime_original_registers 881
881
scale_factor_group_path_weights 882
sdc_filter_match_more_slashes 882
sdc_flat_view_default 882
sdc_match_more_slashes 883
setup 883
show_wns_in_log 883
skip_default_lib_check 884
socv_derate 884
spatial_path_group_effort_level 884
synthesis_skip_pd_timing_derate 885
tim_ignore_data_check_for_non_endpoint_pins 885
time_recovery_arcs 886
timing_analysis_clock_propagation_mode 886
March 2025 61 Product Version 23.1
Genus Attribute Reference
Table of Contents
timing_analysis_clock_source_paths 886
timing_analysis_type 887
timing_case_disabled_arcs 887
timing_defer_mmmc_obj_updates 887
timing_disable_library_data_to_data_checks 888
timing_disable_non_sequential_checks 888
timing_enable_get_ports_for_current_instance 888
timing_no_path_segmentation 889
timing_path 889
timing_propagate_latch_data_uncertainty 890
timing_report_default_formatting 890
890
timing_report_enable_common_header 890
timing_report_endpoint_fields 891
timing_report_exception_data 891
timing_report_fields 891
timing_report_load_unit 891
timing_report_path_type 892
timing_report_unconstrained 892
892
timing_spatial_derate_chip_size 893
total_derate 893
trace_retime 893
893
transition_type 894
ui_units_capacitance_reporting 894
ui_units_timing_reporting 894
use_multi_clks_latency_uncertainty_optimize 895
use_multi_clks_latency_uncertainty_report 895
user_mean_derate 896
user_sigma_derate 896
write_mmmc_forking_enabled 897
write_sdc_use_libset_name_set_dont_use 897
21 898
Datapath 898
apply_booth_encoding 898
March 2025 62 Product Version 23.1
Genus Attribute Reference
Table of Contents
control_logic_optimization 898
dp_analytical_opt 899
dp_area_mode 900
dp_csa 901
dp_csa_factorize 902
dp_rewriting 902
dp_sharing 903
dp_speculation 904
dp_ungroup_during_syn_map 905
dpopt_instance_constant_input_based_speculation 906
906
dpopt_power_opto 906
dpopt_power_opto_scaling 907
dpopt_toggle_skew_threshold_for_booth_encoding 907
hdl_pipeline_comp 908
908
is_booth_encoded 908
one_pass_formal_verification 909
909
22 911
Optimization 911
alias_names 911
allow_seq_in_out_phase_opto 912
area 912
assigned_library_set 913
913
backup_power_pins 913
base_cell 913
boundary_opto 913
default 914
design 915
design Attributes in Opt 915
analysis 916
blackboxes 916
clusters 917
constant_0_loads 917
March 2025 63 Product Version 23.1
Genus Attribute Reference
Table of Contents
constant_0_nets 917
constant_1_loads 918
constant_1_nets 918
constants 918
def_pins 919
dont_touch 919
dont_touch_effective 921
dont_touch_file 922
dont_touch_reason 923
dont_use_base_cell_set 923
dont_use_cells 924
dont_use_cells_effective 925
fills 925
hdl_v2001 926
hinsts 927
hnets 928
hpins 928
ignore_library_drc 928
ignore_library_max_fanout 929
insts 930
insts_area 930
local_hinsts 931
local_hnets 931
local_hpins 931
local_insts 932
local_pins 932
max_cap_cost 933
max_capacitance 933
max_fanout 934
max_fanout_cost 935
max_trans_cost 936
max_transition 937
min_cap_cost 938
min_fanout_cost 938
min_trans_cost 939
modules 939
net_area 940
March 2025 64 Product Version 23.1
Genus Attribute Reference
Table of Contents
nets 940
num_insts 941
num_local_hpins 941
num_nets 941
num_pg_nets 942
pg_hnets 942
pg_nets 943
pg_ports 943
physical_cell_area 943
pins 944
pinstances 945
pnets 945
port_busses 946
ports 946
preserve 947
protected 948
retime 949
retime_period_percentage 950
route_types 950
seq_reason_deleted 951
slots 951
specialnets 952
styles 952
total_area 952
track_patterns 953
use_base_cell_set 953
use_cells 953
use_only_on_power_critical_nets 954
direction 955
dont_touch_sources 960
dont_use_qbar_pin 960
hdl_instantiated 961
hinst 961
hpin_busses 961
hport_busses 962
hports 962
inherited_preserve 962
March 2025 65 Product Version 23.1
Genus Attribute Reference
Table of Contents
inverted_phase 963
iopt_allow_inst_dup 963
963
is_black_box 964
is_buffer 964
is_combinational 964
964
is_cw_component 964
is_dont_touch 965
is_flop 965
is_interface_timing 966
is_inverter 966
is_latch 966
is_macro 967
is_master_slave_flop 967
is_master_slave_lssd_flop 967
is_memory 967
is_pad 968
is_phase_inverted 968
is_physical 968
is_sequential 969
is_tristate 969
lib_cells 969
map_to_multibit_bank_label 969
map_to_multibit_register 970
map_to_mux 970
970
map_to_register 970
merge_combinational_hier_instance 971
module 971
module attributes for Opt 972
dont_touch_hports 972
hard_region 972
logical_hier 973
retime_hard_region 973
ungroup_ok 974
multibit_rejection_reason 974
March 2025 66 Product Version 23.1
Genus Attribute Reference
Table of Contents
negative_edge_clock 974
optimize_constant_0_seq 975
optimize_constant_1_seq 976
optimize_merge_seq 976
parent 977
pg_hports 977
pg_nets_ls 978
pg_pins 978
pin_busses 978
primitive_function 978
relaxed_seq_map_constraints 978
retime_ssw_sync_enable 978
root Attributes in Optimization 979
auto_partition 980
auto_super_thread 981
auto_ungroup 981
auto_ungroup_max_threshold 982
avoid_tied_inputs 982
bit_blasted_port_style 983
boundary_optimize_constant_hpins 983
boundary_optimize_equal_opposite_hpins 984
boundary_optimize_feedthrough_hpins 985
boundary_optimize_invert_hpins 986
boundary_optimize_invert_hpins_rename_nets 986
boundary_optimize_invert_hpins_renaming_extension 987
bus_naming_style 988
comb_seq_merge_message_threshold 988
cts_buffer_cells 988
cts_clock_gating_cells 989
cts_inverter_cells 989
cts_logic_cells 990
current_design 990
delete_flops_on_preserved_net 991
delete_hier_insts_on_preserved_net 991
delete_unloaded_insts 991
delete_unloaded_seqs 992
derive_bussed_pins 993
March 2025 67 Product Version 23.1
Genus Attribute Reference
Table of Contents
design_power_effort 993
designs 994
disable_ungroup_for_hierarchy 994
display_information_of_edit_netlist 994
dont_use_qbar_seq_pins 995
double_cell_search_pattern 995
drc_first 995
drc_max_cap_first 996
drc_max_fanout_first 997
drc_max_trans_first 998
driver_for_unloaded_hier_pins 999
enable_aon_type_in_remove_assign 999
enable_strict_percent_control 999
exact_match_seq_async_ctrls 1000
fix_min_drcs 1000
group_generate_portname_from_netname 1000
group_instance_suffix 1001
handle_ungroup_names 1001
ignore_preserve_in_tiecell_insertion 1002
inst_prefix 1002
iopt_allow_tiecell_with_inversion 1003
iopt_enable_floating_output_check 1003
iopt_force_constant_removal 1003
iopt_remap_avoided_cells 1004
iopt_sequential_duplication 1004
iopt_sequential_resynthesis 1005
iopt_sequential_resynthesis_min_effort 1005
iopt_temp_directory 1006
iopt_ultra_optimization 1006
map_clock_tree 1006
map_drc_first 1007
map_latch_allow_async_decomp 1007
map_prefer_non_inverted_clock_line 1008
map_respect_rtl_clk_phase 1008
map_to_multiple_output_gates 1009
max_cpus_per_server 1009
merge_combinational_hier_instances 1010
March 2025 68 Product Version 23.1
Genus Attribute Reference
Table of Contents
merge_non_scan_to_scan_flops 1010
minimize_uniquify 1011
mtdcl_traverse_by_level 1011
multibit_allow_sr_head_flop_merge 1011
multibit_allow_unused_bits 1012
multibit_area_power_scoring 1012
multibit_aware_seq_mapping 1012
multibit_aware_seq_mapping_higher_priority 1013
multibit_debug 1014
multibit_invert_clock_phase 1014
multibit_mapping_effort_level 1015
multibit_predefined_allow_unused_bits 1015
multibit_unused_input_value 1016
opt_allow_floating_outputs 1016
opt_high_effort_cells 1016
opt_spatial_effort 1017
opt_tns 1017
optimize_constant_0_flops 1018
optimize_constant_1_flops 1018
optimize_constant_across_preserved 1019
optimize_constant_feedback_seqs 1019
optimize_constant_latches 1020
optimize_merge_flops 1021
optimize_merge_latches 1021
optimize_seq_x_to 1022
optimize_yield 1022
partition_based_synthesis 1022
pbs_db_directory 1023
pbs_gen_summary 1023
pbs_iopt_summary 1023
pbs_load_lib_in_group_of 1024
pbs_map_summary 1024
percent_control_tolerance_for_map 1024
predict_floorplan_enable_during_generic 1025
preserve_combinational_loop_ports_nets 1025
print_ports_nets_preserved_for_cb 1025
propagate_constant_from_timing_model 1026
March 2025 69 Product Version 23.1
Genus Attribute Reference
Table of Contents
proto_feasible_target 1026
proto_feasible_target_adjust_slack_pct 1026
proto_feasible_target_threshold 1027
proto_feasible_target_threshold_clock_pct 1027
remove_assigns 1028
retime_async_reset 1028
retime_effort_level 1029
retime_move_mux_loop_with_reg 1029
retime_optimize_reset 1030
retime_reg_naming_suffix 1030
retime_verification_flow 1031
retiming_clocks 1032
skip_ungroup_on_applied_constraint 1032
skip_ungroup_with_exception 1032
st_launch_wait_time 1033
stop_at_iopt_state 1033
super_thread_batch_command 1034
super_thread_debug_directory 1035
super_thread_debug_jobs 1035
super_thread_equivalent_licenses 1036
super_thread_kill_command 1036
super_thread_rsh_command 1037
super_thread_servers 1038
super_thread_shell_command 1039
super_thread_status_command 1039
syn_generic_effort 1040
syn_global_effort 1040
syn_map_effort 1041
syn_opt_effort 1041
tns_critical_range 1042
1042
treat_net_as_analog 1042
ui_respects_preserve 1042
ungroup_separator 1043
uniquify_naming_style 1043
uniquify_rename_all 1044
update_sv_wrapper_post_elab 1044
March 2025 70 Product Version 23.1
Genus Attribute Reference
Table of Contents
use_max_cap_lut 1045
use_tiehilo_for_const 1045
write_db_auto_save_user_globals 1046
write_db_use_relative_filepath 1046
state_retention_rule 1047
1047
std_cell_main_rail_pin 1047
unique_versions 1047
unresolved 1048
usable_flop 1049
usable_latch 1049
user_defined 1049
23 1052
Power 1052
add_pin_name_to_lp_instance 1052
commit_delete_invalid_iso_ls 1053
continuous_fast_report_timing 1053
cpf_macro_inherit_parent_power_domain 1054
cpi_allow_avoided_cells 1054
cpi_allow_dont_touch_cells 1055
cpi_allow_inverted_ls 1055
cpi_enable_third_domain_buffering 1055
cpi_insert_on_switch_network 1056
cpi_invert_preserved_net 1056
cpi_inverter_name_prefix 1057
cpi_iso_ls_skip_const_prop_loads 1057
cpi_output_net_name_prefix 1058
init_power_intent_files 1059
is_isolation 1059
1059
is_level_shifter 1060
1060
is_retention 1061
1061
isolate_zero_pin_retention 1061
isonor_2017 1062
March 2025 71 Product Version 23.1
Genus Attribute Reference
Table of Contents
part_power_intent_file 1062
pi_disable_aon_buffering 1063
pi_parser_error_on_missing_objects 1063
pi_parser_honor_avoided_cells 1064
pi_read_enable_exhaustive_search 1064
pi_relax_map_iso_cell_checks 1064
pi_relax_map_ls_cell_checks 1065
pias_aon_enable_mode_analysis 1066
power_domain 1066
power_domains 1068
power_dynamic 1069
power_internal 1070
power_leakage 1070
power_switching 1071
power_total 1072
preserve_power_domain_boundary 1072
secondary_domain 1073
1073
24 1075
Safety 1075
exclusive_group_gap 1075
exclusive_group_type 1076
exclusive_groups 1076
safety_dcls_isolate_clock 1077
safety_dcls_isolate_groups 1077
safety_dcls_isolate_halo_type 1077
safety_dcls_isolate_inputs 1078
safety_dcls_isolate_is_group_input_cell 1078
safety_dcls_isolate_is_group_output_cell 1079
safety_dcls_isolate_is_halo 1079
safety_dcls_isolate_outputs 1080
safety_dcls_isolate_pin 1080
safety_dcls_isolate_reset 1081
safety_dcls_isolate_scan_enable 1081
safety_dcls_isolate_signal_type 1082
safety_dcls_isolate_type 1082
March 2025 72 Product Version 23.1
Genus Attribute Reference
Table of Contents
safety_dcls_isolate_use_halo 1083
safety_dcls_route_types 1083
safety_failure_mode 1084
safety_flow_enable 1084
safety_mechanism 1085
safety_mechanism_type 1085
safety_midas_enable 1086
safety_parity_bit 1086
safety_parity_bit_cells 1087
safety_parity_endpoint 1087
1087
safety_parity_error_signal_endpoint 1088
safety_parity_group_size_max 1089
safety_parity_group_size_min 1089
safety_ser_cells 1090
safety_ser_type 1090
safety_tmr_clones 1091
safety_tmr_custom_voter_cell 1091
safety_tmr_error_signal_endpoint 1092
safety_tmr_isolate_clock 1093
safety_tmr_isolate_reset 1093
safety_tmr_isolate_scan_enable 1094
safety_tmr_parent 1095
safety_tmr_spacing 1095
safety_tmr_spacing_x 1095
safety_tmr_spacing_y 1096
safety_tmr_voters 1096
safety_tmr_well_tap_cells 1097
safety_tmr_well_tap_left_padding 1097
safety_tmr_well_tap_right_padding 1098
25 1099
Analysis Attributes 1099
clock Attributes for Analysis 1100
actual_period 1102
clock_domain 1102
clock_groups 1102
March 2025 73 Product Version 23.1
Genus Attribute Reference
Table of Contents
clock_relation_to_others 1103
clock_sense_all_stop 1103
clock_sense_clock_source_data_stop_propagation 1103
clock_sense_clock_stop_propagation 1103
clock_sense_data_stop_propagation 1104
clock_sense_logical_stop_propagation 1104
clock_sense_negative 1104
clock_sense_positive 1105
clock_sense_stop_propagation 1105
delay_max_fall 1106
delay_max_rise 1106
delay_min_fall 1107
delay_min_rise 1107
divide_by 1108
divide_by_4prop 1108
divide_fall 1108
divide_period 1109
divide_rise 1109
divide_waveform 1109
duty_cycle 1110
edge_shift 1110
edges 1111
exceptions 1111
fall 1112
generated_clocks 1113
is_generated 1113
is_inverted 1113
is_library_created 1114
is_propagated 1114
is_virtual 1114
master_clock 1114
master_source 1114
min_pulse_width_high 1115
min_pulse_width_low 1115
multiply_by 1115
period 1116
rise 1116
March 2025 74 Product Version 23.1
Genus Attribute Reference
Table of Contents
sources 1117
view_name 1117
waveform 1117
waveform_4prop 1118
constant Attributes for Analysis 1118
capacitance_max_fall 1118
capacitance_max_rise 1119
capacitance_min_fall 1119
capacitance_min_rise 1120
external_net_wire_capacitance 1120
hinst 1121
wire_capacitance 1121
wire_length 1122
wire_resistance 1123
cost_group Attributes for Analysis 1123
exceptions 1124
fep 1124
tslk 1125
exception Attributes for Analysis 1125
adjust_value 1125
delay_value 1126
domain 1126
exception_type 1127
from_points 1127
lenient 1128
paths 1128
precluded_path_adjusts 1129
priority 1129
shift_capture 1129
shift_launch 1130
shift_launch_default 1130
through_points 1130
to_points 1131
external_delay Attributes for Analysis 1132
clock 1132
clock_rise 1132
exceptions 1133
March 2025 75 Product Version 23.1
Genus Attribute Reference
Table of Contents
external_delay_pins 1134
input_delay 1134
level_sensitive 1134
sigma_delay 1135
hdl_architecture Attributes for Analysis 1135
blocks 1136
hdl_lib 1136
hdl_pins 1137
labels 1137
parameters 1137
processes 1138
start_source_line 1138
structural 1138
subprograms 1139
verilog_macros 1139
hdl_bind Attributes for Analysis 1139
hdl_component 1140
operator 1140
hdl_block Attributes for Analysis 1140
blocks 1141
hdl_architecture 1141
hdl_block 1141
hdl_lib 1142
labels 1142
processes 1143
subprograms 1143
hdl_component Attributes for Analysis 1143
bindings 1144
hdl_lib 1144
hdl_pins 1144
implementations 1145
parameters 1145
hdl_configuration Attributes for Analysis 1146
entity 1146
hdl_lib 1146
hdl_implementation Attributes for Analysis 1146
hdl_component 1146
March 2025 76 Product Version 23.1
Genus Attribute Reference
Table of Contents
hdl_inst Attributes for Analysis 1147
component 1147
hdl_architecture 1147
hdl_block 1148
hdl_label Attributes for Analysis 1148
hdl_architecture 1148
hdl_block 1149
hdl_lib Attributes for Analysis 1149
architectures 1150
components 1150
configurations 1150
operators 1150
packages 1151
hdl_operator Attributes for Analysis 1151
hdl_lib 1151
hdl_pins 1151
hdl_package Attributes for Analysis 1152
default_location 1152
hdl_lib 1152
subprograms 1153
hdl_parameter Attributes for Analysis 1153
hdl_architecture 1153
hdl_component 1154
hdl_parameter 1154
hdl_pin Attributes for Analysis 1155
hdl_architecture 1155
hdl_component 1155
hdl_operator 1155
hdl_procedure Attributes for Analysis 1155
hdl_architecture 1156
hdl_block 1156
hdl_subprogram Attributes for Analysis 1157
hdl_architecture 1157
hdl_block 1157
hdl_package 1158
hnet Attributes for Analysis 1158
dont_touch_file 1159
March 2025 77 Product Version 23.1
Genus Attribute Reference
Table of Contents
dont_touch_reason 1159
drivers 1159
hinst 1159
is_constant 1160
is_driven_by_supply0 1160
is_driven_by_supply1 1161
is_ideal 1161
is_part_of_bus 1161
loads 1162
net 1162
num_drivers 1163
num_loads 1163
type 1163
hpin Attributes for Analysis 1164
arrival_max_fall 1166
arrival_max_rise 1166
arrival_min_fall 1167
arrival_min_rise 1167
arrival_window 1167
boundary_optimize_hpin_invertible 1167
capacitance_max_fall 1168
capacitance_max_rise 1169
capacitance_min_fall 1169
capacitance_min_rise 1170
capturer 1170
clock_sense_all_stop 1171
clock_sense_clock_source_data_stop_propagation 1171
clock_sense_clock_stop_propagation 1171
clock_sense_data_stop_propagation 1172
clock_sense_logical_stop_propagation 1172
clock_sense_negative 1172
clock_sense_positive 1173
clock_sense_stop_propagation 1173
clock_sources_inverted 1174
clock_sources_non_inverted 1174
clocks 1175
connect_delay 1175
March 2025 78 Product Version 23.1
Genus Attribute Reference
Table of Contents
delay_max_fall 1176
delay_max_rise 1176
delay_min_fall 1176
delay_min_rise 1177
dont_touch_file 1177
dont_touch_reason 1178
drivers 1178
endpoint 1178
exceptions 1179
external_net_wire_capacitance 1180
generates_clocks 1181
hinst 1181
hnet 1182
hport 1182
is_clock_gating_pin 1183
is_clock_used_as_clock 1183
is_clock_used_as_data 1183
is_physical 1184
launcher 1184
lib_pins 1185
loads 1185
net 1186
pg_hnet 1186
pg_net 1186
propagated_clocks 1187
propagated_ideal_network 1188
rf_slack 1189
slack_max 1189
slack_max_edge 1190
slack_max_fall 1190
slack_max_rise 1191
slew 1191
slew_by_mode 1192
startpoint 1192
timing_arcs 1192
timing_case_computed_value 1193
timing_info 1194
March 2025 79 Product Version 23.1
Genus Attribute Reference
Table of Contents
timing_info_favor_startpoint 1195
wire_capacitance 1196
wire_length 1196
wire_resistance 1197
wireload_model 1197
hpin_bus Attributes in Analysis 1198
bits 1198
hinst 1198
hport_bus 1199
hport Attributes for Analysis 1199
boundary_optimize_hpin_invertible 1200
bus 1201
capacitance_max_fall 1201
capacitance_max_rise 1201
capacitance_min_fall 1201
capacitance_min_rise 1202
drivers 1202
external_net_wire_capacitance 1202
hinst 1202
hnet 1203
hpin 1203
loads 1203
net 1203
pg_hnet 1204
pg_net 1204
wire_capacitance 1204
wire_length 1204
wire_resistance 1204
hport_bus Attributes for Analysis 1205
bits 1205
hinst 1205
hpin_bus 1205
order 1205
message_group Attribute for Analysis 1206
is_user 1206
net Attributes for Analysis 1206
constant 1207
March 2025 80 Product Version 23.1
Genus Attribute Reference
Table of Contents
driver_pins 1207
driver_ports 1207
hinst 1207
is_constant 1208
is_ideal 1208
load_pins 1209
load_ports 1209
num_drivers 1209
num_loads 1210
wire_capacitance_max 1210
pcell Attributes for Analysis 1210
base_cell 1210
pg_hnet Attributes for Analysis 1211
hinst 1211
pg_hport 1212
pg_hports_of_hinsts 1212
pg_net 1212
pins 1213
pg_hport Attributes for Analysis 1213
hinst 1213
parent_pg_hnet 1213
pg_hnet 1214
pg_net Attributes for Analysis 1214
hinst 1214
inst 1215
pins 1215
sub_pg_nets 1216
upper_pg_net 1216
pg_pin Attributes for Analysis 1216
base_pin 1217
drivers 1217
hinst 1218
hnet 1218
inst 1219
is_async 1219
is_data 1219
is_physical 1220
March 2025 81 Product Version 23.1
Genus Attribute Reference
Table of Contents
is_std_cell_main_rail 1220
loads 1220
net 1221
pg_hnet 1221
pg_net 1222
pg_type 1222
physical 1222
pg_hnet 1223
pin Attributes for Analysis 1223
arrival_max_fall 1226
arrival_max_rise 1226
arrival_min_fall 1226
arrival_min_rise 1226
arrival_window 1227
base_pin 1227
bus 1227
capacitance_max_fall 1227
capacitance_max_rise 1227
capacitance_min_fall 1228
capacitance_min_rise 1228
capturer 1228
clock_sense_all_stop 1229
clock_sense_clock_source_data_stop_propagation 1229
clock_sense_clock_stop_propagation 1229
clock_sense_data_stop_propagation 1230
clock_sense_logical_stop_propagation 1230
clock_sense_negative 1230
clock_sense_positive 1230
clock_sense_stop_propagation 1231
clock_sources_inverted 1231
clock_sources_non_inverted 1232
clocks 1232
connect_delay 1233
delay_max_fall 1233
delay_max_rise 1233
delay_min_fall 1234
delay_min_rise 1234
March 2025 82 Product Version 23.1
Genus Attribute Reference
Table of Contents
dont_touch_file 1234
dont_touch_reason 1235
endpoint 1235
exceptions 1235
external_net_wire_capacitance 1236
generates_clocks 1236
hnet 1236
inst 1236
is_async 1236
is_clock 1237
is_clock_gating_pin 1237
is_clock_used_as_clock 1237
is_clock_used_as_data 1238
is_data 1238
is_physical 1238
launcher 1238
lib_pins 1239
net 1239
pg_hnet 1239
pg_net 1239
physical 1239
propagated_clocks 1240
propagated_ideal_network 1241
rf_slack 1242
slack_max 1242
slack_max_edge 1243
slack_max_fall 1243
slack_max_rise 1243
slew 1244
slew_by_mode 1244
startpoint 1245
timing_arcs 1245
timing_case_computed_value 1245
timing_info 1246
timing_info_favor_startpoint 1248
wire_capacitance 1250
wire_length 1250
March 2025 83 Product Version 23.1
Genus Attribute Reference
Table of Contents
wire_resistance 1250
wireload_model 1250
pin_bus Attributes for Analysis 1251
bits 1251
inst 1251
port Attributes for Analysis 1251
arrival_max_fall 1253
arrival_max_rise 1253
arrival_min_fall 1253
arrival_min_rise 1254
arrival_window 1254
bus 1254
capacitance_max_fall 1254
capacitance_max_rise 1255
capacitance_min_fall 1255
capacitance_min_rise 1255
capturer 1255
clock_sources_inverted 1256
clock_sources_non_inverted 1256
clocks 1256
connect_delay 1257
delay_max_fall 1257
delay_max_rise 1257
delay_min_fall 1257
delay_min_rise 1258
endpoint 1258
exceptions 1258
external_net_wire_capacitance 1259
generates_clocks 1259
hnet 1259
is_clock_used_as_clock 1259
is_clock_used_as_data 1260
launcher 1260
lib_pins 1261
min_port_delay 1261
net 1261
pg_hnet 1262
March 2025 84 Product Version 23.1
Genus Attribute Reference
Table of Contents
pg_net 1262
port_delay 1262
propagated_clocks 1262
slack_max 1263
slack_max_edge 1264
slack_max_fall 1264
slack_max_rise 1264
slew_by_mode 1265
startpoint 1265
timing_case_computed_value 1265
timing_info 1266
timing_info_favor_startpoint 1268
wire_capacitance 1268
wire_length 1268
wire_resistance 1269
port_bus Attributes for Analysis 1269
bits 1269
order 1269
timing_bin Attributes for Analysis 1270
is_sub_bin 1270
path_count 1270
paths 1271
root 1271
sub_bins 1272
timing_bin 1272
timing_bin_path Attribute for Analysis 1272
startpoint 1272
timing_path Attributes for Analysis 1272
bin 1274
capturing_clock 1274
capturing_clock_latency 1274
capturing_clock_pin 1275
capturing_network_latency 1275
capturing_point 1275
capturing_source_latency 1275
clock_jitter 1276
cost_group 1276
March 2025 85 Product Version 23.1
Genus Attribute Reference
Table of Contents
drive_adjustment 1276
endpoint 1276
exceptions 1277
external_delay 1278
launching_clock 1278
launching_clock_latency 1279
launching_clock_pin 1279
launching_input_delay 1279
launching_network_latency 1279
launching_point 1280
launching_source_latency 1280
path_delay 1280
path_delay_adjustment 1281
recovery_time 1281
required_time 1281
time_borrowed 1281
timing_bin 1281
timing_points 1282
uncertainty 1282
26 1283
Design for Test 1283
actual_scan_chain Attributes for DFT 1283
analyzed 1284
compressed 1284
connected_shift_enable 1284
ctl_defined 1285
dft_hookup_pin_sdi 1285
dft_hookup_pin_sdo 1285
domain 1285
edge 1286
elements 1286
head_lockup 1286
non_shared_scan_out 1286
other_clocks 1287
power_domain 1287
reg_count 1287
March 2025 86 Product Version 23.1
Genus Attribute Reference
Table of Contents
scan_clock_a 1287
scan_clock_b 1288
scan_in 1288
scan_out 1288
sdi_compression_signal 1289
shared_input 1289
shared_output 1289
shared_select 1289
shift_enable 1290
terminal_lockup 1290
actual_scan_segment Attributes for DFT 1290
active 1291
clock 1291
clock_edge 1292
clock_gating_shift_enable 1292
connected_scan_clock_a 1292
connected_scan_clock_b 1292
connected_shift_enable 1292
core_wrapper 1293
core_wrapper_type 1293
core_wrapper_usage 1293
dft_exclude_abstract_segment_from_los_pipeline 1293
dft_hookup_pin_sdi 1293
dft_hookup_pin_sdo 1294
dft_tail_test_clock 1294
dft_tail_test_clock_edge 1294
dft_tail_test_clock_waveform_edge 1294
elements 1295
head_skew_safe 1295
instance 1295
other_clocks 1296
power_domain 1296
reg_count 1296
reorderable 1296
scan_clock_a 1297
scan_clock_b 1297
scan_in 1297
March 2025 87 Product Version 23.1
Genus Attribute Reference
Table of Contents
scan_out 1298
shift_enable 1298
skew_safe 1298
tail_clock 1298
tail_clock_edge 1299
All Attributes in DFT 1299
dft_1500_child_input 1299
dft_1500_child_output 1300
dft_abstract_dont_scan 1300
dft_custom_se 1301
dft_dont_scan 1301
dft_exclude_flop_from_los_pipeline 1302
dft_exclude_from_shift_register 1303
dft_exclude_instance_from_wrapping 1303
dft_exempt_from_system_clock_check 1303
dft_force_blackbox_for_atpg 1304
dft_hier_instance_for_dedicated_wrapper 1304
dft_icg_was_cloned_or_rewired 1305
1305
dft_is_blackbox_for_atpg 1305
dft_is_los_pipeline_flop 1306
dft_is_testpoint 1306
dft_lockup_name_prefix 1307
dft_mapped 1307
dft_optimize_chain_wirelength_level 1308
dft_part_of_segment 1308
dft_partition 1309
dft_scan_chain 1309
1309
dft_scan_chain_in_multi_mode 1310
dft_status 1310
dft_test_clock 1311
dft_test_clock_edge 1311
dft_test_clock_source 1312
dft_test_clock_waveform_edge 1312
dft_testpoint_type 1313
dft_tpi_no_tp 1314
March 2025 88 Product Version 23.1
Genus Attribute Reference
Table of Contents
1314
dft_violation 1314
fcu_instruction_set 1315
mode_name 1316
1316
pin 1316
pmbist_ffn_cell 1317
1317
pmbist_ffsync_cell 1318
1318
pmbist_instruction_set 1318
pmbist_map2mux_cell 1319
1319
pmbist_unresolved 1319
1319
reset_icg_violation 1320
1320
test_enable_icg_violation 1320
1320
boundary_scan_segment Attributes for DFT 1321
acdcsel_11496 1321
acpclk_11496 1321
acpsen_11496 1322
acptrenbl_11496 1322
acpulse_11496 1322
bsdl 1322
capturedr 1323
clockdr 1323
differential_pairs 1323
highz 1324
instance 1324
mode_a 1324
mode_b 1325
mode_c 1325
shiftdr 1325
tdi 1326
tdo 1326
March 2025 89 Product Version 23.1
Genus Attribute Reference
Table of Contents
updatedr 1326
design Attributes for DFT 1326
actual_scan_chains 1327
actual_scan_segments 1327
boundary_scan 1328
boundary_scan_segments 1328
boundary_type 1328
dft_boundary_scan_exists 1328
dft_clock_edge_for_head_of_scan_chains 1328
dft_clock_edge_for_tail_of_scan_chains 1329
dft_compression_inside_hierarchy 1329
dft_configuration_modes 1330
dft_connect_scan_data_pins_during_mapping 1330
dft_connect_shift_enable_during_mapping 1330
dft_core_max_pipe_depth 1331
dft_locations_for_shared_wrapper_processing 1331
dft_lockup_element_type 1331
dft_lockup_element_type_for_tail_of_scan_chains 1332
dft_max_length_of_scan_chains 1332
dft_min_number_of_scan_chains 1333
dft_mix_clock_edges_in_scan_chains 1333
dft_opcg_edge_mode 1333
dft_scan_map_mode 1333
dft_scan_output_preference 1334
dft_shared_wrapper_exclude_port 1335
dft_shared_wrapper_input_threshold 1335
dft_shared_wrapper_output_threshold 1335
dft_tap_tck_period 1335
direct_access 1336
domain_macro_parameters 1336
formal_verification_constraints 1336
fuse_cells 1336
insert_pmbist_without_liberty_files 1336
jtag_instructions 1337
jtag_macros 1337
jtag_ports 1337
mbist_clock_domains 1337
March 2025 90 Product Version 23.1
Genus Attribute Reference
Table of Contents
mbist_enable_shared_library_domain_set 1337
memory_lib_cells 1337
opcg_domains 1338
opcg_modes 1338
opcg_triggers 1338
osc_sources 1338
pmbist_block_stitching_order 1338
pmbist_hri_async_reset 1339
pmbist_ports 1339
scan_chains 1339
scan_in_pipeline_clock_edge 1339
scan_out_pipeline_clock_edge 1340
scan_segments 1340
tap_ports 1340
test_bus_interfaces 1340
test_bus_ports 1340
test_clock_domains 1340
test_signals 1341
violations 1341
dft_configuration_mode Attributes for DFT 1341
current_mode 1341
decoded_pin 1341
jtag_instruction 1342
mode_enable_high 1342
mode_enable_low 1342
usage 1343
domain_macro_parameters Attributes for DFT 1343
counter_length 1343
max_num_pulses 1344
target_period 1344
trigger_delay 1344
fuse_cell Attributes for DFT 1344
address_limit 1344
data_order 1345
memory_lib_cell 1345
port_access 1345
port_action 1345
March 2025 91 Product Version 23.1
Genus Attribute Reference
Table of Contents
port_alias 1345
read_delay 1345
wrapper 1346
hnet Attributes for DFT 1346
dft_clock_domain_info 1346
dft_constant_value 1346
hpin Attributes for DFT 1346
dft_cloned_port_master 1347
dft_constant_value 1347
dft_controllable 1347
dft_dedicated_wrapper_reason 1348
dft_driven_by_clock 1348
dft_opcg_domain_clock_pin 1348
dft_opcg_domain_fanout_pin 1349
dft_opcg_domain_launch_clock 1349
dft_opcg_domain_se_input_pin 1349
dft_opcg_domain_unfenced_capture 1350
pmbist_dft_controllable 1350
user_differential_negative_pin 1351
user_from_core_data 1351
user_from_core_enable 1351
user_test_receiver_acmode 1351
user_test_receiver_data_output 1352
user_test_receiver_init_clock 1352
user_test_receiver_init_data 1352
user_to_core_data 1352
user_to_core_enable 1353
wrapper_control 1353
wrapper_segment 1353
wrapper_type 1353
hport Attributes for DFT 1354
dft_dedicated_wrapper_reason 1354
dft_driven_by_clock 1354
dft_opcg_domain_clock_pin 1354
dft_opcg_domain_fanout_pin 1355
dft_opcg_domain_launch_clock 1355
dft_opcg_domain_se_input_pin 1356
March 2025 92 Product Version 23.1
Genus Attribute Reference
Table of Contents
dft_opcg_domain_unfenced_capture 1356
wrapper_control 1356
wrapper_segment 1357
wrapper_type 1357
jtag_instruction_register Attributes for DFT 1357
capture 1357
length 1358
jtag_instruction Attributes for DFT 1358
capture 1359
length 1359
opcode 1359
private 1359
register 1359
register_capturedr 1360
register_capturedr_state 1360
register_clockdr 1360
register_decode 1360
register_reset 1361
register_reset_polarity 1361
register_runidle 1361
register_shiftdr 1361
register_shiftdr_polarity 1362
register_shiftdr_state 1362
register_tck 1362
register_tdi 1362
register_tdo 1362
register_updatedr 1363
register_updatedr_state 1363
tap_decode 1363
tap_tdi 1363
tap_tdo 1364
jtag_macro Attributes for DFT 1364
boundary_tdo 1365
bsr_clockdr 1365
bsr_shiftdr 1365
bsr_updatedr 1365
capturedr 1366
March 2025 93 Product Version 23.1
Genus Attribute Reference
Table of Contents
capturedr_state 1366
clockdr 1366
dot6_acdcsel 1366
dot6_acpulse 1366
dot6_preset_clock 1367
dot6_trcell_enable 1367
exitdr 1367
highz 1367
instance 1367
mode_a 1368
mode_b 1368
mode_c 1368
por 1368
reset 1368
runidle 1369
select_wir 1369
shiftdr 1369
shiftdr_state 1369
tck 1369
tdi 1370
tdo 1370
tdo_enable 1370
tms 1370
trst 1370
updatedr 1371
updatedr_state 1371
user_defined_macro 1371
jtag_port Attributes for DFT 1371
aio_pin 1372
bcell_location 1372
bcell_required 1372
bcell_segment 1372
bcell_type 1373
bdy_enable 1373
bdy_in 1373
bdy_out 1373
bsr_dummy_after 1374
March 2025 94 Product Version 23.1
Genus Attribute Reference
Table of Contents
bsr_dummy_before 1374
cell 1374
comp_enable 1374
custom_bcell 1375
differential 1375
pinmap 1375
sys_enable 1375
sys_use 1375
test_use 1376
tr_bdy_in 1377
tr_cell 1377
trcell_acmode 1377
trcell_clock 1377
trcell_enable 1377
mbist_clock Attributes for DFT 1378
dft_hookup_pin 1378
dft_hookup_polarity 1378
hookup_period 1378
internal 1379
is_jtag_tck 1379
is_srclk 1379
period 1379
pmbist_amu_siu_pipeline_controls 1379
pmbist_fcu_ciu_pipeline_controls 1380
sources 1380
memory_data_bit_structure Attributes for DFT 1380
column_order 1380
partial_row_order 1380
row_order 1380
memory_lib_cell Attributes for DFT 1381
address_limit 1381
data_order 1381
memory_lib_cell 1381
parallel_access_groups 1382
port_action 1382
port_access 1382
port_alias 1382
March 2025 95 Product Version 23.1
Genus Attribute Reference
Table of Contents
read_delay 1382
redundancy 1382
wrapper 1382
write_mask_binding 1383
memory_lib_pin_access Attributes for DFT 1383
fuse_cell 1383
is_assign 1383
memory_lib_cell 1383
port_test 1383
value 1383
memory_lib_pin_action Attributes for DFT 1384
fuse_cell 1384
memory_lib_cell 1384
value 1384
memory_lib_pin_alias Attributes for DFT 1384
base_port_name 1384
fuse_cell 1384
memory_lib_cell 1384
memory_spare_column_map_address Attributes for DFT 1385
address_logical_value 1385
address_port 1385
memory_spare_column_map_data Attributes for DFT 1385
data_logical_value 1385
data_port 1385
memory_spare_column Attributes for DFT 1385
address_bits 1386
banks 1386
bankspan 1386
data_bits 1386
db_block_size 1387
enable 1387
memory_lib_cell 1387
srclk 1387
sre 1387
srsi 1388
srso 1388
srst 1388
March 2025 96 Product Version 23.1
Genus Attribute Reference
Table of Contents
memory_spare_row_map_address Attributes for DFT 1388
address_logical_value 1388
address_port 1388
address_port_value 1389
memory_spare_row 1389
memory_spare_row Attributes for DFT 1389
address_bits 1389
banks 1390
bankspan 1390
data_bits 1390
enable 1390
memory_lib_cell 1390
memory_spare_row_map 1390
srclk 1391
sre 1391
srsi 1391
srso 1391
srst 1391
opcg_domain Attributes for DFT 1392
counter_length 1392
divide_by 1392
instance 1392
max_num_pulses 1393
min_domain_period 1393
opcg_trigger 1393
osc_source 1393
scan_clock 1393
shift_enable 1394
opcg_mode Attributes for DFT 1394
jtag_controlled 1394
mode_init 1394
osc_source_references 1394
opcg_trigger Attributes for DFT 1395
active 1395
delay_cycles 1395
inside_inst 1395
instance 1396
March 2025 97 Product Version 23.1
Genus Attribute Reference
Table of Contents
osc_source 1396
scan_clock 1396
test_signal 1396
osc_source_reference Attributes for DFT 1396
opcg_mode 1396
osc_source_period 1397
ref_clk_period 1397
osc_source Attributes for DFT 1397
max_input_period 1397
max_output_period 1397
min_input_period 1398
min_output_period 1398
ref_clock_pin 1398
pin Attributes for DFT 1399
dft_constant_value 1399
dft_controllable 1400
dft_dedicated_wrapper_reason 1400
dft_driven_by_clock 1400
dft_multibit_abstract_segment_present 1400
dft_multibit_input_is_io_bound 1400
dft_multibit_output_is_io_bound 1401
dft_opcg_domain_clock_pin 1401
dft_opcg_domain_fanout_pin 1401
dft_opcg_domain_launch_clock 1401
dft_opcg_domain_se_input_pin 1402
dft_opcg_domain_unfenced_capture 1402
pmbist_dft_controllable 1403
user_differential_negative_pin 1403
user_from_core_data 1403
user_from_core_enable 1404
user_test_receiver_acmode 1404
user_test_receiver_data_output 1404
user_test_receiver_init_clock 1404
user_test_receiver_init_data 1404
user_to_core_data 1405
user_to_core_enable 1405
wrapper_control 1405
March 2025 98 Product Version 23.1
Genus Attribute Reference
Table of Contents
wrapper_segment 1405
wrapper_type 1406
pmbist_port Attributes for DFT 1406
pmbist_port_name 1406
function 1406
port Attributes for DFT 1406
dft_dedicated_wrapper_reason 1407
dft_driven_by_clock 1407
dft_enable_hookup_pin 1407
dft_enable_hookup_polarity 1408
dft_opcg_domain_clock_pin 1408
dft_opcg_domain_fanout_pin 1408
dft_opcg_domain_launch_clock 1409
dft_opcg_domain_se_input_pin 1409
dft_opcg_domain_unfenced_capture 1409
dft_sdi_output_hookup_pin 1410
dft_sdo_input_hookup_pin 1410
wrapper_control 1411
wrapper_segment 1411
wrapper_type 1411
programmable_direct_access_function Attributes for DFT 1411
active 1412
connection 1412
dft_hookup_pin 1412
dft_hookup_polarity 1412
instance 1412
source 1412
root Attributes for DFT 1413
dft_1500_hierarchical_parent_child_wrapping 1414
dft_1500_hierarchical_softcore_wrapping 1414
dft_add_mux_on_pre_connected_ctl_si 1415
dft_allow_dwc_in_top 1415
dft_apply_sdc_constraints 1415
dft_atpg_executable 1416
dft_auto_create_chains_as_internal 1416
dft_auto_identify_shift_register 1417
dft_boundary_cell_module_prefix 1417
March 2025 99 Product Version 23.1
Genus Attribute Reference
Table of Contents
dft_boundary_scan_timing_mode_name 1418
dft_capture_11496_reciever_output 1418
dft_capture_timing_mode_name 1418
dft_check_cfg_mode_aware 1419
dft_clock_waveform_divide_fall 1419
dft_clock_waveform_divide_period 1420
dft_clock_waveform_divide_rise 1420
dft_clock_waveform_fall 1420
dft_clock_waveform_period 1421
dft_clock_waveform_rise 1421
dft_compression_2d_aspect_ratio 1422
dft_compression_2d_decomp_pipeline_distance 1422
dft_compression_2d_grid_max_x 1423
dft_compression_2d_grid_max_y 1423
dft_compression_2d_grid_min_x 1423
dft_compression_2d_grid_min_y 1424
dft_compression_auto_create 1424
dft_compression_channel_length 1425
dft_compression_comp_pipeline_max_xor_depth 1425
dft_compression_compressor_type 1425
dft_compression_decomp_pipeline_max_xor_depth 1426
dft_compression_decompressor_type 1426
dft_compression_elasticity_ratio 1427
dft_compression_extest_decompressor_type 1427
dft_compression_fullscan_support 1428
dft_compression_lp_gating_sharing_ratio 1428
dft_compression_lp_gating_support 1428
dft_compression_mask_and_lp_gating_unload_support 1429
dft_compression_mask_sharing_ratio 1429
dft_compression_mask_support 1430
dft_compression_masken_pipeline_depth 1430
dft_compression_num_extest_scanin 1431
1431
dft_compression_num_extest_scanout 1431
1431
dft_compression_num_scanin 1431
dft_compression_num_scanout 1432
March 2025 100 Product Version 23.1
Genus Attribute Reference
Table of Contents
dft_compression_opcg_unload_support 1432
dft_compression_post_2d_sdc_file 1433
dft_compression_post_2d_sdc_mode_name 1433
dft_compression_ratio 1434
dft_compression_scanin_pipeline_depth 1434
dft_compression_scanout_pipeline_depth 1434
dft_compression_serial_load_support 1435
dft_cross_lp_cells_for_lockup_clk_driver 1435
dft_disable_wrapper_inside_non_scan_elem 1436
dft_dont_merge_multibit_lockup 1436
dft_dont_wrap_if_shared_threshold_exceed 1437
dft_enable_flop_placement_in_test_point_insertion 1437
dft_enable_wir_function_check 1438
dft_exclude_internal_flops_from_shared_wrapper_threshold 1438
dft_exclude_tdrc_fail_seg 1438
dft_extended_scandef 1439
dft_fence_slow_speed_domains 1439
dft_generate_atpg_no_testpoint_file 1439
dft_get_balanced_chains_assignment 1440
dft_identify_internal_test_clocks 1441
dft_identify_non_boundary_shift_registers 1441
dft_identify_shared_wrapper_cells 1442
dft_identify_test_signals 1442
dft_identify_top_level_test_clocks 1443
dft_identify_xsource_violations_from_timing_models 1443
dft_ignore_dont_scan_for_shared_wrapper_processing 1443
dft_ignore_non_scan_for_wrapper_processing 1444
dft_include_controllable_pins_in_abstract_model 1444
dft_include_test_signal_outputs_in_abstract_model 1445
dft_insert_dedicated_inside_sink_hierarchy 1445
dft_jtag_instance_name 1446
dft_jtag_module_name 1446
dft_lbist_capture_timing_mode_name 1447
dft_lbist_shift_timing_mode_name 1447
dft_license_scheme 1447
dft_modedef_internal 1448
dft_modus_version 1448
March 2025 101 Product Version 23.1
Genus Attribute Reference
Table of Contents
dft_opcg_block_input_to_flop_paths 1449
dft_opcg_domain_blocking 1449
dft_opcg_timing_mode_name 1450
dft_physical_aware_test_points 1450
dft_physical_pd_aware_scan_connection 1450
dft_pmbist_jtag_timing_mode_name 1451
dft_pmbist_mda_timing_mode_name 1451
dft_power_aware_lockup_clock_driver 1452
dft_power_aware_wrapper_insertion 1452
dft_prefix 1452
dft_process_multibit_for_shared_wrapper 1453
dft_propagate_test_signals_from_hookup_pins_only 1453
dft_report_empty_test_clocks 1454
dft_report_scan_register_quiet 1454
dft_rtl_insertion 1455
dft_run_test_point_analysis_for_compression 1455
dft_run_test_point_analysis_for_lbist 1455
dft_scan_power_domain_crossing_lockup_latch 1456
dft_scan_style 1456
dft_scanbit_waveform_analysis 1457
dft_sdc_input_port_delay 1457
dft_sdc_output_port_delay 1458
dft_shared_common_logic_threshold 1458
dft_shared_wrapper_through 1458
dft_shift_register_identification_mode 1459
dft_shift_register_max_length 1459
dft_shift_register_min_length 1460
dft_shift_register_with_mbci 1460
dft_shift_timing_mode_name 1461
dft_tap_lockup_clock_from_adjacent 1461
dft_tpi_sharing_scope 1461
dft_true_time_flow 1462
dft_use_abstract_segment_instance_power_domain_for_scan_connection 1462
dft_use_multibit_register_width_for_threshold 1463
dft_use_wck_as_default_wrapper_clock 1463
dft_wait_for_license 1463
non_dft_timing_mode_name 1464
March 2025 102 Product Version 23.1
Genus Attribute Reference
Table of Contents
pmbist_enable_multiple_views 1464
pmbist_full_async_reset 1465
unmap_scan_flops 1465
scan_chain Attributes for DFT 1466
body 1466
complete 1466
compressed 1467
dft_hookup_pin_sdi 1467
dft_hookup_pin_sdo 1467
domain 1467
edge 1467
head 1468
max_length 1468
non_shared_scan_out 1468
scan_clock_a 1468
scan_clock_b 1469
scan_in 1469
scan_out 1469
sdi_compression_signal 1470
shared_input 1470
shared_output 1470
shared_select 1470
shift_enable 1470
tail 1471
terminal_lockup 1471
scan_segment Attributes for DFT 1471
active 1472
clock 1472
clock_edge 1473
clock_gating_shift_enable 1473
connected_scan_clock_a 1473
connected_scan_clock_b 1473
connected_shift_enable 1473
core_wrapper 1474
core_wrapper_ports 1474
core_wrapper_type 1474
core_wrapper_usage 1475
March 2025 103 Product Version 23.1
Genus Attribute Reference
Table of Contents
ctl_defined 1475
dft_hookup_pin_sdi 1475
dft_hookup_pin_sdo 1475
dft_tail_test_clock 1475
dft_tail_test_clock_edge 1476
dft_tail_test_clock_waveform_edge 1476
elements 1476
head_skew_safe 1477
instance 1477
model_defined 1477
other_clocks 1477
power_domain 1478
reg_count 1478
reorderable 1478
scan_clock_a 1479
scan_clock_b 1479
scan_in 1479
scan_out 1479
shift_enable 1480
skew_safe 1480
tail_clock 1480
tail_clock_edge 1481
test_modes 1481
user_defined_segment 1481
tap_port Attributes for DFT 1481
dft_hookup_pin 1482
dft_hookup_polarity 1482
test_bus_port Attributes for DFT 1482
active 1482
dft_hookup_pin 1482
function 1482
test_clock Attributes for DFT 1483
at_speed 1483
atpg_use 1484
blocking_se 1484
controllable 1484
controllable_from 1485
March 2025 104 Product Version 23.1
Genus Attribute Reference
Table of Contents
dft_hookup_pin 1485
dft_hookup_polarity 1485
dft_mask_clock 1485
dft_misr_clock 1485
divide_fall 1486
divide_period 1486
divide_rise 1486
domain_se 1486
fall 1487
function 1487
off_state 1487
period 1487
rise 1488
root_source_pins 1488
root_source_polarity 1488
sources 1488
user_defined_signal 1489
test_signal Attributes for DFT 1489
active 1489
atpg_use 1490
dedicated_pin 1490
default_shift_enable 1491
dft_compression_signal 1491
dft_hookup_pin 1491
dft_hookup_polarity 1492
divide_fall 1492
divide_period 1492
divide_rise 1492
fall 1493
function 1493
has_fanout 1493
ideal 1493
lec_value 1494
master_signal 1494
period 1494
pmbist_use 1495
rise 1495
March 2025 105 Product Version 23.1
Genus Attribute Reference
Table of Contents
scan_shift 1496
user_defined_signal 1496
wir_reset_value 1496
wir_signal 1496
wir_tm_value 1497
violation Attributes for DFT 1497
description 1497
endpoints 1499
file_name 1499
fixed 1499
id 1500
line_number 1500
reg_count 1500
registers 1500
root_node 1501
segments 1501
tristate_net_drivers 1501
tristate_net_load 1501
write_mask_bit Attributes for DFT 1501
masked_bits 1501
memory_lib_cell 1501
27 1503
Low Power Synthesis (LPS) 1503
1801 1503
cpf 1504
incr_joules_instance_threshold_count_MT 1504
instance_internal_power 1505
instance_leakage_power 1506
isolation_rules 1507
joules_incremental_silent 1507
joules_silent 1507
leakage_power 1508
level_shifter_rules 1509
lp_asserted_probability 1510
lp_asserted_toggle_rate 1511
lp_clock_tree_buffers 1512
March 2025 106 Product Version 23.1
Genus Attribute Reference
Table of Contents
lp_clock_tree_leaf_max_fanout 1512
lp_computed_probability 1513
lp_computed_toggle_rate 1514
lp_display_negative_internal_power 1515
lp_dynamic_analysis_scope 1515
lp_get_state_dependent_lkg_pow 1516
lp_internal_power 1516
lp_leakage_power 1517
lp_net_power 1518
lp_power_unit 1520
lp_probability_type 1520
lp_pso_aware_estimation 1521
lp_pso_aware_tcf 1522
lp_system_asserted_probability 1523
lp_system_asserted_toggle_rate 1523
lp_toggle_rate_type 1524
lp_toggle_rate_unit 1525
lp_x_transition_probability_count 1526
lp_x_transition_toggle_count 1526
lp_z_transition_probability_count 1527
lp_z_transition_toggle_count 1528
macro_isolation_rules 1528
macro_model 1529
macro_models 1529
macro_power_domains 1530
nominal_conditions 1530
opt_leakage_to_dynamic_ratio 1530
power_engine 1531
power_model 1532
power_models 1532
power_modes 1533
power_scope 1533
1533
power_scopes 1534
repeater_rules 1535
state_retention_rules 1535
March 2025 107 Product Version 23.1
Genus Attribute Reference
Table of Contents
28 1536
Advanced Low Power 1536
hnet Attributes for Adv LPS 1536
power_duty_cycle 1536
power_switching 1537
power_toggle_rate 1537
power_toggle_rate_source 1537
hpin Attributes for Adv LPS 1537
isolation_rule 1537
level_shifter_rule 1538
hport Attributes for Adv LPS 1538
isolation_rule 1538
level_shifter_rule 1539
isolation_rule Attributes for Adv LPS 1539
cells 1540
cpf_pins 1540
enable_driver 1541
enable_polarity 1541
exclude_pins 1541
from_power_domain 1542
off_domain 1542
output_value 1542
pins 1543
prefix 1543
to_power_domain 1544
within_hierarchy 1544
level_shifter_rule Attributes for Adv LPS 1544
cells 1545
cpf_pins 1545
exclude_pins 1546
from_power_domain 1546
pins 1546
prefix 1547
to_power_domain 1547
within_hierarchy 1548
nominal_condition Attributes for Adv LPS 1548
March 2025 108 Product Version 23.1
Genus Attribute Reference
Table of Contents
ground_voltage 1548
library_set 1549
pin Attributes for Adv LPS 1549
isolation_rule 1549
level_shifter_rule 1550
related_ground_pin 1550
related_power_pin 1550
port Attributes for Adv LPS 1551
isolation_rule 1551
level_shifter_rule 1551
power_domain Attributes for Adv LPS 1552
available_supply_nets 1552
available_supply_sets 1553
base_domains 1553
core_to_bottom 1553
core_to_left 1553
core_to_right 1554
core_to_top 1554
default_tech_site 1554
dft_iso_rule 1554
is_default 1554
is_virtual 1555
primary_ground_is_always_on 1555
primary_ground_net 1555
primary_power_is_always_on 1556
primary_power_net 1556
shutoff_condition 1556
shutoff_condition_inputs 1556
power_mode Attributes for Adv LPS 1556
constraint_mode 1557
domain_conditions 1557
state_retention_rule Attributes for Adv LPS 1557
cell_type 1557
cells 1558
restore 1558
restore_phase 1559
save 1559
March 2025 109 Product Version 23.1
Genus Attribute Reference
Table of Contents
save_phase 1559
29 1560
Joules 1560
cglar_da_threshold 1560
cglar_max_distance 1561
cglar_min_slack_threshold 1562
cglar_ps_threshold 1562
enable_xor_gating_during_map 1563
xedebug_executable 1564
30 1565
Innovus 1565
innovus.add_fillers 1566
add_fillers_cell_name_style 1566
innovus.delaycal 1566
innovus.design 1568
innovus.floorplan 1569
innovus.ilm 1571
innovus.init 1572
innovus.opt 1572
innovus.place 1577
innovus.power_intent 1580
innovus.rc_extraction 1581
innovus.reorder_scan 1582
innovus.route 1583
innovus.route_early_global 1587
innovus.timing 1588
timing_analysis_* 1589
timing_aocv_* 1589
timing_apply_* 1590
timing_check_* 1590
timing_clock_* 1590
timing_collection_* 1590
timing_constraint_* 1591
timing_context_* 1591
timing_cppr_* 1592
timing_derate_* 1592
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timing_disable_* 1593
timing_enable_* 1594
timing_extract_model_* 1595
timing_generate_* 1596
timing_library_* 1596
timing_path_based_* 1597
timing_property_* 1597
timing_report_* 1598
timing_use_* 1599
Other timing_* 1600
31 1602
Alphabetical List of Attributes 1602
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About This Manual
About This Manual
This manual provides a concise reference of the attributes available to the user when using the Genus software with the common
user interface.
Attributes can be used to control the way in which the Genus shell operates. Changing the settings of these attributes is performed
using the set_db command.
The following information is also available in this chapter:
Additional References
Reporting Problems or Errors in Manuals
Customer Support
Supported User Interfaces
Message Details
Man Pages
Command-Line Help
Documentation Conventions
New Attributes
Additional References
The following sources are helpful references, but are not included with the product documentation:
TclTutor, a computer aided instruction package for learning the Tcl language: http://www.msen.com/~clif/TclTutor.html.
TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley Publishing Company
Practical Programming in Tcl and Tk, Brent Welch and Ken Jones
IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (IEEE Std.1364-
1995)
IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (IEEE Std. 1364-
2005)
IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language (IEEE STD 1800-
2009)
IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1987)
IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1993)
IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-2008)
For information on purchasing IEEE specifications go to http://shop.ieee.org/store/ and click on Publications & Standards.
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About This Manual--Reporting Problems or Errors in Manuals
Reporting Problems or Errors in Manuals
The Cadence® Doc Assistant online documentation, lets you view, search, and print Cadence product documentation. You can
access Cadence Doc Assistant by typing cda from your Cadence tools hierarchy. For more information about Doc Assistant, see
Doc Assistant User Guide.
Contact Cadence Customer Support to file a CCR if you find:
An error in the manual
An omission of information in a manual
A problem using the Cadence Doc Assistant documentation system
Customer Support
Cadence offers live and online support, as well as customer education and training programs and these are described in:
Cadence Online Support
Other Support Offerings
Cadence Online Support
The Cadence® online support website offers answers to your most common technical questions. It lets you search more than
40,000 FAQs, notifications, software updates, and technical solutions documents that give you step-by-step instructions on how to
solve known problems. It also gives you product-specific e-mail notifications, software updates, case tracking, up-to-date release
information, full site search capabilities, software update ordering, and much more. For more information on Cadence online
support go to http://support.cadence.com.
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Other Support Offerings
Support centers—Provide live customer support from Cadence experts who can answer many questions related to products
and platforms.
Software downloads—Provide you with the latest versions of Cadence products.
University software program support—Provides you with the latest information to answer your technical questions.
Training Offerings—Cadence offers the following training courses for Genus users:
Basic Static Timing Analysis
Advanced Synthesis with Genus Stylus Common UI
Fundamentals of IEEE 1801 Low-Power Specification Format
Genus Low-Power Synthesis Flow with IEEE 1801
Genus Synthesis Solution with Stylus Common UI
Joules Power Calculator
Low-Power Synthesis Flow with Genus Stylus Common UI
Test Synthesis with Genus Stylus Common UI
The courses listed above are available in North America. For further information on the training courses available in your
region, visit Cadence Training or write to '[email protected]'.
The links in this section open in a new browser.
Digital Badge Exams
Cadence offers Digital Badge exams for all the Genus Synthesis Solution courses for our customers and University students.
The exams can be taken from Training Courses (cadence.com).
Upon passing the exams, you get certificates (verified by https://info.credly.com/), which can then be shared on your LinkedIn
profiles, Facebook, and Twitter. For more information, refer to 'Become Cadence Certified'.
Video Library
Several videos are available on the support website: Genus: Video Library
For more information on the support offerings go to http://www.cadence.com/support.
Supported User Interfaces
Genus supports the following user interfaces:
Unified User Interface. Genus, Innovus and Tempus offer a fully unified Tcl scripting language and GUI environment. This
unified user interface (also referred to as Stylus common UI) streamlines flow development and improves productivity of
multi-tool users.
When you start Genus, you will by default start with the Stylus common UI. You will see the following prompt:
@genus:root: 1>
Legacy User Interface. Genus can also operate in legacy mode which supports RTL Compiler commands/attributes and
scripting.
To start Genus with legacy UI, you can
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About This Manual--Message Details
Start the tool with legacy UI as follows:
%genus -legacy_ui -files script
....
legacy_genus:/>
Switch to legacy UI if you started the tool with the default Stylus common UI.
%genus
@genus:root: 1> set_db common_ui false
legacy_genus:/>
This document provides information specific to the Stylus common user interface.
Message Details
You can get detailed information for each message issued in your current Genus run using the report_messages command.
@genus:root: number> report_messages
The report also includes a summary of how many times each message was issued.
You can also get specific information about a message.
For example, to get more information about the TUI-613 message, you can type the following command:
legacy_genus:/> vls -a TUI-613
message:TUI/TUI-613 (message)
Attributes:
base_name = TUI-613
count = 0
escaped_name = TUI/TUI-613
help = The user_speed_grade is only applicable to datapath subdesigns.
id = 613
name = TUI/TUI-613
obj_type = message
print_count = 0
priority = 1
screen_print_count = 0
severity = Warning
type = The attribute is not applicable to the object.
You can also use the help command:
@genus:root: number> help TUI-613Message:name: TUI/TUI-613severity: Warningtype: The attribute is not
applicable to the object.help: The user_speed_grade is only applicable to datapath subdesigns.
If you do not get the details that you need or do not understand a message, either contact Cadence Customer Support to file a
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About This Manual--Man Pages
CCR or email the message ID you would like improved to '[email protected]'.
Man Pages
In addition to the Command and Attribute References, you can also access information about the commands and attributes using
the man pages in Genus.
To use man pages from UNIX shell:
1. Set your environment to view the correct directory:
setenv MANPATH $CDN_SYNTH_ROOT/share/synth/man_common
2. Access the manpage by either of the following ways:
Enter the name of the command or attribute that you want. For example:
man check_dft_rules
man max_output_voltage
Specify a section number with man command to look for the command or attribute information in the specific section of
the on-line manual.
Commands are in section 1, attributes are in section 2, and messages are in section 3 of the on-line manual. In the
absence of section number, man will search through sections 1, 2, 3 (in this sequence) and display the first matching
manual page.
This is useful in cases where both commands and attributes exist with the same name. For example:
man 1 retime
will display manhelp for retime command
man 2 retime
will display manhelp for retime attribute
Refer to man for more information on the man command.
Command-Line Help
You can get quick syntax help for commands and attributes at the Genus command-line prompt and they are described in the
following sections:
Getting the Syntax for a Command
Getting Attribute Help
Searching For Commands When You Are Unsure of the Name
Getting the Syntax for a Command
Type the help command followed by the command name.
For example:
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@genus:root: number> help path_group
This returns the syntax for the path_group command.
Getting Attribute Help
Type the following:
@genus:root: number> help attribute_name
For example:
@genus:root: number> help wlec_gzip_fv_json
This returns the help for the wlec_gzip_fv_json attribute and shows on which object types the attribute can be specified, as shown
below.
If an attribute belongs to more than one object type, Genus displays its help in compact format. An example is shown below:
@genus:root: help late_fall_cell_check_sigma_derate_factor
Attributes:
late_fall_cell_check_sigma_derate_factor(hinst):
# double, read/write, default=1.0, indices=analysis_view # Specifies derating sigma
factor to the falling edge of late data paths on timing checks.
late_fall_cell_check_sigma_derate_factor(inst):
# double, read/write, default=1.0, indices=analysis_view # Specifies derating sigma
factor to the falling edge of late data path
Searching For Commands When You Are Unsure of the Name
You can use help to find a command or a Tcl process if you only know part of its name, even as little as one letter.
You can type a single letter or sequence of letters and press Tab to get a list of all commands and any user-defined Tcl processes
that start with the letter(s).
For example:
@genus:root: number> ad <Tab>
This returns the following commands:
add_assign_buffer_options add_clock_gates_obsadd_clock_gates_test_connection add_opcg_hold_mux...
There are also enhanced search capabilities so you can more easily search for the command or attribute that you need.
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About This Manual--Documentation Conventions
The command syntax representation in this document does not necessarily match the information that you get when you
type help command_name. In many cases, the order of the arguments is different. Furthermore, the syntax in this document
includes all of the dependencies, where the help information does this only to a certain degree.
If you have any suggestions for improving the command-line help, e-mail them to '[email protected]'.
Documentation Conventions
To aid the readers understanding, a consistent formatting style has been used throughout this manual.
UNIX commands are shown following the unix> string.
Genus commands are shown following the @genus:root: number> string.
Text Command Syntax
The list below describes the syntax conventions used for the Genus attributes:
literal Nonitalic words indicate keywords that you must type literally. These keywords represent command,
attribute or option names
arguments and options Words in italics indicate user-defined arguments or options for which you must substitute a name or a
value.
| Vertical bars (OR-bars) separate possible choices for a single argument.
[] Brackets denote options. When used with OR-bars, they enclose a list of choices from which you can
choose one.
{} Braces denote arguments and are used to indicate that a choice is required from the list of arguments
separated by OR-bars. You must choose one from the list
{ argument1 | argument2 | argument3 }
Braces, used in Tcl command examples, indicate that the braces must be typed in.
... Three dots (...) indicate that you can repeat the previous argument. If the three dots are used with
brackets (that is, [argument]...), you can specify zero or more arguments. If the three dots are used
without brackets (argument...), you must specify at least one argument, but can specify more.
{} Braces in bold-face type must be entered literally.
# The pound sign precedes comments in command files.
New Attributes
New in 23.14
New in 23.13
New in 23.12
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New in 23.11
New in 23.14
The following new attributes are available with this release of Genus:
Genus
dft_1500_child_input
dft_1500_child_output
dft_1500_hierarchical_parent_child_wrapping
dft_lockup_name_prefix
dft_optimize_chain_wirelength_level
dont_break_combo_loops_thr_c_to_q_macro
dont_break_combo_loops_thr_en_to_q
flowtool_schedule_flow_immediate
is_backside
lp_clock_gating_exclude_signal
retime_ssw_sync_enable
safety_parity_error_signal_endpoint
safety_tmr_error_signal_endpoint
Innovus
innovus.delaycal
delaycal_nonlinear_voltage_scaling_improvements
delaycal_use_top_interface_delay_in_context
delaycal_voltage_scaling_compatibility_mode
innovus.opt
opt_enable_clock_pulse_width_checks
innovus.place
place_detail_pgftv_insertion_cell_list
innovus.route
route_disable_route_rule_on_via_pillar_to_special_net_wire
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innovus.timing
timing_report_arrival_property_worstcase_mode
timing_report_constraint_extended_cell_em_flow
timing_report_default_frequency_for_unconstrained_nets
timing_report_drv_per_frequency
timing_report_enable_em_index_clipping_report
New in 23.13
The following new attributes are available with this release of Genus:
Genus
continuous_fast_report_timing
cross_probe_frc_value
dft_get_balanced_chains_assignment
dpopt_power_opto
flow_write_db_snapshot
flow_write_db_snapshot_exclude_time
init_oa_foundry_rule
multibit_invert_clock_phase
opt_allow_floating_outputs
opt_tns
preserve_sdc_annotated_comb_insts
Innovus
innovus.design
design_power_density_target
design_power_density_tile_size_x
design_power_density_tile_size_y
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innovus.timing
timing_context_apply_port_sdc_exceptions
timing_context_enable_unmapped_clock_analysis
timing_enable_hier_context_unmapped_clock_analysis
timing_enable_zero_delay_analysis_mode
New in 23.12
The following new attributes are available with this release of Genus:
avoid (base_cell) corresponding_q_or_ delaycal_advanced_
qn_pin calculation_mode
dft_cross_lp_cells_for_l dft_disable_wrapper extract_rc_quantus_
ockup_clk_driver _inside_non_scan_e executable
lem
floorplan_move_child_c hdl_convert_onebit_ hdl_convert_onebit_
onstraint_with_constrai vector_to_scalar vector_wire_to_scala
nt (hdl_architecture) r
invs_spatial_place_con multibit_aware_seq_ opt_route_opt_recov
nected mapping_higher_prio ery
rity
preserve (base_cell) speed_up_read_soc timing_all_registers_f
v ilter_clock_pins_by_
clock
timing_enable_cap_fan
out_in_copy_drv_assert
ions
New in 23.11
The following new attributes are available with this release of Genus:
delaycal_advanced_accuracy_mod delaycal_enable_input_slew_sensitivi dft_enable_flop_placement_in_test_
e ty_on_constraint point_insertion
dft_icg_was_cloned_or_rewired dft_run_test_point_analysis_for_comp dft_run_test_point_analysis_for_lbist
ression
dft_tpi_no_tp display_information_of_edit_netlist dont_break_combo_loops_thr_c_to_
q
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floorplan_extra_row_pattern handle_ungroup_names invs_init_core_row
is_buffer (hinst) is_flop (hinst) is_inverter (hinst)
is_latch (hinst) latch_max_borrow_interface mark_retention_pin_ideal
metric_capture_vth_metrics multibit_area_power_scoring opt_clone_insts_list
opt_early_hold_fixing opt_enable_targeted_synthesis opt_icg_enable_pin_rebuffering
place_design_enable_3d place_design_integrity_ir_fix_effort report_clock_from_different_views
reset_icg_violation route_design_high_freq_bus_mixed_l route_early_detail_in_preroute
ayer
route_interposer_control_options route_shield_length_threshold route_shield_stripe_layer_range
safety_dcls_isolate_groups safety_dcls_isolate_halo_type safety_dcls_isolate_inputs
safety_dcls_isolate_is_group_input_ safety_dcls_isolate_is_group_output_ safety_dcls_isolate_is_halo
cell cell
safety_dcls_isolate_outputs safety_dcls_isolate_pin safety_dcls_isolate_reset
safety_dcls_isolate_scan_enable safety_dcls_isolate_signal_type safety_dcls_isolate_type
safety_dcls_isolate_use_halo safety_dcls_route_types safety_ser_cells
safety_ser_type safety_tmr_isolate_reset safety_tmr_isolate_scan_enable
safety_tmr_well_tap_cells safety_tmr_well_tap_left_padding safety_tmr_well_tap_right_padding
skip_ungroup_on_applied_constrain speedup_library_establishment test_enable_icg_violation
t
timing_all_registers_identify_macros timing_analysis_aging timing_analysis_enable_robustness
_include_is_macro_cell _mode
timing_apply_default_primary_input timing_context_continue_on_invalid_ timing_derate_voltage_scaling_mod
_assertion module_list e
timing_enable_unique_vt_mode_for timing_enable_vtskew_derate_mode timing_report_constraint_format
_gba
timing_report_constraint_use_infinit timing_report_drv_enable_ghz_notati timing_report_drv_use_worst_timing
y_slack_for_unconstrained on_for_drv_fields _slack
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Introduction
1
Introduction
This document describes the syntax of the Genus attributes.
An attribute is a setting that controls how Genus operates on objects. For example: during synthesis
and technology mapping.
An object is anything Genus can manipulate, such as libraries, designs, modules, instances, ports,
constraints, scan chains, and so on.
This chapter discusses the following topics:
More on Attributes and Objects
Setting and Getting Attribute Values
More on Attributes and Objects
Design data is originally stored in the design hierarchy on the corresponding objects when reading
in the libraries, the HDL files, and the constraints. During the synthesis session, the design
information hierarchy (including the objects and attributes) is continuously updated.
In this book, the attributes are organized according to functional categories:
Input and Output (IO) attributes affect how the HDL files are read in or written out
Design for Test attributes affect scan chain insertion
Low Power Synthesis (LPS) attributes control clock-gating insertion, leakage and dynamic
power optimization and so on
In each functional category, attributes are listed with the object types they can be set on.
Setting and Getting Attribute Values
The following attribute types are discussed in this section:
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Introduction--More on Attributes and Objects
The following attribute types are discussed in this section:
actual_scan_chain Attributes
actual_scan_segment Attributes
analysis_view Attributes
constraint_mode Attributes
delay_corner Attributes
design Attributes
hinst Attributes
inst Attributes
library_domain Attributes
library_set Attributes
mode Attributes
module Attributes
rc_corner Attributes
root Attributes
timing_condition Attributes
actual_scan_chain Attributes
Contain information about the final scan chains connected in the specified design. These attributes
are read-only attributes, so you cannot set their values.
To get an actual_scan_chain attribute value, type:
get_db [vfind /des*/design -actual_scan_chain name] .attribute_name
To get the actual scan chains of a design, type:
@genus:root: number> get_db actual_scan_chains *
These attributes are located at:
/designs/design/dft/report/actual_scan_chains
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Introduction--More on Attributes and Objects
actual_scan_segment Attributes
Contain information about the final scan segments connected in the specified design. These
attributes are read-only attributes, so you cannot set their values.
To get an actual_scan_segment attribute value, type:
get_db [vfind /des*/design -actual_scan_segment name] .attribute_name
To get the actual scan segments of a design, type:
@genus:root: number> get_db actual_scan_segments *
These attributes are located at:
/designs/design/dft/report/actual_scan_segments
analysis_view Attributes
To get an analysis_view attribute value, type:
get_db analysis_view:design/view .attribute_name
To get the analysis views of a design, type:
@genus:root: number> get_db analysis_views *
Example
@genus:root: number> get_db analysis_views
analysis_view:dtmf_recvr_core/view_wcl_slow analysis_view:dtmf_recvr_core/view_wcl_fast
analysis_view:dtmf_recvr_core/view_wcl_typical
constraint_mode Attributes
To get a constraint_mode attribute value, type:
get_db constraint_mode:design/constraint_mode .attribute_name
To get the constraint modes of a design, type:
@genus:root: number> get_db constraint_modes *
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Example
@genus:root: number> get_db constraint_modes *
constraint_mode:dtmf_recvr_core/funct_wcl_slow constraint_mode:dtmf_recvr_core/funct_wcl_fast
constraint_mode:dtmf_recvr_core/funct_wcl_typical
delay_corner Attributes
To get a delay_corner attribute value, type:
get_db delay_corner:design/delay_corner .attribute_name
To get the delay corners of a design, type:
@genus:root: number> get_db delay_corners *
Example
@genus:root: number> get_db delay_corners *
delay_corner:dtmf_recvr_core/delay_corner_wcl_slow
delay_corner:dtmf_recvr_core/delay_corner_wcl_fast
delay_corner:dtmf_recvr_core/delay_corner_wcl_typical
design Attributes
Contain information about the specified design.
To set a design attribute, type:
set_db attribute_name attribute_value /designs/design
or
set_db [vfind /des* -design name] .attribute_name attribute_value
To get a design attribute value, type:
get_db / .attribute_name design
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hinst Attributes
Contain information about a hierarchical instance in the specified design.
To set an hinst attribute, type:
set_db [vfind /des*/design -hinst name] .attribute_name attribute_value
To get an hinst attribute value, type:
get_db [vfind /des*/design -hinst name] .attribute_name
inst Attributes
Contain information about a combinational or sequential instance in the specified design.
To set an inst attribute, type:
set_db [vfind /des*/design -inst name] .attribute_name attribute_value
To get an inst attribute value, type:
get_db [vfind /des*/design -inst name] .attribute_name
library_domain Attributes
Contain information about the libraries associated with a library domain. These attributes are read-
write attributes.
To set a library_domain attribute value, type:
set_db [vfind /libraries -library_domain domain] .attribute_name \attribute_value
To get a library_domain attribute value, type:
get_db [vfind /libraries -library_domain domain] .attribute_name
These attributes are located at:
/libraries/library_domains/domain.
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library_set Attributes
To get a library_set attribute value, type:
get_db library_set:library_set_name .attribute_name
To get the delay corners, type:
@genus:root: number> get_db library_sets
Example
@genus:root: number> get_db library_sets
library_set:wcl_slow library_set:wcl_fast library_set:wcl_typical
mode Attributes
Contain information about the design modes of the design. Mode objects are found in the mode
directory in the design directory. These attributes are read-only attributes, so you cannot set their
values.
To get a mode attribute value, type:
get_db [vfind /des*/design -mode name] .attribute_name
module Attributes
Contain information about the modules in the specified design. Modules correspond to Verilog
modules or VHDL entities instantiated in the top-level Verilog module or top-level VHDL entity.
To set a module attribute, type:
get_db [vfind /des*/design -module name] .attribute_name attribute_value
To get a module attribute value, type:
get_db [vfind /des*/design -module name] .attribute_name
These attributes are located at:
/designs/design/modules
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Introduction--More on Attributes and Objects
rc_corner Attributes
To get an rc_corner attribute value, type:
get_db rc_corner:rc_corner .attribute_name
To get all rc_corners, type:
@genus:root: number> get_db rc_corners
Example
@genus:root: number> get_db rc_corners
rc_corner:rc_corner
root Attributes
Contain information about all loaded designs. The root object is identified by a forward slash (/).
To set a root attribute, type:
set_db / .attribute_name attribute_value /
To get a root attribute value, type:
get_db / .attribute_name /
timing_condition Attributes
To get a timing_condition attribute value, type:
get_db timing_condition:timing_condition .attribute_name
To get all timing_conditions, type:
@genus:root: number> get_db timing_conditions
Example
@genus:root: number> get_db timing_conditions
timing_condition:timing_cond_wcl_slow timing_condition:timing_cond_wcl_fast
timing_condition:timing_cond_wcl_typical
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General
2
General
The chapter describes the attributes of the following object types:
attribute Attributes
base_cell Attributes
command Attributes
command_option Attributes
attribute Attributes
additional_help
category
check_function
compute_function
data_type
default_value
help
indices
is_computed
is_hidden
is_obsolete
is_saved
is_settable
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General--attribute Attributes
is_user_defined
possible_values
set_function
skip_in_db
units
additional_help
additional_help string
Read-only attribute attribute. Returns the additional help for the specified attribute.
Most attributes have no additional help.
Related Information
Related command: define_attribute
category
category string
Read-only attribute attribute. Returns the category that the specified attribute belongs to.
Categories group attributes that perform similar functions. For example, elab indicates that the
attribute is used during elaboration. All categories starting with lp_ indicate that these attributes are
used for low power.
Related Information
Related command: define_attribute
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check_function
check_function string
Read-only attribute attribute. Returns the name of the Tcl proc that ensures that the defined
attribute is valid.
Related Information
Related command: define_attribute
compute_function
compute_function string
Read-only attribute attribute. Returns the name of the Tcl proc that computes the attribute value.
Related Information
Related command: define_attribute
data_type
data_type string
Read-only attribute attribute. Returns the data type of the value of the specified attribute. The
data type can be boolean, fixed point, floating point number, integer, or string.
Related Information
Related command: define_attribute
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General--attribute Attributes
default_value
default_value string
Read-only attribute attribute. Returns the default value of the specified attribute.
Related Information
Related command: define_attribute
help
help string
Read-only attribute attribute. Returns the help string for the specified attribute.
Related Information
Related command: define_attribute
indices
indices string
Read-only attribute attribute. Returns the indices of this attribute.
is_computed
is_computed {false | true}
Read-only attribute attribute. Indicates whether the value of the specified attribute is computed.
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General--attribute Attributes
Related Information
Related command: define_attribute
is_hidden
is_hidden {false | true}
Read-only attribute attribute. Indicates whether this is a hidden attribute.
Related Information
Related command: define_attribute
is_obsolete
is_obsolete {false | true}
Read-only attribute attribute. Indicates whether this attribute is obsolete.
is_saved
is_saved {false | true}
Read-only attribute attribute. Indicates whether this attribute is saved.
is_settable
is_settable {false | true}
Read-only attribute attribute. Indicates whether the value of the specified attribute can be set with
the set_db command.
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is_user_defined
is_user_defined {false | true}
Read-only attribute attribute. Indicates whether this attribute was defined after startup in Tcl with
the define_attribute command.
possible_values
possible_values string_lists
Read-only attribute attribute. Returns the possible values for the attribute.
set_function
set_function string
Read-only attribute attribute. Returns the name of the Tcl proc that allows to override (set) a user-
defined value.
This attribute applies only to user-defined attributes and its value corresponds to the value
set with the -set_function option of the define_attribute command.
Related Information
Related command: define_attribute
skip_in_db
skip_in_db {false | true}
Read-only attribute attribute. Indicates whether the attribute was skipped by the write_db
command.
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General--base_cell Attributes
units
units string
Read-only attribute attribute. Returns the units of the value of the specified attribute.
Most attributes have no units.
base_cell Attributes
drive_strength
drive_strength string
Read-write base_cell attribute. Specifies the drive strength for metric capture.
logic_function
logic_function string
Read-write base_cell attribute. Specifies the logic function for metric capture.
voltage_threshold_group
voltage_threshold_group string
Read-write base_cell attribute. Allows you to assign a base_cell to a voltage threshold group for
metric capture. The threshold group name can be any valid string.
command Attributes
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General--base_cell Attributes
category
help
tcl_defined
usage
version
category
category string
Read-only command attribute. Returns the command category.
help
help string
Read-only command attribute. Returns the command help.
tcl_defined
tcl_defined { false | true}
Default: false
Read-only command attribute. Indicates whether the command is Tcl-defined.
usage
usage string
Read-only command attribute. Returns the command usage or syntax.
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General--command_option Attributes
version
version string
Read-only command attribute. Returns the command version.
command_option Attributes
command
data_type
help
is_list
required
command
command string
Read-only command_option attribute. Returns the command to which this option belongs.
data_type
data_type string
Read-only command_option attribute. Returns the data type to be used for this command option. The
data type can be boolean, fixed point, floating point number, integer, or string.
help
help string
Read-only command_option attribute. Returns the command option help.
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General--command_option Attributes
is_list
is_list { false | true}
Default: false
Read-only command_option attribute. Indicates whether the command option is a list.
required
required { false | true}
Read-only command_option attribute. Indicates whether the command option is a required option.
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Tcl User Interface
3
Tcl User Interface
all Attributes in TUI attribute_path attributes
beta_feature categories cmd_file
command_log commands common_ui
continue_on_error cpu_runtime design Attributes in TUI
dont_report_library dont_report_operating_conditions elapsed_runtime
enable_ui_precision fail_on_error_mesg floorplan_default_blockage_name_prefix
get_db_display_limit heartbeat heartbeat_print_date
information_level init_ground_nets init_lib_search_path
init_min_dbu_per_micron init_oa_abstract_views init_oa_default_rule
init_oa_foundry_rule init_oa_layout_views init_oa_ref_libs
init_oa_search_libs init_oa_special_rule init_physical_only
init_power_nets init_state limited_access_feature
load_average log_command_error log_file
memory_usage mesg_severity_downgrade message Attributes
messages obj_types path
peak_memory physical_memory_usage platform_wordsize
print_error_info program_major_version program_name
program_short_name program_version prompt_print_cwd
real_runtime report_library_message_summary report_tcl_command_error
restore_history_file save_history_file script_search_path
set_db_verbose show_report_options source_suspend_on_error
source_verbose source_verbose_info source_verbose_proc
startup_license stdout_log support_ui_units
tcl_partial_cmd_argument_matching tcl_return_display_length_limit tinfo_include_load
tinfo_tstamp_file trigger_post_time_info ui_precision
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Tcl User Interface--all Attributes in TUI
ui_precision_capacitance ui_precision_derating ui_precision_power
ui_precision_sensitivities ui_precision_timing ui_units_capacitance
ui_units_timing xm_protect_version
See also:
parent
all Attributes in TUI
Objects can be object types or attributes. The list is as follows:
accept_user_defined_attributes
base_name
escaped_name
max_print
name
obj_type
screen_max_print
accept_user_defined_attributes
Syntax
accept_user_defined_attributes {true | false}
Applies to:
all objects
Description
Default: false
Data_type: bool, read only
Specifies whether user attributes can be defined on the object type.
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Tcl User Interface--all Attributes in TUI
base_name
Syntax
base_name <string>
Applies to:
all objects
Description
Default:
Data_type: string, read only
Returns the leaf name of the object.
escaped_name
Syntax
escaped_name <string>
Applies to:
all objects
Description
Default:
Data_type: string, read only
Returns the escaped name of the object.
max_print
Syntax
max_print <integer>
Applies to:
message
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Description
Default: 20
Data_type: integer, read/write
Specifies the maximum number of times a message can be printed to the log file and the screen.
Related Information
Related attribute: screen_max_print
name
Syntax
name <string>
Applies to:
all objects
Description
Default:
Data_type: string, read only
Returns the object name used for get_db/set_db/reset_db queries.
obj_type
Syntax
obj_type <string>
Applies to:
all objects
Description
Default:
Data_type: string, read only
Returns the object type.
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Tcl User Interface--attribute_path
screen_max_print
Syntax
screen_max_print {infinity | integer}
Applies to:
message
Description
Default: inf (infinity)
Data_type: integer, read/write
Specifies the maximum number of times this message can be printed to the screen. The max_print message attribute takes
precedence if its value is smaller than the value of screen_max_print.
Related Information
Related attribute: max_print
attribute_path
attribute_path {basename | pathname | vname}
Default: basename
Read-write root attribute. Specifies the format to use for the object names in the command output of the set_attribute and
reset_attribute commands. The format can help you find an object when multiple objects in the design have the same (base)
name.
The attribute can have the following values:
basename Specifies to return the object name.
pathname Specifies to return the full vdir path to the object.
vname Specifies to return the Verilog style names where appropriate, otherwise defaults to the basename.
Related Information
Related commands: reset_db
set_db
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Tcl User Interface--attributes
attributes
attributes list_of_attributes
Read-only 'obj_type' attribute. Returns the list of all attribute objects.
beta_feature
beta_feature {{feature key}...}
Read-write root attribute. Specifies a list of sub-lists to enable beta features. Each sublist contains a feature name and the
corresponding key to access the feature.
You need to contact Cadence to access a limited-access feature and get the required key.
categories
Syntax
categories <string>
Applies to:
flow_step (read/write)
root (read only)
Description
Default:
Data_type: string
For flow_step, specifies the metric categories to calculate for this step.
For root, specifies all attribute categories.
cmd_file
cmd_file string
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Tcl User Interface--command_log
Default: genus.cmd
Read-write root attribute. Specifies the output file to which to write all commands executed in the session.
command_log
command_log string
Default: rc.cmd
Read-write root attribute. Specifies the output file to which to write all commands executed in the session.
commands
commands list_of_commands
Read-only root attribute. Returns the list of all commands. This is a computed attribute. Computed attributes are potentially very
time consuming to process and not listed by the ls command by default.
common_ui
common_ui {true |false}
Default: true
Read-write root attribute. Enables the common-UI command mode. By default, the tool starts with common UI.
continue_on_error
continue_on_error {false | true}
Default: false
Read-write root attribute. Controls whether to continue processing the scripts even if an error occurs. Set this attribute to true to
continue processing when an error occurred.
cpu_runtime
cpu_runtime float
Read-only root attribute. Returns the total runtime (in seconds) which is computed as the sum of the cpu time of the
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Tcl User Interface--design Attributes in TUI
main/foreground process and the cpu time across all background threads for a super-threaded session. In a single-threaded run,
this will be the runtime consumed by the main process.
Since this attribute keeps track of total CPU seconds, it is very dependent on the processor and clock-speed. Faster
processors will generally have lower run-times, all else being equal. Run-time is affected by machine-loading to the order
of 10-15% because increased loading leads to more context-switching, which in turn contributes to more stalls and general
inefficiency in the program’s execution. Run-time is also affected more significantly by memory. Processes that start to page
affect the CPU run-time.
design Attributes in TUI
obsolete_state state state_ignore_cdn_exception_buff
obsolete_state
Syntax
obsolete_state <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns the current state of the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the
ls/vls command by default.
state
Syntax
state {no_value | <state> }
Applies to:
design
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Tcl User Interface--dont_report_library
Description
Default:
Data_type: string, read only
Returns the current state of the design.
The '<state>' argument can have the following values:
generic Indicates that the design has been synthesized to generic gates.
generic_placed Indicates that the design has been synthesized and placed using generic gates.
hdl Indicates that the design has not been synthesized yet.
mapped Indicates that the design has been synthesized to mapped gates.
mapped_placed Indicates that the design has been synthesized and placed with mapped gates.
state_ignore_cdn_exception_buff
Syntax
state_ignore_cdn_exception_buff <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Specifies the current state of the design. The attribute can have the following values:
generic Indicates that the design has been synthesized to generic gates.
generic_placed Indicates that the design has been synthesized and placed using generic gates.
hdl Indicates that the design has not been synthesized yet.
mapped Indicates that the design has been synthesized to mapped gates.
mapped_placed Indicates that the design has been synthesized and placed with mapped gates.
dont_report_library
dont_report_library {false | true}
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Tcl User Interface--dont_report_operating_conditions
Default: false
Read-write root attribute. If set to true, the library information in the report headers is suppressed.
dont_report_operating_conditions
dont_report_operating_conditions {false | true}
Default: false
Read-write root attribute. If set to true, the library information in the report headers is suppressed.
elapsed_runtime
elapsed_runtime integer
Read-only root attribute. Returns the elapsed wall clock time (in seconds) for the current Genus session.
enable_ui_precision
enable_ui_precision {false | true}
Description
Default: false
Data_type: bool, read/write
Enables UI precision reporting.
Example
set_db / enable_ui_precision true
Applies to:
root
fail_on_error_mesg
fail_on_error_mesg {false | true}
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Tcl User Interface--floorplan_default_blockage_name_prefix
Default: false
Read-write root attribute. If set to true, Genus commands will fail (stop) whenever they produce an ERROR message.
This behavior applies automatically to all commands implemented in C++. However, for a command implemented in Tcl,
the attribute has no effect unless the command checks the value of this attribute to drive its behavior.
floorplan_default_blockage_name_prefix
floorplan_default_blockage_name_prefix string
Read-write root attribute. Specifies the prefix for newly created place and route blockages.
Related Information
Related commands: create_place_blockage
create_route_blockage
get_db_display_limit
get_db_display_limit integer
Default: 10
Read-write root attribute. Controls how many elements in the object list are displayed. Any object list from get_db is limited to 10
for display purposes.
heartbeat
heartbeat integer
Default: 0
Read-write root attribute. Causes a periodic output to stderr which includes current memory, runtime, and loading statistics.
heartbeat_print_date
heartbeat_print_date integer
Default: 0
Read-write root attribute. Adds date and time to the heartbeat message head.
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Tcl User Interface--information_level
information_level
Syntax
information_level <integer>
Applies to:
root
Description
Default: 1
Data_type: integer, read/write
Controls the amount of information Genus produces when executing commands. Specify a number of 0 through 11. The higher the
value, the more verbose the output. The extra verbosity can be useful when debugging problem designs.
level 0 error message
level 1 warning or info message
levels 2 - 11 info messages
Example
If you set the value of the information_level attribute to 3 before you run the check_dft_rules command, the output of the
command will list details, such as the valid scan cells it found in the technology library.
Related Information
Affects these commands: all commands
init_ground_nets
Syntax
init_ground_nets <string>
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Tcl User Interface--init_lib_search_path
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the global ground net.
init_lib_search_path
Syntax
init_lib_search_path {Tcl_list}
Applies to:
root
Description
Default: { . /install_dir/lib/tech}
Date_type: string, read/write
Specifies a list of UNIX directories that Genus should search to locate the technology libraries and LEF libraries.
The "~" is supported.
Related Information
Affects these attributes: library
lef_library
init_min_dbu_per_micron
Syntax
init_min_dbu_per_micron <integer>
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Tcl User Interface--init_oa_abstract_views
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the minimum DBU per micron.
init_oa_abstract_views
init_oa_abstract_views string
Read-write root attribute. Specifies the name of the view to be used by read_physical.
Related Information
Related command: read_physical
init_oa_default_rule
init_oa_default_rule string
Read-write root attribute. Specifies the constraint group for standard nets.
init_oa_foundry_rule
Syntax
init_oa_foundry_rule <string>
Applies to:
root
Description
Default:
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Tcl User Interface--init_oa_layout_views
Data_type: string, read/write
Specifies the foundry for multi-technology OA.
init_oa_layout_views
init_oa_layout_views string
Read-write root attribute. Specifies the list of the view names to process.
init_oa_ref_libs
init_oa_ref_libs string
Read-write root attribute. Specifies the list of OA libraries that were loaded.
init_oa_search_libs
init_oa_search_libs string
Read-write root attribute. Specifies the list of OA libraries to search if cells are not found in the OA reference.
init_oa_special_rule
init_oa_special_rule string
Read-write root attribute. Specifies the constraint group for special nets.
init_physical_only
Syntax
init_physical_only {true | false}
Applies to:
root
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Tcl User Interface--init_power_nets
Description
Default: false
Data_type: bool, read only
Indicates whether the tool is in physical-only mode.
init_power_nets
Syntax
init_power_nets <string>
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the global power net.
init_state
Syntax
init_state <state>
Applies to:
design
root
Description
Default:
Data_type: string, read only
Returns the current state of the initialization. The attribute can have the following values:
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Tcl User Interface--limited_access_feature
design_initialized State of the design after successfully reading the HDL files, netlist, or after elaborating.
initialization_complete State of the design when the design is consistent after successfully completing init_design.
physical_initialized State of the design when the physical data is loaded after successfully completing read_physical.
power_initialized State of the design after successfully completing read_power_intent.
timing_initialized State of the design when the libraries are loaded after successfully completing read_mmmc.
uninitialized Default value when you start the tool.
limited_access_feature
limited_acces_feature {{feature key}...}
Read-write root attribute. Specifies a list of sub-lists to enable limited access features. Each sublist contains a feature name and
the corresponding key to access the feature.
You need to contact Cadence to access a limited-access feature and get the required key.
Example
set_attribute limited_access_feature {{ieee_1801 nnnn}} /
load_average
load_average float
Read-only root attribute. Returns the load average of this server for the last fifteen minutes. The fifteen-minute load average is the
average number of active (cpu-bound) processes on the server where Genus is running. It gives an indication whether the server
is overloaded. It is important that the load average does not exceed the number of cpus on a server.
log_command_error
log_command_error {false | true}
Default: false
Read-write root attribute. Controls whether a failing command is reported in the logfile.
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Tcl User Interface--log_file
Related Information
Affects these commands: all commands
log_file
log_file log_file_name
Default: genus.log
Read-write root attribute. Specifies the log file name for the current session. All information printed to standard out will be
recorded in the specified log file.
memory_usage
memory_usage integer
Read-only root attribute. Returns the current memory consumption (in megabytes) by Genus for this process. This can be useful in
Tcl scripts.
Example
legacy_genus:/> get_attribute memory_usage /25.26
mesg_severity_downgrade
mesg_severity_downgrade {true| false}
Description
Default: false
Data_type: bool, read/write
Allows to downgrade the severity of a message from error to warning.
Applies to:
root
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Tcl User Interface--message Attributes
Related Information
Affects this attribute: severity
message Attributes
The section describes the attributes of the 'message' object type:
count
help
help_always_visible
id
print_count
priority
screen_print_count
severity
truncate
type
count
Syntax
count <integer>
Applies to:
message
Description
Default:
Data_type: integer, read only
Returns the number of times the message has been issued. The value of this attribute is larger than or equal to the value of the
print_count attribute.
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Tcl User Interface--message Attributes
help
Syntax
help <string>
Applies to:
attribute
command
command_option
obj_type
message
Description
Default:
Data_type: string, read only
Returns a more detailed explanation of the message (or other objects). Also includes help to debug the problem.
help_always_visible
Syntax
help_always_visible {false | true}
Applies to:
message
Description
Default: false
Data_type: bool, read/write
When enabled, the help for the message will be shown each time the message occurs. By default, the extended help is only
shown the first time the message occurs.
id
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Tcl User Interface--message Attributes
Syntax
id <integer>
Applies to:
message
violation
Description
Default:
Data_type: integer, read only
message Returns the identification number of the message.
violation Returns the violation ID number given by check_dft_rules.
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
Related attributes: dft_violation
print_count
Syntax
print_count <integer>
Applies to:
message
Description
Default:
Data_type: integer, read only
Specifies the number of times the message has been printed to the logfile and the screen. The value of this attribute is:
smaller than or equal to the value of the max_print and count attributes.
determined by the value of the information_level attribute.
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Related Information
Related attribute: screen_print_count
priority
Syntax
priority <integer>
Applies to:
exception
hdl_bind
hdl_implementation
message
Description
Default:
Data_type: integer, read only (exception) read/write (hdl_bind, hdl_implementation, message)
exception Determines the priority of the timing exception in absence of a user-priority setting. Genus sets the
priority on the timing exceptions to match the behavior of PrimeTime.
hdl_bind Specifies an integer representing the priority of the binding among all the valid bindings of the specified
synthetic operator. The highest value indicates the highest priority.
hdl_implementation Specifies an integer representing the priority of the implementation among all the valid implementations
of the specified component. The highest value indicates the highest priority.
message Returns the priority of the message. If the priority of a message is higher than the value of the
information_level attribute, it will not be printed.
Related Information
Affected by this attribute: user_priority
screen_print_count
Syntax
screen_print_count <integer>
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Tcl User Interface--message Attributes
Applies to:
message
Description
Default:
Data_type: integer, read only
Specifies the number of times the message has been printed to the the screen. The value of this attribute is:
smaller than or equal to the value of the screen_max_print and count attributes.
determined by the value of the information_level attribute.
Related Information
Related attribute: print_count
severity
Syntax
severity {Info | Error | Warning}
Applies to:
message
Description
Default:
Data_type: string, read/write
Returns the severity of the message. You can upgrade the severity of a particular message. For example, you can change the
severity of a message from Warning to Error, but you cannot change the severity from Error to Info.
Example
The following example upgrades the severity of the LBR-34 message from Warning to Error:
get_db message:LBR/LBR-34 .severity
Warning
set_db message:LBR/LBR-34 .severity Error
Setting attribute of message 'LBR-34': 'severity' = Error
1 Error
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Tcl User Interface--message Attributes
truncate
Syntax
truncate {true | false}
Applies to:
message
Description
Default: true
Data_type: bool, read/write
Limits messages in Genus to 4000 characters. All characters after the 4000 character limit are truncated. To remove this limit, set
the attribute to false. However, this may dramatically increase the size of the log file.
type
Syntax 1
type <string>
Applies to:
Object Data_type
blockage string, read only
layer string, read only
lib_arc enum, read only
message string, read only
place_blockage string, read/write
route_blockage string, read only
specialnet string, read only
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Tcl User Interface--message Attributes
Description
Object Detail
blockage Returns the blockage type. For this object, the attribute can return one of the following values:
place_blockage
route_blockage
layer Returns the type of the layer. For this object, the attribute can return one of the following values:
cut | implant | masterslice | overlap | routing
lib_arc Returns the timing arc type. For this object, the attribute return one of the following values:
borrow_arc | clear_arc | clock_edge_arc | combo_arc | hold_arc | nonseq_hold_arc | min_pulse_width |
minimum_period | nonseq_setup_arc | preset_arc | recovery_arc | removal_arc | setup_arc |
tristate_disable_arc | tristate_enable_arc
message Returns a brief explanation for the message.
specialnet Returns the routing wiring type of the special net. For this object, the attribute can return one of the following
values:
cover | fixed | routed
Example
obj: layer
get_db [get_db layers METAL2] .type
routing
Related Information
Set by this command: read_def
Set by this attribute: lef_library
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Tcl User Interface--message Attributes
Syntax 2
type {derived_fence | fence | guide | region}
Applies to:
region
Description
Default:
Data_type: enum, read/write
Specifies the type of the region. For this object, the attribute can specify one of the following values:
derived_fence indicates that this region is a fence derived from a power domain boundary.
fence indicates that all instances assigned to this region must be exclusively placed inside the region boundaries.
No other instances are allowed inside this region.
guide indicates that all instances assigned to this region should be placed inside this region; however, it is a
preference, not a hard constraint.
region indicates that the region was defined as a plain region in the DEF.
Related Information
Set by this command: create_region
read_def
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Tcl User Interface--message Attributes
Syntax 3
type {wire | wand | wor | supply0 | supply1}
Applies to:
hnet
Description
Default: wire
Data_type: enum, read/write
Specifies the type of the net.
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Tcl User Interface--message Attributes
Syntax 4
type {abstract | fixed | floating | preserve | shift_register}
Applies to:
Object Data_type
actual_scan_segment string, read only
scan_segment string, read only
Description
Returns the type of the tool-created / user-defined scan segment. This attribute can have the following values:
abstract Indicates that this segment is an abstract segment (that is, embedded in a blackbox or logic abstract module,
or defined for a lib_cell timing model).
fixed Indicates that the elements in this segment are connected in the user-specified order.
floating Indicates that the elements in this segment are not necessarily connected in the user-specified order.
preserve Indicates that the order of the presumed connected elements was preserved.
shift_register Indicates that this segment is a shift register. This implies that the order of the elements in the segment is
fixed.
Related Information
Set by this command: connect_scan_chains
Set by these constraints: define_scan_abstract_segment
define_scan_fixed_segment
define_scan_floating_segment
define_scan_preserved_segment
define_shift_register_segment
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Tcl User Interface--message Attributes
Syntax 5
type <string>
Applies to:
Object Data_type
dft_configuration_mode string, read only
jtag_port enum, read only
Description
Object Details
dft_configuration_mode Returns the type of the configuration mode. Possible values are:
scan | mbist | compression | wrapper
jtag_port Specifies the type of the JTAG port. Possible values are:
tdi | tdo | trst | tms | tck | non_jtag
Related Information
Set by these commands: add_jtag_boundary_scan
define_dft_cfg_mode
read_dft_jtag_boundary_file
Affects these commands: add_core_wrapper_cell
check_dft_rules
compress_scan_chains
connect_scan_chains
connect_serial_scan_chains
define_scan_abstract_segment
write_dft_abstract_model
write_dft_atpg
write_dft_atpg_other_vendor_files
write_scandef
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Tcl User Interface--message Attributes
Syntax 6
type <test_signal_type>
Applies to:
Object Data_type
tap_port string, read only
test_signal enum, read/write
Description
Object Details
tap_port Returns the type of this signal . This attribute can have one the following values:
tck | tdi | tdo | tms | trst | tdo_enable
test_signal Specifies whether this signal is a scan clock of an LSSD scan cell, a shift-enable or a test-mode signal. This
attribute can have one the following values:
scan_clock_a | scan_clock_b | shift_enable | test_mode
Related Information
Set by these constraints: define_jtag_tap_port
define_shift_enable
define_test_mode
Set by this command: check_dft_rules
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Tcl User Interface--messages
Syntax 7
type {async | clock | abstract segment test mode | shift register | tristate net | race | xsource }
Applies to:
violation
Description
Default:
Data_type: string, read only
Returns the type of the violation.
Related Information
Set by this command: check_dft_rules -advanced
Affects this command: report_dft_violations
Related attribute: dft_violation
messages
Syntax
messages <list_of_message_groups>
Applies to:
root (read only)
Description
Default:
Data_type: message_group*, read only
Returns a list of message_group objects.
obj_types
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Tcl User Interface--path
Syntax
obj_types <list_of_object_types>
Applies to:
root
Description
Default:
Data_type: obj_type*, read only
Returns a list of object_types.
path
path string
Default: . / /libraries/* /libraries/library_domains/*/*
/libraries/library_sets/*/* /libraries/library_domains/*
/libraries/library_sets/* /designs/* /designs/*/timing/clocks/
/designs/*/timing/clock_domains/*
/designs/*/dft/test_clock_domains/* /designs/*/dft/mbist/mbist_clock_domains/* /designs/*/modes
/designs/*/modes/*/clocks /designs/*/modes/*/clock_domains/* /mmmc_designs_spec/* /designs/*/mmmc/*
Read-write root attribute. Specifies the search paths for implicit finds. During an implicit find, Genus will perform an exhaustive
search by recursively searching the specified paths.
Example
In the following example, Genus recursively searches the paths specified with the path attribute and sets a false path between all
clock objects named clk1 and clk2.
legacy_genus:/> set_false_path -from clk1 -to clk2
In this case, Genus interprets the names clk1 and clk2 to be clock names because the inherent object search order of the SDC
command set_false_path is clocks, ports, instances, pins. If there were no clocks named clk1 or clk2, Genus would have
interpreted the names to have been port names.
peak_memory
peak_memory float
Read-only root attribute. Returns the peak memory consumption (in Mbytes) for this process (either the main process in a non-
superthreaded run, or the foreground process in a super-threaded run).
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Tcl User Interface--physical_memory_usage
physical_memory_usage
physical_memory_usage float
Read-only root attribute. Returns the physical memory (in Mb) for this process and all its children and their children.
platform_wordsize
platform_wordsize integer
Read-only root attribute. Returns the word size of the program in bits. Value is 32 or 64.
print_error_info
print_error_info {false | true}
Default: false
Read-write root attribute. Controls whether the tool prints the errorInfo variable when a command fails. If this attribute is set to
true, the tool prints out a stack of Tcl errorInfo for the current script.
Example
legacy_genus:/> set_attr print_error_info true Setting attribute of root ’/’: ’print_error_info’ = truelegacy_genus:> proc
report::timing::listify {} {} ;# overwrite existing proc so ’report timing’ will faillegacy_genus:/> report timingWarning :
Possible timing problems have been detected in this design. [TIM-11] : The design is
’test2’.============================================================ Generated by: Genus Synthesis Solution 15.10-s-xxx
Generated on: date ...============================================================
errorInfo: wrong # args: should be "listify"
while executing"listify $the_pin"errorInfo: wrong # args: should be "listify" (procedure "report_pin_name" line 19)
invoked from within"report_pin_name $rsl $full_pin_names"errorInfo: wrong # args: should be "listify" ("pin" arm line 3)
invoked from within"switch $field_name { "pin" { if {[llength $rsl]} { set rsl [report_pin_name $rsl
$full_pin_names] } } "type" { if {[lle..."errorInfo: wrong # args: should be "listify" (procedure "field_value"
line 15) invoked from within"field_value fields $desired_column $full_pin_names domain2id $map_timing"errorInfo: wrong # args:
should be "listify" (procedure "format_line" line 32) invoked from within"format_line $fil $line $desired_columns $cols_0
col_widths $full_pin_namesshow_first_pin_hier $debug_proc shown_flags domain2id $map_timing"errorInfo: ......
program_major_version
program_major_version string
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Tcl User Interface--program_name
Default: 21.1
Read-write root attribute. Specifies the major version of the program.
program_name
program_name string
Default: Genus Synthesis Solution
Read-only root attribute. Returns the name of the program being run. This may be useful for generating headers in customized
reports.
program_short_name
program_short_name string
Default: genus
Read-only root attribute. Returns the short name of the program being run. This name is used for the prompt, the command file,
and so on.
program_version
program_version string
Read-only root attribute. Returns the version of the program being run. This may be useful for generating headers in customized
reports.
Example
legacy_genus:/> get_att program_version /17.10-p001_1
prompt_print_cwd
prompt_print_cwd {true | false}
Default: true
Read-write root attribute. Includes the current working directory (cwd) in the command prompt.
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Tcl User Interface--real_runtime
Example
@genus:root: 5> set_db prompt_print_cwd false Setting attribut of root ’/’: ’prompt_print_cwd’ = false1 false@genus 6>
real_runtime
real_runtime float
Read-only root attribute. Returns the runtime (in seconds) which is computed as the sum of the cpu time of the foreground process
and the cpu time spent in the longest thread amongst the super-thread servers.
Since this attribute keeps track of total CPU seconds, it is very dependent on the processor and clock-speed. Faster
processors will generally have lower run-times, all else being equal. Run-time is affected by machine-loading to the order
of 10-15% because increased loading leads to more context-switching, which in turn contributes to more stalls and general
inefficiency in the program’s execution. Run-time is also affected more significantly by memory. Processes that start to page
affect the CPU run-time.
report_library_message_summary
report_library_message_summary {true| false}
Description
Default: true
Data_type: bool, read/write
Enables the printing of a summary of the messages issued during library parsing. Messages issued during the processing of the
library are not included.
Example
Loading library /.../lib/mylib.lib
Info : An unsupported construct was detected in this library. [LBR-40]
: /.../lib/mylib.lib:102:16: Construct ’output_voltage’ is not supported.
: Check to see if this construct is really needed for synthesis. Many
liberty constructs are not actually required.
Info : An unsupported construct was detected in this library. [LBR-40]
: /.../lib/mylib.lib:108:15: Construct ’input_voltage’ is not supported.
Info : Created nominal operating condition. [LBR-412]
: Operating condition ’_nominal_’ was created for the PVT values (1.000000,
2.250000, 125.000000) in library ’/.../lib/mylib.lib’.
:The nominal operating condition represents either the nominal PVT values
if specified in the library source, or the default PVT values (1.0, 1.0, 1.0).
Message Summary for Library /.../lib/mylib.lib:
************************************************************
An unsupported construct was detected in this library. [LBR-40]: 2
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Tcl User Interface--report_tcl_command_error
Created nominal operating condition. [LBR-412]: 1
************************************************************
Applies to:
root
report_tcl_command_error
report_tcl_command_error {false | true}
Default: false
Read-write root attribute. Enables printing of RC messages for Tcl command errors, such as wrong number of arguments, or bad
set command. This allows to catch these errors with the report messages. By default, Tcl command errors are not registered.
Example
legacy_genus:/> set_attr report_tcl_command_error true /legacy_genus:/> set foo Error : Tcl ’set’ command has encountered an
error. [TUI-7] : can’t read "foo": no such variable while executing "set foo" : Check the syntax and rerun.can’t
read "foo": no such variablelegacy_genus:/> set foo 1 2Error : Tcl command has wrong number of arguments. [TUI-9] : wrong
# args: should be "set varName ?newValue?" : Check the syntax and rerun.errorInfo: wrong # args: should be "set varName ?
newValue?"Error : Tcl ’set’ command has encountered an error. [TUI-7] : wrong # args: should be "set varName ?newValue?"
while executing "set foo1 2"wrong # args: should be "set varName ?newValue?"legacy_genus:/>
restore_history_file
restore_history_file {false | true}
Default: false
Read-write root attribute. Controls the restoration of a history file. When you enable this attribute, the true history is restored from
the ~/.genus_history file.
Example
Assume the .genus_history file contains:
set_attr library typical.libload test.velaborateq
Now restart Genus and enable the restore_history_file attribute:
legacy_genus:/> set_attr restore_history_file true / Setting attribute of root ’/’: ’restore_history_file’ = true
legacy_genus:/> history
1 set_attr restore_history_file true /
2 set_attr library typical.lib
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Tcl User Interface--save_history_file
3 load test.v 4 elaborate 5 q 6 historylegacy_genus:/> !2set_attr library typical.lib / Setting attribute of
root ’/’: ’library’ = typical.lib
Related Information
Related attribute: save_history_file
save_history_file
save_history_file {false | true}
Default: false
Read-write root attribute. Controls the creation of a history file. When you enable this attribute, the command history is saved to
the ~/.rc_history file.
Example
Assume the following commands were entered on the legacy_genus:/> prompt:
set_attr save_history_file true /set_attr library typical.libload test.velaborateq
In this case, the .rc_history file contains the following commands:
set_attr library typical.libload test.velaborateq
Related Information
Related attribute: restore_history_file
script_search_path
script_search_path string
Default: { . /install_dir/lib/etc}
Read-write root attribute. Specifies the search path for script files. The "~" is supported.
This attribute affects the include and the source commands.
Examples
The following example sets the script path to /home/monicas/Genus/scripts and then uses the include command to run the
example.g script in the directory:
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Tcl User Interface--set_db_verbose
legacy_genus:/> set_attribute script_search_path /home/monicas/Genus/scripts
Setting attribute of root /: ’script_search_path’ = /home/monicas/Genus/scripts
legacy_genus:/> include example.g
Related Information
Affects this command: include
set_db_verbose
set_db_verbose {true | false}
Default: true
Read-write root attribute. Controls the verbosity of the messages when you set and attribute. Disable this attribute to suppress the
info messages given when you set an attribute.
Related Information
Affects this command: set_db
show_report_options
show_report_options {false | true}
Default: false
Read-write root attribute. Controls whether the report command options used to generate a report are printed in the report header.
By default, the command options are not printed.
Example
The following report shows the command options:
legacy_genus:/> set_attribute show_report_options true /
legacy_genus:/> report timing -lint
============================================================ Generated by: Genus Synthesis Solution 15.10-s-xxx
Generated on: date Generated with: report timing -lint Module: mult_bit_muxed_add Technology
library: tutorial 1.0 Operating conditions: typical_case (balanced_tree) Wireload mode: enclosed Area mode:
timing library============================================================
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Tcl User Interface--source_suspend_on_error
source_suspend_on_error
source_suspend_on_error {false | true)
Default: false
Read-write root attribute. If set to true, the tool enters the suspend mode if an error occurs while sourcing the script. You can then
interactively correct the error in the script and resume to run the script.
source_verbose
source_verbose {true | false}
Default: false
Read-write root attribute. If you set this attribute to true, each command in a file is printed as it is executed along with the file
name from which it came and the line number. All information is printed to standard output. Since each command is evaluated
when it executes, setting this attribute to true can have some impact on the runtime and logfile sizes due to the amount of extra
data being dumped.
Example
The following example shows the information printed when the set_attr library command of the test3.g command file is
executed.
#At ./test3.g:3 4.21secs 25.26MB Fri Feb 20 04:45:28 PM PST 2009
set_attr library /home/rcap/lib/tech/tsmc_25.lib
source_verbose_info
source_verbose_info {false | true}
Default: false
Read-write root attribute. Controls the information printed to standard output when the source_verbose attribute is set to true. If
you set this attribute to true, the tool writes out the command along with the file name from which it came, line number, current
memory usage, and CPU time. By default, only the command name will be printed.
Related Information
Related attribute: source_verbose
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Tcl User Interface--source_verbose_proc
source_verbose_proc
source_verbose_proc {false | true}
Default: false
Read-write root attribute. Enables printing of the proc bodies in the script files to the command file. This attribute is only taken into
account if the source_verbose root attribute was set to true. Because some of the procs can be very large, enabling this attribute
can result in a huge command file.
Related Information
Affected by this attribute: source_verbose
startup_license
startup_license string
Read-only root attribute. Returns the name of the primary license that was used to start the tool.
Example
legacy_genus:/> get_attribute startup_license /
Genus_Synthesis
This information is also printed in the beginning of the log file:
Checking out license: Genus_Synthesis
stdout_log
stdout_log log_file_name
Default: genus.log
Read-write root attribute. Specifies the log file name for the current session. All information printed to standard out will be
recorded in the specified log file. You can specify different log files multiple times during one session, thereby recording
information that begins from a different part of the flow.
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Tcl User Interface--support_ui_units
support_ui_units
Syntax
support_ui_units {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Provides support for the 'ui_units_timing' and 'ui_units_capacitance' attributes.
tcl_partial_cmd_argument_matching
tcl_partial_cmd_argument_matching {quiet | warn | error}
Default: quiet
Read-write root attribute. Specifies how to handle conflicts when a partial match of an attribute name is specified with the get_db
command. You can request to report a warning or error, but by default no message is given.
tcl_return_display_length_limit
tcl_return_display_length_limit integer
Default: 4096
Read-write root attribute. Limits the string length of the command results printed by the Tcl interpreter in Genus.
tinfo_include_load
tinfo_include_load {false | true}
Default: false
Read-write root attribute.Controls whether to include average system load information in the output of the time_info command.
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Tcl User Interface--tinfo_tstamp_file
tinfo_tstamp_file
tinfo_tstamp_file file
Default: .rs.tstamp
Read-write root attribute. Specifies the file path of the time_info .tstamp file that saves the runtime information reported by the
time_info command.
trigger_post_time_info
trigger_post_time_info string
Read-write root attribute. Specifies the list of procedures and arguments to execute after the time_info command has been run.
ui_precision
Syntax
ui_precision <integer>
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Valid values are between 0 and 8. Specifies the number of significant digits to be displayed in the absence of an explicit precision
for any type. Set enable_ui_precision to true for before setting this attribute.
Examples
The following commands sets the number of significant digits precision to 2:
set_db / .enable_ui_precision true
set_db / .ui_precision 2
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Tcl User Interface--ui_precision_capacitance
Related Information
Related commands: all Reporting commands
ui_precision_capacitance
Syntax
ui_precision_capacitance <integer>
Applies to:
root
Description
Default: 3
Data_type: int, read/write
Valid values are between 0 and 8. Specifies the number of significant digits to be displayed for quantities of type 'capacitance'. Set
enable_ui_precision to true for before setting this attribute.
Examples
The following command sets the number of significant digits precision to 4:
set_db / .enable_ui_precision true
set_db / .ui_precision 2
set_db / .ui_precision_derating 4
Related Information
Affects this command: report_cell_delay_calculation
report_instance -power
report_timing
ui_precision_derating
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Tcl User Interface--ui_precision_power
Syntax
ui_precision_derating <integer>
Applies to:
root
Description
Default: 3
Data_type: int, read/write
Valid values are between 0 and 8. Specifies the number of significant digits to be displayed for derating factors, such as those
specified via set_timing_derate constraints or AOCV derating libraries. Set enable_ui_precision to true for before setting this
attribute.
Examples
The following command sets the number of significant digits precision to 4:
set_db / .enable_ui_precision true
set_db / .ui_precision 2
set_db / .ui_precision_derating 4
ui_precision_power
Syntax
ui_precision_power <integer>
Applies to:
root
Description
Default: 3
Data_type: int, read/write
Valid values are between 0 and 8. Specifies the number of significant digits to be displayed for quantities of type 'power'. Set
enable_ui_precision to true for before setting this attribute.
Examples
The following command sets the number of significant digits precision to 4:
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Tcl User Interface--ui_precision_sensitivities
set_db / .enable_ui_precision true
set_db / .ui_precision 2
set_db / .ui_precision_power 4
Related Information
Affects this command: report_instance -power
report_power
ui_precision_sensitivities
Syntax
ui_precision_sensitivities <integer>
Applies to:
root
Description
Default: 3
Data_type: int, read/write
Valid values are between 0 and 8. Specifies the number of significant digits to be displayed for statistical sensitivity values and
SOCV sigma values. Set enable_ui_precision to true for before setting this attribute.
Examples
The following command sets the number of significant digits precision to 4:
set_db / .enable_ui_precision true
set_db / .ui_precision 2
set_db / .ui_precision_sensitivities 4
ui_precision_timing
Syntax
ui_precision_timing <integer>
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Tcl User Interface--ui_units_capacitance
Applies to:
root
Description
Default: 3
Data_type: int, read/write
Valid values are between 0 and 8. Specifies the number of significant digits to be displayed for delay type values, including cell
and net delays, transitions, arrival and required times, and slacks. Set enable_ui_precision to true for before setting this attribute.
Examples
The following command sets the number of significant digits precision to 4:
set_db / .enable_ui_precision true
set_db / .ui_precision 2
set_db / .ui_precision_timing 4
Related Information
Affects this command: report_cell_delay_calculation
report_instance -timing
report_timing
ui_units_capacitance
Syntax
ui_units_capacitance { }
Applies to:
root
Description
Default:
Data_type: enum, read/write
If set, this value is used to set sdc_cap_unit at init_design before any MMMC SDC constraints are loaded. Valid values are 1pf,
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Tcl User Interface--ui_units_timing
1ff, 10ff, and 100ff.
Related Information
Related commands: read_mmmc
init_design
ui_units_timing
Syntax
ui_units_timing { }
Applies to:
root
Description
Default:
Data_type: enum, read/write
If set, this value is used to set sdc_time_unit at init_design before any MMMC SDC constraints are loaded. Valid values are 1ns,
1ps, 10ps, and 100ps.
Related Information
Related commands: read_mmmc
init_design
xm_protect_version
xm_protect_version string
Default: 23.06-a071
Read-only root attribute. Indicates which release of the xmprotect utiltiy is supported by Genus.
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Tcl User Interface--ui_units_timing
The xmprotect utility is a utility of the Cadence® Xcelium Simulators.
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Unified Metrics
4
Unified Metrics
metric_advanced_url_endpoint metric_capture_3d_hotspots metric_capture_depth
metric_capture_design_image metric_capture_design_image_blockages metric_capture_design_image_blockages_threshold
metric_capture_design_image_power_intent metric_capture_design_image_route_drc metric_capture_max_drc_markers
metric_capture_min_count metric_capture_overwrite metric_capture_pba_tns_histogram
metric_capture_per_view metric_capture_reg2reg_metrics metric_capture_timing_analysis_mode
metric_capture_timing_path_groups metric_capture_timing_paths metric_capture_tns_histogram
metric_capture_tns_histogram_buckets metric_capture_tns_histogram_max_slack metric_capture_tns_histogram_paths
metric_capture_vth_metrics metric_capture_vth_per_power_domain metric_category_default
metric_current_run_id metric_enable metric_summary_metrics
metric_advanced_url_endpoint
metric_advanced_url_endpoint string
Read-write root attribute. Specifies the base URL for the advanced metric server.
metric_capture_3d_hotspots
Syntax
metric_capture_3d_hotspots {true | false}
Applies to:
blockage
place_blockage
Description
Default: true
Data_type: bool, read/write
Captures 3d hotspot metrics.
metric_capture_depth
metric_capture_depth integer
Default: 0
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Unified Metrics--metric_capture_design_image
Read-write root attribute. Specifies the depth for capturing hinst design and power metrics.
metric_capture_design_image
metric_capture_design_image string
Default: true
Read-write root attribute. Captures design image.
metric_capture_design_image_blockages
metric_capture_design_image_blockages string
Default: true
Read-write root attribute. Capture place and route blockages objects in design image.
metric_capture_design_image_blockages_threshold
Syntax
metric_capture_design_image_blockages_threshold <integer>
Applies to:
root
Description
Default: 100
Data_type: integer, read/write
Specifies the threshold for capturing blockages in metric image. Use it to control when to disable the capture of the blockage image metric. The value is the
combined number of placement and routing blockages.
Related Information
Affects this command: syn_opt -spatial
metric_capture_design_image_power_intent
metric_capture_design_image_power_intent string
Default: true
Read-write root attribute. Capture power_intent objects in design image.
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Unified Metrics--metric_capture_design_image_route_drc
metric_capture_design_image_route_drc
metric_capture_design_image_route_drc string
Default: true
Read-write root attribute. Capture route_drc objects in design image.
metric_capture_max_drc_markers
metric_capture_max_drc_markers max_number
Default: 100000
Read-write root attribute. Specifies the maximum number of DRC markers to include in metric image.
metric_capture_min_count
metric_capture_min_count integer
Default: 1000
Read-write root attribute. Specifies the minimum instance count for capturing the instance design and power metrics.
metric_capture_overwrite
metric_capture_overwrite {false | true}
Default: false
Read-write root attribute. Overwrites pending metrics during create_snapshot category capture.
metric_capture_pba_tns_histogram
metric_capture_pba_tns_histogram {true | false}
Default: true
Read-write root attribute. Captures the path-based analysis histogram data for TNS.
metric_capture_per_view
metric_capture_per_view {true | false}
Default: true
Read-write root attribute. Captures the timing metrics per analysis_view.
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Unified Metrics--metric_capture_reg2reg_metrics
metric_capture_reg2reg_metrics
metric_capture_reg2reg_metrics {true | false}
Default: true
Read-write root attribute. Force the capture of reg2reg metrics regardless of path groups.
metric_capture_timing_analysis_mode
Syntax
metric_capture_timing_analysis_mode {gba | pba | epba | ipba}
Applies to:
root
Description
Default: gba
Data_type: enum, read/write
Specifies the timing analysis mode for metric capture during create_snapshot categories setup and hold.
The valid values of the attribute are:
gba graph based analysis
pba path based analysis, where:
retime_method == path_slew_propagation
retime_mode == path (default)
epba path based analysis, where:
retime_method == path_slew_propagation,
retime_mode == exhaustive,
timing_path_based_exhaustive_pba_bounded_mode == false
ipba path based analysis, where:
retime_method == path_slew_propagation,
retime_mode == exhaustive,
timing_path_based_exhaustive_pba_bounded_mode == true
metric_capture_timing_path_groups
metric_capture_timing_path_groups integer
Default: 10
Read-write root attribute. Specifies the list of path groups to capture in the timing.setup.paths and timing.hold.paths metrics which hold the detailed timing
path information. These paths can also be displayed on the design imaged. When this is not set, we capture all and reg2reg.
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Unified Metrics--metric_capture_timing_paths
Example
set_db metric_capture_timing_path_groups "reg2reg mem2reg reg2mem reg2cgate"
metric_capture_timing_paths
metric_capture_timing_paths integer
Default: 10
Read-write root attribute. Specifies the number of paths to capture for detailed display.
metric_capture_tns_histogram
metric_capture_tns_histogram {true | false}
Default: true
Read-write root attribute. Captures the histogram data for TNS.
metric_capture_tns_histogram_buckets
metric_capture_tns_histogram_buckets integer
Default: 50
Read-write root attribute. Specifies the number of buckets for the TNS histogram.
metric_capture_tns_histogram_max_slack
metric_capture_tns_histogram_max_slack integer
Default: 0
Read-write root attribute. Specifies the maximum slack for the TNS histogram.
metric_capture_tns_histogram_paths
metric_capture_tns_histogram_paths integer
Default: 10000
Read-write root attribute. Specifies the number of paths to capture for the TNS histogram.
metric_capture_vth_metrics
Syntax
metric_capture_vth_metrics {true | false}
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Unified Metrics--metric_capture_vth_per_power_domain
Applies to:
root
Description
Default: true
Data_type: bool, read/write
This attribute enables the capture of threshold voltage metrics based on the base_cell .voltage_threshold_group attribute which is seeded by the liberty
threshold_voltage_group lib_cell attribute.
metric_capture_vth_per_power_domain
metric_capture_vth_per_power_domain {true | false}
Default: true
Read-write root attribute. This attribute enables the capture of threshold voltage metrics per power domain which includes cell_type breakdown.
metric_category_default
metric_category_default category
Default: design
Read-write root attribute. Specifies to capture the default metric categories if none are provided.
metric_current_run_id
metric_current_run_id string
Read-write root attribute. Specifies the current unique run ID returned by the advanced metric server.
metric_enable
metric_enable {true | false}
Default: true
Read-write root attribute. Enables a metric snapshot capture with create_snapshot.
metric_summary_metrics
metric_summary_metrics string
Default: flow.cputime flow.realtime timing.setup.tns timing.setup.wns
Read-write root attribute. Specifies summary metrics to be inherited when viewing snapshots and runs.
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Flow Attributes
5
Flow Attributes
The chapter describes the attributes of the following object types:
flow Attributes for Flows
flow_step Attributes for Flows
root attributes for Flows
flow Attributes for Flows
feature_values
features
owner
run_count
skip_metric
steps
tool
tool_options
feature_values
feature_values string
Read-write flow attribute. Specifies the feature values for instances of this flow.
features
features string
Read-write flow attribute. Specifies the features defined for this flow
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owner
owner string
Read-write flow attribute. Specifies the owner of this flow.
run_count
run_count string
Default: 0
Read-write flow attribute. Specifies the number of times this flow has been run.
skip_metric
skip_metric {false | true}
Default: false
Read-write flow attribute. Skips generating a metric snapshot for the flow. By default, a snapshot is generated.
steps
steps string
Read-write flow attribute. Specifies the steps to run in this flow. This value can also be set by the create_flow command.
Related Information
Related command: create_flow
tool
tool string
Read-write flow attribute. Specifies the tool to use for this flow. This value can also be set by the -tool option of the
create_flow command.
Related Information
Related command: create_flow
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Flow Attributes--flow_step Attributes for Flows
tool_options
tool_options string
Read-write flow attribute. Specifies the tool options to use for this flow. This value can also be set by the -tool_options
option of the create_flow command.
Related Information
Related command: create_flow
flow_step Attributes for Flows
begin_tcl
body_tcl
categories
check_tcl
end_tcl
exclude_time_metric
feature_values
features
owner
quiet
run_count
skip_db
skip_metric
status
begin_tcl
begin_tcl string
Read-write flow_step attribute. Specifies a block of Tcl to run at the start of the step. This value can also be set by the -begin
option of the create_flow_step command.
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Flow Attributes--flow_step Attributes for Flows
Related Information
Related command: create_flow_step
body_tcl
body_tcl string
Read-write flow_step attribute. Specifies the body of the step. This value can also be set by the create_flow_step
command.
Related Information
Related command: create_flow_step
categories
categories string
Read-write flow_step attribute. Specifies the metric categories tp calculate for this step.
Related Information
Related command: create_flow_step
check_tcl
check_tcl string
Read-write flow_step attribute. Specifies the procedure to run to check the flow step. This value can also be set by the -proc
option of the check_flow command.
Related Information
Related command: create_flow_step
end_tcl
end_tcl string
Read-write flow_step attribute. Specifies a block of Tcl to run at the end of the step.
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Flow Attributes--flow_step Attributes for Flows
exclude_time_metric
exclude_time_metric {false | true}
Default: false
Read-write flow_step attribute. Controls whether to include cpu and wall time in the parent steps.
feature_values
feature_values string
Read-write flow_step attribute. Specifies the feature values for instances of this flow step.
features
features string
Read-write flow_step attribute. Specifies the features defined for this flow step.
owner
owner string
Read-write flow_step attribute. Specifies the owner of this flow step.
quiet
quiet {false | true}
Default: false
Read-write flow_step attribute. Specifies to hide the flow step.
run_count
run_count
Default: 0
Read-write flow_step attribute. Specifies the number of times this flow step has been run.
skip_db
skip_db {true | false}
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Flow Attributes--root attributes for Flows
Default: true
Read-write flow_step attribute. Controls whether to prevent that a db is saved when the flow step is complete. By default,
prevents that a db is saved once the flow step is completed.
skip_metric
skip_metric {false | true}
Default: false
Read-write flow_step attribute. Skips generating metrics when the step is complete. By default, every step saves the design
and runs metrics when completed.
status
status string
Default: not_run
Read-write flow_step attribute. Specifies the status of the flow step. This value can be set by the -init_state option of the
write_flow command.
Related Information
Related command: write_flow
root attributes for Flows
design_flow_effort flow_branch flow_caller_data
flow_db_directory flow_error_errorinfo flow_error_message
flow_error_write_db flow_exclude_time_for_init_flow flow_exit_when_done
flow_feature_values flow_features flow_footer_tcl
flow_header_tcl flow_hier_path flow_history
flow_log_directory flow_log_prefix_generator flow_mail_on_error
flow_mail_to flow_metrics_file flow_metrics_snapshot_parent_uuid
flow_metrics_snapshot_uuid flow_overwrite_db flow_plugin_names
flow_plugin_steps flow_post_db_overwrite flow_remark
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flow_report_directory flow_run_tag flow_schedule
flow_starting_db flow_startup_directory flow_status_file
flow_step_begin_tcl flow_step_canonical_current flow_step_check_tcl
flow_step_current flow_step_end_tcl flow_step_last
flow_step_last_msg flow_step_last_status flow_step_next
flow_steps flow_summary_tcl flow_template_feature_definition
flow_template_tools flow_template_type flow_template_version
flow_top flow_user_templates flow_verbose
flow_working_directory flow_write_db_snapshot flow_write_db_snapshot_exclude_time
flow_yamllint_exec flows flowtool_exit_timeout
flowtool_extra_arguments flowtool_metrics_qor_excel flowtool_metrics_qor_html
flowtool_metrics_qor_text flowtool_metrics_qor_vivid flowtool_predict_full_names
flowtool_schedule_flow_immediate flowtool_summary_tcl
design_flow_effort
design_flow_effort {standard | express | extreme}
Default: standard
Read-write root attribute. Specifies the flow effort level.
flow_branch
flow_branch string
Read-write root attribute. Specifies the branch run for this hierarchical flow. The value can be set through the -branch option
of the schedule_flow command.
Related Information
Related command: schedule_flow
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Flow Attributes--root attributes for Flows
flow_caller_data
flow_caller_data string
Read-write root attribute. Specifies the data used by the caller of the tool to identify the flow.
flow_db_directory
flow_db_directory string
Default: dbs
Read-write root attribute. Specifies the directory where the store the results databases.
flow_error_errorinfo
flow_error_errorinfo string
Read-write root attribute. Specifies the TCL error stack in the error database.
flow_error_message
flow_error_message string
Read-write root attribute. Specifies the TCL error message in the error database.
flow_error_write_db
flow_error_write_db {true | false}
Default: true
Read-write root attribute. Writes a database when an error occurs in a flow step.
flow_exclude_time_for_init_flow
Syntax
flow_exclude_time_for_init_flow {true | false}
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Applies to:
root
Description
Default: false
Data_type: bool, read/write
The attribute marks all snapshots created during the init_flow command as 'exclude_time_metric'. This includes user steps
added to the init_flow internal plugin locations. As a result, runtime accumulated during the init_flow command and
associated actions are not included in metrics.
flow_exit_when_done
flow_exit_when_done {false | true}
Default: false
Read-write root attribute. Specifies whether to exit the tool after running the final step in the flow.
flow_feature_values
flow_feature_values string
Default: false
Read-write root attribute. Specifies the global feature settings.
flow_features
flow_features string
Default: false
Read-write root attribute. Specifies the global feature settings.
flow_footer_tcl
flow_footer_tcl string
Read-write root attribute. Specifies a block of Tcl to run when a flow ends.
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Flow Attributes--root attributes for Flows
flow_header_tcl
flow_header_tcl string
Read-write root attribute. Specifies a block of Tcl to run when a flow starts.
flow_hier_path
flow_hier_path string
Read-write root attribute. Displays the path of the current flow within the flow hierarchy.
flow_history
flow_history string
Read-write root attribute. Contains the complete flow run history. This attribute is updated by the report_flow command.
Related Information
Related command: report_flow
flow_log_directory
flow_log_directory string
Default: logs
Read-write root attribute. Specifies the directory where the log files are stored.
flow_log_prefix_generator
flow_log_prefix_generator string
Default:
set logPrefix $start_step
# Work out the subset of steps we are running
set startPath [split $start_step "."]
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Flow Attributes--root attributes for Flows
set endPath [split $end_step "."]
for {set i 0} {$i < [llength $startPath]} {incr i} {
if {[lindex $startPath $i] ne [lindex $endPath $i]}
{ if {$subflow_start_step && $subflow_end_step} { set logPrefix [join [lrange $startPath 0 [expr $i - 1]] "."] }
else { set logPrefix $start_step if {$i < [llength $endPath]} { set logPrefix "${logPrefix}-[join [lrange $endPath
$i end] "."]" } } break } }
# Add the branch name
if {$branch ne {}} {
if {$logPrefix eq {}} {
set logPrefix $branch
} else {
set logPrefix "$branch.$logPrefix"
}
}
# Add the top-level flow to the prefix
if {$logPrefix eq {}} {
set logPrefix [string range $flow 5 end]
} else {
set logPrefix "[string range $flow 5 end].$logPrefix"
}
# Fall back to tool name
if {$logPrefix eq {}} {
set logPrefix $tool } # Add the flow log directory set logPrefix [file join $flow_log_directory $logPrefix] return
$logPrefix
Read-write root attribute. Specifies the Tcl script to create log filenames in the flowtool.
flow_mail_on_error
flow_mail_on_error {false | true}
Default: false
Read-write root attribute. Indicates whether to send email to the address specified in the flow_mail_to attribute when an
error is detected.
Related Information
Related command: report_flow
Related attribute: flow_mail_to
flow_mail_to
flow_mail_to string
Read-write root attribute. Specifies the email address where to send results.
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Flow Attributes--root attributes for Flows
Related Information
Related command: report_flow
Related attribute: flow_mail_on_error
flow_metrics_file
flow_metrics_file string
Read-write root attribute. Specifies the file to which the metrics results must be written.
flow_metrics_snapshot_parent_uuid
flow_metrics_snapshot_parent_uuid string
Read-write root attribute. Specifies the snapshot uuid to which the results from this flow will be appended.
Related Information
Related command: run_flow
flow_metrics_snapshot_uuid
flow_metrics_snapshot_uuid string
Read-write root attribute. Specifies the snapshot uuid of the most recent flow step executed.
Related Information
Related command: run_flow
flow_overwrite_db
flow_overwrite_db {false | true}
Default: false
Read-write root attribute. Controls whether to overwrite existing databases when saving.
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Flow Attributes--root attributes for Flows
flow_plugin_names
Syntax
flow_plugin_names <string>
Applies to:
root
Description
Default: Cadence.plugin.syn_gen.ungroup.pre Cadence.plugin.preplace.pre Cadence.plugin.preplace.post
Cadence.plugin.place.pre Cadence.plugin.place.post Cadence.plugin.prects.pre Cadence.plugin.prects.exp.mbff
Cadence.plugin.prects.post Cadence.plugin.cts.pre Cadence.plugin.cts.post Cadence.plugin.postcts.pre
Cadence.plugin.postcts.post Cadence.plugin.postcts.hold.pre Cadence.plugin.postcts.hold.post
Cadence.plugin.route.pre Cadence.plugin.route.trackopt.pre Cadence.plugin.route.trackopt.hold.pre
Cadence.plugin.route.trackopt.hold.post Cadence.plugin.route.trackopt.post Cadence.plugin.route.post
Cadence.plugin.postroute.pre Cadence.plugin.postroute.hold.pre Cadence.plugin.postroute.hold.post
Cadence.plugin.postroute.eco_route.pre Cadence.plugin.postroute.eco_route.post
Cadence.plugin.postroute.recovery.pre Cadence.plugin.postroute.recovery.hold.pre
Cadence.plugin.postroute.recovery.hold.post Cadence.plugin.postroute.recovery.eco_route.pre
Cadence.plugin.postroute.recovery.eco_route.post Cadence.plugin.postroute.recovery.post
Cadence.plugin.postroute.post Cadence.plugin.flowkit.snapshot Cadence.plugin.flowkit.read_db.pre
Cadence.plugin.flowkit.read_db.post Cadence.plugin.flowkit.flow.pre Cadence.plugin.flowkit.flow.post
Data_type: string, read/write
Displays the names of all the internal plugin points.
flow_plugin_steps
flow_plugin_steps string
Read-write root attribute. Displays the list of plugin steps that have been added through edit_flow.
flow_post_db_overwrite
flow_post_db_overwrite string
Read-write root attribute. This attribute is used to overwrite the database name and type which the next flow would start with.
This attribute should be placed within a flow_step object and should contain a valid DB name and type. It should be noted
that this attribute does not change the naming style for saved database names (this is done using the
"flow_log_prefix_generator" attribute) and only has effect if the current step is NOT marked as write_db. Since a DB can have
many different connotations, a database can be specified as a Tcl script, a Genus database, or an Innovus database (with or
without OA libraries). To support all these configurations, the attribute supports simple as well as long form formats to specify
the database.
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Flow Attributes--root attributes for Flows
flow_remark
flow_remark string
Default: no_value
Read-write root attribute. Specifies the remarks from the last loaded flow.yaml file.
flow_report_directory
flow_report_directory string
Default: reports
Read-write root attribute. Specifies the directory where to write the reports.
flow_run_tag
flow_run_tag string
Read-write root attribute. Specifies the tags for the particular flow run.
flow_schedule
flow_schedule string
Read-write root attribute. Specifies the flow (and its details) to be run after the current flow completes.
Related Information
Related command: schedule_flow
flow_starting_db
flow_starting_db string
Read-write root attribute. Specifies with which database to start the flow. The value can be set by the -db option of the
schedule_flow command.
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Flow Attributes--root attributes for Flows
Related Information
Related command: schedule_flow
flow_startup_directory
flow_startup_directory string
Read-write root attribute. This attribute contains the directory where flowtool was started from. This attribute is useful when
building file paths that need to be relative to the directory where the process was invoked.
flow_status_file
flow_status_file string
Read-write root attribute. Specifies the file to which to write the status of the flow. This attribute can be set by the -filename
option of the write_flow command.
Related Information
Related command: write_flow
flow_step_begin_tcl
flow_step_begin_tcl string
Read-write root attribute. Specifies a block of Tcl to be run at the start of each step.
flow_step_canonical_current
flow_step_canonical_current string
Read-write root attribute. Specifies the full path to the flow_step to uniquely identify the flow_step when several flows are
present.
flow_step_check_tcl
flow_step_check_tcl string
Read-write root attribute. Specifies the block of Tcl to check the steps.
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flow_step_current
flow_step_current string
Read-write root attribute. Returns the step that is currently run.
flow_step_end_tcl
flow_step_end_tcl string
Read-write root attribute. Specifies a block of Tcl to be run at the end of each step.
flow_step_last
flow_step_last string
Read-write root attribute. Returns the last step that was run.
flow_step_last_msg
flow_step_last_msg string
Read-write root attribute. Returns the message that was provided for the last step that was run.
flow_step_last_status
flow_step_last_status string
Read-write root attribute. Returns the status for the last flow step that was run.
flow_step_next
flow_step_next string
Read-write root attribute. Returns the next flow step to run in the flow.
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flow_steps
flow_steps list_of_flow_steps
Read-only root attribute. Returns a list of the flow steps.
flow_summary_tcl
flow_summary_tcl string
Read-write root attribute. Specifies the Tcl script to run to create the summary at the end of the run_flow command.
flow_template_feature_definition
flow_template_feature_definition string
Read-write root attribute. Specifies the features list and the status of the current template.
flow_template_tools
flow_template_tools string
Read-write root attribute. When loading a flow script generated using the write_flow_template command, this attribute
contains the list of tools specified in the -tools argument.
flow_template_type
flow_template_type string
Read-write root attribute. Specifies the type of template that is run.
flow_template_version
flow_template_version {false | true}
Default: false
Read-write root attribute. Specifies the version of template that is run.
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Flow Attributes--root attributes for Flows
flow_top
flow_top string
Read-write root attribute. Specifies the name of the flow to be run by default. The value can be set through the -flow option
of the run_flow command.
Related Information
Related commands: run_flow
flow_user_templates
flow_user_templates string
Read-write root attribute. Contains the flow user template definitions.
flow_verbose
flow_verbose {true | false}
Default: true
Read-write root attribute. Controls printing of the run information in the log file.
flow_working_directory
flow_working_directory string
Read-write root attribute. Specifies the directory where the flow is being run.
flow_write_db_snapshot
Syntax
flow_write_db_snapshot {true | false}
Applies to:
root
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Description
Default: true
Data_type: bool, read/write
Controls creation of a snapshot after write_db.
flow_write_db_snapshot_exclude_time
Syntax
flow_write_db_snapshot_exclude_time {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls the -exclude_time_metric argument to create_snapshot for the write_db snapshot.
flow_yamllint_exec
flow_yamllint_exec string
Read-write root attribute. Specifies the path to the yamllint executable to be run for validating yaml syntax in YAML files
used during execution of run_flow command.
Default: yamllint -d {extends: default, rules: {line-length: disable, comments: {require-starting-space:
false}, comments-indentation: disable}}
Related Information
Related Commands: read_flow
run_flow
flows
flows list_of_flows
Read-only root attribute. Returns a list of all flow objects.
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flowtool_exit_timeout
flowtool_exit_timeout integer
Default: 30
Read-write root attribute. Specifies the maximum amount of time in seconds flowtool waits after a tool exits for a completed
status.
flowtool_extra_arguments
flowtool_extra_arguments string
Read-write root attribute. When flowtool is specified as the tool using the 'create_flow' command, this attribute returns any
extra arguments stored in the tool_options attribute, which need to be passed into the flow running. This attribute is most
often used when flowtool is a wrapper to call an outside executable. This technique is helpful when metric capture is desired
and the designated executable does not directly support them.
Related Information
Related Commands: read_flow
run_flow
flowtool_metrics_qor_excel
Syntax
flowtool_metrics_qor_excel <string>
Applies to:
root
Description
Default:
Data_type: string, read/write
This attribute contains the file name to create at the end of the tool session using the 'report_metric -format excel'
command. If the flowtool_metrics_qor_excel attribute is populated, metrics in XML format will be reported to the file name
specified.
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Related Information
Related commands: read_metric
report_metric
flowtool_metrics_qor_html
Syntax
flowtool_metrics_qor_html <string>
Applies to:
root
Description
Default:
Data_type: string, read/write
This attribute contains the file name to create at the end of the tool session using the 'report_metric -format html'
command. If the flowtool_metrics_qor_excel attribute is populated, metrics in HTML format will be reported to the file name
specified.
Related Information
Related commands: read_metric
report_metric
flowtool_metrics_qor_text
Syntax
flowtool_metrics_qor_text <string>
Applies to:
root
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Description
Default:
Data_type: string, read/write
This attribute contains the file name to create at the end of the tool session using the 'report_metric -format text'
command. If the flowtool_metrics_qor_text attribute is populated, metrics in text format will be reported to the file name
specified.
Related Information
Related commands: read_metric
report_metric
flowtool_metrics_qor_vivid
Syntax
flowtool_metrics_qor_vivid <string>
Applies to:
root
Description
Default:
Data_type: string, read/write
This attribute contains the file name to create at the end of the tool session using the 'report_metric -format vivid'
command. If the flowtool_metrics_qor_vivid attribute is populated, metrics in vivid HTML format will be reported to the file
name specified.
Related Information
Related commands: read_metric
report_metric
flowtool_predict_full_names
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Flow Attributes--root attributes for Flows
Syntax
flowtool_predict_full_names {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether flows that are marked as skip_metric are displayed during flow prediction and reporting.
flowtool_schedule_flow_immediate
Syntax
flowtool_schedule_flow_immediate {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the flows scheduled with the schedule_flow command.
true Flowtool starts the flows scheduled with the schedule_flow command immediately.
false Flowtool waits for the tool to exit before starting the scheduled flows.
flowtool_summary_tcl
flowtool_summary_tcl string
Default: puts [report_metric -format text]
Read-write root attribute. Specify the Tcl script to run at the end of flowtool.
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Hierarchical Flow
6
Hierarchical Flow
assemble_design_generic_hier
ilm_filter_internal_path
ilm_keep_async
is_ilm
assemble_design_generic_hier
assemble_design_generic_hier {true | false}
Description
Default: false
Data_type: bool, read/write
Allows to read in hierarchical DEF in assemble_design.
Applies to:
root
Related Information
Affects this command: assemble_design
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Hierarchical Flow--ilm_filter_internal_path
ilm_filter_internal_path
Syntax
ilm_filter_internal_path {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Allows you to disable internal paths in ILM.
Related Information
Affects this command: syn_opt
ilm_keep_async
Syntax
ilm_keep_async {false | true}
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Genus Attribute Reference
Hierarchical Flow--is_ilm
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether to retain all asynchronous interface paths during ILM generation.
Related Information
Affects these commands: generate_ilm
is_ilm
Syntax
is_ilm {false | true}
Applies to:
module
Description
Default: false
Data_type: bool, read/write
Marks this module as an ILM module. This is used for the hierarchical flow.
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Design for Manufacturing
7
Design for Manufacturing
The chapter describes the following attribute:
yield
yield
Syntax
yield <string>
Applies to:
design
Description
Default: 1.0
Data_type: string, read only
Returns the total yield for the design.
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Design for Manufacturing--yield
Related Information
Design For Manufacturing Flow in the Genus Synthesis Flows Guide.
Affected by this command: read_dfm
Affects these commands: report_gates -yield
report_yield
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Elaboration and Synthesis
8
Elaboration and Synthesis
The chapter describes the attributes of the following object types:
All Attributes in Elab-N-Synth design Attributes for Elab-n-Synth
hdl_subprogram Attributes for Elab-n-Synth hnet Attributes for Elab-n-Synth
hpin Attributes for Elab-n-Synth hport Attributes for Elab-n-Synth
net Attributes for Elab-n-Synth pg_pin Attributes for Elab-n-Synth
pin Attributes for Elab-n-Synth port Attributes for Elab-n-Synth
root Attributes for Elab-n-Synth
See also:
location
parameters
pins
All Attributes in Elab-N-Synth
blackbox
cross_probe_frc_value
encrypted
group
hdl_convert_onebit_vector_to_scalar
hdl_convert_onebit_vector_wire_to_scalar
hdl_preserve_signals
hdl_proc_name
instances
ungroup
blackbox
Syntax
blackbox {false | true}
Applies to:
hdl_architecture
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Description
Default: false
Data_type: bool, read/write
When set to true, this architecture will not be elaborated causing it to be written out as a blackbox (empty module with complete port information).
This attribute is supported only in the RTL flow.
Related Information
black_box Pragmas in Verilog in Genus HDL Modeling Guide.
Affects this command: elaborate
Related attribute: hdl_error_on_blackbox
cross_probe_frc_value
Syntax
cross_probe_frc_value <char*>
Applies to:
design
hinst
hpin
inst
module
pg_pin
pin
port
Description
Default:
Data_type: list of {file row col} lists, read only
Returns the file, row, and column information for the current design/instance/pin/port/module. If the object is newly created and not available in the RTL, it
inherits its information from the parent (or parent of parent etc.) in the RTL.
encrypted
Syntax
encrypted {false | true}
Applies to:
hdl_architecture
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Description
Default: false
Data_type: bool, read only
Indicates whether the format of the input architecture was encrypted.
Related Information
Related command: read_hdl
group
Syntax
group {group_name}
Applies to:
hdl_block
hdl_procedure
hinst
inst
power_domain
region
Description
Default:
Data_type: string, read only (power_domain, region), read/write (hdl_block, hdl_procedure, hinst, inst)
Object Description
hdl_object In VHDL, the group attribute specifies the name of the group to which this particular VHDL block belongs. During elaboration, a level of
design hierarchy is created for each group. All VHDL blocks in an entity that belong to a particular group are put into a module
created for that group. If this attribute is an empty string, the VHDL block remains at the same level in the design hierarchy described in
the RTL code.
After using the read_hdl command and before using the elaborate command, you can change the value of group attributes to instruct
elaboration to create an extra level of design hierarchy.
hdl_procedure Specifies the name of the group to which this particular Verilog or VHDL process belongs.
In VHDL, the group attribute specifies the name of the group to which the specified process belongs. During elaboration a level of design
hierarchy is created for each group. All processes in an entity that belong to a particular group are put into a module created for that
group. If this attribute is an empty string, then this process remains at the same level in the design hierarchy described in the RTL code.
In Verilog, the group attribute specifies the name of the group to which the specified always construct belongs. During elaboration a
level of design hierarchy is created for each group. All always constructs in a module that belong to a particular group are put into a
module created for that group. If this attribute is an empty string, then the always construct remains at the same level in the design
hierarchy described in the RTL code.
After using the read_hdl command and before using the elaborate command, you can change the value of group attributes to instruct
elaboration to create an extra level of design hierarchy.
This attribute is supported only in the RTL flow.
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hinst
inst Returns the group that the instance belongs to.
power_domain Returns the DEF group associated with this power domain.
region Returns the group associated with this region.
hdl_convert_onebit_vector_to_scalar
Syntax
hdl_convert_onebit_vector_to_scalar {false | true}
Applies to:
hdl_architecture
root
Description
Default: false
Data_type: bool, read/write
Specifies whether to convert one-bit vectors present in RTL to scalars when elaborating the design.
Example
Consider the following RTL code:
module x(X, A1, A2);
input [0:0] A1 ;
input [0:0] A2 ;
output X;
and U$1(X, A1, A2);
endmodule
If you use the default value (false), the netlist after elaboration will look like:
module x(X, A1, A2);
input [0:0] A1, A2;
output X;
wire [0:0] A1, A2;
wire X;
and U$1 (X, A1, A2);
endmodule
If you set this attribute to true, the netlist after elaboration will look like:
module x(X, A1, A2);
input A1, A2;
output X;
wire A1, A2;
wire X;
and U$1 (X, A1, A2);
endmodule
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Related Information
Affects these commands: elaborate
read_hdl
Related attribute: hdl_convert_onebit_vector_wire_to_scalar
hdl_convert_onebit_vector_wire_to_scalar
Syntax
hdl_convert_onebit_vector_wire_to_scalar {false | true}
Applies to:
hdl_architecture
root
Description
Default: false
Data_type: bool, read/write
Converts a one-bit vector declaration into a scalar.
Example
In the following example, hdl_convert_onebit_vector_wire_to_scalar affects vector wire y in module mid1:
module mid1(a, b);
input a;
output b;
wire [0:0] y;
mid2 m3(a, y[0]);
mid2 m4(y[0], b);
endmodule
The following netlist is created post elaboration, by using the default value (false) for hdl_convert_onebit_vector_wire_to_scalar attribute:
module mid1(a, b);
input a;
output b;
wire a;
wire b;
wire [0:0] y;
mid2 m3(a, y);
mid2 m4(y, b);
endmodule
The following netlist is created post elaboration, by setting the value true for hdl_convert_onebit_vector_wire_to_scalar attribute:
module mid1(a, b);
input a;
output b;
wire a;
wire b;
wire y;
mid2 m3(a, y);
mid2 m4(y, b);
endmodule
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The single bit vector wire y was converted to a scalar.
Related Information
Affects these commands: elaborate
read_hdl
Related attribute: hdl_convert_onebit_vector_to_scalar
hdl_preserve_signals
Syntax
hdl_preserve_signals <list_of_signals>
Applies to:
hdl_architecture
Description
Default:
Data_type: string, read/write
Specifies a list signals that must be preserved until external connections are made. Genus preserves these signals even if they are unconnected or unused.
Example
set_db hdl_architecture:default/example(example1) .hdl_preserve_signals \
"signal1 signal2"
Related Information
Affects these commands: elaborate
read_hdl
hdl_proc_name
Syntax
hdl_proc_name <string>
Applies to:
hinst
inst
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Description
Default:
Data_type: string, read/write
If the hdl_enable_proc_name attribute is set to true, specifies the name of the:
The Verilog block identifier of the named always block that infers this sequential element.
or
The VHDL label of the process that infers this sequential element.
If no name was given to the Verilog block or VHDL process, a tool-generated name is given.
This attribute is created during elaboration. After elaboration, it has no value for hierarchical instances, or for instances that are not sequential elements.
Related Information
Affects this command: elaborate
Affected by this attribute: hdl_enable_proc_name
instances
Syntax 1
instances <list_of_hdl_insts>
Applies to:
hdl_architecture
hdl_block
Description
Default:
Data_type: hdl_inst*, read only
Returns the list of hdl_inst objects for this architecture/block.
Syntax 2
instances <string>
Applies to:
gcell
Description
Default:
Data_type: string, read only
Lists the names of the instances that the gcell contains.
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Related Information
Set by this command: read_def
ungroup
Syntax
ungroup {false | true}
Applies to:
hdl_architecture
hdl_component
hdl_implementation
hdl_inst
Description
Default: false
Data_type: bool, read/write
Determines whether all instances of the specified component architecture/component/entity (in VHDL) or module (in Verilog)/instance should be inlined during
elaboration.
This attribute is supported only in the RTL flow.
design Attributes for Elab-n-Synth
arch_filename arch_name embedded_script
entity_filename entity_name hdl_all_filelist
hdl_config_name hdl_cw_list hdl_elab_command_params
hdl_filelist hdl_parameters hdl_user_name
hdl_vdp_list language library_name
logic_abstract
arch_filename
Syntax
arch_filename <string>
Applies to:
design
module
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Description
Default:
Data_type: string, read/write
Returns the name and physical location of the source file that contains the specified architecture (in VHDL) or module (in Verilog).
This attribute is only supported in the RTL flow.
Related Information
Related attribute: entity_filename
arch_name
Syntax
arch_name <string>
Applies to:
design
module
Description
Default:
Data_type: string, read only
Returns the name of the Verilog module or the VHDL architecture from which the design is derived.
Related Information
Related command: read_hdl
embedded_script
Syntax
embedded_script <string>
Applies to:
design
module
Description
Default:
Data_type: string, read/write
Stores the embedded SDC command script in the RTL code describing the module or entity of this design or module. Using the run_embedded_script command
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applies the stored script onto the design or module.
You can use a synthesis script to modify the contents of the embedded_script attribute before executing it. The embedded script can have any SDC command
that is supported by the read_sdc command.
Related Information
Related command: read_sdc
entity_filename
Syntax
entity_filename <string>
Applies to:
design
module
Description
Default:
Data_type: string, read/write
Returns the name and physical location of the source file that contains the specified VHDL entity. Since Verilog does not have the concept of VHDL entities,
this attribute will return the file that contains the Verilog module. For Verilog modules, the entity_filename and arch_filename attributes behave identically.
This attribute is only supported in the RTL flow.
Related Information
Related attribute: arch_filename
entity_name
Syntax
entity_name <string>
Applies to:
design
module
Description
Default:
Data_type: string, read only
Returns the name of the Verilog module or the VHDL entity from which the design is derived.
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Related Information
Related command: read_hdl
hdl_all_filelist
Syntax
hdl_all_filelist {hdl_library language_standard {define_value ...} {hdl_file ...} {search_path}}...
Applies to:
design
module
Description
Default:
Data_type: string, read only
Stores the information required by the read_hdl command to elaborate the design/module. The information is stored as a list of values that can be used as
options for the read_hdl command. The list of files includes any ‘include and package files read into Genus for the specified design.
Value Description
hdl_library is the value for the -library option.
language_standard corresponds to one of the following:
-v1995, -v2001, -vhdl1987, -vhdl1193, -vhdl2008, or -sv.
For vhdl, the value of the hdl_vhdl_read_version attribute is appended to -vhdl.
define_value is the value for the -define option (default: SYNTHESIS).
hdl_file corresponds to the list of files required to elaborate the design.
search_path is the directory location of the HDL files. An empty value signifies the current directory.
Since the attribute contains only those files that have been used during elaboration, you can use this attribute to prune unnecessary read_hdl commands
from your scripts.
This attribute is supported in the RTL flow and the structural flow.
Example
Consider the following RTL files:
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# File top.v
module top(a,b);
input [1:0] a;
output [1:0] b;
bot u1(.x(a),.y(b));
endmodule
#File bot.v
`include "siz.h"
`include "inc.h"
module bot(x,y);
input [`SIZE:0] x;
output [`SIZE:0] y;
wire [`SIZE:0] tmp;
assign y = `ADD(x,tmp);
endmodule
# File siz.h
`define SIZE 1
#File inc.h
`define ADD(a,b) a+b
Consider the following script:
set_db / .library tutorial.lib
read_hdl top.v
read_hdl bot.v
elaborate top
After elaboration, the hdl_all_filelist for design top will return:
{default -v2001 {SYNTHESIS} {top.v} {}} {default -v2001 {SYNTHESIS} {bot.v siz.h inc.h} {}}
The difference between hdl_filelist and hdl_all_filelist is that hdl_all_filelist also lists the include files siz.h and inc.h.
Related Information
Related attribute: hdl_filelist
hdl_config_name
Syntax
hdl_config_name <string>
Applies to:
design
module
Description
Default:
Data_type: string, read/write
Specifies the name of the configuration used to build this design/module.
hdl_cw_list
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Elaboration and Synthesis--design Attributes for Elab-n-Synth
Syntax
hdl_cw_list {{language library component}...}
Applies to:
design
module
Description
Default:
Data_type: string, read/write
Returns a Tcl list of Tcl lists. There can be as many Tcl lists as there are types of Chipware components in the top module. Each Tcl list contains three
elements:
language is the module in which the ChipWare component is instantiated.
library is the name of the ChipWare that contains the ChipWare component.
component is the name of the ChipWare
Each ChipWare component used in the design appears just once in the hdl_cw_list attribute, no matter how many times it is instantiated.
Related Information
Affected by this command: elaborate
hdl_elab_command_params
Syntax
hdl_elab_command_params {{<parameter value>}...}
Applies to:
design
module
Description
Default:
Data_type: string, read only
Returns a Tcl-list of the {parameter value} pairs that were specified as value for the -parameters option of the most recently executed elaborate command.
Related Information
Affects this command: elaborate
hdl_filelist
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Syntax
hdl_filelist {hdl_library language_standard {define_value ...} {hdl_file ...} {search_path}}...
Applies to:
design
module
Description
Default:
Data_type: string, read/write
Stores the information required by the read_hdl command to elaborate the design/module. The information is stored as a list of values that can be used as
options for the read_hdl command.
Values Description
hdl_library is the value for the -library option.
language_standard corresponds to one of the following: -v1995, -v2001, -vhdl1987, -vhdl1193, -vhdl2008, or -sv.
For vhdl, the value of the hdl_vhdl_read_version attribute is appended to -vhdl.
define_value is the value for the -define option (default: SYNTHESIS).
hdl_file corresponds to the list of files required to elaborate the design.
search_path is the directory of the location of the HDL files. An empty value signifies the current directory.
Since the attribute contains only those files that have been used during elaboration, you can use this attribute to prune unnecessary read_hdl commands
from your scripts.
This attribute is supported in the RTL flow and the structural flow.
Related Information
Affects this command: elaborate
Affected by this attribute: hdl_vhdl_read_version
Related attribute: hdl_all_filelist
hdl_parameters
Syntax
hdl_parameters {{parameter current_value cmdset default_value}...}
Applies to:
design
module
Description
Default:
Data_type: string, read only
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Returns a Tcl list of Tcl lists. There can be as many Tcl lists as there are parameters and localparams in the top module. Each Tcl list contains four elements:
parameter or is the name.
localparam
current_value is the current parameter value
cmd_set is a binary number. If the binary number is 1, it indicates that the parameter value was set through the elaborate -parameters command.
For localparam, the status value will always be 0 because it cannot be overwritten.
default_value is the default value of the parameter before it is overridden during instantiation or using the elaborate command.
Related Information
Affected by this command: elaborate
hdl_user_name
Syntax
hdl_user_name <string>
Applies to:
design
module
Description
Default:
Data_type: string, read/write
Represents the name of the Verilog module or the VHDL entity from which the given design/module was derived. The design’s name may differ from the
hdl_user_name value and from the addition of suffixes for the module name uniquification.
For example, a parameterized module named adder with wA and wB parameters may result in a design whose name is adder_wA5_wB3. However, the
hdl_user_name attribute for this design would still be adder.
hdl_vdp_list
Syntax
hdl_vdp_list <string>
Applies to:
design
module
Description
Default:
Data_type: string, read only
Returns the list of Genus-ted datapath function primitives which have been instantiated in the design/module.
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Related Information
Affected by this command: elaborate
language
Syntax
language <string>
Applies to:
design
hdl_architecture
hdl_implementation
module
Description
Default:
Data_type: string (design, hdl_architecture, and module), enum (hdl_implementation), read only
design Specifies whether the design is a Verilog module or VHDL entity.
hdl_architecture Specifies whether the hdl_architecture is a Verilog module or VHDL entity.
hdl_implementation Returns the HDL language version in which the RTL code for the specified architecture was written.
Possible values are: v1995 / v2001 / vhdl87 / vhdl93
module Specifies whether the module is a Verilog module or VHDL entity.
Related Information
Related command: read_hdl
library_name
Syntax
library_name <string>
Applies to:
design
module
Description
Default:
Data_type: string, read only
Returns the name of the Verilog or VHDL library in which the module or entity definition is stored. This name corresponds to the name specified with the -lib
option of the read_hdl command. If this option was not specified, the name defaults to default.
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Related Information
Related command: read_hdl
logic_abstract
Syntax
logic_abstract {false | true}
Applies to:
design
module
Description
Default: false
Data_type: bool, read only
design Specifies whether the design is inferred as a logic abstract from an empty module, an entity without an architecture, or an entity whose architecture
is empty in the input design description.
If the attribute value is true, the design is considered an empty module with port directions and bit widths, and is treated as an unresolved
reference.
If the attribute value is false, the design can be optimized by the generic optimization engine.
module Specifies whether the module is inferred as a logic abstract from an empty module, an entity without an architecture, or an entity whose architecture
is empty in the input design description.
If the attribute value is true, the module is treated as an unresolved reference in the design.
If the attribute value is false, the module is considered a normal module in the design hierarchy and can be optimized by the generic
optimization engine.
This attribute is used in the RTL and structural flows.
Related Information
Affected by this command: elaborate
hdl_subprogram Attributes for Elab-n-Synth
map_to_module
map_to_operator
return_port
map_to_module
map_to_module string
Read-only hdl_subprogram attribute. For valid modules, the specified function, task, or procedure is mapped to the module during elaboration. If the specified
function, task, or procedure has a valid map_to_module pragma, this attributes keeps the name of the module specified in the pragma. It is a null string if this
function, task, procedure does not carry a map_to_module pragma.
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This attribute is supported only in the RTL flow.
map_to_operator
map_to_operator string
Read-only hdl_subprogram attribute. For valid synthetic operators, the specified function, task, or procedure is mapped to the synthetic operator during
elaboration. If the specified function, task, or procedure has a valid map_to_operator pragma, this attributes keeps the name of the synthetic operator specified
in the pragma. It is a null if string if this function, task, or procedure does not carry a map_to_operator pragma.
This attribute is supported only in the RTL flow.
return_port
return_port string
Read-only hdl_subprogram attribute. The operator output pin will supply a return value for the specified function. If the specified function has a valid
return_port_name pragma, this attributes keeps the name of the output pin of the synthetic operator. It is a null string if this function does not carry a
return_port_name pragma.
This attribute is supported only in the RTL flow.
hnet Attributes for Elab-n-Synth
constant
dont_touch
constant
constant {no_constant | 0 | 1}
Default: no_constant
Read-write hnet attribute. Specifies the type of constant that drives the net.
You can set the following options:
0 Specifies that the net is driven by a constant 0.
1 Specifies that the net is driven by a constant 1.
no_constant Specifies that the net is not driven by a constant.
Related Information
Related attributes: (hpin) constant
(hport) constant
(pin) constant
(port) constant
(pg_pin) constant
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dont_touch
dont_touch {false | true | delete_ok}
Default: false
Read-write hnet attribute. Controls the preservation of the hnet during optimization. Setting this will preserve all connections on the hnet at the level of hierarchy
where the hnet exists (it will stop at the hpins and hports connected to this hnet).
You can set the following values:
delete_ok Allows the specified hnet to be deleted if it is not driving any logic.
false Allows the specified hnet to be optimized.
true Prevents the specified hnet from being optimized.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: (design) dont_touch
(hinst) dont_touch
(hpin) dont_touch
(inst) dont_touch
(lib_cell) dont_touch
(module) dont_touch
(net) dont_touch
(pin) dont_touch
hpin Attributes for Elab-n-Synth
cap_violation
cap_violation_by_mode
constant
dont_touch
fo_violation
fo_violation_by_mode
iopt_avoid_tiecell_replacement
lssd_master_clock
prune_unused_logic
trans_violation
trans_violation_by_mode
cap_violation
cap_violation double
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Default: no value
Read-only hpin attribute. Gets the capacitance violation on the pin.
cap_violation_by_mode
cap_violation_by_mode tcl_list_of_modes corresponding_resistance_values
Default: no value
Read-only hpin attribute. Gets the capacitance violation of the pin for all modes in multimode design.
constant
constant {no_constant | 0 | 1}
Default: no_constant
Read-write hpin attribute. Specifies the type of constant that drives the hierarchical pin.
You can set the following options:
0 Specifies that the hpin is driven by a constant 0.
1 Specifies that the hpin is driven by a constant 1.
no_constant Specifies that the hpin is not driven by a constant.
Related Information
Related attributes: (hnet) constant
(hport) constant
(pin) constant
(port) constant
(pg_pin) constant
dont_touch
dont_touch {none | false | true | add_ok | delete_ok | ad_invert_ok | invert_ok}}
Default: none
Read-write hpin attribute. Controls the preservation of the hpin during synthesis. A preserved hpin means the logical function of the hpin must be preserved to
maintain a simulation or test-point hpin in the netlist. However, the name does not need to be preserved.
You can set the following values:
add_invert_ok Allows changing the hpin’s polarity and adding or duplicating the pin.
add_ok Allows adding an hpin or duplicating the hpin.
delete_ok Allows the specified hpin to be deleted if it has no fanout.
false Allows the specified hpin to be optimized.
invert_ok Allows to change the polarity of the hpin.
none Inherits the setting from the module or hinst.
true Prevents the specified hpin from being optimized.
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Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affects this attribute: map_to_multibit_bank_label
Related attributes: (design) dont_touch
(hinst) dont_touch
(hnet) dont_touch
(inst) dont_touch
(lib_cell) dont_touch
(module) dont_touch
(net) dont_touch
(pin) dont_touch
fo_violation
fo_violation double
Default: no value
Read-only hpin attribute. Gets the fanout violation on the pin.
fo_violation_by_mode
fo_violation_by_mode tcl_list_of_modes corresponding_resistance_values
Default: no value
Read-only hpin attribute. Gets the fanout violation on the pin for all modes in multimode design.
iopt_avoid_tiecell_replacement
iopt_avoid_tiecell_replacement {false | true}
Default: false
Read-write hpin attribute. Controls whether a constant assignment on this hpin can be replaced with a tie cell during incremental optimization. Set this attribute
to true to prevent this replacement.
Related Information
Affects this command: syn_opt
Related attributes: (hport) iopt_avoid_tiecell_replacement
(pin) iopt_avoid_tiecell_replacement
(port) iopt_avoid_tiecell_replacement
lssd_master_clock
lssd_master_clock master_clock
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Read-write hpin attribute. Identifies two pins on a hierarchical instance as the master clock and slave clock pins. The pin on which you set this attribute is the
slave clock pin, while the pin you specify as the value of this attribute is the master clock pin. You must set this attribute before mapping. During mapping,
Genus will make connections from the master clock pin to the master clock pins of all master-slave flip-flops driven by this slave clock.
Related Information
Affects this command: syn_map
Affected by this attribute: map_to_master_slave_lssd
Related attributes: (hport) lssd_master_clock
(pin) lssd_master_clock
(port) lssd_master_clock
prune_unused_logic
prune_unused_logic {true | false}
Default: true
Read-write hpin attribute. Allows pruning (removing) of logic driving a hierarchical pin if the hierarchical pin does not drive any loads.
Related Information
Affects this attribute: boundary_opto
trans_violation
trans_violation delay
Default: no value
Read-only hpin attribute. Gets the transition violation on the hpin.
trans_violation_by_mode
trans_violation_by_mode tcl_list_of_modes corresponding_delays
Default: no value
Read-only hpin attribute. Gets the transition violation on the pin for all modes in multimode design.
hport Attributes for Elab-n-Synth
constant
iopt_avoid_tiecell_replacement
lssd_master_clock
constant
constant {no_constant | 0 | 1}
Default: no_constant
Read-write hport attribute. Specifies the type of constant that drives the hierarchical port.
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You can set the following options:
0 Specifies that the hport is driven by a constant 0.
1 Specifies that the hport is driven by a constant 1.
no_constant Specifies that the hport is not driven by a constant.
Related Information
Related attributes: (hnet) constant
(hpin) constant
(pin) constant
(port) constant
(pg_pin) constant
iopt_avoid_tiecell_replacement
iopt_avoid_tiecell_replacement {false | true}
Default: false
Read-write hport attribute. Controls whether a constant assignment on this port can be replaced with a tie cell during incremental optimization. Set this attribute
to true to prevent this replacement.
Related Information
Affects this command: syn_opt
Related attributes: (hpin) iopt_avoid_tiecell_replacement
(pin) iopt_avoid_tiecell_replacement
(port) iopt_avoid_tiecell_replacement
lssd_master_clock
lssd_master_clock master_clock
Read-write hport attribute. Identifies two ports on a module as the master clock and slave clock ports. The port on which you set this attribute is the slave clock
port, while the port you specify as the value of this attribute is the master clock port. You must set this attribute before mapping. During mapping, Genus will
make connections from the master clock port to the master clock pins of all master-slave flip-flops driven by this slave clock.
Related Information
Affects this command: syn_map
Affected by this attribute: map_to_master_slave_lssd
Related attributes: (hpin) lssd_master_clock
(pin) lssd_master_clock
(port) lssd_master_clock
net Attributes for Elab-n-Synth
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dont_touch
dont_touch {false | true | delete_ok}
Default: false
Read-write net attribute. Controls the preservation of the net segment during optimization. Setting this attribute will preserve all connections on this net. When
set, this overrides any setting on hnets of this net. The use attribute for the net can also cause the net to be preserved.
You can set the following values:
delete_ok Allows the specified net segment to be deleted if it is not driving any logic.
false Allows the specified net segment to be optimized.
true Prevents the specified net from being optimized.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: (design) dont_touch
(hinst) dont_touch
(hnet) dont_touch
(hpin) dont_touch
(inst) dont_touch
(lib_cell) dont_touch
(module) dont_touch
(pin) dont_touch
pg_pin Attributes for Elab-n-Synth
constant
constant {no_constant | 0 | 1}
Default: no_constant
Read-write pg_pin attribute. Specifies the type of constant that drives the pg_pin.
You can set the following options:
0 Specifies that the pg_pin is driven by a constant 0.
1 Specifies that the pg_pin is driven by a constant 1.
no_constant Specifies that the pg_pin is not driven by a constant.
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Related Information
Related attributes: (hnet) constant
(hpin) constant
(hport) constant
(pin) constant
(port) constant
pin Attributes for Elab-n-Synth
cap_violation
cap_violation_by_mode
constant
dont_touch
fo_violation
fo_violation_by_mode
iopt_avoid_tiecell_replacement
lssd_master_clock
trans_violation
trans_violation_by_mode
cap_violation
cap_violation double
Default: no value
Read-only pin attribute. Gets the capacitance violation on the pin.
cap_violation_by_mode
cap_violation_by_mode tcl_list_of_modes corresponding_resistance_values
Default: no value
Read-only pin attribute. Gets the capacitance violation of the pin for all modes in multimode design.
constant
constant {no_constant | 0 | 1}
Default: no_constant
Read-write pin attribute. Specifies the type of constant that drives the pin.
You can set the following options:
0 Specifies that the pin is driven by a constant 0.
1 Specifies that the pin is driven by a constant 1.
no_constant Specifies that the pin is not driven by a constant.
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Related Information
Related attributes: (hnet) constant
(hpin) constant
(hport) constant
(port) constant
(pg_pin) constant
dont_touch
dont_touch {none | false | true | add_ok | delete_ok | add_invert_ok | invert_ok}
Default: none
Read-write pin attribute. Controls the preservation of the pin during optimization.
You can set the following values:
add_invert_ok Allows changing the pin’s polarity and adding or duplicating the pin.
add_ok Allows adding a pin or duplicating the pin.
delete_ok Allows the specified pin to be deleted if it has no fanout.
false Allows the specified pin to be optimized.
invert_ok Allows to change the polarity of the pin.
none Inherits the setting from the module or hinst.
true Prevents the specified pin from being optimized.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affects this attribute: map_to_multibit_bank_label
Related attributes: (design) dont_touch
(hinst) dont_touch
(hnet) dont_touch
(hpin) dont_touch
(inst) dont_touch
(lib_cell) dont_touch
(module) dont_touch
(net) dont_touch
fo_violation
fo_violation double
Default: no value
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Read-only pin attribute. Gets the fanout violation on the pin.
fo_violation_by_mode
fo_violation_by_mode tcl_list_of_modes corresponding_resistance_values
Default: no value
Read-only pin attribute. Gets the fanout violation on the pin for all modes in multimode design.
iopt_avoid_tiecell_replacement
iopt_avoid_tiecell_replacement {false | true}
Default: false
Read-write pin attribute. Controls whether a constant assignment on this pin can be replaced with a tie cell during incremental optimization. Set this attribute to
true to prevent this replacement.
Related Information
Affects this command: syn_opt
Related attributes: (hpin) iopt_avoid_tiecell_replacement
(hport) iopt_avoid_tiecell_replacement
(port) iopt_avoid_tiecell_replacement
lssd_master_clock
lssd_master_clock master_clock
Read-write pin attribute. Identifies two pins on a hierarchical instance as the master clock and slave clock pins. The pin on which you set this attribute is the
slave clock pin, while the pin you specify as the value of this attribute is the master clock pin. You must set this attribute before mapping. During mapping,
Genus will make connections from the master clock pin to the master clock pins of all master-slave flip-flops driven by this slave clock.
Related Information
Affects this command: syn_map
Affected by this attribute: map_to_master_slave_lssd
Related attributes: (hpin) lssd_master_clock
(hport) lssd_master_clock
(port) lssd_master_clock
trans_violation
trans_violation delay
Default: no value
Read-only pin attribute. Gets the transition violation on the pin.
trans_violation_by_mode
trans_violation_by_mode tcl_list_of_modes corresponding_delays
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Default: no value
Read-only pin attribute.Gets the transition violation on the pin for all modes in multimode design.
port Attributes for Elab-n-Synth
cap_violation
cap_violation_by_mode
constant
fo_violation
fo_violation_by_mode
ignore_external_driver_drc
iopt_avoid_tiecell_replacement
lssd_master_clock
trans_violation
trans_violation_by_mode
cap_violation
cap_violation double
Default: no value
Read-only port attribute. Gets the capacitance violation on the pin.
cap_violation_by_mode
cap_violation_by_mode tcl_list_of_modes corresponding_resistance_values
Default: no value
Read-only port attribute. Gets the capacitance violation of the pin for all modes in multimode design.
constant
constant {no_constant | 0 | 1}
Default: no_constant
Read-write port attribute. Specifies the type of constant that drives the pin.
You can set the following options:
0 Specifies that the port is driven by a constant 0.
1 Specifies that the port is driven by a constant 1.
no_constant Specifies that the port is not driven by a constant.
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Related Information
Related attributes: (hnet) constant
(hpin) constant
(hport) constant
(pin) constant
(pg_pin) constant
fo_violation
fo_violation double
Default: no value
Read-only port attribute. Gets the fanout violation on the pin.
fo_violation_by_mode
fo_violation_by_mode tcl_list_of_modes corresponding_resistance_values
Default: no value
Read-only port attribute. Gets the fanout violation on the pin for all modes in multimode design.
ignore_external_driver_drc
ignore_external_driver_drc {false | true}
Default: false
Read-write port attribute. Indicates whether to use or ignore the design rule constraints specified on the external driver.
Related information
Affects this command: syn_opt
iopt_avoid_tiecell_replacement
iopt_avoid_tiecell_replacement {false | true}
Default: false
Read-write port attribute. Controls whether a constant assignment on this port can be replaced with a tie cell during incremental optimization. Set this attribute
to true to prevent this replacement.
Related Information
Affects this command: syn_opt
Related attributes: (hpin) iopt_avoid_tiecell_replacement
(hport) iopt_avoid_tiecell_replacement
(pin) iopt_avoid_tiecell_replacement
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lssd_master_clock
lssd_master_clock master_clock
Read-write port attribute. Identifies two ports on a module as the master clock and slave clock ports. The port on which you set this attribute is the slave clock
port, while the port you specify as the value of this attribute is the master clock port. You must set this attribute before mapping. During mapping, Genus will
make connections from the master clock port to the master clock pins of all master-slave flip-flops driven by this slave clock.
Related Information
Affects this command: syn_map
Affected by this attribute: map_to_master_slave_lssd
Related attributes: (hpin) lssd_master_clock
(hport) lssd_master_clock
(pin) lssd_master_clock
trans_violation
trans_violation delay
Default: no value
Read-only port attribute. Gets the transition violation on the port.
trans_violation_by_mode
trans_violation_by_mode tcl_list_of_modes corresponding_delays
Default: no value
Read-only port attribute. Gets the transition violation on the pin for all modes in multimode design.
root Attributes for Elab-n-Synth
dp_ungroup_separator frc_treat_modules_as_leaf_insts hdl_allow_inout_const_port_connect
hdl_allow_instance_name_conflict hdl_allow_positional_connections_for_pg_inst hdl_append_generic_ports
hdl_array_naming_style hdl_async_set_reset hdl_auto_async_set_reset
hdl_auto_exec_sdc_scripts hdl_auto_sync_set_reset hdl_bidirectional_assign
hdl_bidirectional_wand_wor_assign hdl_bus_wire_naming_style hdl_case_mux_threshold
hdl_case_sensitive_instances hdl_cdfg_early_redundancy_removal hdl_create_label_for_unlabeled_generate
hdl_decimal_parameter_name hdl_delete_transparent_latch hdl_enable_proc_name
hdl_enable_real_support hdl_error_on_blackbox hdl_error_on_latch
hdl_error_on_logic_abstract hdl_error_on_negedge hdl_exclude_params_in_cell_search
hdl_ff_keep_explicit_feedback hdl_ff_keep_feedback hdl_flatten_complex_port
hdl_flatten_complex_port_in_bottom_up_flow hdl_generate_index_style hdl_generate_separator
hdl_ignore_pragma_names hdl_index_mux_threshold hdl_instance_array_naming_style
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hdl_interface_separator hdl_keep_first_module_definition hdl_language
hdl_latch_keep_feedback hdl_libraries hdl_link_from_any_lib
hdl_max_loop_limit hdl_max_map_to_mux_control_width hdl_max_memory_address_range
hdl_max_recursion_limit hdl_module_definition_resolution hdl_nc_compatible_module_linking
hdl_new_bidirectional_assign hdl_overwrite_command_line_macros hdl_parameter_naming_style
hdl_parameterize_module_name hdl_preserve_async_sr_priority_logic hdl_preserve_dangling_output_nets
hdl_preserve_supply_nets hdl_preserve_sync_ctrl_logic hdl_preserve_sync_set_reset
hdl_preserve_unused_flop hdl_preserve_unused_latch hdl_preserve_unused_registers
hdl_primitive_input_multibit hdl_record_naming_style hdl_reg_array_naming_style
hdl_reg_naming_style hdl_reg_record_naming_style hdl_rename_cdn_flop_pins
hdl_rename_cdn_latch_pins hdl_report_case_info hdl_resolve_instance_with_libcell
hdl_resolve_parameterized_instance_with_structural_module hdl_sv_module_wrapper hdl_sync_set_reset
hdl_track_filename_row_col hdl_track_module_elab_memory_and_runtime hdl_unconnected_value
hdl_use_block_prefix hdl_use_case_generate_prefix hdl_use_current_dir_before_hdl_search_path
hdl_use_cw_first hdl_use_default_parameter_values_in_name hdl_use_for_generate_prefix
hdl_use_if_generate_prefix hdl_use_port_default_value hdl_verilog_defines
hdl_vhdl_assign_width_mismatch hdl_vhdl_case hdl_vhdl_environment
hdl_vhdl_lrm_compliance hdl_vhdl_preferred_architecture hdl_vhdl_range_opto
hdl_vhdl_read_version hdl_zero_replicate_is_null init_blackbox_for_undefined
init_hdl_search_path input_assert_one_cold_pragma input_assert_one_hot_pragma
input_asynchro_reset_blk_pragma input_asynchro_reset_pragma input_case_cover_pragma
input_case_decode_pragma input_map_to_mux_pragma input_pragma_keyword
input_synchro_enable_blk_pragma input_synchro_enable_pragma input_synchro_reset_blk_pragma
input_synchro_reset_pragma proto_hdl script_begin
script_end synthesis_off_command synthesis_on_command
dp_ungroup_separator
dp_ungroup_separator string
Description
Default: :
Data_type: string, read/write
Specifies the user-defined booth encoded setting to input port.
Applies to:
root
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Related Information
Affects this command: elaborate
frc_treat_modules_as_leaf_insts
frc_treat_modules_as_leaf_insts string
Description
Default:
Data_type: string, read/write
Specifies a list of modules that should be treated as leaf level instances. All the instances within those modules get the same file, row, and column tracking
information as the module, assuming it was a leaf level instance.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
read_netlist
Related attribute hdl_track_filename_row_col
hdl_allow_inout_const_port_connect
hdl_allow_inout_const_port_connect {false | true}
Description
Default: false
Data_type: bool, read/write
When set to false, issues an error message if an output or inout pin of an instantiated submodule is connected to a constant value.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
HDL-Related Attributes in Genus HDL Modeling Guide.
hdl_allow_instance_name_conflict
hdl_allow_instance_name_conflict {false | true}
Description
Default: false
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Data_type: bool, read/write
Controls whether the input Verilog file can have a variable (reg or wire) and an instance with the same name. By default, this results in an error. Set this attribute
to true to allow this situation.
Applies to:
root
Related Information
Affects these commands: read_hdl
read_netlist
hdl_allow_positional_connections_for_pg_inst
hdl_allow_positional_connections_for_pg_inst {false | true}
Description
Default: false
Data_type: bool, read/write
Specifies whether to allow positional association for instantiation of cell with power and ground pins.
Applies to:
root
hdl_append_generic_ports
hdl_append_generic_ports {true | false}
Description
Default: true
Data_type: bool, read/write
When set to false, does not append generic port information to the module name. By default, the tool changes the name of the module by appending the
interface name and modport name to the original module name.
Example
Consider the following RTL:
interface nand_intf (
input wire [1:0] a,
input wire [1:0] b,
output wire [1:0] y );
modport FOO (
input a, b,
output y);
endinterface
// Top module
module top;
nand_intf intf_inst ();
test1 t1(
intf_inst.FOO
);
endmodule
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// Sub Module
module test1(nand_intf.FOO intf);
assign intf.y = intf.a & intf.b;
endmodule
By default, the generated netlist after elaboration looks like:
module test1_intf_nand_intf_FOO(intf_a, intf_b, intf_y);
input [1:0] intf_a, intf_b;
output [1:0] intf_y;
wire [1:0] intf_a, intf_b;
wire [1:0] intf_y;
and g1 (intf_y[0], intf_a[0], intf_b[0]);
and g2 (intf_y[1], intf_a[1], intf_b[1]);
endmodule
module top;
wire [1:0] intf_inst_a;
wire [1:0] intf_inst_b;
wire [1:0] intf_inst_y;
test1_intf_nand_intf_FOO t1(intf_inst_a, intf_inst_b, intf_inst_y);
endmodule
When you set the hdl_append_generic_ports to false before reading in the RTL file, the generated netlist after elaboration looks like:
module test1(intf_a, intf_b, intf_y);
input [1:0] intf_a, intf_b;
output [1:0] intf_y; wire [1:0] intf_a, intf_b;
wire [1:0] intf_y;
and g1 (intf_y[0], intf_a[0], intf_b[0]);
and g2 (intf_y[1], intf_a[1], intf_b[1]);
endmodule
module top;
wire [1:0] intf_inst_a;
wire [1:0] intf_inst_b;
wire [1:0] intf_inst_y;
test1 t1(intf_inst_a, intf_inst_b, intf_inst_y);
endmodule
Applies to:
root
Related Information
Affects this command: elaborate
hdl_array_naming_style
hdl_array_naming_style string
Description
Default: %s[%d]
Data_type: string, read/write
Specifies the format used to name individual bits of array variables in the RTL. %s is the variable name and %d is the individual bit. Set this attribute before using
the elaborate command.
This attribute is supported only in the RTL flow.
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Applies to:
root
Related Information
Naming Individual Bits of Array and Record Ports and Registers in Genus User Guide.
Affects these commands: elaborate
read_hdl
hdl_async_set_reset
hdl_async_set_reset Tcl_list
Description
Default: ""
Data_type: string, read/write
Specifies that the tool should implement the listed signals using an asynchronous set and reset pins on a latch if that logic controls an asynchronous
assignment.
This attribute is supported only in the RTL flow and does not affect the syn_map command, which may implement the set and reset logic using latch data
pins.
Example
set_db hdl_async_set_reset {r1 r2} /
The above command has the same effect as using the async_set_reset pragma in the RTL. For example:
// cadence async_set_reset "r1 r2"
Applies to:
root
Related Information
See HDL-Related Attributes for the RTL example and the corresponding schematic for hdl_async_set_reset in the Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_auto_async_set_reset
hdl_auto_async_set_reset {false | true}
Description
Default: false
Data_type: bool, read/write
When set to true, specifies that the tool should implement logic using asynchronous set and reset pins on a latch if that logic controls an asynchronous
assignment of a constant 0 or a constant 1.
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This attribute is supported only in the RTL flow and does not affect the syn_map command, which may implement the set and reset logic using latch data
pins.
Example
The following command implements the reset signal in the RTL using a latch asynchronous reset pin:
set_db hdl_auto_async_set_reset true
Applies to:
root
Related Information
See HDL-Related Attributes for the RTL example and the corresponding schematic in the Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_auto_exec_sdc_scripts
hdl_auto_exec_sdc_scripts {false | true}
Description
Default: true
Data_type: bool, read/write
When set to true, scripts found in the input HDL file of this architecture are automatically run during elaboration. If this attribute is set to false, then scripts are
not automatically started and you will need to use the run_embedded_script command to apply the scripts onto the design when elaborating the netlist.
The embedded script can have any SDC command that is supported by the read_sdc command.
This attribute is supported only in the RTL flow.
Example
An embedded script in the RTL code is a sequence of comments between the script_begin pragma and the script_end pragma:
module my_xor (y, a, b);
parameter w = 8;
input [w-1:0] a, b;
output [w-1:0] y;
assign y = a ^ b;
// synopsys dc_script_begin
// create_clock -name vCLK -period 1 -waveform {0 0.5}
// set_input_delay 0.25 -clock [get_clocks {vCLK}] a*
// set_input_delay 0.25 -clock [get_clocks {vCLK}] b*
// set_output_delay 0.25 -clock [get_clocks {vCLK}] y*
// synopsys dc_script_end
endmodule
module test (y, a, b);
parameter w = 8;
input [w-1:0] a, b;
output [w-1:0] y;
my_xor u1 (y, a, b);
endmodule
The pragma keyword of the script_begin pragma is controlled by the script_begin attribute.
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The pragma keyword of the script_end pragma is controlled by the script_end attribute.
Applies to:
hdl_architecture
root
Related Information
Affects these commands: elaborate
read_hdl
run_embedded_script
Affected by these attributes: script_begin
script_end
hdl_auto_sync_set_reset
hdl_auto_sync_set_reset {false | true}
Description
Default: true
Data_type: bool, read/write
When set to true, specifies that the tool should implement logic using a synchronous set and reset pins on a flip-flop if that logic controls a synchronous
assignment of a constant 0 or a constant 1.
This attribute does not affect the syn_map command, which may implement the set and reset logic using flip-flop data pins.
This attribute is supported only in the RTL flow.
Example
The following command implements the reset signal shown in the RTL using a flip-flop synchronous reset pin:
set_db hdl_auto_sync_set_reset true
Applies to:
hdl_architecture
root
Related Information
HDL-Related Attributes of Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_bidirectional_assign
hdl_bidirectional_assign {false | true}
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Description
Default: false
Data_type: bool, read/write
When set to true, specifies that the tool must interpret Verilog continuous assign statements where the right-hand-side is undriven as being bidirectional. In this
case, the tool matches the behavior of the Conformal ® Logical Equivalence Checker. To prevent bidirectional assignments, set this attribute to false. When set
to false, the tool matches the behavior of the Verilog Language Reference and the Incisive® Simulator.
This attribute does not affect VHDL designs.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_bidirectional_wand_wor_assign
hdl_bidirectional_wand_wor_assign {false | true}
Description
Default: false
Data_type: bool, read/write
Controls the handling of assignments involving signal names declared as wand or wor net types in System Verilog (SV) designs.
The tool can treat assignments as bidirectional, if the LHS and RHS of the assignment only consists of simple signal references or their constant-indexed part-
selects or concatenations. In such assignments, the driver pins or load pins can be on either side of the assignment, since the assignment is treated like a
simple connection between the pins.
If connections involve multiple driver pins then the type of the net (as per declaration type wand/wor/wire) determines the final value of the net and this value is
used to drive all the load pins on the net.
The attribute addresses situations, when two conditions are present:
1. A connection (net) is determined by one/more bidirectional assignments.
2. One or more of the signals involved in the assignments are declared as wand/wor.
When the attribute is set to false (default), assignments to wand/wor declared signals are treated as unidirectional and the driver/loads on the LHS side of the
assignment are not considered part of the same net as the driver-loads of the RHS side of the assignment.
When the attribute is set to true, assignments to wand/wor declared signals are treated as bidirectional and the driver/loads on the LHS side of the assignment
are considered part of the same net as the driver-loads of the RHS side of the assignment. As a result, all drivers (from both sides) are resolved as per wand/wor
resolution to determine the value of the net.
Example
Consider the following RTL:
module t (input in1, in2, in4, input in3, output out1, out2 );
wire temp1,temp2,temp3;
wor temp1_wor;
assign temp1 = (in1 == in2);
assign temp2 = (in3 == in4);
assign out1 = temp1;
assign temp1_wor = temp1; //// assignment to a wor type
assign temp1_wor = temp2; //// assignment to a wor type
assign out2 = ~temp3;
assign temp3 = temp1_wor & in3;
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endmodule
By default, the generated netlist after elaboration looks as follows:
module t(in1, in2, in4, in3, out1, out2);
input in1, in2, in4, in3;
output out1, out2;
wire in1, in2, in4, in3;
wire out1, out2;
wire n_2, temp1_wor, temp3;
not g1 (out2, temp3);
and g2 (temp3, temp1_wor, in3);
or g3 (temp1_wor, out1, n_2);
xnor g4 (out1, in1, in2);
xnor g5 (n_2, in3, in4);
endmodule
## Note: out1 is xnor of in1 and in2. out1 does not depend on in3, in4.
When you set this attribute to true, the generated netlist after elaboration looks as shown below:
module t(in1, in2, in4, in3, out1, out2);
input in1, in2, in4, in3;
output out1, out2;
wire in1, in2, in4, in3;
wire out1, out2;
wire n_1, n_2, temp3;
not g1 (out2, temp3);
and g2 (temp3, out1, in3);
or g3 (out1, n_1, n_2);
xnor g4 (n_1, in1, in2);
xnor g5 (n_2, in3, in4);
endmodule
## Note: out1 depends on all four inputs: in1, in2, in3 and in4.
Applies to:
root
hdl_bus_wire_naming_style
hdl_bus_wire_naming_style string
Description
Default: %s[%d]
Data_type: string, read/write
Specifies the format used to name individual bits of bus wires. %s is the variable name and %d is the individual bit. Set this attribute before using the elaborate
command.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_case_mux_threshold
hdl_case_mux_threshold integer
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Description
Default: 2
Data_type: int, read/write
Determines whether a binary multiplexer (encoded select inputs) or a one-hot multiplexer (decoded select inputs) is generated to implement signals assigned
within case, if-then-else, and choice statements. If the number of distinct values assigned to the signal is greater than or equal to the specified value, a binary
multiplexer is implemented; otherwise, a one-hot multiplexer is implemented.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_case_sensitive_instances
hdl_case_sensitive_instances {none | false | true}
Description
Default: none
Data_type: string, read/write
Controls how Verilog instances must be linked to modules. Following the language rules, instances in Verilog files will by default be linked case sensitively to
modules in Verilog/ VHDL files, while instances in VHDL files will be linked case-insensitively to modules in Verilog/VHDL files.
This attribute can have the following values:
false Allows case-insensitive instance name matching for Verilog instances to modules in Verilog/VHDL files.
none Indicates that the parent language rules govern.
true Allows only case-sensitive instance name matching for Verilog instances to modules in Verilog/VHDL files during linking.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_cdfg_early_redundancy_removal
hdl_cdfg_early_redundancy_removal {false | true}
Description
Default: true
Data_type: bool, read/write
Specifies whether to do an early cleanup of redundant steering logic nodes. An early cleanup of redundant steering logic nodes is performed, by default.
Applies to:
hdl_architecture
root
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hdl_create_label_for_unlabeled_generate
hdl_create_label_for_unlabeled_generate {false | true}
Description
Default: true
Data_type: bool, read/write
Controls whether or not to create a label for an unnamed block. The created label will be of the form genblkx.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_decimal_parameter_name
hdl_decimal_parameter_name {false | true}
Description
Default: false
Data_type: bool, read/write
Controls the format for parameters that are appended to the names of instantiated parameterized modules in the netlist after elaboration. When set to true, the
tool uses a decimal format for parameters with values less than or equal to the size of a 32-bit integer, prepending the value with width and sign information (if
any). Otherwise, the tool uses binary or hex format, as applicable.
Example
Consider the following RTL code:
// RTL file test.v
module TOP(q, d);
output q;
input d;
SUB #(32’b1) u1(q, d);
endmodule
module SUB(q, d);
parameter p = 123;
output q;
input d;
assign q = d > p;
endmodule
Using the default (false) setting of the hdl_decimal_parameter_name attribute, the following netlist is printed after elaboration:
module TOP(q, d);
input d;
output q;
wire d;
wire q;
SUB_p32h00000001 u1(q, d);
endmodule
......
......
If the hdl_decimal_parameter_name attribute is set to true before elaboration, the following netlist is printed:
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module TOP(q, d);
input d;
output q;
wire d;
wire q;
SUB_p32d1 u1(q, d);
endmodule
......
......
Applies to:
root
Related Information
Affects this command: elaborate
Related attribute: hdl_parameter_naming_style
hdl_delete_transparent_latch
hdl_delete_transparent_latch {false | true}
Description
Default: true
Data_type: bool, read/write
Controls whether transparent latches are preserved or deleted during elaboration. When set to true, deletes latches that are always enabled.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_enable_proc_name
hdl_enable_proc_name {false | true}
Description
Default: false
Data_type: bool, read/write
When set to true, updates the value of the hdl_proc_name instance attribute for sequential elements during elaboration.
Applies to:
root
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Related Information
Affects these commands: elaborate
Affects this attribute hdl_proc_name
hdl_enable_real_support
hdl_enable_real_support {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, enables elaboration of constant expressions of real type.
Real support is disabled by default to ensure that users are extra conscious about any real usage in their designs. Cadence recommends using gate-
level simulation to verify the designs when reals are used.
Applies to:
root
hdl_error_on_blackbox
hdl_error_on_blackbox {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, issues an error message if there is an unresolved reference (black-box) during elaboration.
This attribute is supported only in the RTL flow.
Applies to:
hdl_architecture
root
If the root and hdl_architecture attributes are set to different values, the last specification takes precedence.
Related Information
Global Versus User Control on Elaboration in Genus HDL Modeling Guide.
Affects this command: elaborate
hdl_error_on_latch
hdl_error_on_latch {true | false}
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Description
Default: false
Data_type: bool, read/write
When set to true, issues an error message if a latch is inferred for a design.
This attribute is supported only in the RTL flow.
Applies to:
hdl_architecture
root
If the root and hdl_architecture attributes are set to different values, the last specification takes precedence.
Related Information
Global Versus User Control on Elaboration in Genus HDL Modeling Guide.
Affects these commands: elaborate
hdl_error_on_logic_abstract
hdl_error_on_logic_abstract {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, issues an error message if a logic abstract is inferred for a design.
This attribute is supported only in the RTL flow.
Applies to:
hdl_architecture
root
If the root and hdl_architecture attributes are set to different values, the last specification takes precedence.
Related Information
Global Versus User Control on Elaboration in Genus HDL Modeling Guide for Legacy UI.
Affects these commands: elaborate
hdl_error_on_negedge
hdl_error_on_negedge {true | false}
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Description
Default: false
Data_type: bool, read/write
When set to true, issues an error message if a design infers a flip-flop that is triggered by a falling clock edge.
This attribute is supported only in the RTL flow.
Applies to:
hdl_architecture
root
If the root and hdl_architecture attributes are set to different values, the last specification takes precedence.
Related Information
HDL-Related Attributes in Genus HDL Modeling Guide.
Global Versus User Control on Elaboration in Genus HDL Modeling Guide.
Affects these commands: elaborate
hdl_exclude_params_in_cell_search
hdl_exclude_params_in_cell_search string
Description
Default:
Data_type: string, read/write
Controls how a parameterized module instantiation is resolved with a liberty complex cell as opposed to an HDL module. Lists the names of the cells for which
the search must be done with the name of the module but without the parameter information.
Applies to:
root
Related Information
Affects these commands: read_hdl
read_netlist
hdl_ff_keep_explicit_feedback
hdl_ff_keep_explicit_feedback {true | false}
Description
Default: true
Data_type: bool, read/write
Controls how flip-flop stable states are implemented for feedback assignments that are explicitly specified in the RTL.
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This attribute is supported only in the RTL flow.
This attribute is ignored, and all flip-flop feedback is removed when the lp_insert_clock_gating attribute is set to true.
Applies to:
hdl_architecture
root
For hdl_architecture object type, this attribute affects only the module or entity represented by this particular hdl_architecture.
If the root and hdl_architecture attributes are set to different values, this attribute will overwrite and will be the initial value for the hdl_architecture
object type also. That is, hdl_ff_keep_explicit_feedback on a root object will overwrite and be the initial value for
hdl_ff_keep_explicit_feedback on an hdl_architecture object type.
Related Information
HDL-Related Attributes in Genus HDL Modeling Guide.
Global Versus User Control on Elaboration in Genus HDL Modeling Guide.
Affects this command: elaborate
hdl_ff_keep_feedback
hdl_ff_keep_feedback {true | false}
Description
Default: false
Data_type: bool, read/write
Controls how flip-flop stable states are implemented. When set to true, implements a feedback path from the Q output to the D input. When set to false, uses a
synchronous flip-flop enable signal to implement the stable states.
This attribute is supported only in the RTL flow.
This attribute is ignored, and all flip-flop feedback is removed when the lp_insert_clock_gating attribute is set to true.
Examples
The following command implements a feedback path from the Q output to the D input for the RTL:
set_attribute hdl_ff_keep_feedback true /
The following command implements a synchronous enable signal from the Q output to the D input for the RTL:
set_attribute hdl_ff_keep_feedback false /
Applies to:
hdl_architecture
root
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For hdl_architecture object type, this attribute affects only the module or entity represented by this particular hdl_architecture.
If the root and hdl_architecture attributes are set to different values, this attribute will overwrite and will be the initial value for the hdl_architecture
object type also. That is, hdl_ff_keep_feedback on a root object will overwrite and be the initial value for hdl_ff_keep_feedback on an
hdl_architecture object type.
Related Information
HDL-Related Attributes in Genus HDL Modeling Guide.
Global Versus User Control on Elaboration in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_flatten_complex_port
hdl_flatten_complex_port {true | false}
Description
Default: false
Data_type: bool, read/write
Controls how complex ports in the RTL are represented in the generated netlist. A port is considered complex, when it is not declared as a simple vector of bits,
or as a single bit scalar signal. For example, a port declared using a structure typedef is a complex port.
When you set this attribute to true, elaboration creates a single lumped (packed) vector port for any complex port. The bits in the single vector port (created with
the true setting) are set in the order in which the fields/dimensions are ordered in the definition of the complex port. By default, elaboration generates (and
names) multiple bit-vector ports, which correspond to various disjoint fields/pieces of the complex port.
Limitation
This attribute has no impact on any complex port that is defined using interface modport. The tool will continue to generate (and name) multiple ports for
such a complex port.
Applies to:
hdl_architecture
root
Related Information
Affects these commands: elaborate
flatten_complex_ports
read_hdl
hdl_flatten_complex_port_in_bottom_up_flow
hdl_flatten_complex_port_in_bottom_up_flow {true | false}
Description
Default: true
Data_type: bool, read/write
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Creates one-dimensional packed version of complex ports in the bottom-up flow.
Applies to:
hdl_architecture
root
hdl_generate_index_style
hdl_generate_index_style string
Description
Default: %s[%d]
Data_type: string, read/write
Specifies the format to be used to compose the instance name of instances instantiated inside a for-generate statement.
The format string contains the for-generate block label (%s) and optionally the individual for-generate bit index (%d). The default value of %s[%d] complies with
the naming rules defined in Section 12.1.3.1 in Verilog-2001 LRM and in Section 12.4.1 in Verilog-2005 LRM.
In VHDL, a generate statement must have a label. In Verilog, the block of a generate statement can be unnamed. If a generate block is unlabeled, it is given a
name based on the rules defined in the Verilog-2005 LRM (in Section 12.4.3 of IEEE Std 1364-2005).
You must specify this attribute before you elaborate the design.
This attribute affects instances in a for-generate statement. It does not affect instances in a if-generate or case-generate statement.
Applies to:
hdl_architecture
root
Related Information
Affects this command: elaborate
Related attributes: hdl_generate_separator
hdl_use_block_prefix
hdl_generate_separator
hdl_generate_separator string
Description
Default: .
Data_type: string, read/write
Specifies the separator string that appears between block labels in the instance name of an instance instantiated inside a generate statement. A generated
instance name contains multiple block labels if it is inside of nested generate statements.
In Verilog, each layer of the nested generate can be a for-generate, an if-generate, or a case-generate. In VHDL, each layer can be either a for-generate or
an if-generate.
You must specify this attribute before you elaborate the design.
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Applies to:
hdl_architecture
root
Related Information
Affects this command: elaborate
Related attributes: hdl_generate_index_style
hdl_use_block_prefix
hdl_use_if_generate_prefix
hdl_ignore_pragma_names
hdl_ignore_pragma_names string
Description
Default: coverage
Data_type: string, read/write
Specifies a Tcl list of one or more pragma names that must be ignored when reading in Verilog or VHDL.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
hdl_index_mux_threshold
hdl_index_mux_threshold integer
Description
Default: 0
Data_type: int, read/write
Specifies the minimum number of data inputs the tool requires to implement binary multiplexers instead of AND/OR logic for variable index array references,
such as y = x[i].
Applies to:
root
Related Information
Affects these commands: elaborate
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hdl_instance_array_naming_style
hdl_instance_array_naming_style string
Description
Default: %s[%d]
Data_type: string, read/write
Specifies the format used to name individual instance names of an array in the RTL. %s is the array name and %d is the individual bit. Set this attribute before
using the elaborate command.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_interface_separator
hdl_interface_separator string
Description
Default: _
Data_type: string, read/write
Specifies the string used to separate the interface elements.
Applies to:
root
Related Information
Affects these commands: elaborate
write_hdl
hdl_keep_first_module_definition
hdl_keep_first_module_definition {false | true}
Description
Default: false
Data_type: bool, read/write
Controls whether the first seen or last seen definition for a given module name is used. When encountering multiple definitions for the same module name,
Genus keeps the last seen definition by default while ignoring other definitions for the same module name. To force Genus to retain the first seen (instead of the
last seen) definition for a given module name, set the hdl_keep_first_module_definition attribute to true.
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Applies to:
root
Related Information
Affects these commands: read_hdl
hdl_language
hdl_language {v2001 | v1995 | vhdl | sv}
Description
Default: v2001
Data_type: string, read/write
Specifies the default HDL language mode assumed when you run the read_hdl command without specifying the language mode.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_latch_keep_feedback
hdl_latch_keep_feedback {true | false}
Description
Default: false
Data_type: bool, read/write
Controls how explicitly-specified latch stable states (for example, q <= q) are implemented. When set to true, implements a feedback path from the Q output to
the D input, resulting in a combinational loop. When set to false, implements a latch with an enable signal.
This attribute is supported only in the RTL flow.
This attribute is ignored, and all flip-flop feedback is removed when the lp_insert_clock_gating attribute is set to true.
Applies to:
hdl_architecture
root
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For hdl_architecture object type, this attribute affects only the module or entity represented by this particular hdl_architecture.
If the root and hdl_architecture attributes are set to different values, this attribute will overwrite and will be the initial value for the hdl_architecture
object type also. That is, hdl_latch_keep_feedback on a root object will overwrite and be the initial value for hdl_latch_keep_feedback on an
hdl_architecture object type.
Related Information
HDL-Related Attributes in Genus HDL Modeling
Guide.
Global Versus User Control on Elaboration in
Genus HDL Modeling Guide.
Affects these elaborate
commands:
read_hdl
hdl_libraries
Syntax
hdl_libraries <list_of_hdl_libs>
Applies to:
root
Description
Default:
Data_type: hdl_lib*, read only
Returns a list of hdl_lib objects. This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
hdl_link_from_any_lib
hdl_link_from_any_lib {true | false}
Description
Default: true
Data_type: bool, read/write
Links to a unique definition from any library. This is useful when a module is instantiated and there is no specification in the instantiation as to the definition to
which it should be linked. If there are multiple definitions, the instantiated module is not linked.
Applies to:
root
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hdl_max_loop_limit
hdl_max_loop_limit integer
Description
Default: 4096
Data_type: int, read/write
Determines the maximum number of iterations for unfolding a loop construct of any type. The tool stops and produces an error message when it needs to unroll
a loop that has more iterations than the specified threshold.
This is a safety measure to avoid infinite unrolling, as well as to avoid loops with an unexpectedly large number of iterations, which can cause errors in the RTL
code. Usually the overflow detection mechanism catches overflow conditions that cause infinite unrolling.
For example, unrolling the following loop causes an infinite loop and is therefore disallowed by the overflow detection mechanism:
reg [3:0] i;
for (i=0; i<16; i=i+1)
...
Being 4-bit wide, the loop index goes back to 0 after reaching 15.
The overflow detection mechanism also catches infinite unrolling that is not caused by overflow conditions. For example:
parameter incr = 0;
reg [4:0] i;
for (i=0; i<16; i=i+incr)
...
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_max_map_to_mux_control_width
hdl_max_map_to_mux_control_width integer
Description
Default: 10
Data_type: int, read/write
Specifies the maximum size of multiplexers that can be generated by the tool for HDL case statements that are marked with the map_to_mux pragma. If the width
of the case condition, which is implemented as the multiplexer control input, exceeds the value set by this attribute, the tool will ignore the pragma and generate
more efficient logic using AND and OR gates.
Applies to:
root
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Related Information
Affects these commands: elaborate
read_hdl
hdl_max_memory_address_range
hdl_max_memory_address_range integer
Description
Default: 16384
Data_type: int, read/write
Specifies the maximum range of indexed memory access (read or write) that can be elaborated and synthesized.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_max_recursion_limit
hdl_max_recursion_limit integer
Description
Default: 1024
Data_type: int, read/write
Sets the maximum number of elaborations for recursive instantiations to prevent possible infinite recursions.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_module_definition_resolution
hdl_module_definition_resolution {last | first | first_dir_netlist | first_dir_rtl}
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Description
Default: last
Data_type: string, read/write
Controls which definition of a given module name is used when using the read_hdl command with or without the -netlist option. When encountering multiple
definitions for the same module name, the tool keeps the last seen definition by default while ignoring other definitions for the same module name.
This attribute can have the following values:
first Uses the first seen definition in case of multiple definitions of the same module.
first_dir_netlist Uses the first read module definition in case different files exist in different directories containing the same module definition and uses
the last read module in case the same directory contains multiple files with the same module definition when using read_hdl -
netlist.
In case of a conflict, modules read with read_hdl -netlist are given priority over the same modules read with the read_hdl
and read_hdl -vhdl commands.
first_dir_rtl Uses the first read module definition in case different files exist in different directories containing the same module definition and uses
the last read module in case the same directory contains multiple files with the same module definition when using read_hdl without
the -netlist option.
last Uses the last seen definition in case of multiple definitions of the same module.
Applies to:
root
Related Information
Affects this command: read_hdl
hdl_nc_compatible_module_linking
hdl_nc_compatible_module_linking {true | false}
Description
Default: true
Data_type: bool, read/write
By default, implements Native Compiler (NC) compatible binding rules for linking module or entity instantiations with corresponding definitions.
To link a module instantiation and choose a definition that should be linked, the following rules describe the order in which a search is applied to find a module
to link.
For a Verilog instance, searches:
The entity in the work default library.
All libraries if the hdl_nc_compatible_module_linking attribute is set to true.
For a VHDL instance, searches:
The specified library to find a module definition if the library name is specified as part of the instantiation, for example:
instance_name: entity lib_name.entity_name
If the library is not found, the search is not attempted across any other library and a message is issued stating that the specified binding was not
found.
The library in which the component was compiled.
A design unit made visible with a USE clause given to the architecture instantiating the component.
A design unit made visible with a USE clause given to the entity of the architecture instantiating the component.
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A design unit in Genus’s default library.
A design unit made visible with a LIBRARY clause given to the architecture instantiating the component.
A design unit made visible with a LIBRARY clause given to the entity of the architecture instantiating the component.
With these rules in place, if more than one match is found for a particular search rule, the search order is as follows:
For a Verilog instance, searches only for a case-sensitive match.
For a VHDL instance, searches:
A VHDL-specific binding. A matching VHDL module that was read in first will be picked up for linking.
A Verilog module whose name and case matches that used in the component declaration.
A Verilog module with a matching name that is all lowercase.
A Verilog module with a matching name in any case.
When multiple module definitions exist for an instantiation, setting the attribute to false allows the tool to search in all libraries for a module definition. The
module resolution for the instance may or may not be successful depending on finding the exact match. If there are multiple matches, linking resolution may not
happen. When set to false, the tool does not follow any particular set of rules when performing linking resolution.
It is recommended to set the attribute to true, especially when multiple definitions exist for the same module.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_new_bidirectional_assign
hdl_new_bidirectional_assign {false | true}
Description
Default: true
Data_type: bool, read/write
Controls whether to interpret Verilog continuous assign statements as being bidirectional.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_overwrite_command_line_macros
hdl_overwrite_command_line_macros {false | true}
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Description
Default: true
Data_type: bool, read/write
Enables overwriting of the values of macros passed with the read_hdl -define command with the values specified in the RTL files. If you set this attribute to
false, the command-line values are retained throughout unless a particular macro is undefined in some file. You need to set this attribute before you read the
RTL files.
Example
Consider the following RTL file:
// test1.v
‘define MACRO1 4
module test1 (out1);
output[7:0] out1;
ssign out1 = ‘MACRO1;
endmodule // test1
Consider the following script:
read_hdl -define MACRO1=5 test1.v
When you use the default setting (true), the value used for MACRO1 will be 4. That is, the value in the RTL file (4) overwrites the value of the command line
(5).
When you set the hdl_overwrite_command_line_macros to false, the value of the command line will be used, and the value of MACRO1 will be 5.
Applies to:
root
Related Information
Affects this command: read_hdl
hdl_parameter_naming_style
hdl_parameter_naming_style string
Description
Default: _%s%d
Data_type: string, read/write
Specifies the format of the suffix added to the original module name for each parameter overwrite.
Each uniquified parameterized module is named by concatenating the original module name and a number of suffix strings, one string per parameter.
For the top-level module, the attribute applies to the parameters whose values are specified with the -parameters option of the elaborate command.
For an instantiated module, the attribute is effective if both of the following conditions apply:
The module name of the child module is not parameterized.
The parameter value is given by the instantiation statement.
This attribute is useful when you have a design where Verilog parameters or generic ports in the VHDL are causing long module names that exceed another
tool’s internal limit.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
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Affects these commands: elaborate
read_hdl
hdl_parameterize_module_name
hdl_parameterize_module_name {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether to add the parameter values in the parameterized module name for the top-level design or the design specified with the elaborate command.
By default, the parameter value is added to the design name.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_preserve_async_sr_priority_logic
hdl_preserve_async_sr_priority_logic {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, the tool is prevented from generating redundant logic when, during mapping, a flip-flop cell is selected that has the same priority for the
asynchronous set and reset operations as specified in the input HDL.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_preserve_dangling_output_nets
hdl_preserve_dangling_output_nets {true | false}
Description
Default: true
Data_type: bool, read/write
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When set to true, the tool preserves the names of dangling nets connected to instance output ports.
This attribute is supported only in the structural flow.
Applies to:
root
Related Information
Affects these commands: read_netlist
read_hdl -netlist
hdl_preserve_supply_nets
hdl_preserve_supply_nets {true | false}
Description
Default: true
Data_type: bool, read/write
When set to true, the tool preserves the supply nets in the design that is read in.
Example
The following module has two supply nets in the design.
module test_64(Y, Z, A);
input A;
output Y, Z;
supply0 s0;
supply1 s1;
assign Z = s1;
and u1 (Y, s0, A);
endmodule
Using the default value for the hdl_preserve_supply_nets attribute produces the following post-elaboration netlist:
module test_64(Y, Z, A);
input A;
output Y, Z;
wire A;
wire Y, Z;
supply0 s0;
supply1 s1;
assign Z = s1;
and u1 (Y, s0, A);
endmodule
Setting the value for the hdl_preserve_supply_nets attribute to false produces the following post-elaboration netlist:
module test_64(Y, Z, A);
input A;
output Y, Z;
wire A;
wire Y, Z;
assign Z = 1’b1;
and u1 (Y, 1’b0, A);
endmodule
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Applies to:
root
Related Information
Affects these commands: elaborate
read_netlist
write_hdl
hdl_preserve_sync_ctrl_logic
hdl_preserve_sync_ctrl_logic {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, the tool will try to keep the synchronous control logic close to the flip-flops and prevent merging it with surrounding logic in the fanin cone.
You must set this attribute before reading the design so the tool can automatically preserve the synchronous control pins of the flip-flops. Enabling this attribute
can impact QoR.
Applies to:
root
Related Information
Affects this command: elaborate
hdl_preserve_sync_set_reset
hdl_preserve_sync_set_reset {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, the tool will try to keep the synchronous set (reset) control logic close to the flip-flops and prevent merging it with surrounding logic in the fanin
cone.
You must set this attribute before reading in the design so the tool can automatically preserve the synchronous control pins of the flip-flops. Enabling this
attribute can impact QoR.
Applies to:
root
Related Information
Affects this command: elaborate
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hdl_preserve_unused_flop
hdl_preserve_unused_flop {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, the tool does not remove flip-flops that do not, directly or indirectly, affect any outputs. This can be used, for example, to keep flops that are
only used to observe internal nets through scan chains in test mode.
This attribute only affects flops that are inferred by elaboration. It does not affect flops that are explicitly instantiated in the HDL code.
This attribute is supported only in the RTL flow and ignored in the structural flow.
Example
In the following example, the hdl_preserve_unused_flop attribute affects the xl_3_reg and yf_3_reg instances that are inferred during elaboration. It does not
affect the u3 and u4 instances that are explicitly instantiated in the HDL code.
module test (y, d, clk);
input clk, d;
output y;
wire xl_2, yf_2;
reg xl_3, yf_3;
latch_in_lib u3 (.D(d), .G(clk), .Q(xl_2));
flop_in_lib u4 (.CP(clk), .D(d), .Q(yf_2));
always @(clk or d)
begin if (clk)
xl_3 <= d;
end
always @(posedge clk)
begin
yf_3 <= d;
end
assign y = ~d;
endmodule
Using the default setting (false) of the hdl_preserve_unused_flop attribute creates the following post-elaboration netlist:
module test (y, d, clk);
input d, clk;
output y;
wire d, clk;
wire y;
wire xl_2, yf_2;
latch_in_lib u3(.D (d), .G (clk), .Q (xl_2));
flop_in_lib u4(.CP (clk), .D (d), .Q (yf_2));
not g1 (y, d);
endmodule
Setting the hdl_preserve_unused_flop attribute to true creates the following post-elaboration netlist:
module test (y, d, clk);
input d, clk;
output y;
wire d, clk;
wire y;
wire UNCONNECTED, xl_2, yf_2;
latch_in_lib u3(.D (d), .G (clk), .Q (xl_2));
flop_in_lib u4(.CP (clk), .D (d), .Q (yf_2));
not g2 (y, d);
CDN_flop yf_3_reg(.clk (clk), .d (d), .sena (1’b1), .aclr (1’b0),
.apre (1’b0), .srl (1’b0), .srd (1’b0), .q (UNCONNECTED));
endmodule
`ifdef RC_CDN_GENERIC_GATE
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`else
module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
input clk, d, sena, aclr, apre, srl, srd;
output q;
wire clk, d, sena, aclr, apre, srl, srd;
wire q;
reg qi;
assign #1 q = qi;
always
@(posedge clk or posedge apre or posedge aclr)
if (aclr)
qi <= 0;
else if (apre)
qi <= 1;
else if (srl)
qi <= srd;
else begin
if (sena)
qi <= d;
end
initial
qi <= 1’b0;
endmodule
`endif
Applies to:
hdl_architecture
root
Related Information
Affects these commands: elaborate
read_hdl
Related attribute: hdl_preserve_unused_registers
hdl_preserve_unused_latch
hdl_preserve_unused_latch {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, the tool does not remove latches that do not, directly or indirectly, affect any output. This can be used, for example, to keep registers that are
only used to observe internal nets through scan chains in test mode.
This attribute affects only latches that are inferred by elaboration. It does not affect latches that are explicitly instantiated in the HDL code.
This attribute is supported only in the RTL flow and ignored in the structural flow.
Example
In the following example, the hdl_preserve_unused_latch attribute affects the xl_3_reg and yf_3_reg instances that are inferred during elaboration. It does not
affect the u3 and u4 instances that are explicitly instantiated in the HDL code.
module test (y, d, clk);
input clk, d;
output y;
wire xl_2, yf_2;
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reg xl_3, yf_3;
latch_in_lib u3 (.D(d), .G(clk), .Q(xl_2));
flop_in_lib u4 (.CP(clk), .D(d), .Q(yf_2));
always @(clk or d)
begin if (clk)
xl_3 <= d;
end
always @(posedge clk)
begin
yf_3 <= d;
end
assign y = ~d;
endmodule
Using the default setting (false) of the hdl_preserve_unused_latch attribute creates the following post-elaboration netlist:
module test (y, d, clk);
input d, clk;
output y;
wire d, clk;
wire y;
wire xl_2, yf_2;
latch_in_lib u3(.D (d), .G (clk), .Q (xl_2));
flop_in_lib u4(.CP (clk), .D (d), .Q (yf_2));
not g1 (y, d);
endmodule
Setting the hdl_preserve_unused_latch attribute to true, creates the following post-elaboration netlist:
module test (y, d, clk);
input d, clk;
output y;
wire d, clk;
wire y;
wire UNCONNECTED, xl_2, yf_2;
latch_in_lib u3(.D (d), .G (clk), .Q (xl_2));
flop_in_lib u4(.CP (clk), .D (d), .Q (yf_2));
not g2 (y, d);
CDN_latch xl_3_reg(.d (d), .ena (clk), .aclr (1’b0), .apre (1’b0),
.q (UNCONNECTED));
endmodule
`ifdef RC_CDN_GENERIC_GATE
`else
module CDN_latch(ena, d, aclr, apre, q);
input ena, d, aclr, apre;
output q;
wire ena, d, aclr, apre;
wire q;
reg qi;
assign #1 q = qi;
always
@(d or ena or apre or aclr)
if (aclr)
qi <= 0;
else if (apre)
qi <= 1;
else begin
if (ena)
qi <= d;
end
initial
qi <= 1’b0;
endmodule
`endif
Applies to:
hdl_architecture
root
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Related Information
Affects these commands: elaborate
read_hdl
Related attribute: hdl_preserve_unused_registers
hdl_preserve_unused_registers
hdl_preserve_unused_registers {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, Genus does not remove registers (latches and flip-flops) that do not, directly or indirectly, affect any outputs. This can be used, for example, to
keep registers that are only used to observe internal nets through scan chains in test mode.
This attribute only affects registers that are inferred by elaboration. It does not affect registers that are explicitly instantiated in the HDL code.
This attribute is supported only in the RTL flow and ignored in the structural flow.
Example
In the following example, the hdl_preserve_unused_registers attribute affects the xl_3_reg and yf_3_reg instances that are inferred during elaboration. It does
not affect the u3 and u4 instances that are explicitly instantiated in the HDL code.
module test (y, d, clk);
input clk, d;
output y;
wire xl_2, yf_2;
reg xl_3, yf_3;
latch_in_lib u3 (.D(d), .G(clk), .Q(xl_2));
flop_in_lib u4 (.CP(clk), .D(d), .Q(yf_2));
always @(clk or d)
begin if (clk)
xl_3 <= d;
end
always @(posedge clk)
begin
yf_3 <= d;
end
assign y = ~d;
endmodule
Using the default setting (false) of the hdl_preserve_unused_registers attribute creates the following post-elaboration netlist:
module test (y, d, clk);
input d, clk;
output y;
wire d, clk;
wire y;
wire xl_2, yf_2;
latch_in_lib u3(.D (d), .G (clk), .Q (xl_2));
flop_in_lib u4(.CP (clk), .D (d), .Q (yf_2));
not g1 (y, d);
endmodule
Setting the hdl_preserve_unused_registers attribute to true creates the following post-elaboration netlist:
module test (y, d, clk);
input d, clk;
output y;
module test (y, d, clk);
input d, clk;
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output y;
wire d, clk;
wire y;
wire UNCONNECTED, UNCONNECTED0, xl_2, yf_2;
latch_in_lib u3(.D (d), .G (clk), .Q (xl_2));
flop_in_lib u4(.CP (clk), .D (d), .Q (yf_2));
not g3 (y, d);
CDN_latch xl_3_reg(.d (d), .ena (clk), .aclr (1’b0), .apre (1’b0),
.q (UNCONNECTED));
CDN_flop yf_3_reg(.clk (clk), .d (d), .sena (1’b1), .aclr (1’b0),
.apre (1’b0), .srl (1’b0), .srd (1’b0), .q (UNCONNECTED0));
endmodule
`ifdef RC_CDN_GENERIC_GATE
`else
module CDN_latch(ena, d, aclr, apre, q);
input ena, d, aclr, apre;
output q;
wire ena, d, aclr, apre;
wire q;
reg qi;
assign #1 q = qi;
always
@(d or ena or apre or aclr)
if (aclr)
qi <= 0;
else if (apre)
qi <= 1;
else begin
if (ena)
qi <= d;
end
initial
qi <= 1’b0;
endmodule
`endif
`ifdef RC_CDN_GENERIC_GATE
`else
module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
input clk, d, sena, aclr, apre, srl, srd;
output q;
wire clk, d, sena, aclr, apre, srl, srd;
wire q;
reg qi;
assign #1 q = qi;
always
@(posedge clk or posedge apre or posedge aclr)
if (aclr)
qi <= 0;
else if (apre)
qi <= 1;
else if (srl)
qi <= srd;
else begin
if (sena)
qi <= d;
end
initial
qi <= 1’b0;
endmodule
`endif
Applies to:
hdl_architecture
root
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Related Information
Affects these commands: elaborate
read_hdl
hdl_primitive_input_multibit
hdl_primitive_input_multibit {false | true}
Description
Default: false
Data_type: bool, read/write
Controls whether a Verilog primitive gate instantiated in RTL can have a multibit output pin connected to the primitive. For example, gates like NOT, bufif0,
bufif1, notif0, notif1, and tran expect a single bit output. However, sometimes multibit outputs are connected in the RTL to these primitives.
Set this attribute to true to allow the LSB bit of a multibit output to be connected to the input of these primitives. By default, RTL with multibit signals connected
to the input would not be allowed.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_record_naming_style
hdl_record_naming_style string
Description
Default: %s[%s]
Data_type: string, read/write
Specifies the format used to name individual bits of record variables in the RTL. The first %s the variable name and the second %s is the field name. Set this
attribute before using the elaborate command.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Naming Individual Bits of Array and Record Ports and Registers in Genus User Guide for examples on how to use this attribute.
Affects these commands: elaborate
read_hdl
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hdl_reg_array_naming_style
hdl_reg_array_naming_style string
Description
Default:
Data_type: string, read/write
Specifies the format for naming array type registers.
Applies to:
root
hdl_reg_naming_style
hdl_reg_naming_style string
Description
Default: %s_reg%s
Data_type: string, read/write
Specifies the format used to name flip-flop and latch instances inferred from scalar and vector variables in the RTL. The first %s is the variable name. If the
variable is a vector, the second %s is the individual bit of the vector as specified by the hdl_array_naming_style attribute.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Naming Individual Bits of Array and Record Ports and Registers in Genus User Guide.
Affects these commands: elaborate
read_hdl
hdl_reg_record_naming_style
hdl_reg_record_naming_style string
Description
Default:
Data_type: string, read/write
Specifies the format for naming record type registers.
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Applies to:
root
hdl_rename_cdn_flop_pins
hdl_rename_cdn_flop_pins list_of_pin_mappings
Description
Default: ""
Data_type: string, read/write
Renames the specified pins of inferred CDN_flop components. Specify a list of pin mappings, where each mapping renames the given pin.
After elaboration and prior to mapping, the tool uses CDN_flop components to represent the flip-flops. The default CDN_flop pin names are:
Pin Name Pin Function
aclr asynchronous clear
apre asynchronous preset
clk clock
d data input
q output
sena synchronous data enable
srd synchronous set/reset data
srl synchronous set/reset load
When different CDN_flop pin names are required (for example, an SDC constraints file may use different pin names), use this attribute to rename the CDN_flop
pins.
Applies to:
root
Related Information
Elaborating the Design in Genus User Guide.
Affects these commands: elaborate
read_hdl
hdl_rename_cdn_latch_pins
hdl_rename_cdn_latch_pins list_of_pin_mappings
Description
Default: ""
Data_type: string, read/write
Renames the specified pins of inferred CDN_latch components. Specify a list of pin mappings, where each mapping renames the given pin.
After elaboration and prior to mapping, Genus uses CDN_latch components to represent the latches.
When different CDN_latch pin names are required (for example, an SDC constraints file may use different pin names), use this attribute to rename the
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CDN_latch pins.
Applies to:
root
Related Information
Elaborating the Design in Genus User Guide.
Affects these commands: elaborate
read_hdl
hdl_report_case_info
hdl_report_case_info {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, reports information about how the elaborate command infers full_case and parallel_case for every "multi-way decision statement" (like a
case statement). The reporting is module-by-module, with one report for each module. Since full_case and parallel_case pragmas are not yet supported in the
tool for VHDL case statements, no information is printed for VHDL modules (entities/architectures).
The reports can help users understand whether the tool:
Honored the full_case or parallel_case pragma
Automatically inferred a full or parallel case
Applies to:
root
hdl_resolve_instance_with_libcell
hdl_resolve_instance_with_libcell {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, the tool binds the instances of design M to component M from the technology library. If there is no M component in the technology library, the
tool binds the instances of M to a user-defined module M, provided this module exists. If there is no M user-defined module, the instances of M are assumed to be
unresolved references (blackboxes).
This attribute is supported in the RTL flow and the structural flow.
If you want to bind an instance of design M to component M from the technology library even when a parameterized user module with name M is present, and you
are using the RTL flow, you must also set the root attribute hdl_resolve_parameterized_instance_with_structural_module to true.
Applies to:
root
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Related Information
Logic Abstract Modeling in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
read_netlist
hdl_resolve_parameterized_instance_with_structural_module
hdl_resolve_parameterized_instance_with_structural_module {true | false}
Description
Default: false
Data_type: bool, read/write attribute
Controls whether module linking uses the parameterized module name. During elaboration, the tool tries to identify a child module for every instantiation
statement in the RTL code.
By default, the tool does not look for a parameterized module name to resolve the instantiation, but instead looks for a module with the exact same name as
given in the instantiation statement.
If you set this attribute to true, the tool looks for the parameterized module names during module linking.
If the instantiation statement provides the parameter name(s), the child module name is parameterized using the _%s%d style as illustrated in the first
example.
If the instantiation statement does not provide a parameter name, the child module name is parameterized using the _%d style as illustrated in the second
example.
Child modules with a parameter in their body are not considered during linking as illustrated in the third example.
At the module-linking step during elaboration, the hdl_parameter_naming_style attribute setting does not affect how the instantiated module name is
parameterized.
This attribute is supported only in the RTL flow.
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Examples
The following RTL code of the top-level module has an instantiation statement that contains the parameter name p and references the parameter value 16:
module top (y, a, b);
parameter w = 16;
input [w-1:0] a, b;
output [w-1:0] y;
btm #(.p(w)) u1 (y, a, b);
endmodule
If the attribute is set to false, the tool links this instance to a Verilog module (or a VHDL entity) whose name is btm. If set to true, the tool links the instance
to a module or entity whose name is btm_p16. The parameterized module name includes both the parameter name p and the parameter value 16.
The linked child module might be similar to:
module btm_p16 (z, c, d);
input [15:0] c, d;
output [15:0] z;
...
endmodule
The following RTL code of the top-level module has an instantiation statement that references a parameter value (16) but has no parameter name:
module top (y, a, b);
parameter w = 16;
input [w-1:0] a, b;
output [w-1:0] y;
btm #(w) u1 (y, a, b);
endmodule
If the attribute is set to false, the tool links this instance of instantiation to a Verilog module (or a VHDL entity) whose name is btm. If set to true, the tool
links the instance to a module or entity whose name is btm_16. This parameterized module name does not include the parameter name, because the tool
cannot derive that from the instantiation statement. The linked child module might be similar to:
module btm_16 (z, c, d);
input [15:0] c, d;
output [15:0] z;
...
endmodule
The following RTL code of the top-level module has an instantiation statement that references a parameter value (16) and has no parameter name. Even
when the attribute is set to true, the tool will not link instance uo to module btm_16 because module btm_16 has a parameter statement:
module top (...);
btm #(16) u0 (...);
....
endmodule
module btm_16 (...);
parameter p = 32;
...
endmodule
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_sv_module_wrapper
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hdl_sv_module_wrapper {true | false}
Description
Default: false
Data_type: bool, read/write
Enables the generation of a System Verilog module wrapper that connects the original I/O interfaces to the port names in the Verilog netlist.
Set this attribute to true before you elaborate the design to generate the module wrapper with the definitions of the complex types used.
This attribute applies only to RTL using System Verilog interfaces. When interfaces are used, the I/O ports written in the Verilog netlist will by default not
match the test bench.
Applies to:
root
Related Information
Elaborating the Design in Genus User Guide.
Affects this command: elaborate
write_sv_wrapper
hdl_sync_set_reset
hdl_sync_set_reset Tcl_list
Description
Default:
Data_type: string, read/write
Specifies that the tool should implement the listed signals using a synchronous set and reset pins on a flip-flop if that logic controls a synchronous assignment.
This attribute is supported only in the RTL flow.
This attribute does not affect the syn_map command, which may implement the set and reset logic using flip-flop data pins.
Example
set_db / .hdl_sync_set_reset {r1 r2}
This command has the same effect as using the sync_set_reset pragma in the RTL:
// cadence sync_set_reset "r1 r2"
Applies to:
root
Related Information
HDL-Related Attributes in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
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hdl_track_filename_row_col
hdl_track_filename_row_col {true | false}
Description
Default: false
Data_type: bool, read/write
Enables or disables file, row, and column information tracking. By default, all the file, row, and column information is deleted. Set this attribute to true before
using the elaborate command to enable file, row, column information tracking.
This attribute enables the tool to keep track of filenames, line numbers, and column numbers for all instances before optimization and use this information in
selected reports and messages.
Enabling this attribute can have an impact on the runtime.
This attribute is supported in the RTL flow and the structural flow.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
read_netlist
Related attribute: frc_treat_modules_as_leaf_insts
hdl_track_module_elab_memory_and_runtime
hdl_track_module_elab_memory_and_runtime {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether the tool tracks the memory used (in MegaBytes) and run time taken (cpu-time in seconds) during elaboration of each module.
If you set this attribute to true, the run time and memory usage numbers are printed (to standard output) for each module during elaboration. The numbers
printed for each module indicate the time and memory needed to elaborate that module, but the numbers do not include the time and memory taken to elaborate
other modules instantiated by the module.
Set this attribute to true for designs that have a long elaboration time to identify the modules that are impacting performance.
This attribute is supported only in the RTL flow. The attribute will only print out the numbers for modules, which are read and elaborated by the read_hdl
command (the high level RTL flow) and will have no effect for modules which are read by the read_netlist command (the structural elaboration flow).
Applies to:
root
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Related Information
Affects these commands: elaborate
read_hdl
hdl_unconnected_value
hdl_unconnected_value {0 | 1 | X | none}
Description
Default: 0
Data_type: string, read/write
Connects any undriven signal (undriven input in module or cell instantiation, undriven output or undriven signal) in a module to the specified value during
generic synthesis.
If you set the attribute value to none, then an undriven signal remains undriven. If you specify the X value, then an undriven signal is driven by an x dont-care
value. The specified value is case-insensitive. You can specify x, X, none, None, or NONE.
Examples
Example 1: In the following example, the wc signal is undriven:
module test (y, a, b);
input [3:0] a, b;
output [3:0] y;
wire [3:0] wa, wb, wc;
assign wa = a;
assign wb = b;
assign y = wa & wb & wc;
endmodule
If you set the attribute to 0, the netlist after generic synthesis will look as follows:
module test(y, a, b);
input [3:0] a, b;
output [3:0] y;
wire [3:0] a, b;
wire [3:0] y;
assign y[0] = 1'b0;
assign y[1] = 1'b0;
assign y[2] = 1'b0;
assign y[3] = 1'b0;
endmodule
If you set the attribute to 1, the netlist after generic synthesis will look as follows:
module test(y, a, b);
input [3:0] a, b;
output [3:0] y;
wire [3:0] a, b;
wire [3:0] y;
and g18 (y[1], a[1], b[1]);
and g19 (y[0], a[0], b[0]);
and g20 (y[2], a[2], b[2]);
and g21 (y[3], a[3], b[3]);
endmodule
If you set the attribute to none, the netlist after generic synthesis will look like:
module test(y, a, b);
input [3:0] a, b;
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output [3:0] y;
wire [3:0] a, b;
wire [3:0] y;
wire [3:0] wc;
wire n_19, n_22, n_25, n_28;
nand g29 (n_19, a[1], b[1]);
nand g30 (n_22, a[0], b[0]);
nand g31 (n_28, a[3], b[3]);
nand g32 (n_25, a[2], b[2]);
and g33 (y[1], wc0, wc[1]);
not gc (wc0, n_19);
and g34 (y[2], wc1, wc[2]);
not gc0 (wc1, n_25);
and g35 (y[0], wc2, wc[0]);
not gc1 (wc2, n_22);
and g36 (y[3], wc3, wc[3]);
not gc2 (wc3, n_28);
endmodule
If you set the attribute to x, the netlist after generic synthesis will look like:
module test(y, a, b);
input [3:0] a, b;
output [3:0] y;
wire [3:0] a, b;
wire [3:0] y;
assign y[0] = 1'b0;
assign y[1] = 1'b0;
assign y[2] = 1'b0;
assign y[3] = 1'b0;
endmodule
Example 2: In the following example, the c input port of the and3 sub-module is unconnected in all three instantiation statements:
module and3 (y, a, b, c);
input [7:0] a, b, c;
output [7:0] y;
assign y = a & b & c;
endmodule
module test (x, y, z, a, b);
input [7:0] a, b;
output [7:0] x, y, z;
and3 u1 (.y(x), .a(a), .b(b), .c());
and3 u2 (.y(y), .a(a), .b(b));
and3 u3 (z, a, b);
endmodule
If you specify 0, the netlist after generic synthesis will look like:
module test(x, y, z, a, b);
input [7:0] a, b;
output [7:0] x, y, z;
wire [7:0] a, b;
wire [7:0] x, y, z;
assign z[0] = 1'b0;
assign z[1] = 1'b0;
assign z[2] = 1'b0;
assign z[3] = 1'b0;
assign z[4] = 1'b0;
assign z[5] = 1'b0;
assign z[6] = 1'b0;
assign z[7] = 1'b0;
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assign y[0] = 1'b0;
assign y[1] = 1'b0;
assign y[2] = 1'b0;
assign y[3] = 1'b0;
assign y[4] = 1'b0;
assign y[5] = 1'b0;
assign y[6] = 1'b0;
assign y[7] = 1'b0;
assign x[0] = 1'b0;
assign x[1] = 1'b0;
assign x[2] = 1'b0;
assign x[3] = 1'b0;
assign x[4] = 1'b0;
assign x[5] = 1'b0;
assign x[6] = 1'b0;
assign x[7] = 1'b0;
endmodule
If you specify 1, the netlist after generic synthesis will look like:
module and_op(A, B, Z);
input [7:0] A, B;
output [7:0] Z;
wire [7:0] A, B;
wire [7:0] Z;
and g25 (Z[7], A[7], B[7]);
and g26 (Z[6], A[6], B[6]);
and g27 (Z[5], A[5], B[5]);
and g28 (Z[0], A[0], B[0]);
and g29 (Z[3], A[3], B[3]);
and g30 (Z[2], A[2], B[2]);
and g31 (Z[1], A[1], B[1]);
and g32 (Z[4], A[4], B[4]);
endmodule
module and3(y, a, b, c);
input [7:0] a, b, c;
output [7:0] y;
wire [7:0] a, b, c;
wire [7:0] y;
and_op g1(.A (a), .B (b), .Z (y));
endmodule
module test(x, y, z, a, b);
input [7:0] a, b;
output [7:0] x, y, z;
wire [7:0] a, b;
wire [7:0] x, y, z;
assign z[0] = x[0];
assign z[1] = x[1];
assign z[2] = x[2];
assign z[3] = x[3];
assign z[4] = x[4];
assign z[5] = x[5];
assign z[6] = x[6];
assign z[7] = x[7];
assign y[0] = x[0];
assign y[1] = x[1];
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assign y[2] = x[2];
assign y[3] = x[3];
assign y[4] = x[4];
assign y[5] = x[5];
assign y[6] = x[6];
assign y[7] = x[7];
and3 u1(.y (x), .a (a), .b (b), .c (8'b11111111));
endmodule
If you specify none, the netlist after generic synthesis will look like:
module …..
……
endmodule
module test(x, y, z, a, b);
input [7:0] a, b;
output [7:0] x, y, z;
wire [7:0] a, b;
wire [7:0] x, y, z;
wire UNCONNECTED, UNCONNECTED0, UNCONNECTED1, UNCONNECTED2,UNCONNECTED3,
UNCONNECTED4, UNCONNECTED5, UNCONNECTED6;
wire UNCONNECTED7, UNCONNECTED8, UNCONNECTED9, UNCONNECTED10,
UNCONNECTED11, UNCONNECTED12, UNCONNECTED13, UNCONNECTED
wire UNCONNECTED15, UNCONNECTED16, UNCONNECTED17, UNCONNECTED18,
UNCONNECTED19, UNCONNECTED20, UNCONNECTED21, UNCONNECTED22;
and3 u1(.y (x), .a (a), .b (b), .c ({UNCONNECTED6, UNCONNECTED5,
UNCONNECTED4, UNCONNECTED3, UNCONNECTED2, UNCONNECTED1,UNCONNECTED0,
UNCONNECTED}));
and3_1 u2(.y (y), .a (a), .b (b), .c ({UNCONNECTED14, UNCONNECTED13,
UNCONNECTED12, UNCONNECTED11, UNCONNECTED10, UNCONNECTED9,UNCONNECTED8,
UNCONNECTED7}));
and3_2 u3(z, a, b, {UNCONNECTED22, UNCONNECTED21, UNCONNECTED20,
UNCONNECTED19,UNCONNECTED18, UNCONNECTED17, UNCONNECTED16,UNCONNECTED15});
endmodule
If you specify x, the netlist after generic synthesis will look like:
module test(x, y, z, a, b);
input [7:0] a, b;
output [7:0] x, y, z;
wire [7:0] a, b;
wire [7:0] x, y, z;
assign z[0] = 1'b0;
assign z[1] = 1'b0;
assign z[2] = 1'b0;
assign z[3] = 1'b0;
assign z[4] = 1'b0;
assign z[5] = 1'b0;
assign z[6] = 1'b0;
assign z[7] = 1'b0;
assign y[0] = 1'b0;
assign y[1] = 1'b0;
assign y[2] = 1'b0;
assign y[3] = 1'b0;
assign y[4] = 1'b0;
assign y[5] = 1'b0;
assign y[6] = 1'b0;
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assign y[7] = 1'b0;
assign x[0] = 1'b0;
assign x[1] = 1'b0;
assign x[2] = 1'b0;
assign x[3] = 1'b0;
assign x[4] = 1'b0;
assign x[5] = 1'b0;
assign x[6] = 1'b0;
assign x[7] = 1'b0;
endmodule
Example 3: In the following example, the X output port is undriven:
module test (x, y, a, b);
input [3:0] a, b;
output [3:0] x, y;
assign y = a & b;
endmodule
If you specify none, the netlist after generic synthesis will look as follows:
module and_op(A, B, Z);
input [3:0] A, B;
output [3:0] Z;
wire [3:0] A, B;
wire [3:0] Z;
and g13 (Z[3], A[3], B[3]);
and g14 (Z[0], A[0], B[0]);
and g15 (Z[1], A[1], B[1]);
and g16 (Z[2], A[2], B[2]);
endmodule
module test(x, y, a, b);
input [3:0] a, b;
output [3:0] x, y;
wire [3:0] a, b;
wire [3:0] x, y;
and_op g1(.A (a), .B (b), .Z (y));
endmodule
If you specify 0, the netlist after generic synthesis will look like:
module and_op(A, B, Z);
input [3:0] A, B;
output [3:0] Z;
wire [3:0] A, B;
wire [3:0] Z;
and g13 (Z[3], A[3], B[3]);
and g14 (Z[0], A[0], B[0]);
and g15 (Z[1], A[1], B[1]);
and g16 (Z[2], A[2], B[2]);
endmodule
module test(x, y, a, b);
input [3:0] a, b;
output [3:0] x, y;
wire [3:0] a, b;
wire [3:0] x, y;
assign x[0] = 1'b0;
assign x[1] = 1'b0;
assign x[2] = 1'b0;
assign x[3] = 1'b0;
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and_op g1(.A (a), .B (b), .Z (y));
endmodule
If you specify 1, the netlist after generic synthesis will look like:
module and_op(A, B, Z);
input [3:0] A, B;
output [3:0] Z;
wire [3:0] A, B;
wire [3:0] Z;
and g13 (Z[3], A[3], B[3]);
and g14 (Z[0], A[0], B[0]);
and g15 (Z[1], A[1], B[1]);
and g16 (Z[2], A[2], B[2]);
endmodule
module test(x, y, a, b);
input [3:0] a, b;
output [3:0] x, y;
wire [3:0] a, b;
wire [3:0] x, y;
assign x[0] = 1'b1;
assign x[1] = 1'b1;
assign x[2] = 1'b1;
assign x[3] = 1'b1;
and_op g1(.A (a), .B (b), .Z (y));
endmodule
If you specify X, the netlist after generic synthesis will look like:
module and_op(A, B, Z);
input [3:0] A, B;
output [3:0] Z;
wire [3:0] A, B;
wire [3:0] Z;
and g13 (Z[3], A[3], B[3]);
and g14 (Z[0], A[0], B[0]);
and g15 (Z[1], A[1], B[1]);
and g16 (Z[2], A[2], B[2]);
endmodule
module test(x, y, a, b);
input [3:0] a, b;
output [3:0] x, y;
wire [3:0] a, b;
wire [3:0] x, y;
assign x[0] = 1'b0;
assign x[1] = 1'b0;
assign x[2] = 1'b0;
assign x[3] = 1'b0;
and_op g1(.A (a), .B (b), .Z (y));
endmodule
Applies to:
root
Related Information
Affects this command: syn_generic
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hdl_use_block_prefix
hdl_use_block_prefix {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether block statement labels should be used as a prefix for the instance names specified in the input RTL description.
Applies to:
hdl_architecture
root
Related Information
Affects this command: elaborate
Related attributes: hdl_generate_index_style
hdl_generate_separator
hdl_use_if_generate_prefix
hdl_use_case_generate_prefix
hdl_use_case_generate_prefix {true | false}
Description
Default: true
Data_type: bool, read/write
Specifies whether 'case' generate labels should be used to prefix instances.
Applies to:
hdl_architecture
root
hdl_use_current_dir_before_hdl_search_path
hdl_use_current_dir_before_hdl_search_path {true | false}
Description
Default: false
Data_type: bool, read/write
Controls the order of the directories from where the include files must be read. By default, the tool uses the directories specified with the init_hdl_search_path
attribute to search for include files. When the hdl_use_current_dir_before_hdl_search_path attribute is set to true, the tool uses the directory of the source file
(containing the include file) before the HDL search path.
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Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
read_netlist
hdl_use_cw_first
hdl_use_cw_first {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, uses ChipWare components to instantiate the functionality in the design, instead of user-defined modules (Verilog) or entities (VHDL). This
attribute is applicable in the cases in which the RTL code has a user-defined module with the identical name of a ChipWare component.
Applies to:
root
hdl_use_default_parameter_values_in_name
hdl_use_default_parameter_values_in_name {true | false}
Description
Default: false
Data_type: bool, read/write
Shortens the name of the parametrized module by using only the parameter values specified at instantiation, by default. On setting this attribute to true, the tool
uses all the available parameters in the parametrized module name.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_use_for_generate_prefix
hdl_use_for_generate_prefix {true | false}
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Description
Default: true
Data_type: bool, read/write
Controls whether the block label of a for-generate statement will be used with the for-generate index values as prefix of the name of an instance instantiated
within the generate construct.
If this attribute is set tofalse, the for-generate index values are appended to the name of instances instantiated within the generate construct.
If this attribute is set to true, instance naming follows the naming style defined in the Verilog-2005 LRM (in Section 12.4.2 and 12.4.3 of IEEE Std 1364-
2005).
You must specify this attribute before you elaborate the design.
Example
For the following examples consider the following VHDL code:
L1: FOR i IN 2 TO 4 generateu1 : sub port map(q => q(i), d1 => d1(i), d2 => d2(i));end generate;
When you set the hdl_use_for_generate_prefix attribute to true, the tool generates the following:
sub \L1[2].u1 (.q (q[2]), .d1 (d1[2]), .d2 (d2[2]));
sub \L1[3].u1 (.q (q[3]), .d1 (d1[3]), .d2 (d2[3]));
sub \L1[4].u1 (.q (q[4]), .d1 (d1[4]), .d2 (d2[4]));
When you set the hdl_use_for_generate_prefix attribute to false, the tool generates the following:
sub \u1.[2] (.q (q[2]), .d1 (d1[2]), .d2 (d2[2]));
sub \u1.[3] (.q (q[3]), .d1 (d1[3]), .d2 (d2[3]));
sub \u1.[4] (.q (q[4]), .d1 (d1[4]), .d2 (d2[4]));
Applies to:
hdl_architecture
root
Related Information
Affects this command: elaborate
Related attributes: hdl_generate_index_style
hdl_generate_separator
hdl_use_if_generate_prefix
hdl_use_if_generate_prefix {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether the block label of an if-generate statement will be used as prefix of the instance name of an instance instantiated within the generate
construct.
If this attribute is set to false, this part of instance naming is backward-compatible with prior releases.
If this attribute is set to true, this part of instance naming follows the naming style defined in the Verilog-2005 LRM (in Section 12.4.2 of IEEE Std 1364-
2005).
In VHDL, a generate statement must have a label. In Verilog, the block of a generate statement can be unnamed. If without a label, it is given a name based on
the rules defined in the Verilog-2005 LRM (in Section 12.4.3 of IEEE Std 1364-2005).
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This attribute does not affect a Verilog case-generate statement, with which the block label is always used when composing instance names.
You must specify this attribute before you elaborate the design.
Applies to:
hdl_architecture
root
Related Information
Affects this command: elaborate
Related attributes: hdl_generate_separator
hdl_use_block_prefix
hdl_use_port_default_value
hdl_use_port_default_value {true | false}
Description
Default: true
Data_type: bool, read/write
When set to true, the tool honors the default initial values of the input ports in a VHDL component declaration or entity declaration.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
hdl_verilog_defines
hdl_verilog_defines macro_definition_list
Description
Default: SYNTHESIS
Data_type: string, read/write
Specifies a list of global macro definitions that must be applied to each subsequent read_hdl (except with -vhdl) and read_netlist command. This includes
calls to read_hdl made during a call to elaborate -libpath.
Each macro definition has the form id or id=expr.
Applies to:
root
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Related Information
Affects these commands: elaborate -libpath
read_hdl
read_netlist
hdl_vhdl_assign_width_mismatch
hdl_vhdl_assign_width_mismatch {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether to allow an assignment in VHDL when the left-hand side (LHS) and right-hand side (RHS) have the same array type but mismatching width.
When set to true, the RHS gets truncated or extended to the width of the LHS. By default, VHDL does not allow such assignments.
Example
Consider the following RTL where the ports Mult_A and Z have the same array type but have incompatible bit widths:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity mmnumeric1 is
generic (wmA : integer := 2;
wZ : integer := 5);
port ( Mult_A : in signed (wmA-1 downto 0);
Z : out signed (wZ-1 downto 0) );
end;
architecture rtl of mmnumeric1 is
begin
Z <= Mult_A;
end;
With the default setting of hdl_vhdl_assign_width_mismatch (false), the tool issues the error message CDFG-283 during elaboration.
When you set hdl_vhdl_assign_width_mismatch to true, the RTL will successfully elaborate, but the tool issues the warning message CDFG-239.
Applies to:
root
Related Information
VHDL-Specific Attributes in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_vhdl_case
hdl_vhdl_case {original | lower | upper}
Description
Default: original
Data_type: string, read/write
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Stores VHDL identifiers and operators in lowercase, uppercase, or the case given in the source file.
Applies to:
root
Related Information
VHDL-Specific Attributes in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_vhdl_environment
hdl_vhdl_environment {common | synergy}
Description
Default: common
Data_type: string, read/write
Specifies the selection of the predefined arithmetic libraries.
Applies to:
root
Related Information
VHDL-Specific Attributes in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_vhdl_lrm_compliance
hdl_vhdl_lrm_compliance {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, the read_hdl command enforces a strict interpretation of the VHDL LRM. This variable lets you verify that your VHDL code is compliant with
the LRM, such that it is likely to work on other VHDL tools.
When set to false the following features are allowed:
Treats a concatenation as a locally static expression, which allows constructs such as the following:
case expr is
when "001" & ’1’ => ...
Initializes an interface object with a function call.
Lets you use name X in the definition of a different X:
constant c : integer := 3;
function f (c : integer := c) is ...
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In VHDL-1987, treats a function call with globally static arguments as a globally static expression. For instance:
function f(x : integer) return integer;
generic (y : integer := f(3));
Applies to:
root
Related Information
VHDL-Specific Attributes in Genus HDL Modeling
Guide.
Affects these elaborate
commands:
read_hdl
hdl_vhdl_preferred_architecture
hdl_vhdl_preferred_architecture string
Description
Default:
Data_type: string, read/write
Sets the name of preferred architecture to use with an entity when there are multiple architectures.
Applies to:
root
Related Information
VHDL-Specific Attributes in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_vhdl_range_opto
hdl_vhdl_range_opto {true | false}
Description
Default: false
Data_type: bool, read/write
Controls the optimization of the widths of arithmetic operators (+, *, -) that have ranged integer arguments in VHDL.
Example
Consider the following RTL:
entity rngopt is port(
in1 : in integer range 0 to 12;
in2 : in integer range 0 to 3;
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output : out integer);
end;
architecture rtl of rngopt is
begin
output <= in1 + in2;
end;
When you set hdl_vhdl_range_opto to true, the tool infers an unsigned adder with an output width of 4 bits during elaboration, because the result will be
in the range of 0 to 15 (12+3).
When you use the default setting (false), the tool infers an unsigned adder with an output width of 5 bits during elaboration.
Applies to:
root
Related Information
VHDL-Specific Attributes in Genus HDL Modeling Guide.
Affects this command: elaborate
hdl_vhdl_read_version
hdl_vhdl_read_version {1993 | 1987 | 2008}
Description
Default: 1993
Data_type: string, read/write
Specifies the VHDL version to be used when reading VHDL designs. If you change the hdl_vhdl_read_version read version at any time, the tool automatically
re-maps the IEEE and STD VHDL libraries to the correct directory in the software release. In this way, the correct versions of the standard packages in these
libraries are picked up.
Applies to:
root
Related Information
VHDL-Specific Attributes in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
hdl_zero_replicate_is_null
hdl_zero_replicate_is_null {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether a zero-length replication is treated as a null expression having zero width. This matches the behavior of Conformal® Equivalence Checking.
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Example
Consider the following expression:
{ {0{8’hff}}, 3’b111 }
If the attribute is set to false, this expression evaluates to 4’b0111.
If the attribute is set to true, the expression evaluates to 3’b111.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
init_blackbox_for_undefined
Syntax
init_blackbox_for_undefined {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls how a logic abstract that is inferred from an empty module, an entity without an architecture, or an entity whose architecture is empty, is interpreted.
If set to true, the logic abstract becomes an unresolved reference in the design. Genus tries to find a library cell with a name corresponding to that of the logic
abstract. If it finds such a cell, the logic abstract is represented as an instance of that library cell. Otherwise, the logic abstract becomes an unresolved reference.
If set to false, the logic abstract remains as a module in the design hierarchy. In this case, an empty module is created which is not considered
unresolved. This is an unrealistic situation. The tool would treat the output ports of the module as undriven and would assign them values based on the
setting of the hdl_unconnected_value attribute. This can potentially create false non-eq points during verification with LEC. Therefore, this setting should
be avoided.
This attribute is supported in the RTL flow and the structural flow.
Related Information
Logic Abstract Modeling in Genus HDL Modeling Guide.
Affects these commands: elaborate
read_hdl
read_netlist
Affected by this attribute: hdl_resolve_instance_with_libcell
init_hdl_search_path
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init_hdl_search_path string
Description
Default: .
Data_type: string, read/write
Specifies the list of UNIX directories in which the tool should search for files associated with the read_hdl command. The behavior is similar to the search path
in UNIX.
In Verilog, this attribute directs the search of Verilog files specified with the read_hdl command and `include files specified in the Verilog code.
In VHDL, this attribute directs the search of VHDL files specified with the read_hdl command.
This attribute is supported in the RTL flow and the structural flow.
The "~" character is supported.
Applies to:
root
Related Information
Affects these commands: elaborate
read_hdl
read_netlist
input_assert_one_cold_pragma
input_assert_one_cold_pragma string
Description
Default: assert_one_cold one_cold
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a one_cold pragma when reading in Verilog or VHDL.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_assert_one_hot_pragma
input_assert_one_hot_pragma string
Description
Default: assert_one_hot one_hot
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Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a one_hot pragma when reading in Verilog or VHDL.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_asynchro_reset_blk_pragma
input_asynchro_reset_blk_pragma string
Description
Default: async_set_reset_local asynchro_reset_blk
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as an asynchro_reset_blk pragma when reading in Verilog or VHDL.
Specifies the aliases for the asynchro_reset_blk pragma:
//cadence asynchro_reset_blk <namedBlock> [{rst1 rst2}]
Any if conditions in the specified block containing rst1 and rst2 are considered as asynchronous reset condition inside the asynchronous if-then-else
decoding code.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_asynchro_reset_pragma
input_asynchro_reset_pragma string
Description
Default: async_set_reset asynchro_reset
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as an asynchro_reset pragma when reading in Verilog or VHDL.
Specifies the aliases for the asynchro_reset pragma:
//cadence asynchro_reset [{rst1 rst2}]
Any if conditions containing rst1 and rst2 are considered as asynchronous reset conditions inside the asynchronous if-then-else decoding code.
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This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_case_cover_pragma
input_case_cover_pragma string
Description
Default: full_case
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a full_case pragma when reading in Verilog or VHDL.
Specifies the equivalent used in input pragmas for the case_logic cover pragma.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_case_decode_pragma
input_case_decode_pragma string
Description
Default: parallel_case
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a parallel_case pragma when reading in Verilog or VHDL.
Specifies the equivalent used in input pragmas for the case_logic no_priority pragma.
This attribute is supported only in the RTL flow.
Applies to:
root
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Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_map_to_mux_pragma
input_map_to_mux_pragma string
Description
Default: map_to_mux infer_mux_override
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a map_to_mux pragma when reading in Verilog or VHDL.
Specifies the equivalent used in input pragmas for the map_to_mux pragma.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
Related attribute: map_to_mux
input_pragma_keyword
input_pragma_keyword string
Description
Default: cadence synopsys ambit pragma synthesis
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as the keyword indicating a pragma when reading in Verilog or VHDL.
A pragma is a comment whose first word is a pragma keyword specified in this attribute.
You cannot remove the cadence keyword from the list.
This attribute is supported in the RTL flow and the structural flow.
Applies to:
root
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Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects these commands: read_hdl
read_netlist
input_synchro_enable_blk_pragma
input_synchro_enable_blk_pragma string
Description
Default: synchro_enable_blk
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a synchro_enable_blk pragma when reading in Verilog or VHDL.
Specifies the alias names for the synchro_reset_blk pragma.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_synchro_enable_pragma
input_synchro_enable_pragma string
Description
Default: synchro_enable
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a synchro_enable pragma when reading in Verilog or VHDL.
Specifies the alias names for the synchro_enable pragma.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
read_netlist
input_synchro_reset_blk_pragma
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input_synchro_reset_blk_pragma string
Description
Default: sync_set_reset_local synchro_reset_blk
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a synchro_reset_blk pragma when reading in Verilog or VHDL.
Specifies the aliases for the sync_set_reset_local pragma.
//cadence sync_set_reset_local namedBlock "comma-separated_list_of_signals"
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
input_synchro_reset_pragma
input_synchro_reset_pragma string
Description
Default: sync_set_reset synchro_reset
Data_type: string, read/write
Carries a Tcl list of one or more names, each being treated as a synchro_reset pragma when reading in Verilog or VHDL.
Specifies the aliases for the synchro_reset pragma:
//cadence sync_set_reset [{rst1 rst2}]
Any if conditions containing rst1 and rst2 are considered as synchronous reset conditions inside the synchronous if-then-else decoding code.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
proto_hdl
proto_hdl string
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Description
Default:
Data_type: string, read/write
Enables support for incomplete HDL.
Applies to:
root
Related Information
Affects this command: elaborate
script_begin
script_begin string
Description
Default: dc_script_begin dc_tcl_script_begin script_begin
Data_type: string, read/write
Specifies the keyword in the RTL netlist that indicates the beginning of a script included in the netlist.
This attribute is supported only in the RTL flow.
Applies to:
root
Related Information
Supported Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
Affects this attribute: hdl_auto_exec_sdc_scripts
Related attribute: script_end
script_end
script_end string
Description
Default: dc_script_end dc_tcl_script_end script_end
Data_type: string, read/write
Specifies the keyword in the RTL netlist that indicates the end of a script included in the netlist.
Applies to:
root
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Related Information
Supported Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
Affects this attribute: hdl_auto_exec_sdc_scripts
Related attribute: script_begin
synthesis_off_command
synthesis_off_command string
Description
Default: translate_off synthesis_off
Data_type: string, read/write
Specifies the pragma that is used to indicate the beginning of non-synthesizable constructs in the RTL source code or in the generated generic netlist.
This attribute is supported in the RTL flow and the structural flow.
Applies to:
root
Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
read_netlist
Related attributes: synthesis_on_command
input_pragma_keyword
synthesis_on_command
synthesis_on_command string
Description
Default: translate_on synthesis_on
Data_type: string, read/write
Specifies the pragma that is used to indicate the end of non-synthesizable constructs in the RTL source code or in the generated generic netlist.
This attribute is supported in the RTL flow and the structural flow.
Applies to:
root
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Related Information
Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: read_hdl
read_netlist
Related attributes: synthesis_off_command
input_pragma_keyword
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GUI
9
GUI
The chapter describes the following attributes:
gui_auto_update
gui_enabled
gui_hv_phys_threshold
gui_hv_threshold
gui_pv_highlight_hier_instances_show_legend
gui_show_old_legend
gui_sv_threshold
gui_sv_update
gui_visible
imm_block_view_brightness
win_fp_inst_threshold
Most of the GUI attributes are available in both the new GUI and legacy GUI. A note is added
for attributes that apply only to the legacy GUI.
gui_auto_update
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GUI--gui_enabled
Syntax
gui_auto_update {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Indicates whether the GUI should be automatically updated.
This attribute is available only in the legacy GUI.
gui_enabled
Syntax
gui_enabled {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read only
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GUI--gui_hv_phys_threshold
Indicates whether the tool was started in GUI mode.
Related Information
Set by this command: genus
gui_hv_phys_threshold
Syntax
gui_hv_phys_threshold <integer>
Applies to:
root
Description
Default: 10
Data_type: int, read/write
Specifies the number of instances that a hierarchical instance should have to be highlighted in the
Physical Viewer when you select the Highlight Physical command. If the number of instances in a
hierarchical instance is below the threshold, the hierarchical instance is not highlighted.
This attribute is available only in the legacy GUI.
gui_hv_threshold
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GUI--gui_pv_highlight_hier_instances_show_legend
Syntax
gui_hv_threshold <integer>
Applies to:
root
Description
Default: 50
Data_type: bool, read/write
Sets the threshold for the number of objects that are listed for each hierarchical-level in the
Hierarchy Viewer. If the number of objects for a given hierarchy level exceeds the threshold, the list
is truncated.
This attribute is available only in the legacy GUI.
gui_pv_highlight_hier_instances_show_legend
Syntax
gui_pv_highlight_hier_instances_show_legend {true | false}
Applies to:
root
Description
Default: true
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GUI--gui_show_old_legend
Data_type: bool, read/write
When set to false, the legend dialog will not be shown with gui_highlight_hier_instances_pv
command. By default, legend dialog will be shown.
gui_show_old_legend
Syntax
gui_show_old_legend {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, the TK style legend dialog will be displayed.
gui_sv_threshold
Syntax
gui_sv_threshold <integer>
Applies to:
root
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GUI--gui_sv_update
Description
Default: 2000
Data_type: int, read/write
Sets the threshold for the number of instances that can be displayed in the current hierarchy level. If
the number of instances in the current hierarchy level exceeds the threshold, the display mode for
the Schematic Viewer is set to manual. This implies that the value of the gui_sv_update attribute is
set to manual, even if the attribute was set to auto.
gui_sv_update
Syntax
gui_sv_update {auto | manual}
Applies to:
root
Description
Default: auto
Data_type: string, read/write
Controls the display mode for the Schematic Viewer.
Mode Description
auto You can display the schematic of an instance by double-clicking:
The left or middle mouse button on the instance in the Hierarchy Viewer.
The left mouse button on the instance in the Schematic Viewer.
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GUI--gui_visible
manual You can display the schematic of an instance by selecting the instance in:
The Hierarchy Viewer and selecting the Open in – Schematic Viewer (main)
command from the context menu.
The main Schematic Viewer and selecting the Open in – Schematic Viewer (new)
command from the context menu.
Related Information
Affected by this attribute: gui_sv_threshold
gui_visible
Syntax
gui_visible {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read only
Indicates whether the GUI is currently visible.
By default, the tool is started in GUI mode (unless you started with the -nogui option). However, the
GUI is only visible by entering the gui_raise or gui_show command.
Before you use the gui_raise or gui_show commands, this attribute will return false. After you use
either of these commands, the attribute returns true.
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GUI--imm_block_view_brightness
imm_block_view_brightness
Syntax
imm_block_view_brightness <integer>
Applies to:
root
Description
Default: 100
Data_type: int, read/write
Specifies the brightness level of block views.
win_fp_inst_threshold
Syntax
win_fp_inst_threshold <integer>
Applies to:
root
Description
Default: 1000
Data_type: int, read only
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GUI--imm_block_view_brightness
Specifies the maximum number of instances the modules can contain for automatic floor-planning.
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ChipWare
10
ChipWare
The chapter describes the attributes of the following object types:
avoid bit_width candidate_impls
constraint cw_library_version cwd_setup_file
designware_compatibility formula hdl_parameter
legal obsolete operator
param_association parameters permutable_group
pin_association pre_elab_script preferred_comp
preferred_impl preserve_techelts report_as_datapath
selected_impl signed speed_grade
sub_arch technology unbound_oper_pin
user_speed_grade user_sub_arch
See also:
direction
language
location
pins
priority
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ChipWare--avoid
avoid
Syntax
avoid {false | true}
Applies to:
base_cell
lib_cell
hdl_bind
hdl_component
hdl_implementation
hdl_lib
Description
Default: false
Data_type: bool, read/write
base_cell
lib_cell When set to true, prevents a library cell from being used by the
technology mapper. If certain library cells are not desired, setting the
'avoid' attribute on them will cause them not to be selected during
mapping.
hdl_bind Determines whether the specified binding should be used during
elaboration.
hdl_component Determines whether a particular ChipWare component from the specified
library should be used during elaboration.
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ChipWare--bit_width
hdl_implementation Specifies whether a particular architecture of a specific ChipWare
component should be used during elaboration.
hdl_lib Determines whether ChipWare components from the specified library
should be used during elaboration.
Related Information
Affects this command: syn_map
Affected by this attribute: is_usable
bit_width
Syntax 1
bit_width <string>
Applies to:
hdl_pin
Description
Default:
Data_type: string, read/write
Specifies a formula, in Tcl, to compute the bit-width of the specified pin. The values are usually
based on the parameters of the component.
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ChipWare--candidate_impls
Syntax 2
bit_width <integer>
Applies to:
lib_cell
Description
Default: 1
Data_type: int, read only
Specifies the width of the cell in terms of number of unit components.
Related Information
Related attributes: multibit_cells_from_different_busses
use_multibit_cells
use_multibit_combo_cells
use_multibit_seq_and_tristate_cells
candidate_impls
Syntax
candidate_impls {{impl_directory_1 bind_name_1} {impl_directory_2 bind_name_2} ...}
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ChipWare--constraint
Applies to:
module
Description
Default:
Data_type: string, read only
Returns all the implementations available for a particular a module. The returned value is a Tcl list
of a Tcl list, where impl_directory represents the implementation directory and bind_name
represents the binding name. Each list item represents a possible implementation, which is a valid
binding to a particular instance.
Related Information
Related attributes: selected_impl
preferred_impl
constraint
Syntax
constraint <constraint_setting>
Applies to:
hdl_bind
Description
Default:
Data_type: string, read/write
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ChipWare--cw_library_version
Specifies the constraint setting, which is a set of conditions that must be satisfied to make the
specified binding valid during elaboration.
cw_library_version
Syntax
cw_library_version <string>
Applies to:
root
Description
Default:
Data_type: string, read only
Returns the current version of Chipware library being used.
cwd_setup_file
cwd_setup_file string
Description
Default:
Data_type: string, read/write
Specifies the setup file that contains the commands for the ChipWare Developer flow.
ChipWare Developer enables you to add user-defined ChipWare components and user-defined
implementations of tool-defined ChipWare components. The commands to set up the ChipWare
Developer flow must be specified in the setup file. The tool automatically sources this file to set up
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ChipWare--designware_compatibility
the necessary infrastructure. This is required to correctly pass the information to the super-thread
servers.
Applies to:
root
designware_compatibility
Syntax
designware_compatibility {true | false}
Applies to:
hdl_component
Description
Default: false
Data_type: bool, read/write
Indicates whether the component is compatible with an existing DesignWare component. When
false, the component has no corresponding DesignWare counterpart. When true, the component
is compatible with an existing DesignWare component.
When you use such a component the tool prints message CDFG-820 to the log file to point out that
while the features and functions are compatible they cannot be guaranteed to be exactly
implementation-equivalent. It is your responsibility to verify if the specific Cadence implementation
matches your requirements.
formula
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ChipWare--hdl_parameter
Syntax
formula <string>
Applies to:
hdl_parameter
Description
Default:
Data_type: string, read/write
Specifies a formula, in Tcl, to compute the value of a parameter.
hdl_parameter
Syntax
hdl_parameter {true | false}
Applies to:
hdl_parameter
Description
Default: false
Data_type: bool, read only
Returns whether the specified parameter is visible within the ChipWare component. If the specified
parameter was created with the create_component_parameter command without its -hdl_invisible
option, the default value of this attribute will be false. If the specified parameter was created with
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ChipWare--legal
the -hdl_invisible option, this attribute value becomes true. This attribute is valid on all
parameters (hdl_parameter objects), not just those created by the create_component_parameter
command.
Related Information
Related command: create_component_parameter
legal
Syntax
legal <formula>
Applies to:
hdl_implementation
Description
Default:
Data_type: string, read/write
Specifies a formula, in Tcl, to determine the legality of the specified implementation. The criteria is
usually based on the bit-width of input/output signals.
obsolete
Syntax
obsolete {false | true}
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ChipWare--operator
Applies to:
hdl_component
hdl_implementation
Description
Default: false
Data_type: bool, read/write
Indicates whether the specified ChipWare component (or its implementation) will be obsolete. If the
attribute returns a value of true, you should replace the component/implementation with a
comparable one that will not be obsoleted.
operator
Syntax
operator <string>
Applies to:
hdl_bind
Description
Default:
Data_type: string, read only
Returns the name of the synthetic operator to which the specified binding applies.
param_association
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ChipWare--parameters
Syntax
param_association <string>
Applies to:
hdl_bind
Description
Default:
Data_type: string, read/write
Specifies the method to compute values for parameters of the component. The parameter values
can be obtained either from
Input pins of the synthetic operator that are driven by constant values in the HDL subprogram
Constant values
parameters
Syntax
parameters <string>
Applies to:
hdl_architecture
hdl_component
Description
Default:
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ChipWare--permutable_group
Data_type: string, read only
Object Description
hdl_architecture In Verilog, this attribute keeps an ordered list of all parameters of the
module represented by the hdl_architecture object. In VHDL, this attribute
keeps an ordered list of generics of the entity represented by the
hdl_architecture object.
hdl_component Returns an ordered list of all parameters of the specified ChipWare
component.
Do not confuse this attribute with the parameters branch of vdir objects attached to the hdl
/ hdl_component object. Under that branch, each parameter is represented by its own
hdl_parameter object.
permutable_group
Syntax
permutable_group <group_name>
Applies to:
hdl_pin
Description
Default:
Data_type: string, read/write
Specifies the name of the permutation group to which this pin belongs. The value is the null string if
no group is specified.
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ChipWare--pin_association
pin_association
Syntax
pin_association <string>
Applies to:
hdl_bind
Description
Default:
Data_type: string, read/write
Specifies how pins of the specified component are to be mapped. They can be mapped either
through:
Pins of the synthetic operator
Constant values
pre_elab_script
Syntax
pre_elab_script <UNIX_path>
Applies to:
hdl_implementation
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ChipWare--preferred_comp
Description
Default:
Data_type: string, read/write
Specifies the UNIX path that contains the pre-elaboration script. Each CWD synthesis model can
be accompanied by a "pre-elaboration script". When this synthesis model is to be used to
implement something, this script is sourced after its HDL code is parsed, but before its HDL code is
elaborated (hence the name).
A pre-elaboration script is exercised on an hdl_architecture object.
Related Information
Related attributes: preferred_comp
preferred_impl
preferred_comp
Syntax
preferred_comp {component_name}
Applies to:
hdl_label
Description
Default:
Data_type: string, read/write
Used with the attribute preferred_impl, the preferred_comp attribute specifies a preferred
component for the HDL operator annotated by a label in the RTL code. For example, the following
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ChipWare--preferred_impl
operation in the RTL code is label L1:
p <= a + b; -- pragma label L1
During elaboration, if the specified component is available, Genus uses it to implement the HDL
operator. Otherwise, the component will be ignored and Genus will choose the best component.
Related Information
Affects this attribute: wireload
Related attributes: user_speed_grade
pre_elab_script
preferred_impl
preferred_impl
Syntax
preferred_impl {implementation_name [hdl_inst_pathname]}
Applies to:
hdl_inst
hdl_label
Description
Default:
Data_type: string, read/write
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ChipWare--preferred_impl
hdl_inst Specifies a preferred implementation for the specified CWD component instance.
When Genus is choosing an implementation for a particular CWD component, it
applies a rigorous selection process to select the best implementation. This
attribute allows you to explicitly communicate to Genus a preference for a particular
implementation for a particular CWD component.
This attribute needs to be set before the elaborate command is issued.
As the name of this attribute indicates, it is a preference. The specified
implementation must pass all of the following criteria to be conclusively honored:
Its legal attribute is evaluated to true
Its priority attribute is greater than 0
Its avoid attribute is false
Its technology attribute is either empty or consistent with the current library
setting.
If any of these criteria fail for the specified implementation the following actions
occur:
A warning message is issued to explain the failure
The preference is ignored
The default implementation selection mechanism is used
hdl_label Used with the attribute preferred_comp, the preferred_impl attribute specifies a
preferred implementation for the HDL operator annotated by a label in the RTL
code. For example, the following operation in the RTL code is label L1:
p <= a + b; -- pragma label L1
During elaboration, if the specified implementation is available, Genus uses it to
implement the HDL operator. Otherwise, the implementation will be ignored and
Genus will choose the best implementation.
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ChipWare--preserve_techelts
Related Information
Affects this attribute: wireload
Related attributes: user_speed_grade
pre_elab_script
preferred_comp
preserve_techelts
Syntax
preserve_techelts {false | true | const_prop_delete_ok | const_prop_size_delete_ok |
delete_ok | map_size_ok | size_ok | size_delete_ok}
Applies to:
hdl_implementation
Description
Default:
Data_type: string, read/write
Determines how to optimize the technology cells that are explicitly instantiated in the synthesis
model of the specified ChipWare implementation.
You can specify one of the following values:
const_prop_delete_ok Allows deleting the technology cells, and allows constant
propagation through the technology cells, but does not allow
resizing, renaming or remapping them.
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ChipWare--report_as_datapath
const_prop_size_delete_ok Allows deleting and resizing the technology cells and allows
constant propagation through them, but does not allow renaming
or remapping. them
delete_ok Allows the technology cells to be deleted during optimization, but
does not allow resizing, renaming, or remapping them.
false Allows changes to all the technology cells in the synthesis model
during optimization.
map_size_ok Allows resizing, unmapping, and remapping of the technology
cells, but not renaming or deleting them.
size_delete_ok Allows resizing or deleting of the technology cells during
optimization, but not renaming or remapping them.
size_ok Allows resizing of the technology cells during optimization, but
not deleting, renaming, or remapping them.
true Prevents logic changes to the technology cells during
optimization.
report_as_datapath
Syntax
report_as_datapath {false | true}
Applies to:
hdl_component
Description
Default: false
Data_type: bool, read/write
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ChipWare--selected_impl
When set to true, the ChipWare component represented by this attribute is considered a datapath
component, and it will be included in the datapath report generated by the report_dp command.
When set to false, this ChipWare component will not be included in the datapath report.
Regarding ChipWare components, this attribute is set to true by default for datapath components
and set to false by default for other components.
selected_impl
Syntax
selected_impl {impl_directory bind_name}
Applies to:
module
Description
Default:
Data_type: string, read only
Returns the implementation of the module at any stage in the synthesis flow. The returned value is
a Tcl list, where impl_directory (implementation directory) can be the name of the hdl_lib,
hdl_component, or hdl_implementation object. bind_name (binding name) is the name of the
hdl_bind object.
Related Information
Affected by this attribute: preferred_impl
Related attribute: candidate_impls
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ChipWare--signed
signed
Syntax
signed {true | false}
Applies to:
hdl_pin (read/write)
hdl_operator (read only)
Description
Default: false
Data_type: bool
Determines whether the input or output pin of a synthetic operator is a signed or unsigned pin. By
default, all inputs and outputs of a synthetic operator have the same signedness as the operator
itself. Usually, you do not need to set this attribute. However, if a particular pin has a different
signedness than the operator, you must set this attribute for that pin.
speed_grade
Syntax
speed_grade {very_slow | slow | medium| fast | very_fast | timing_driven}
Applies to:
module
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ChipWare--sub_arch
Description
Default:
Data_type: string, read only
Specifies the speed of an internal component, such as a datapath component. A component can
have several implementations with different speeds. Genus automatically determines which
implementation to choose to meet timing and area requirements.
Related Information
Affects this command: syn_generic
Affected by this attribute: user_speed_grade
sub_arch
Syntax
sub_arch {no_value | non_booth | booth | ao | barrel | radix8 | radix8_fast}
Applies to:
module
Description
Default:
Data_type: enum, read only
Returns the partial product encoding scheme (non_booth/booth/radix8/radix8_fast) that the tool
used for a particular multiplier component and the scheme (ao/barrel) that the tool used for a
particular shifter component.
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ChipWare--technology
Related Information
Affects this command: syn_generic
Affected by this attribute: user_sub_arch
technology
Syntax
technology <library_name>
Applies to:
hdl_implementation
Description
Default:
Data_type: string, read/write
Specifies the name of a technology library, if the specified architecture (implementation) is
technology-specific. The value should be a null string if it is technology-neutral.
unbound_oper_pin
Syntax
unbound_oper_pin <unbound_setting>
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ChipWare--user_speed_grade
Applies to:
hdl_bind
Description
Default:
Data_type: string, read/write
Specifies the unbound setting. The unbound setting is a set of constant values that can be given to
the input pins of the synthetic operator. The input pins cannot already be mapped to signals in an
HDL subprogram that specifies the synthetic operator through the map_to_operator pragma.
user_speed_grade
Syntax
user_speed_grade {very_slow | slow | medium| fast | very_fast}
Applies to:
module
Description
Default:
Data_type: string, read/write
Allows you to choose a fixed implementation of an internal Genus component, such as a datapath
component. A component can have several implementations with different speeds. Genus
automatically determines which implementation to choose to meet timing and area requirements,
but this attribute allows you to choose a different implementation.
Set this attribute only on datapath modules inferred by Genus.
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ChipWare--user_sub_arch
Related Information
Affects these commands: syn_generic
syn_map
Affects this attribute: speed_grade
user_sub_arch
Syntax
user_sub_arch {no_value | non_booth | booth | ao | barrel | radix8 | radix8_fast}
Applies to:
module
Description
Default:
Data_type: enum, read/write
Controls the partial product encoding scheme (non_booth/booth/radix8/radix8_fast) that you want
the tool to use for a multiplier, which affects the number of partial products generated and the
scheme (ao/barrel) that you want the tool to use for a shifter.
Related Information
Affects this command: syn_generic
Affects this attribute: sub_arch
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Library Attributes
11
Library Attributes
The chapter describes the attributes of the following object types:
Additional Attributes for Library All Attributes for Library base_cell_set Attributes for Library
base_cell Attributes for Library base_pin Attributes for Library internal_power
is_backside level_shifter_group Attributes for Library lib_arc Attributes for Library
lib_cell Attributes for Library lib_pin Attributes for Library library Attributes for Library
operating_condition Attributes for Library pg_base_pin Attributes for Library pg_lib_pin Attributes for Library
pin Attribute for Library root Attributes for Library seq_function Attribute for Library
wireload_selection Attribute for Library wireload Attributes for Library
See also:
avoid
direction
is_level_shifter
is_retention
leakage_power
preserve
type
Additional Attributes for Library
Additional attributes are:
bit_width
default
is_buffer
is_flop
is_inverter
is_latch
All Attributes for Library
constraint_high corresponding_q_or_qn_pin dont_merge_multibit
dont_split_multibit is_auto_library_domain is_synchronizer
is_usable leakage_power_scale_in_nW lib_cell
library_domain library_side_file merge_multibit
power_library sync_enable_pins timing_model_reason
tristate unusable_reason via_variation_file
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Library Attributes--Additional Attributes for Library
voltage
constraint_high
Syntax
constraint_high <float>
Applies to:
lib_arc
Description
Default:
Data_type: double, read only
Defines the constraint high value specified for the timing arc.
corresponding_q_or_qn_pin
Syntax
corresponding_q_or_qn_pin <string>
Applies to:
lib_pin
Description
Default:
Data_type: pg_lib_pin | lib_pin, read only
Returns the q pin of a qn pin or vice-versa..
dont_merge_multibit
dont_merge_multibit {false | true}
Default: false
Read-write inst attribute. Controls whether the instance should be avoided during multibit merging.
As shown in the following table, the tool only avoids multibit merging for the instance when the merge_multibit for this instance is not set.
dont_merge_multibit merge_multibit Multibit merging is
false false attempted if use_multibit_cells is set to true.
false true attempted.
true false not attempted.
true true attempted. The dont_merge_multibit attribute setting is ignored.
This attribute applies only to sequential and tristate instances.
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Library Attributes--Additional Attributes for Library
Related Information
Affects this command: syn_opt
Affected by this attribute: merge_multibit
Related attribute: use_multibit_cells
dont_split_multibit
dont_split_multibit {false | true}
Default: false
Read-write inst attribute. Controls whether the multibit cell used for this instance can be split during incremental optimization.
Related Information
Affects this command: syn_opt
Related attribute: use_multibit_cells
is_auto_library_domain
Syntax
is_auto_library_domain {false | true}
Applies to:
library_domain
Description
Default: false
Data_type: bool, read only
Indicates whether library domain is created in auto-library-domain flow.
is_synchronizer
Syntax
is_synchronizer {true | false}
Applies to:
base_cell
hinst
inst
lib_cell
Description
Default: false
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Library Attributes--Additional Attributes for Library
Data_type: bool, read only
Returns if the selected is a synchronizer. Library cell with back to back connected flops is considered a synchronizer.
is_usable
Syntax
is_usable {true | false}
Applies to:
lib_cell
Description
Default: true
Data_type: bool, read only
Indicates if the lib_cell can be used during mapping or incremental optimization.
If the tool cannot infer the lib_cell, or the lib_cell cannot be used during mapping or incremental optimization, this attribute will be set to false.
Even when the avoid attribute can indicate that a lib_cell can be used for mapping or optimization, the tool can consider the lib_cell not to be usable, for
example because the function or timing is too complex.
Related Information
Affects this attribute: avoid
leakage_power_scale_in_nW
Syntax
leakage_power_scale_in_nW <float>
Applies to:
library
Description
Default:
Data_type: double, read only
Returns the scaling factor used to compute the cell leakage power in the library. This attribute is determined by the value of the leakage_power_unit attribute
defined in the Liberty library.
If the leakage_power_unit in the Liberty library is 10 pW, then this value is 0.01.
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Library Attributes--Additional Attributes for Library
Related Information
Affects these commands: report_gates
report_power
Affects this attribute: leakage_power
lib_cell
Syntax
lib_cell lib_cell
Applies to:
lib_arc
lib_pin
pg_lib_pin
seq_function
Description
Default:
Data_type: lib_cell, read only
Object Description
lib_arc Returns the lib_cell that this library timing arc is associated with.
lib_pin Returns the lib_cell that this pin belongs to.
pg_lib_pin Returns the lib_cell that this library pin belongs to.
seq_function Returns the lib_cell that this sequential function is associated with.
library_domain
Syntax
library_domain <domain>
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Library Attributes--Additional Attributes for Library
Applies to:
Object Default Data_type
design string, read/write
hdl_architecture string, read/write
hinst string, read/write
inst string, read/write
module string, read/write
power_domain {} string, read/write
Description
Object
design Sets the target library domain for technology mapping. During mapping only library cells from libraries in the target domain can be
used. If you do not set this attribute explicitly on the design, Genus will (during elaboration) choose for each module the library domain
that minimizes the number of blackboxes. You can modify as needed after elaboration.
The order in which you set the library_domain attributes on the design and modules matters! You must set the library domain of
the design first. The design attribute applies hierarchically to all instances and modules of this design.
You cannot set this attribute, if the design is marked preserved.
hdl_architecture Sets the target library domain for technology mapping of the specified architecture. During mapping only library cells from libraries
in the target domain can be used.
This attribute is not hierarchical. It only applies to the specified architecture.
hinst Identifies the library domain to use for the mapping of this hierarchical instance. You can only set this attribute on a timing model
instance.
inst Identifies the library domain to use for the mapping of this instance. You can only set this attribute on a timing model instance.
module Sets the target library domain for technology mapping of the specified module. During mapping only library cells from libraries in the
target domain can be used. By default, a module inherits the library domain setting from its parent module or design.
The order in which you set the library_domain attributes on the design and modules matters! You must set the library domain of
the design first. The design attribute applies hierarchically to all instances and modules of this design.
You cannot set this attribute, if the design is marked preserved.
power_domain Specifies the library domain to be used to optimize or analyze this power domain.
In the CPF flow, this attribute is automatically set for the default power mode.
Related Information
Affected by this command: read_power_intent
Related attribute: default
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Library Attributes--Additional Attributes for Library
library_side_file
Syntax
library_side_file <file>
Applies to:
library_set
Description
Default:
Data_type: string, read only
Returns the name of the library specified with the '-library_side_file' option of the 'create_library_set' command.
Example
The following command turns off RTL sharing transformations:
genus@root:> get_db library_set:wcl_slow .library_side_file
Related Information
Set by this command: create_library_set
merge_multibit
merge_multibit {false | true}
Default: false
Read-write inst attribute. Controls whether the instance can be considered for multibit merging. If set, the instance can be considered.
The following table shows when the tool considers multibit merging for the instance:
dont_merge_multibit merge_multibit Multibit merging is
false false attempted if use_multibit_cells is set to true.
false true attempted.
true false not attempted.
true true attempted. The dont_merge_multibit attribute setting is ignored.
This attribute applies only to sequential and tristate instances.
Related Information
Affects this command: syn_opt
Affected by this attribute: dont_merge_multibit
Related attribute: use_multibit_cells
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Library Attributes--Additional Attributes for Library
power_library
Syntax
power_library <domain>
Applies to:
library_domain
Description
Default:
Data_type: library_domain, read/write
Specifies the name of the library domain with which the libraries to be used for power analysis are associated.
sync_enable_pins
Syntax
sync_enable_pins (lib_pins | pg_lib_pins}
Applies to:
lib_cell
Description
Default:
Data_type: pg_lib_pin* | lib_pin*, read only
Returns the path to the library pin(s) that corresponds to the synchronous enable pin(s) of this library cell.
An empty string indicates that this library cell either is not a flip-flop cell, or has no synchronous enable pin.
timing_model_reason
Syntax
timing_model_reason <string>
Applies to:
lib_cell
Description
Default:
Date_type: string, read only
Returns the reason why the library cell is considered a timing model.
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Library Attributes--Additional Attributes for Library
tristate
tristate {true | false}
Read-only inst attribute. Indicates if the instance has a tristate output pin.
Related Information
Related attribute: (lib_cell) tristate
unusable_reason
Syntax
unusable_reason <string>
Applies to:
lib_cell
Description
Default:
Date_type: string, read only
Returns the reason why the library cell is considered unusable.
Related Information
Related attribute: is_usable
via_variation_file
Syntax
via_variation_file <file>
Applies to:
rc_corner
Description
Default:
Data_type: string, read only
Returns the name of the via_variation file specified with the '-via_variation_file' option of the 'create_rc_corner' command.
Example
The following command turns off RTL sharing transformations:
genus@root:> get_db rc_corner:wc_rcc .via_variation_file
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Library Attributes--Additional Attributes for Library
Related Information
Set by this command: create_rc_corner
voltage
Syntax 1
voltage <float>
Applies to:
opcond
operating_condition
specialnet
Description
Default:
Data_type: double, read only (opcond, specialnet), read/write (operating_condition)
Object Description
opcond Returns the voltage of the opcond.
operating_condition Specifies the operating voltage.
This attribute is useful when tracking down timing discrepancies between different
tools. A common source of timing discrepancies is caused by differences in the
technology library files. If the voltage is missing, Genus defaults to the nominal voltage.
If the nominal voltage value is missing, Genus defaults to 1.0V.
specialnet Returns the voltage of the specialnet.
Related Information
Set by this command (object - specialnet): read_def
Set by this command (object - opcond): create_opcond
Syntax 2
voltage <voltage_list>
Applies to:
nominal_condition
timing_point
Description
Default:
Data_type: string, read only (timing_point), read/write (nominal_condition)
Object Description
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Library Attributes--base_cell_set Attributes for Library
nominal_condition Returns the supply voltage(s) for this nominal condition. This value corresponds to the value specified for -voltage option of the
create_nominal_condition CPF command specified for this nominal condition. The list can contain up to three voltages: minimum,
nominal, and maximum voltages. The list must contain increasing values.
You cannot assign any other voltage to a nominal condition with voltage 0.
timing_point
Related Information
create_nominal_condition in the Common Power Format Language Reference.
Affected by this command: read_power_intent
base_cell_set Attributes for Library
base_cells
orig_base_cells
base_cells
base_cells list_of_lib_cells
Read-only base_cell_set attribute. Returns the lib_cells that belong to this lib set.
orig_base_cells
orig_base_cells list_of_lib_cells
Read-only base_cell_set attribute. Returns the user-defined base_cells that belong to this lib set.
base_cell Attributes for Library
area
base_class
base_pins
bottom_padding
class
dont_touch
dont_use
integrated_clock_gating_type
is_always_on
is_black_box
is_combinational
is_eeq_cell
is_fall_edge_triggered
is_inferred_macro
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Library Attributes--base_cell_set Attributes for Library
is_interface_timing
is_iso_nor
is_macro
is_master_slave_flop
is_master_slave_lssd_flop
is_memory
is_negative_level_sensitive
is_pad
is_physical_defined
is_pll
is_positive_level_sensitive
is_power_on_bottom
is_power_switch
is_rise_edge_triggered
is_sequential
is_timing_defined
is_timing_model
is_tristate
left_padding
level_shifter_type
lib_cells
library_set
master_physical_variant_cell
num_base_pins
pg_base_pins
physical_variant_cells
right_padding
symmetry
timing_model_type
top_padding
area
area float
Read-write base_cell attribute. Specifies the area of the base_cell in the technology library. You can only overwrite this area for synthesis when the
interconnect_mode design attribute is set to wireload.
Related Information
Affects these commands: report_area
report_gates
Related attribute (lib_cell) area
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Library Attributes--base_cell_set Attributes for Library
base_class
base_class {none | block | core | corener | cover | pad}
Read-only base_cell attribute. Returns the base_class of the cell as defined in the LEF library.
base_pins
base_pins list_of_base_pins
Read-only base_cell attribute. Returns the list of base_pin objects.
bottom_padding
bottom_padding integer
Default: 0
Read-write base_cell attribute. Returns the bottom padding of the base_cell.
class
class string
Read-only base_cell attribute. Returns the class of the cell as defined in the LEF library.
Possible values are: none, block, block_blackbox, block_ring, block_soft, core, core_antenna, core_endcap_post, core_endcap_pre, core_feedthru,
core_spacer, core_tie_high, core_tie_low, core_welltap, corner_bottom_left, corner_bottom_right, corner_top_left, corner_top_right, cover,
cover_bump, pad, pad_area_io, pad_inout, pad_input, pad_output, pad_power, pad_spacer
Related Information
Affects these commands: report_area
report_gates
Related attribute (lib_cell) class
dont_touch
dont_touch {false | true}
Read-write base_cell attribute. Controls whether instances of this cell should be preserved during optimization.
Related Information
Related attribute: (lib_cell) dont_touch
dont_use
dont_use {false |true}
Read-write base_cell attribute. Controls whether the cell can be used during optimization.
Related Information
Related attribute: (lib_cell) dont_use
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Library Attributes--base_cell_set Attributes for Library
integrated_clock_gating_type
integrated_clock_gating_type string
Read-only base_cell attribute. Describes the functionality of the integrated clock-gating cell: type of sequential cell, whether the cell is appropriate for positive
or negative-edge triggered registers, whether the test control logic is located before or after the latch or flip-flop, or does not exist, and whether the cell contains
observability logic or not.
An empty string indicates that the cell is not an integrated clock-gating cell.
Related Information
Clock-Gating Cell Specification in Genus Library Guide.
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: (lib_cell) clock_gating_integrated_cell
lp_clock_gating_add_obs_port
lp_clock_gating_control_point
lp_clock_gating_style
is_always_on
is_always_on {false | true}
Default: false
Read-write base_cell attribute. Specifies whether the lib_cell is an always-on cell.
Related Information
Related attribute: (lib_cell) is_always_on
is_black_box
is_black_box {true | false}
Read-only base_cell attribute. Indicates if the base_cell is a blackbox.
This cell either has no .lib definition or has a .lib definition but no timing_arcs. In either case, timing analysis cannot propagate through this cell.
Related Information
Related attributes: (inst) is_black_box
(lib_cell) is_black_box
is_combinational
is_combinational {false | true}
Read-only base_cell attribute. Indicates if the base_cell is a combinational cell.
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Related Information
Related attributes: (inst) is_combinational
(lib_cell) combinational
is_eeq_cell
is_eeq_cell {false | true}
Read-only base_cell attribute. Specify to check whether the library cell is EEQ or physical variant defined cell.
is_fall_edge_triggered
is_fall_edge_triggered
Read-only base_cell attribute. Indicates whether the base_cell has a falling clock.
Related Information
Related attribute: (lib_cell) is_fall_edge_triggered
is_inferred_macro
is_inferred_macro {false| true}
Read-only base_cell attribute. Indicates whether the base_cell is inferred as a macro cell. This applies
in case of pad cells
in case of timing models (other than cgic cells)
in case that output function is not set
in case the cell is only a physical cell
Related Information
Related attribute: (lib_cell) is_inferred_macro
is_interface_timing
is_interface_timing {false | true}
Read-only base_cell attribute. Indicates whether the base_cell has the interface_timing Liberty cell attribute.
Related Information
Related attributes: (inst) is_interface_timing
(lib_cell) is_interface_timing
is_iso_nor
is_iso_nor {false | true}
Default: false
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Library Attributes--base_cell_set Attributes for Library
Read-write base_cell attribute. Indicates whether the base_cell is an 'ISONOR' cell based on the constructs specified on library.
is_macro
is_macro {false | true}
Default: false
Read-only base_cell attribute. Indicates whether this base_cell is a macro cell.
Related Information
Related attributes: (inst) is_macro
(lib_cell) is_macro
is_master_slave_flop
is_master_slave_flop {false | true}
Read-only base_cell attribute. Indicates if the base_cell is a master-slave flip-flop.
Related Information
Related attributes: (lib_cell) is_master_slave_flop
is_master_slave_lssd_flop
is_master_slave_lssd_flop {false | true}
Read-only base_cell attribute. Indicates if the base_cell is a master-slave LSSD flip-flop.
Related Information
Related attributes: (inst) is_master_slave_lssd_flop
(lib_cell) is_master_slave_lssd_flop
is_memory
is_memory {false | true}
Read-only base_cell attribute. Indicates whether this base_cell is a memory.
Related Information
Related attributes: (inst) is_memory
is_negative_level_sensitive
is_negative_level_sensitive {false | true}
Read-only base_cell attribute. Indicates whether the base_cell is negative level-sensitive.
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Library Attributes--base_cell_set Attributes for Library
Related Information
Related attribute: (lib_cell) is_negative_level_sensitive
is_pad
is_pad {false | true}
Read-only base_cell attribute. Indicates if the base_cell is a pad cell.
The attribute value will be set to true if the cell has a corresponding cell in the LEF library defined as CLASS PAD.
Related Information
Related attributes: (inst) is_pad
(lib_cell) is_pad
is_physical_defined
is_physical_defined {false | true}
Read-only base_cell attribute. Indicates whether the base_cell is only defined in the LEF library.
Related Information
Related attribute: (lib_cell) is_pll
is_pll
is_pll {false | true}
Read-only base_cell attribute. Indicates whether the base_cell has unknown internal functionality.
Related Information
Related attribute: (lib_cell) is_pll
is_positive_level_sensitive
is_positive_level_sensitive {false | true}
Read-only base_cell attribute. Indicates whether the base_cell is positive level-sensitive.
Related Information
Related attribute: (lib_cell) is_positive_level_sensitive
is_power_on_bottom
is_power_on_bottom {false | true}
Default: false
Read-only base_cell attribute. Indicates if the standard cell has a power pin along the bottom of the cell.
This is derived from the power and ground pin information in the cell. It is used by the placer to align multi-height cells properly to the rows. It is not meaningful
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Library Attributes--base_cell_set Attributes for Library
for non-standard cells.
is_power_switch
is_power_switch {false | true}
Read-only base_cell attribute. Indicates if the base_cell is a power swicth cell.
Related Information
Related attribute: (lib_cell) is_power_switch
is_rise_edge_triggered
is_rise_edge_triggered {false | true}
Read-only base_cell attribute. Indicates whether the base_cell has a rising clock.
Related Information
Related attribute: (lib_cell) is_rise_edge_triggered
is_sequential
is_sequential {false | true}
Read-only base_cell attribute. Indicates if the base_cell is a sequential cell
Related Information
Related attributes: (inst) is_sequential
(lib_cell) sequential
is_timing_defined
is_timing_defined {false | true}
Read-only base_cell attribute. Indicates if the base_cell has timing information.
is_timing_model
is_timing_model {false | true}
Read-only base_cell attribute. Indicates if the internal functionality of the base_cell is unknown.
Related Information
Related attributes: (lib_cell) is_timing_model
timing_model_reason
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Library Attributes--base_cell_set Attributes for Library
is_tristate
is_tristate {true | false}
Read-only base_cell attribute. Indicates if the base_cell has at least one tristate output.
Related Information
Related attributes: (inst) is_tristate
(lib_cell) is_tristate
left_padding
left_padding integer
Read-write base_cell attribute. Returns the left padding of the base_cell.
Related Information
Related attribute: (lib_cell) left_padding
level_shifter_type
level_shifter_type {LH | HL | HL_LH}
Read-only base_cell attribute. Returns the value of the Liberty level_shifter_type attribute or the supported voltage conversion by the level shifter cell. Valid
values for a level shifter are:
LH—Low to High
HL—High to Low
HL_LH—High to Low and Low to High.
The attribute value can be null if this library cell is not a level shifter, or if the level shifter does not have the level_shifter_type base_cell attribute in
the Liberty library. In the latter case, the default type for the level shifter is HL_LH.
Related Information
Related attribute: (lib_cell) level_shifter_type
lib_cells
lib_cells list_of_lib_cells
Read-only base_cell attribute. Returns the list of lib_cells that have this base_cell.
Related Information
Related attributes: (library) lib_cells
library_set
library_set set_of_libraries
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Library Attributes--base_cell_set Attributes for Library
Read-only base_cell attribute. Displays the library set of the specified library.
Example
The following example returns the library set for the library LS_2/scalar.
get_db library:LS_2/scalar .library_set
master_physical_variant_cell
master_physical_variant_cell base_cell
Read-only base_cell attribute. Returns the master cell, which stores the complete description of all the child physical variant cells.
Related Information
Related attributes (lib_cell) master_physical_variant_cell
(base_cell) physical_variant_cells
(lib_cell) physical_variant_cells
num_base_pins
num_base_pins integer
Read-only base_cell attribute. Returns the number of logical pins that the base_cell has.
Related Information
Related attribute: (lib_cell) num_base_pins
pg_base_pins
pg_base_pins list_of_pg_pins
Read-only base_cell attribute. Returns the list of pg_pins that the base_cell has.
Related Information
Related attribute: (lib_cell) pg_lib_pins
physical_variant_cells
physical_variant_cells list_of_base_cell
Read-only base_cell attribute. Returns the list of physical variant cells of the master cell where it is defined.
Related Information
Related attributes: (lib_cell) physical_variant_cells
(base_cell) master_physical_variant_cell
(lib_cell) master_physical_variant_cell
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Library Attributes--base_pin Attributes for Library
right_padding
right_padding integer
Read-write base_cell attribute. Returns the right padding of the base_cell.
Related Information
Related attribute: (lib_cell) right_padding
symmetry
symmetry string
Read-only base_cell attribute. Returns the symmetry info of the base_cell. Valid values are r, x, y, xy, and rxy, where
r—Indicates that the cell is symmetrical in 90 degree counterclockwise rotation
x—Indicates that the cell is symmetrical about the x-axis
y—Indicates that the cell is symmetrical about the y-axis
Related Information
Related attribute: (lib_cell) symmetry
timing_model_type
timing_model_type string
Read-only base_cell attribute. Returns the value of the base_cell timing_model_type attribute.
top_padding
top_padding integer
Default: 0
Read-write base_cell attribute. Returns the top padding of the base_cell.
base_pin Attributes for Library
base_cell
is_always_on
is_analog
is_async
is_isolated
is_isolation_cell_clock
is_isolation_cell_data
is_isolation_cell_enable
is_level_shifter_enable
is_power_switch_enable
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Library Attributes--base_pin Attributes for Library
is_retention_cell_enable
is_unconnected
pg_type
related_ground_pin
related_power_pin
restore_action
restore_edge_type
save_action
tied_to
use
base_cell
base_cell object
Read-only base_pin attribute. Returns the base_cell that this base_pin belongs to.
Related Information
Related attributes: (lib_cell) base_cell
(pg_base_pin) base_cell
is_always_on
is_always_on {false | true}
Default: false
Read-write base_pin attribute. Indicates if this base_pin is an always-on pin on an always-on cell.
Related Information
Related attributes: (lib_pin) is_always_on
(pg_lib_pin) is_always_on
is_analog
is_analog {false| true}
Default: false
Read-write base_pin attribute. Identifies an analog signal pin as analog so it can be recognized by the tools.
Related Information
Related attribute: (lib_pin) is_analog
is_async
is_async {false| true}
Read-only pg_lib_pin attribute. Indicates whether this pin is an asynchronous pin.
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Related Information
Related attribute: (lib_pin) is_async
is_isolated
is_isolated {false| true}
Read-only base_pin attribute. Indicates if this pin is internally isolated and does not require the insertion of an external isolation cell.
Related Information
Related attributes: (lib_pin) is_isolated
(pg_lib_pin) is_isolated
is_isolation_cell_clock
is_isolation_cell_clock {false | true}
Default: false
Read-only base_pin attribute. Clock pin of a clock isolation cell.
Related Information
Related attributes: (lib_pin) is_isolation_cell_clock
(pg_lib_pin) is_isolation_cell_clock
is_isolation_cell_data
is_isolation_cell_data {false | true}
Default: no_value
Read-only base_pin attribute. Returns a value of true if the Liberty library is_isolation_cell_data attribute is set to true for lib_pin.
Related Information
Related Attributes: (lib_pin) is_isolation_cell_data
(pin) is_isolation_cell_data
is_isolation_cell_enable
is_isolation_cell_enable {false | true}
Default: false
Read-write base_pin attribute. Indicates if this pin is the enable pin of an isolation cell.
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Library Attributes--base_pin Attributes for Library
Related Information
Related attributes: is_isolation_cell
(lib_pin) is_isolation_cell_enable
(pg_lib_pin) is_isolation_cell_enable
is_level_shifter_enable
is_level_shifter_enable {false | true}
Default: false
Read-write base_pin attribute.Indicates if this pin is the enable pin of a level shifter cell.
Related Information
Related attributes: (lib_pin) is_level_shifter_enable
(pg_lib_pin) is_level_shifter_enable
is_power_switch_enable
is_power_switch_enable {false | true}
Default: false
Read-write base_pin attribute. Indicates if this pin is the enable pin of an isolation cell.
Related Information
Related attribute: (lib_pin) is_power_switch_enable
is_retention_cell_enable
is_retention_cell_enable {false | true}
Read-only base_pin attribute. Indicates if this pin is the retention pin of a lib cell.
Related Information
Related attributes: (lib_pin) is_level_shifter_enable
is_unconnected
is_unconnected {false| true}
Read-only lib_pin attribute. Indicates whether the lib pin is connected.
Related Information
Related attributes: (lib_pin) is_unconnected
(pg_lib_pin) is_unconnected
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Library Attributes--base_pin Attributes for Library
pg_type
pg_type string
Read-write base_pin attribute. Specifies the pg_type info of the pin. This corresponds to the value of the pg_type Liberty pin attribute.
Related Information
Related attributes: (lib_pin) pg_type
(pg_base_pin) pg_type
(pg_lib_pin) pg_type
related_ground_pin
related_ground_pin (lib_pins|pg_lib_pins}
Read-only base_pin attribute. Associates a predefined ground pin with the specified base_pin.
Related Information
Related attribute: (lib_pin) related_ground_pin
related_power_pin
related_power_pin (lib_pins|pg_lib_pins}
Read-only base_pin attribute. Associates a predefined power pin with the specified base_pin.
Related Information
Related attribute: (lib_pin) related_power_pin
restore_action
restore_action string
Default: no value
Read-only base_pin attribute. Returns the restore_action information of the lib pin.
restore_edge_type
restore_edge_type string
Default: no value
Read-only base_pin attribute. Returns the restore_edge_type information of the lib pin.
save_action
save_action string
Default: no value
Read-only base_pin attribute. Returns the save_action information of the base pin.
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Library Attributes--internal_power
tied_to
tied_to string
Read-only base_pin attribute. Returns the value to which the power or ground pin is tied.
Related Information
Related attribute: (lib_pin) tied_to
(pg_base_pin) tied_to
(pg_lib_pin) tied_to
use
use {signal | analog | clock | ground | power}
Read-only base_pin attribute. Returns the use of the base_pin. If the cell was read from a library in Liberty format, the use will be signal. If a LEF library is read
later, the value of this attribute might change if the pin’s use was defined through the USE statement in the LEF library.
Related Information
Related attributes: lef_library
library
(lib_pin) use
(pg_lib_pin) use
internal_power
Syntax
internal_power <float>
Applies to:
lib_cell
Description
Default:
Data_type: double, read/write
Specifies the internal power of the cell. The unit of the power value is determined by the value of the lp_power_unit attribute.
By default, the internal cell power is derived from the power tables in the library. When you overwrite the internal cell power, the tool issues a warning message.
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Library Attributes--is_backside
Related Information
Affects these commands: report_gates
report_power
syn_generic
syn_map
syn_opt
Related attribute: lp_power_unit
is_backside
Syntax
is_backside {true | false}
Applies to:
lib_pin
pg_lib_pin
pin
Description
Default: false (lib_pin, pg_lib_pin)
Data_type: bool, read only
Indicates if the lib_pin/pg_lib_pin/pin is on a backside routing layer.
level_shifter_group Attributes for Library
ground_direction
level_shifter_cells
max_ground_input_voltage
max_ground_output_voltage
max_input_voltage
max_output_voltage
min_ground_input_voltage
min_ground_output_voltage
min_input_voltage
min_output_voltage
valid_location
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Library Attributes--is_backside
ground_direction
ground_direction {up | down | bidir}
Read-only level_shifter_group attribute. Specifies the direction in which this group of ground level shifters can shift the ground voltage.
up indicates that the level shifters connect from a lower voltage domain to a higher voltage domain.
down indicates that the level shifters connect from a higher voltage domain to a lower voltage domain.
bidir indicates that the direction of the level shifters can be up or down.
Related Information
Affected by this command: read_power_intent
level_shifter_cells
level_shifter_cells string
Read-only level_shifter_group attribute. Returns the list of library cells in this group that can be used as level shifters between the voltages specified in the
min_input_voltage (and max_input_voltage) and the min_output_voltage (and max_output_voltage) attributes.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
max_ground_input_voltage
max_ground_input_voltage float
Read-only level_shifter_group attribute. Returns the maximum voltage for the input (source) ground supply voltage that can be handled by this level shifter.
This attribute only applies to ground level shifters.
Related Information
Affected by this command: read_power_intent
Related attributes: (lib_cell) max_ground_input_voltage
(level_shifter_group) min_ground_input_voltage
(lib_cell) min_ground_input_voltage
max_ground_output_voltage
max_ground_output_voltage float
Read-only level_shifter_group attribute. Returns the maximum voltage for the output (destination) ground supply voltage that can be handled by this level
shifter.
This attribute only applies to ground level shifters.
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Library Attributes--is_backside
Related Information
Affected by this command: read_power_intent
Related attributes: (lib_cell) max_ground_output_voltage
(level_shifter_group) min_ground_output_voltage
(lib_cell) min_ground_output_voltage
max_input_voltage
max_input_voltage float
Read-only level_shifter_group attribute. Specifies the upper bound of the voltage range (in volt) that can be handled by the level shifter for the source
domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
Related attribute: (lib_cell) max_input_voltage
max_output_voltage
max_output_voltage float
Read-only level_shifter_group attribute. Specifies the upper bound of the voltage range (in volt) that can be handled by the level shifter for the destination
domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
Related attribute: (lib_cell) max_output_voltage
min_ground_input_voltage
min_ground_input_voltage float
Read-only level_shifter_group attribute. Returns the minimum voltage for the input (source) ground supply voltage that can be handled by this level shifter.
This attribute only applies to ground level shifters.
Related Information
Affected by this command: read_power_intent
Related attributes: (lib_cell) min_ground_input_voltage
(level_shifter_group) max_ground_input_voltage
(lib_cell) max_ground_input_voltage
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Library Attributes--is_backside
min_ground_output_voltage
min_ground_output_voltage float
Read-only level_shifter_group attribute. Returns the minimum voltage for the output (destination) ground supply voltage that can be handled by this level
shifter.
This attribute only applies to ground level shifters.
Related Information
Affected by this command: read_power_intent
Related attributes: (lib_cell) min_ground_output_voltage
(level_shifter_group) max_ground_output_voltage
(lib_cell) max_ground_output_voltage
min_input_voltage
min_input_voltage float
Read-only level_shifter_group attribute. Specifies the lower bound of the voltage range (in volt) that can be handled by the level shifter for the source domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
Related attribute: (lib_cell) min_input_voltage
min_output_voltage
min_output_voltage float
Read-only level_shifter_group attribute. Specifies the lower bound of the voltage range (in volt) that can be handled by the level shifter for the destination
domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
Related attribute: (lib_cell) min_output_voltage
valid_location
valid_location {from|to|on|off|either|any}
Read-only level_shifter_group attribute. Specifies where the level shifters must be placed.
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Library Attributes--lib_arc Attributes for Library
Related Information
define_level_shifter_cell in the Common Power Format Language Reference.
Affected by this command: read_power_intent
Related attribute: (lib_cell) level_shifter_valid_location
lib_arc Attributes for Library
drive_resistance_fall
drive_resistance_rise
enabled
from_lib_pin
is_disabled
liberty_attributes
mode
real_enabled
sdf_cond
sdf_conf
sense
timing_type
to_lib_pin
when
drive_resistance_fall
drive_resistance_fall float
Read-only lib_arc attribute. Returns the driving resistance of the cell for falling transistions.
drive_resistance_rise
drive_resistance_rise float
Read-only lib_arc attribute. Returns the driving resistance of the cell for rising transistions.
enabled
enabled {true | false}
Default: true
Read-write lib_arc attribute. Generally, all timing arcs (lib_arcs) defined in the library are valid. Using this attribute you can disable one or more timing arcs of a
particular cell in the design, or re-enable a previously disabled arc.
Related Information
Affected by this attribute: real_enabled
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Library Attributes--lib_arc Attributes for Library
from_lib_pin
from_lib_pin {lib_pin | pg_lib_pin}
Read-only lib_arc attribute. Specifies the lib_pin from where this timing path originated.
is_disabled
is_disabled {true | false}
Default: true
Read-write lib_arc attribute. Specifies whether this library timing arc is disabled by the user.
Related Information
Affected by this attribute: real_enabled
liberty_attributes
liberty_attributes string
Read-only lib_arc attribute. Returns a list of Liberty attributes and values that were specified for this timing arc in the library.
Related Information
Related attributes: (library) liberty_attributes
(lib_cell) liberty_attributes
(lib_pin) liberty_attributes
(operating_condition) liberty_attributes
(pg_lib_pin) liberty_attributes
(wireload) liberty_attributes
mode
mode string
Read-only lib_arc attribute. Returns the mode to which this timing arc applies.
real_enabled
real_enabled {true | false}
Read-only lib_arc attribute. Represents the enabling of the timing arc internally.
Even when the enabled attribute indicates that the timing arc is enabled, the tool can consider it otherwise.
Related Information
Affects this attribute: enabled
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Library Attributes--lib_cell Attributes for Library
sdf_cond
sdf_cond string
Read-only lib_arc attribute. Defines the SDF condition for the timing arc.
sdf_conf
sdf_cond {no_value | string}
Read-only lib_arc attribute. Returns the SDF condition specified for the timing arc.
sense
sense {postive_unate | negative_unate}
Read-only lib_arc attribute. Returns the sense of the timing arc.
timing_type
timing_type string
Read-only lib_arc attribute. Defines the type of timing arc for the library.
to_lib_pin
to_lib_pin {lib_pin | pg_lib_pin}
Read-only lib_arc attribute. Specifies the lib_pin to where this timing arc is destined.
when
when string
Read-only lib_arc attribute. Specifies the condition that a timing arc depends on to activate a path.
lib_cell Attributes for Library
area
area_multiplier
async_clear_pins
async_preset_pins
backup_power_pins
base_cell
bottom_padding
cell_delay_multiplier
cell_min_delay_multiplier
class
clock_pins
combinational
congestion_avoid
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Library Attributes--lib_cell Attributes for Library
constraint_multiplier
data_pins
dont_touch
dont_use
failure_probability
has_lvf
has_non_seq_setup_arc
height
integrated_clock_gating_type
is_adder
is_always_on
is_black_box
is_clock_isolation_cell
is_combinational
is_dummy_scmr_iw_cell
is_eeq_cell
is_fall_edge_triggered
is_inferred_macro
is_interface_timing
is_isolation_cell
is_macro
is_master_slave_flop
is_master_slave_lssd_flop
is_memory
is_negative_level_sensitive
is_pad
is_pll
is_positive_level_sensitive
is_power_switch
is_retention_cell
is_rise_edge_triggered
is_sequential
is_timing_model
is_tristate
keep_as_physical
latch_enable
latch_enable_pins
leakage_scale_factor
lef_inconsistent
left_padding
level_shifter_direction
level_shifter_type
level_shifter_valid_location
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Library Attributes--lib_cell Attributes for Library
lib_arcs
lib_pins
liberty_attributes
library
master_physical_variant_cell
max_ground_input_voltage
max_ground_output_voltage
max_input_voltage
max_output_voltage
min_ground_input_voltage
min_ground_output_voltage
min_input_voltage
min_output_voltage
mode_definition
non_seq_setup_arc
num_base_pins
pg_lib_pins
physical_variant_cells
power_gating_cell
power_gating_cell_type
preserve_avoid
primary_power
required_condition
right_padding
scan_enable_pins
scan_in
scan_in_pins
scan_out
scan_out_pins
seq_functions
sequential
short
std_cell_main_rail_pin
switch_off_enables
switched_power
symmetry
sync_clear_pins
sync_preset_pins
timing_model_type
top_padding
tristate
type_changed_pin_names
usable_flop
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Library Attributes--lib_cell Attributes for Library
usable_latch
width
area
area float
Read-write lib_cell attribute. Specifies the area of the cell in the technology library. You can only overwrite this area for synthesis when the
interconnect_mode design attribute is set to wireload.
Related Information
Affects these commands: report_area
report_gates
Related attribute (base_cell) area
area_multiplier
area_multiplier float
Default: 1.0
Read-write lib_cell attribute. Specifies the area scaling factor to use for this cell. Increasing the multiplier can prevent the use of this cell during synthesis,
while specifying a number smaller than the default, can favor the use of the cell. This attribute is applied to the cell area in both the Liberty and LEF cell libraries
that are read.
Related Information
Affects these commands: report_area
report_gates
syn_map
async_clear_pins
async_clear_pins {lib_pins | pg_lib_pins}
Read-only lib_cell attribute. Returns the full path to the library pin(s) that corresponds to the asynchronous clear pin of this library cell.
The attribute can return a collection of library pins in case of a multibit lib_cell with multiple asynchronous clear pins.
An empty string indicates that this library cell is either not a sequential cell, or that the sequential cell has no asynchronous clear pin.
async_preset_pins
async_preset_pins {lib_pins | pg_lib_pins}
Read-only lib_cell attribute. Returns the full path to the library pin that corresponds to the asynchronous preset pin of this library cell.
The attribute can return a collection of library pins in case of a multibit lib_cell with multiple asynchronous preset pins.
An empty string indicates that this library cell is either not a sequential cell, or that the sequential cell has no asynchronous preset pin.
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Library Attributes--lib_cell Attributes for Library
backup_power_pins
backup_power_pins backup_power_pins
Read-only lib_cell attribute. Returns the back up power pins of the library cell. Each library pin whose pg_type attribute equals backup_power will be part of
the list.
Related Information
Related attribute: (inst) backup_power_pins
base_cell
base_cell base_cell
Read-only lib_cell attribute. Returns the base_cell for this lib_cell.
Related Information
Related attributes: (base_pin) base_cell
(pg_base_pin) base_cell
bottom_padding
bottom_padding integer
Default: 0
Read-write lib_cell attribute. Returns the bottom padding of the lib_cell.
cell_delay_multiplier
cell_delay_multiplier float
Default: 1.0
Read-write lib_cell attribute. Specifies the scaling factor for all the delay arcs of this lib_cell.
This attribute can also be set by the following SDC command:
set_timing_derate -late -data -cell_delay lib_cell_name
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
cell_min_delay_multiplier
cell_min_delay_multiplier float
Default: 1.0
Read-write lib_cell attribute. Scales the minimum delay of the lib_cell by the specified value. This scaled delay is used to compute the input delay to the
from_pin during data-to-data checking.
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Library Attributes--lib_cell Attributes for Library
This attribute can also be set by the following SDC command:
set_timing_derate -early -data -cell_delay lib_cell
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
Related attribute: (inst) disabled_arcs
class
class string
Read-only lib_cell attribute. Returns the class of the lib_cell.
Related Information
Affects these commands: report_area
report_gates
Related attribute (base_cell) class
clock_pins
clock_pins {lib_pins | pg_lib_pins}
Read-only lib_cell attribute. Returns the path to the library pins that correspond to the clock pins of this library cell.
For timing models, it returns the path to the pin which has the clock-constraints.
An empty string indicates that this library cell is not a flip-flop cell.
combinational
combinational {false | true}
Read-only lib_cell attribute. Indicates if the lib_cell is a combinational cell.
congestion_avoid
congestion_avoid {false | true}
Default: false
Read-write lib_cell attribute. Indicates whether this lib_cell should be avoided in congested regions and replaced with other available lib_cells in the library.
Related Information
Affects this command: syn_opt -incr
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Library Attributes--lib_cell Attributes for Library
constraint_multiplier
constraint_multiplier float
Default: 1.0
Read-write lib_cell attribute. Specifies the scaling factor for all the constraint arcs (setup, removal, recovery) of this lib_cell.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
data_pins
data_pins {lib_pins | pg_lib_pins}
Read-only lib_cell attribute. Returns the data pins that are used in the next_state statement of the sequential cell.
dont_touch
dont_touch {false | true}
Read-write lib_cell attribute. Controls whether instances of this cell should be preserved during optimization.
Related Information
Related attribute (base_cell) dont_touch
dont_use
dont_use {false |true}
Read-write lib_cell attribute. Controls whether the cell can be used during optimization.
Related Information
Related attribute (base_cell) dont_use
failure_probability
failure_probability float
Default: 0.0
Read-write lib_cell attribute. Specifies the probability that one instance of the cell will fail. The probability is specified as a floating point number (with double
precision) between 0.0 and 1.0.
Related Information
Set by this command: read_dfm
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Library Attributes--lib_cell Attributes for Library
has_lvf
has_lvf {false | true}
Read-only lib_cell attribute. Indicates whether the cell has LVF timing tables.
has_non_seq_setup_arc
has_non_seq_setup_arc {false | true}
Read-only lib_cell attribute. Indicates whether the cell has non-sequential setup arcs.
height
height float
Read-only lib_cell attribute. Returns the height, in microns, of the object based on the information from the physical library.
Related Information
Related attribute: (lib_cell) width
integrated_clock_gating_type
integrated_clock_gating_type string
Read-only lib_cell attribute. Describes the functionality of the integrated clock-gating cell: type of sequential cell, whether the cell is appropriate for positive or
negative-edge triggered registers, whether the test control logic is located before or after the latch or flip-flop, or does not exist, and whether the cell contains
observability logic or not.
An empty string indicates that the cell is not an integrated clock-gating cell.
Related Information
Affects this command: syn_generic
Related attributes: (base_cell) integrated_clock_gating_type
lp_clock_gating_add_obs_port
lp_clock_gating_control_point
lp_clock_gating_style
is_adder
is_adder {true |false}
Read-only lib_cell attribute. Indicates if the lib_cell is a 1-bit half adder or full adder.
is_always_on
is_always_on {false | true}
Default: false
Read-write lib_cell attribute. Specifies whether the lib_cell is an always-on cell.
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Related Information
Related attribute: (base_cell) is_always_on
is_black_box
is_black_box {false | true}
Read-only lib_cell attribute. Indicates if the base_cell is a blackbox.
This cell either has no .lib definition or has a .lib definition but no timing_arcs. In either case, timing analysis cannot propagate through this cell.
Related Information
Related attribute: (base_cell) is_black_box
(inst) is_black_box
is_clock_isolation_cell
is_clock_isolation_cell {false | true}
Read-only lib_cell attribute. Indicates if the lib_cell is a clock isolation cell.
is_combinational
is_combinational {false | true}
Read-only lib_cell attribute. Indicates if the lib_cell is a combinational cell.
Related Information
Related attribute: (base_cell) is_combinational
is_dummy_scmr_iw_cell
is_dummy_scmr_iw_cell {0 | 1 | false | true}
Default: false
Read-only lib_cell attribute. Specify whether the lib_cell is dummy std_cell_main_rail IW cell.
is_eeq_cell
is_eeq_cell {false | true}
Read-only base_cell attribute. Specify to check whether the library cell is EEQ or physical variant defined cell.
is_fall_edge_triggered
is_fall_edge_triggered
Read-only lib_cell attribute. Indicates whether the base_cell has a falling clock.
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Related Information
Related attribute: (base_cell) is_fall_edge_triggered
is_inferred_macro
is_inferred_macro {false| true}
Read-only lib_cell attribute. Indicates whether the lib_cell is inferred as a macro cell. This applies
in case of pad cells
in case of timing models (other than cgic cells)
in case that output function is not set
in case the cell is only a physical cell
Related Information
Related attribute: (base_cell) is_inferred_macro
is_interface_timing
is_interface_timing {false | true}
Read-only lib_cell attribute. Indicates whether the lib_cell has the interface_timing Liberty cell attribute.
Related Information
Related attributes: (base_cell) is_interface_timing
(inst) is_interface_timing
is_isolation_cell
is_isolation_cell {false | true}
Default: false
Read-write lib_cell attribute. Indicates if the lib_cell is an isolation cell. Isolation cells are used in n designs with switchable power domains.
Related Information
Related attributes: (base_cell) is_isolation_cell
(inst) is_isolation
is_isolation_cell_enable
is_macro
is_macro {false | true}
Default: false
Read-only lib_cell attribute. Indicates whether this lib_cell is a macro cell.
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Related Information
Related attributes: (base_cell) is_macro
(inst) is_macro
is_master_slave_flop
is_master_slave_flop {false | true}
Read-only lib_cell attribute. Indicates if the lib_cell is a master-slave flip-flop.
Related Information
Related attributes: (base_cell) is_master_slave_flop
(inst) is_memory
is_master_slave_lssd_flop
is_master_slave_lssd_flop {false | true}
Read-only lib_cell attribute. Indicates if the lib_cell is a master-slave LSSD flip-flop.
Related Information
Related attributes: (base_cell) is_master_slave_lssd_flop
(inst) is_master_slave_lssd_flop
is_memory
is_memory {false | true}
Read-write lib_cell attribute. Specifies that this lib_cell is a memory. You should only set this if the cell has address, data, and enable pins.
Related Information
Related attributes: (base_cell) is_memory
(inst) is_memory
is_negative_level_sensitive
is_negative_level_sensitive {false | true}
Read-only lib_cell attribute. Indicates whether the lib_cell is negative level-sensitive.
Related Information
Related attribute: (base_cell) is_negative_level_sensitive
is_pad
is_pad {false | true}
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Library Attributes--lib_cell Attributes for Library
Read-only lib_cell attribute. Indicates if the lib_cell is a pad cell.
The attribute value will be set to true if the cell has a corresponding cell in the LEF library defined as CLASS PAD.
Related Information
Related attributes: (base_cell) is_pad
(inst) is_pad
is_pll
is_pll {false | true}
Read-only lib_cell attribute. Indicates if the lib_cellhas unknown internal functionality
Related Information
Related attribute: (base_cell) is_pll
is_positive_level_sensitive
is_positive_level_sensitive {false | true}
Read-only lib_cell attribute. Indicates whether the base_cell is positive level-sensitive.
Related Information
Related attribute: (base_cell) is_positive_level_sensitive
is_power_switch
is_power_switch {false | true}
Read-only lib_cell attribute. Indicates if the lib_cell is a power swicth cell.
Related Information
Related attribute: (base_cell) is_power_switch
is_retention_cell
is_retention_cell {false | true}
Read-only lib_cell attribute. Indicates if the lib_cell is a retention cell
Related Information
Related attribute: (base_cell) is_retention_cell
is_rise_edge_triggered
is_rise_edge_triggered {false | true}
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Library Attributes--lib_cell Attributes for Library
Read-only lib_cell attribute. Indicates whether the base_cell has a rising clock.
Related Information
Related attribute: (base_cell) is_rise_edge_triggered
is_sequential
is_sequential {true | false}
Read-only lib_cell attribute. Indicates if the lib_cell is a sequential cell.
Related Information
Related attributes: (base_cell) is_sequential
(inst) is_sequential
is_timing_model
is_timing_model {true | false}
Read-only lib_cell attribute. Indicates if the internal functionality of the lib_cell is unknown.
Related Information
Related attributes: (base_cell) is_timing_model
(inst) timing_model
timing_model_reason
is_tristate
is_tristate {true | false}
Read-only lib_cell attribute. Indicates if the lib_cell has at least one tristate output.
Related Information
Related attributes: (base_cell) is_tristate
(inst) is_tristate
keep_as_physical
keep_as_physical {1 | 0 | true | false}
Default: false
Read-only lib_cell attribute. When set to true, retains the physical cell during read_def -keep_all_physical_cells execution.
latch_enable
latch_enable {lib_pin | pg_lib_pin}
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Library Attributes--lib_cell Attributes for Library
Read-only lib_cell attribute. Returns the path to the library pin that corresponds to the latch enable pin of this library cell.
An empty string indicates that this library cell is not a latch cell.
latch_enable_pins
latch_enable_pins {lib_pins | pg_lib_pins}
Read-only lib_cell attribute. Returns the path to the library pin(s) that correspond to the latch enable pin(s) of this library cell.
An empty string indicates that this library cell is not a latch cell.
leakage_scale_factor
leakage_scale_factor {1.0 | double}
Default: 1.0
Read-write lib_cell attribute. Specifies the scaling factor of leakage power of the lib_cell.
set_db lib_cell:ls_of_ld_lib_1p08v/slow/SDFFRHQX4 .leakage_scale_factor 10set_db lib_cell:ls_of_ld_lib_1p08v/pwr_mgmt/LVLH2L .leakage_scale_factor 15
If the value of leakage_scale_factor is 10 and the value of cell_leakage_power is 0.5231, the leakage power of this cell is 5.231 nW.
Related Information
Affects these commands: report_gates
report_power
syn_generic
syn_map
syn_opt
lef_inconsistent
lef_inconsistent {1 | 0 | true | false}
Default: false
Read-only lib_cell attribute. Specifies whether the lib_cell cannot be used during optimization. Set this attribute to true when lib_cell is marked as avoid.
As the value of lib cells marked as avoid tend to change in some typical flow and at that point it is not possible to know which lib cells were marked as avoid. In
that case, this attribute helps by keeping the backup of the lib cells marked as avoid and keep track of the lib cells that were marked as avoid.
Example
genus:root: > get_property [vfind / -libcell *] lef_inconsistent
left_padding
left_padding float
Read-write lib_cell attribute. Returns the left padding of the lib_cell.
Related Information
Related attribute: (base_cell) left_padding
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Library Attributes--lib_cell Attributes for Library
level_shifter_direction
level_shifter_direction {up|down|bidir}
Read-only lib_cell attribute. Specifies whether the level shifter can be used between a lower and higher voltage, or between a higher and lower voltage, or
both.
level_shifter_type
level_shifter_type {LH | HL | HL_LH}
Read-only lib_cell attribute. Returns the supported voltage conversion by the level shifter cell. Valid values for a level shifter are:
LH—Low to High
HL—High to Low
HL_LH—High to Low and Low to High.
The attribute value can be null if this library cell is not a level shifter, or if the level shifter does not have the level_shifter_type lib_cell attribute in the
Liberty library. In the latter case, the default type for the level shifter is HL_LH.
Related Information
Related attribute: (base_cell) level_shifter_type
level_shifter_valid_location
level_shifter_valid_location {from|to|on|off|either|any}
Read-write lib_cell attribute. Specifies where the level shifters can be placed.
Related Information
define_level_shifter_cell in the Common Power Format Language Reference.
Affected by this command: read_power_intent
lib_arcs
lib_arcs list_of_lib_arcs
Read-only lib_cell attribute. Returns the list of lib_arcs associated with the lib_cell.
lib_pins
lib_pins list_of_lib_pins
Read-only lib_cell attribute. Returns the list of lib_pins associated with the lib_cell.
liberty_attributes
liberty_attributes string
Read-only lib_cell attribute. Returns a list of Liberty attributes and values that were specified for this cell in the library.
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Related Information
Related attributes: (library) liberty_attributes
(lib_arc) liberty_attributes
(lib_pin) liberty_attributes
(operating_condition) liberty_attributes
(pg_lib_pin) liberty_attributes
(wireload) liberty_attributes
library
library library_object
Read-only lib_cell attribute. Returns the name of the library that this lib_cell belongs to.
Related Information
Related attributes: (library_domain) library
(operating_condition) library
(wireload) library
(wireload_selection) library
master_physical_variant_cell
master_physical_variant_cell lib_cell
Read-only lib_cell attribute. Returns the master cell, which stores the complete description of all the child physical variant cells.
Related Information
Related attributes (base_cell) master_physical_variant_cell
(base_cell) physical_variant_cells
(lib_cell) physical_variant_cells
max_ground_input_voltage
max_ground_input_voltage float
Default: 0.0
Read-write lib_cell attribute. Specifies the maximum voltage for the input (source) ground supply voltage that can be handled by this level shifter cell.
This attribute only applies to ground level shifters.
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Related Information
Affected by this command: read_power_intent
Related attributes: (level_shifter_group) max_ground_input_voltage
(level_shifter_group) min_ground_input_voltage
(lib_cell) min_ground_input_voltage
max_ground_output_voltage
max_ground_output_voltage float
Default: 0.0
Read-write lib_cell attribute. Specifies the maximum voltage for the output (destination) ground supply voltage that can be handled by this level shifter.
This attribute only applies to ground level shifters.
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_group) max_ground_output_voltage
(level_shifter_group) min_ground_output_voltage
(lib_cell) min_ground_output_voltage
max_input_voltage
max_input_voltage float
Default: 0.0
Read-write lib_cell attribute. Specifies the upper bound of the voltage range (in volt) that can be handled by the level shifter for the source domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
Related attribute: (level_shifter_group) max_input_voltage
max_output_voltage
max_output_voltage float
Default: 0.0
Read-write lib_cell attribute. Specifies the upper bound of the voltage range (in volt) that can be handled by the level shifter for the destination domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
Related attribute: (level_shifter_group) max_output_voltage
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Library Attributes--lib_cell Attributes for Library
min_ground_input_voltage
min_ground_input_voltage float
Default: 0.0
Read-write lib_cell attribute. Specifies the minimum voltage for the input (source) ground supply voltage that can be handled by this level shifter.
This attribute only applies to ground level shifters.
Related Information
Affected by this command: read_power_intent
Related attributes: (level_shifter_group) min_ground_input_voltage
(level_shifter_group) max_ground_input_voltage
(lib_cell) max_ground_input_voltage
min_ground_output_voltage
min_ground_output_voltage float
Default: 0.0
Read-write lib_cell attribute. Specifies the minimum voltage for the output (destination) ground supply voltage that can be handled by this level shifter.
This attribute only applies to ground level shifters.
Related Information
Affected by this command: read_power_intent
Related attributes: (level_shifter_group) min_ground_output_voltage
(level_shifter_group) max_ground_output_voltage
(lib_cell) max_ground_output_voltage
min_input_voltage
min_input_voltage float
Default: 0.0
Read-write lib_cell attribute. Specifies the lower bound of the voltage range (in volt) that can be handled by the level shifter for the source domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
Related attribute: (level_shifter_group) min_input_voltage
min_output_voltage
min_output_voltage float
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Default: 0.0
Read-only lib_cell attribute. Specifies the lower bound of the voltage range (in volt) that can be handled by the level shifter for the destination domain.
Related Information
Affected by this command: read_power_intent
Affected by this attribute: (library_domain) library
mode_definition
mode_definition tcl_list
Read-write lib_cell attribute. Extracts mode definition details of the specified library cell(s).
Example
get_db lib_cell:default_emulate_libset_max/s40iolib_s40e_hsio_stdln_pad_tt_tt_1p10lv_3p3hsio_enh_2_25c_typ_fs_tpnl_PVT16/s40iolib_s40e_hsio_stdln_pad
.mode_definition]
Output of the above command:
{ttl_0p8f2r {ttl_0p8f2r {} {}} {normal_ttl2 {} {}}} {ttl_0p8r2f {ttl_0p8r2f {} {}} {normal_ttl1 {} {}}} {smif_30f70r {smif_30f70r {} {}} {normal_smif2 {} {}}} {smif_30r70f
{smif_30r70f {} {}} {normal_smif1 {} {}}} {normal {normal {} {}} {normal_normal {} {}}}
non_seq_setup_arc
non_seq_setup_arc {false | true}
Read-only lib_cell attribute. Specifies whether the lib_cell has an enabled non_seq_setup timing arc.
Related Information
Related attributes: (lib_pin) non_seq_setup_arc
(pg_lib_pin) non_seq_setup_arc
num_base_pins
num_base_pins integer
Read-only lib_cell attribute. Returns the number of logical pins that the lib_cell has.
pg_lib_pins
pg_lib_pins list_of_pg_lib_pins
Read-only lib_cell attribute. Returns the list of power and ground lib_pins associated with the lib_cell.
physical_variant_cells
physical_variant_cells list_of_lib_cell
Read-only lib_cell attribute. Returns the list of physical variant cells of the master cell where it is defined.
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Related Information
Related attributes: (base_cell) physical_variant_cells
(base_cell) master_physical_variant_cell
(lib_cell) master_physical_variant_cell
power_gating_cell
power_gating_cell {false | true}
Default: false
Read-write lib_cell attribute. Indicates if the cell is configured to support state-retention power gating (SRPG).
Related Information
Related attributes: power_gating_cell_type
power_gating_class
power_gating_pin_phase
power_gating_cell_type
power_gating_cell_type string
Read-write lib_cell attribute. Identifies the type of a state-retention cell. By default, the type corresponds to the value of the power_gating_cell Liberty cell
attribute.
Related Information
Related attributes: power_gating_cell
power_gating_class
power_gating_pin_phase
preserve_avoid
preserve_avoid {false | true}
Default: false
Read-write lib_cell attribute. This attribute sets both preserve and avoid attributes.
This attribute has been introduced to retain old behavior of preserve and avoid. In old behavior, setting avoid attribute internally changes preserve value.
Examples
set_db [vfind / -libcell * ] .preserve_avoid false
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Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affects these attributes: avoid
preserve
primary_power
primary_power {pg_lib_pin | lib_pin}
Read-only lib_cell attribute. Returns the primary power pin of a power switch cell.
required_condition
required_condition string
Read-only lib_cell attribute. Returns the required_condition attribute of the retention_condition group in the .lib cell description of a retention cell,
right_padding
right_padding float
Read-write lib_cell attribute. Returns the right padding of the lib_cell.
Related Information
Related attribute: (base_cell) right_padding
scan_enable_pins
scan_enable_pins (libpins|pg_lib_pins}
Read-only lib_cell attribute. Returns the path(s) to the library pin(s) that correspond(s) to the scan enable pin(s) of this library cell.
An empty string indicates that this library cell is not a scan flip-flop.
scan_in
scan_in string
Read-only lib_cell attribute. Returns the path to the library pin that corresponds to the scan data input pin of this library cell.
An empty string indicates that this library cell is not a scan flip-flop.
scan_in_pins
scan_in_pins (lib_pins|pg_lib_pins}
Read-only lib_cell attribute. Returns the list of lib_pins that are scan data input pins.
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An empty string indicates that this library cell is not a scan flip-flop.
scan_out
scan_out string
Read-only lib_cell attribute. Returns the path to the library pin that corresponds to the scan data output pin of this library cell.
An empty string indicates that this library cell is not a scan flip-flop.
scan_out_pins
scan_out_pins (lib_pins|pg_lib_pins}
Read-only lib_cell attribute. Returns the list of lib_pins that are scan data output pins.
An empty string indicates that this library cell is not a scan flip-flop.
seq_functions
seq_functions object_list
Read-only lib_cell attribute. Returns the list of sequential functions associated with this lib_cell.
sequential
sequential {true | false}
Read-only lib_cell attribute. Indicates if the lib_cell is a sequential logic circuit.
Related Information
Related attribute: (inst) is_sequential
short
short {lib_pin_list | pg_lib_pin_list}...
Read-write lib_cell attribute. Lists the shorted pins that are connected together by a metal or poly trace. The attribute value is a list of lists, and each list
contain a set of pins that are shorted.
Related Information
Set by this command: read_power_intent -1801
std_cell_main_rail_pin
std_cell_main_rail_pin {lib_pin | pg_lib_pin}
Read-only lib_cell attribute. Returns the power pin which is the main rail in the cell.
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Library Attributes--lib_cell Attributes for Library
Related Information
Related attribute: (inst) std_cell_main_rail_pin
switch_off_enables
switch_off_enables {lib_pin | pg_lib_pin}...
Read-only lib_cell attribute. Returns the switch-off enables of a power switch cell.
switched_power
switched_power {lib_pin | pg_lib_pin}
Read-only lib_cell attribute. Returns the switched power pin of a power switch cell.
symmetry
symmetry string
Read-only lib_cell attribute. Returns the symmetry info of the lib_cell. Valid values are r, x, y, xy, and rxy, where
r—Indicates that the cell is symmetrical in 90 degree counterclockwise rotation
x—Indicates that the cell is symmetrical about the x-axis
y—Indicates that the cell is symmetrical about the y-axis
Related Information
Related attribute: (base_cell) symmetry
sync_clear_pins
sync_clear_pins (lib_pins|pg_lib_pins}
Read-only lib_cell attribute. Returns the path to the library pin(s) that correspond to the synchronous clear pin(s) of this library cell.
An empty string indicates that this library cell either is not a flip-flop cell, or has no synchronous clear pin.
Related Information
Related attribute: use_nextstate_type_only_to_assign_sync_ctrls
sync_preset_pins
sync_preset_pins (lib_pins|pg_lib_pins}
Read-only lib_cell attribute. Returns the path to the library pin(s) that corresponds to the synchronous preset pin(s) of this library cell.
An empty string indicates that this library cell either is not a flip-flop cell, or has no synchronous preset pin.
timing_model_type
timing_model_type string
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Read-only lib_cell attribute. Returns the value of the Liberty timing_model_type attribute.
The attribute value can be null if this library cell does not have the timing_model_type attribute in the Liberty library.
top_padding
top_padding integer
Default: 0
Read-write lib_cell attribute. Returns the top padding of the lib_cell.
tristate
tristate {true | false}
Read-only lib_cell attribute. Indicates if the lib_cell has at least one tristate output.
Related Information
Related attributes: (inst) tristate
(lib_pin) tristate
(pg_lib_pin) tristate
type_changed_pin_names
type_changed_pin_names string
Default: no value
Read-only lib_cell attribute. Returns the list of pin names changed to power or ground pin.
usable_flop
usable_flop {1 | 0 | true | false}
Default: false
Read-only lib_cell attribute. Indicates whether the lib_cell is a non timing model flip flop.
usable_latch
usable_latch {1 | 0 | true | false}
Default: false
Read-only lib_cell attribute. Indicates whether the lib_cell is a non timing model latch.
width
width float
Read-only lib_cell attribute. Returns the width, in microns, of the cell based on the information from the physical library.
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Library Attributes--lib_pin Attributes for Library
Related Information
Related attribute (lib_cell) width
lib_pin Attributes for Library
alive_during_partial_power_down
alive_during_power_up
all_q_pin_of_d_pin
all_qb_pin_of_d_pin
async_clear_polarity
async_preset_polarity
base_pin
bundle
capacitance
capacitance_max_fall
capacitance_max_rise
capacitance_min_fall
capacitance_min_rise
capacitance_rf
clock_polarity
drive_resistance
driver_type
fanout_load
from_lib_arcs
function
function_type
higher_drive_pin
is_always_on
is_analog
is_async
is_clock
is_data
is_generated_clock
is_ground
is_inverted
is_iq_function
is_iqn_function
is_isolated
is_isolation_cell_clock
is_isolation_cell_data
is_isolation_cell_enable
is_level_shifter_enable
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is_pad
is_power
is_power_switch_enable
is_retention_cell_enable
is_scan_out
is_scan_out_inverted
is_std_cell_main_rail
is_tristate
is_unconnected
isolation_enable_condition
isolation_enable_phase
latch_enable_polarity
liberty_attributes
lower_drive_pin
min_capacitance
min_fanout
min_transition
mother_power
non_seq_setup_arc
pg_function
pg_type
physical_connection
power_gating_class
power_gating_pin_phase
power_gating_polarity
pulse_clock
rail_connection
related_bias_pin
related_ground_pin
related_power_pin
restore_action
restore_edge_type
save_action
scan_enable_polarity
scan_in_polarity
signal_level
slew_threshold_percent_fall_high
slew_threshold_percent_fall_low
slew_threshold_percent_rise_high
slew_threshold_percent_rise_low
stack_via_list
stack_via_required
switch_off_enable_polarity
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Library Attributes--lib_pin Attributes for Library
sync_clear_polarity
sync_enable_polarity
sync_preset_polarity
tied_to
to_lib_arcs
tristate
use
user_function
voltage_name
voltage_value
x_offset
y_offset
alive_during_partial_power_down
alive_during_partial_power_down {false | true}
Default: false
Read-write lib_pin attribute. Indicates whether the pin is alive during partial power down.
alive_during_power_up
alive_during_power_up {false | true}
Default: false
Read-write lib_pin attribute. Indicates whether the pin is alive during power up.
all_q_pin_of_d_pin
all_q_pin_of_d_pin {lib_pin|pg_lib_pin}
Read-only lib_pin attribute. Returns the output pin(s) that corresponds to the data pin of the sequential cell. Use this for sequential cells with multiple data pins
and output pins.
Related Information
Related attribute: (pg_lib_pin) all_q_pin_of_d_pin
all_qb_pin_of_d_pin
all_qb_pin_of_d_pin {libpin}
Read-only lib_pin attribute. Returns the inverted output pin that corresponds to the data pin of the sequential cell. Use this for sequential cells with multiple
data pins and output pins.
async_clear_polarity
async_clear_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the asynchronous clear pin of a sequential cell.
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The value none indicates that the pin is not an asynchronous clear pin.
Related Information
Related attribute: (pg_lib_pin) async_clear_polarity
async_preset_polarity
async_preset_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the asynchronous preset pin of a sequential cell.
The value none indicates that this pin is not an asynchronous preset pin.
Related Information
Related attribute: (pg_lib_pin) async_preset_polarity
base_pin
base_pin base_pin
Read-only lib_pin attribute. Returns the reference base pin of this library pin.
Related Information
Related attribute: (pg_lib_pin) base_pin
bundle
bundle string_list
Read-only lib_pin attribute. Returns for every pin that is part of a bundle, a string of the following format:
bundle bundle_name: bundle_member bundle_member ...
For multi-bit cells, all pins that have similar timing or functionality are grouped in a bundle. The attribute value for all bundle members will be the same.
This attribute has no value for single-bit cells.
Related Information
Related attribute: (pg_lib_pin) bundle
capacitance
capacitance string
Read-only lib_pin attribute. Returns the value of the capacitance attribute from the Liberty library at the pin, cell, or library level depending on the precedence
rules.
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Related Information
Related attribute: (pg_lib_pin) capacitance
capacitance_max_fall
capacitance_max_fall max_cap
Read-only lib_pin attribute. Returns the maximum fall capacitance of the lib_pin.
Related Information
Related attributes: (lib_pin) capacitance_max_rise
(pg_lib_pin) capacitance_max_fall
(pg_lib_pin) capacitance_max_rise
capacitance_max_rise
capacitance_max_rise max_cap
Read-only lib_pin attribute. Returns the maximum rise capacitance of the lib_pin.
Related Information
Related attributes: (lib_pin) capacitance_max_fall
(pg_lib_pin) capacitance_max_fall
(pg_lib_pin) capacitance_max_rise
capacitance_min_fall
capacitance_min_fall min_cap
Read-only lib_pin attribute. Returns the minimum fall capacitance of the lib_pin.
Related Information
Related attributes: (lib_pin) capacitance_min_rise
(pg_lib_pin) capacitance_min_fall
(pg_lib_pin) capacitance_min_rise
capacitance_min_rise
capacitance_min_rise min_cap
Read-only lib_pin attribute. Returns the minimum rise capacitance of the lib_pin.
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Related Information
Related attributes: (lib_pin) capacitance_min_fall
(pg_lib_pin) capacitance_min_fall
(pg_lib_pin) capacitance_min_rise
capacitance_rf
capacitance_rf string
Read-write lib_pin attribute. Specifies the rise and fall capacitive load of the pin in femtofarads.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
(pg_lib_pin) capacitance_rf
clock_polarity
clock_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the clock pin of a sequential cell
The value none indicates that this pin is not a clock pin of a sequential cell.
Related Information
Related attribute: (pg_lib_pin) clock_polarity
drive_resistance
drive_resistance int
Read-only lib_pin attribute. Returns the approximate drive resistance of the pin in Ohm.
Related Information
Related attribute: (pg_lib_pin) drive_resistance
driver_type
driver_type {bus_hold | open_drain | open_source | pull_up | pull_down
| resistive | resistive_0 | resistive_1}
Read-only lib_pin attribute. Returns the driver type of the output or inout pin.
If the pin is an inout pin, the attribute can have a driver type for the input and output. In this case the following applies:
if pull_up or pull_down is returned with open_drain, the pull_up or pull_down value will be applied to the input, while the open_drain will be applied to the
output
if the value returned is bus_hold, it will be applied to the input and output
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if the value returned is not bus_hold, it will be applied to the output.
For output pins only one of the possible values can be returned.
This attribute has no value for input pins.
Related Information
Related command: report_dft_violations
Related attribute: (pg_lib_pin) driver_type
fanout_load
fanout_load float
Read-only lib_pin attribute. Specifies the internal fanout of the input pin. Resolution is 1/1000. Typical units are standard loads or pin count.
Related Information
Related attribute: (pg_lib_pin) fanout_load
from_lib_arcs
from_lib_arcs lib_arc
Read-only lib_pin attribute. Returns a list of outgoing timing arcs.
Related Information
Related attribute: (pg_lib_pin) from_lib_arcs
function
function string
Read-only lib_pin attribute. Specifies the value (Boolean expression) of an output pin as a function of the cell’s input or inout pins.
Related Information
Related attribute: (pg_lib_pin) function
function_type
function_type {none | async_clear | async_preset | clear | clock | clock_gate_enable | data_enable | ground | latch_enable | power | preset | scan_out | scan_in
| scan_enable | tristate_enable}
Read-only lib_pin attribute. Returns the function of the pin.
Example
genus@root:> get_db lib_pin:my_lib/slow/DFFSRX1/RN .function_typeasync_clear
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Related Information
Related attribute: (pg_lib_pin) function_type
higher_drive_pin
higher_drive_pin (lib_pin|pg_lib_pin}
Read-only lib_pin attribute. Returns the path to the library pin of a cell that has the same functionality, but has a higher drive strength. If your library contains
several cells with the same functionality, this attribute points to the pin with the next higher drive strength. The attribute value on the pin with the highest drive
strength is an empty string.
Related Information
Related attribute: (pg_lib_pin) higher_drive_pin
(pg_lib_pin) lower_drive_pin
(lib_pin) lower_drive_pin
is_always_on
is_always_on {false | true}
Default: false
Read-write lib_pin attribute. Indicates if this pin is an always-on pin on an always-on cell.
Related Information
Related attributes: (base_pin) is_always_on
(pg_lib_pin) is_always_on
is_analog
is_analog {false| true}
Read-write lib_pin attribute. Identifies an analog signal pin as analog so it can be recognized by the tools.
Related Information
Related attributes: (base_pin) is_analog
is_async
is_async {false| true}
Read-only lib_pin attribute. Indicates whether this pin is an asynchronous pin.
Related Information
Related attribute: (pg_lib_pin) is_async
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is_clock
is_clock {false| true}
Read-only lib_pin attribute. Indicates whether this pin is a clock pin.
Example
Below is a sample clock path in a design.
## Capture clock path:
#--------------------------------------------------------------------------------
# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
(fF) (ps) (ps) (ps) Location
#--------------------------------------------------------------------------------
in1 (i) - R (arrival) 3 0.0 200000 0 0 (-,-)
buf2/Y (i,m) A->Y R BUF_X3M_C35 2 0.0 0 8418 8418 (-,-)
and1/Y (i,m) B->Y R AND2_X1M_C35 8 0.0 0 10 8428 (-,-)
D_pin/CK <<< - R SDFFRPQ_C35 8 - 0 0 8428 (-,-)
#--------------------------------------------------------------------------------
If you query is_clock attribute on all the pins in the clock path, it will return true for only flops/CK pin as it is defined ’clock pin’ in the library and hence you see
only the flops/CK pin while running the loop using is_clock attribute.
## From library:
pin(CK) {
capacitance : 0.000559972 ;
clock : true ;
direction : input ;
genus:root:> get_db pin:top/buf2/Y .is_clock
false
genus:root:> get_db pin:top/and1/Y .is_clock
false
genus:root:> get_db pin:top/D_pin/CK .is_clock
true
is_data
is_data {false | true}
Read-only lib_pin attribute. Indicates if this pin is a data pin.
Related Information
Related attribute: (pg_lib_pin) is_data
is_generated_clock
is_generated_clock string
Read-only lib_pin attribute. Returns the Liberty attributes and corresponding values that were specified in the generated_clock group for the lib_cell to which
this pin belongs.
The following Liberty attributes can be specified in a generated_clock group:
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clock_pin
master_pin
divided_by
multipled_by
invert
duty_cycle
edges
shifts
Related Information
Related attribute: (pg_lib_pin) is_generated_clock
is_ground
is_ground {false | true}
Read-only lib_pin attribute. Indicates if the pin is a ground pin.
Related Information
Related attribute: (pg_lib_pin) is_ground
is_inverted
is_inverted {false | true}
Read-only lib_pin attribute. Indicates if this pin is an inverted lib pin.
Related Information
Related attribute: (pg_lib_pin) is_inverted
is_iq_function
is_iq_function {true | false}
Read-only lib_pin attribute. Indicates if this pin is an IQ (noninverting output) pin.
Related Information
Related attribute: (pg_lib_pin) is_iq_function
is_iqn_function
is_iqn_function {true | false}
Read-only lib_pin attribute. Indicates if this pin is an IQN (inverting output) pin.
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Related Information
Related attribute: (pg_lib_pin) is_iqn_function
is_isolated
is_isolated {false| true}
Read-only lib_pin attribute. Indicates if this pin is internally isolated and does not require the insertion of an external isolation cell.
Related Information
Related attribute: (pg_lib_pin) is_isolated
is_isolation_cell_clock
is_isolation_cell_clock {false | true}
Default: false
Read-only lib_pin attribute. Clock pin of a clock isolation cell.
Related Information
Related attributes: (base_pin) is_isolation_cell_clock
(pg_lib_pin) is_isolation_cell_clock
is_isolation_cell_data
is_isolation_cell_data {false | true}
Default: no_value
Read-only lib_pin attribute. Returns a value of true if the Liberty library is_isolation_cell_data attribute is set to true for lib_pin.
Related Information
Related attributes: (base_pin) is_isolation_cell_data
(pin) is_isolation_cell_data
is_isolation_cell_enable
is_isolation_cell_enable {false | true}
Default: false
Read-write lib_pin attribute. Indicates if this pin is the enable pin of an isolation cell.
Related Information
Related attributes: is_isolation_cell
(base_pin) is_isolation_cell_enable
(pg_lib_pin) is_isolation_cell_enable
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is_level_shifter_enable
is_level_shifter_enable {false | true}
Default: false
Read-write lib_pin attribute. Indicates if this pin is the enable pin of a level shifter cell.
Related Information
Related attributes: (base_pin) is_level_shifter_enable
(pg_lib_pin) is_level_shifter_enable
is_pad
is_pad {false | true}
Read-only lib_pin attribute. Indicates if the lib_pin is a pad pin.
Related Information
Related attribute: (pg_lib_pin) is_pad
is_power
is_power {false | true}
Read-only lib_pin attribute. Indicates if the pin is a power pin.
Related Information
Related attribute: (pg_lib_pin) is_power
is_power_switch_enable
is_power_switch_enable {false | true}
Default: false
Read-write lib_pin attribute. Indicates if this pin is the enable pin of a power switch cell.
Related Information
Related attribute: (base_pin) is_power_switch_enable
is_retention_cell_enable
is_retention_cell_enable {false | true}
Read-only lib_pin attribute. Indicates if this pin is the retention pin of a lib cell.
Related Information
Related attribute: (base_pin) is_retention_cell_enable
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is_scan_out
is_scan_out {false| true}
Read-only lib_pin attribute. Indicates whether the pin is a scan data output pin.
Related Information
Related attribute: (pg_lib_pin) is_scan_out
is_scan_out_inverted
is_scan_out_inverted {false| true}
Read-only lib_pin attribute. Indicates whether the pin is a scan data output pin.
Related Information
Related attribute: (pg_lib_pin) is_scan_out_inverted
is_std_cell_main_rail
is_std_cell_main_rail {false | true}
Read-only lib_pin attribute. Indicates whether this pin is a primrary power pin on the main rail in the cell.
Related Information
Related attribute: (pg_lib_pin) is_std_cell_main_rail
is_tristate
is_tristate {true | false}
Read-only lib_pin attribute. Indicates whether the pin is a tristate output.
Related Information
Related attribute: (pg_lib_pin) is_tristate
is_unconnected
is_unconnected {false| true}
Read-only lib_pin attribute. Indicates whether the pin is connected.
Related Information
Related attributes: (base_pin) is_unconnected
(pg_lib_pin) is_unconnected
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isolation_enable_condition
isolation_enable_condition string
Read-only lib_pin attribute. Returns the condition of isolation for an internally isolated pin. The ocndition is specified as a Boolean expression in terms of input
and inout pins.
Related Information
Related attribute: (pg_lib_pin) isolation_enable_condition
isolation_enable_phase
isolation_enable_phase {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the isolation enable pin of an isolation cell.
The value none indicates that this pin is not an isolation enable pin.
Related Information
Related attribute: (pg_lib_pin) isolation_enable_phase
latch_enable_polarity
latch_enable_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the latch enable pin of a sequential cell.
The value none indicates that this pin is not a latch input enable.
Related Information
Related attribute: (pg_lib_pin) latch_enable_polarity
liberty_attributes
liberty_attributes string
Read-only lib_pin attribute. Returns a list of Liberty attributes and values that were specified for this pin in the library.
Related Information
Related attributes: (library) liberty_attributes
(lib_arc) liberty_attributes
(lib_cell) liberty_attributes
(operating_condition) liberty_attributes
(pg_lib_pin) liberty_attributes
(wireload) liberty_attributes
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lower_drive_pin
lower_drive_pin (lib_pin|pg_lib_pin}
Read-only lib_pin attribute. Returns the path to the library pin of a cell that has the same functionality, but has a lower drive strength. If your library contains
several cells with the same functionality, this attribute points to the pin with the next lower drive strength. The attribute value on the pin with the lowest drive
strength is an empty string.
Related Information
Related attributes: (lib_pin) higher_drive_pin
(pg_lib_pin) higher_drive_pin
(pg_lib_pin) lower_drive_pin
min_capacitance
min_capacitance float
Default: 0.0
Read-write lib_pin attribute. Specifies the minimum capacitance in femtofarads that an output pin can drive.
Minimum DRC values are used to ensure the predictability of the timing by ensuring it falls within the characterization range, and to ensure that high drive cells
are only used when needed.
This attribute has no value for input pins.
Related Information
Related attribute: (pg_lib_pin) min_capacitance
min_fanout
min_fanout float
Read-write lib_pin attribute. Specifies the minimum fanout that an output pin of the library cell can drive.
Minimum DRC values are used to ensure the predictability of the timing by ensuring it falls within the characterization range, and to ensure that high drive cells
are only used when needed.
This attribute has no value for input pins.
Related Information
Related attribute: (pg_lib_pin) min_fanout
min_transition
min_transition float
Default: 0.0
Read-write lib_pin attribute. Specifies the minimum acceptable transition time on the library pin. This attribute applies to input and output pins.
Minimum DRC values are used to ensure the predictability of the timing by ensuring it falls within the characterization range, and to ensure that high drive cells
are only used when needed.
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Related Information
Related attribute: (pg_lib_pin) min_transition
mother_power
mother_power {pg_lib_pin|lib_pin}
Read-only lib_pin attribute. Returns the mother pin of the switched power of a power switch cell.
Related Information
Related attributes (pg_lib_pin) mother_power
non_seq_setup_arc
non_seq_setup_arc {false | true}
Read-only lib_pin attribute. Specifies whether the pin has an enabled non_seq_setup timing arc.
Related Information
Related attributes: (lib_cell) non_seq_setup_arc
(pg_lib_pin) non_seq_setup_arc
pg_function
pg_function string
Read-only lib_pin attribute. Specifies the pg_function info of the pg pin. This corresponds to the value of the pg_function Liberty attribute defined in pg_pin
construct.
pg_type
pg_type string
Read-write lib_pin attribute. Specifies the pg_type info of the pin. This corresponds to the value of the pg_type Liberty pin attribute.
Related Information
Related attributes: (base_pin) pg_type
(pg_base_pin) pg_type
(pg_lib_pin) pg_type
physical_connection
physical_connection string
Read-only lib_pin attribute. Returns the physical_connection info of the power or ground pin. This corresponds to the value of the physical_connection
Liberty pin attribute.
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Related Information
Related attribute: (pg_lib_pin) physical_connection
power_gating_class
power_gating_class string
Read-write lib_pin attribute. Specifies the class of the power gating pin of a state-retention cell. The value is of the form power_pin_x, where x can take an
integer value from 1 through 5.
The value corresponds to the first part of the power_gating_pin pin Liberty attribute value.
Related Information
Related attributes: power_gating_cell
power_gating_cell_type
(lib_pin) power_gating_pin_phase
(pg_lib_pin) power_gating_class
(pg_lib_pin) power_gating_pin_phase
power_gating_pin_phase
power_gating_pin_phase {none | active_low | active_high}
Default: none
Read-write lib_pin attribute. Specifies the active phase of the pin of a state-retention cell.
active_low indicates that an active low signal (0) applied to this pin puts the gate in sleep mode.
active_high indicates that an active high signal (1) applied to this pin puts the gate into sleep mode.
The value of this attribute is the opposite of the value of the power_gating_pin pin Liberty attribute.
The value none indicates that the pin is not a power gating pin.
Related Information
Related attributes: power_gating_cell
power_gating_cell_type
(lib_pin) power_gating_class
(pg_lib_pin) power_gating_class
(pg_lib_pin) power_gating_pin_phase
power_gating_polarity
power_gating_polarity {none | active_low | active_high}
Default: none
Read-write lib_pin attribute. Specifies the active phase of the pin of a state-retention cell.
active_low indicates that an active low signal (0) applied to this pin puts the gate in sleep mode.
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active_high indicates that an active high signal (1) applied to this pin puts the gate into sleep mode.
The value of this attribute is the opposite of the value of the power_gating_pin pin Liberty attribute.
The value none indicates that the pin is not a power gating pin.
Related Information
Related attributes: (pg_lib_pin) power_gating_polarity
power_gating_cell
power_gating_cell_type
power_gating_class
pulse_clock
pulse_clock string
Read-only lib_pin attribute. Returns the attribute value of the Liberty pulse_clock pin attribute.
Related Information
Related attribute: (pg_lib_pin) pulse_clock
rail_connection
rail_connection string
Read-only lib_pin attribute. Returns the rail connection of the pin.
Related Information
Related attribute: (pg_lib_pin) rail_connection
related_bias_pin
related_bias_pin (lib_pins|pg_lib_pins}
Read-only lib_pin attribute. Defines all bias pins associated with a signal pin.
Related Information
Related attribute: (pg_lib_pin) related_bias_pin
related_ground_pin
related_ground_pin (lib_pin|pg_lib_pin}
Read-only lib_pin attribute. Associates a predefined ground pin with the specified library pin.
Related Information
Related attributes: (base_pin) related_ground_pin
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Library Attributes--lib_pin Attributes for Library
related_power_pin
related_power_pin (lib_pins|pg_lib_pins}
Read-only lib_pin attribute. Associates a predefined power pin with the specified library pin.
Related Information
Related attributes: (base_pin) related_power_pin
restore_action
restore_action string
Default: no value
Read-only lib_pin attribute. Returns the restore_action information of the lib pin.
restore_edge_type
restore_edge_type string
Default: no value
Read-only lib_pin attribute. Returns the restore_edge_type information of the lib pin.
save_action
save_action string
Default: no value
Read-only lib_pin attribute. Returns the save_action information of the lib pin.
scan_enable_polarity
scan_enable_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the scan enable pin of a scan flip-flop.
The value none indicates that the pin is not a scan enable pin.
Related Information
Related attribute: (pg_lib_pin) scan_enable_polarity
scan_in_polarity
scan_in_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the scan data input pin of a scan flip-flop.
The value none indicates that the pin is not a scan data input pin.
Related Information
Related attribute: (pg_lib_pin) scan_in_polarity
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Library Attributes--lib_pin Attributes for Library
signal_level
signal_level string
Read-only lib_pin attribute. Returns the name of the power supply that the pin is connected to. This information is defined in the .lib file through the
input_signal_level (output_signal_level) attribute for an input (output) pin.
Related Information
Related attribute: (pg_lib_pin) signal_level
slew_threshold_percent_fall_high
slew_threshold_percent_fall_high float
Read-only lib_pin attribute. Returns the value of the higher threshold point used for modeling the delay of a falling transition at the pin.
slew_threshold_percent_fall_low
slew_threshold_percent_fall_low float
Read-only lib_pin attribute. Returns the value of the lower threshold point used for modeling the delay of a falling transition at the pin.
slew_threshold_percent_rise_high
slew_threshold_percent_rise_high float
Read-only lib_pin attribute. Returns the value of the higher threshold point used for modeling the delay of a rising transition at the pin.
slew_threshold_percent_rise_low
slew_threshold_percent_rise_low float
Read-only lib_pin attribute. Returns the value of the lower threshold point used for modeling the delay of a rising transition at the pin.
stack_via_list
stack_via_list string
Read-write lib_pin attribute. Specifies a list of stacked vias (via pillar) to be used for this pin. Set this attribtue before spatial or physical optimization.
Related Information
Related attribute: (pg_lib_pin) stack_via_list
stack_via_required
stack_via_required {false |true}
Default: false
Read-write lib_pin attribute. Specifies whether a list of stacked vias (via pillar) must be used for all its pins in the design. A list of stacked vias (via pillar) must
be defined for this library pin through the stack_vias_list attribute.
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Library Attributes--lib_pin Attributes for Library
Related Information
Related attribute: (pg_lib_pin) stack_via_required
switch_off_enable_polarity
switch_off_enable_polarity {none | active_low | active_high}
Read-only lib_pin attribute. Returns the phase of the switch-off enable pin.
The value none indicates that the pin is not a switch-off enable pin.
sync_clear_polarity
sync_clear_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the synchronous clear pin of a sequential cell.
The value none indicates that the pin is not a synchronous clear pin.
Related Information
Related attribute: (pg_lib_pin) sync_clear_polarity
sync_enable_polarity
sync_enable_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the synchronous enable pin of a sequential cell.
The value none indicates that the pin is not a synchronous enable pin.
Related Information
Related attribute: (pg_lib_pin) sync_enable_polarity
sync_preset_polarity
sync_preset_polarity {active_high | active_low | none}
Read-only lib_pin attribute. Returns the active phase of the synchronous preset pin of a sequential cell.
The value none indicates that this pin is not an synchronous preset pin.
Related Information
Related attribute: (pg_lib_pin) sync_preset_polarity
tied_to
tied_to string
Read-only lib_pin attribute. Returns the value to which the power or ground libpin is tied.
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Library Attributes--lib_pin Attributes for Library
Related Information
Related attribute: (base_pin) tied_to
(pg_base_pin) tied_to
(pg_lib_pin) tied_to
to_lib_arcs
to_lib_arcs lib_arc
Read-only lib_pin attribute. Returns a list of incoming timing arcs.
Related Information
Related attribute: (pg_lib_pin) to_lib_arcs
tristate
tristate {true | false}
Read-only lib_pin attribute. Indicates if this pin is a tristate output.
Related Information
Related attributes: (inst) tristate
(lib_cell) tristate
(pg_lib_pin) tristate
use
use {signal | analog | clock | ground | power}
Read-only lib_pin attribute. Returns the use of the pin. If the cell was read from a library in Liberty format, the use will be signal. If a LEF library is read later,
the value of this attribute might change if the pin’s use was defined through the USE statement in the LEF library.
Related Information
Related attributes: lef_library
library
(base_pin) use
(pg_lib_pin) use
user_function
user_function string
Read-write lib_pin attribute. Specifies the user-defined function for the cell on the output pin.
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Library Attributes--library Attributes for Library
Related Information
Related attribute: (pg_lib_pin) user_function
voltage_name
voltage_name float
Read-only lib_pin attribute. Returns the attribute value of the Liberty voltage_name pin attribute in case the library pin is a power or ground pin.
Related Information
Related attribute: (pg_lib_pin) voltage_name
voltage_value
voltage_value float
Read-only lib_pin attribute. Returns the voltage value in case the library pin is a power or ground pin.
Related Information
Related attribute: (pg_lib_pin) voltage_value
x_offset
x_offset float
Read-only lib_pin attribute. Specifies the x-offset (in microns) of the pin in the corresponding LEF cell.
Related Information
Related attribute: (pg_lib_pin) x_offset
y_offset
y_offset float
Read-only lib_pin attribute. Specifies the y-offset (in microns) of the pin in the corresponding LEF cell.
Related Information
Related attribute: (pg_lib_pin) y_offset
library Attributes for Library
cap_scale_in_ff
default_opcond
default_power_rail
default_wireload
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Library Attributes--library Attributes for Library
files
has_cells_having_power_ground_pins
input_threshold_pct_fall
input_threshold_pct_rise
lib_cells
liberty_attributes
library_type
max_operating_voltage
min_operating_voltage
nominal_process
nominal_temperature
nominal_voltage
operating_conditions
output_threshold_pct_fall
output_threshold_pct_rise
power_rails
slew_derate_from_library
slew_lower_threshold_pct_fall
slew_lower_threshold_pct_rise
slew_upper_threshold_pct_fall
slew_upper_threshold_pct_rise
time_scale_in_ps
usable_comb_cells
usable_seq_cells
usable_timing_models
version
wireload_models
wireload_selections
cap_scale_in_ff
cap_scale_in_ff float
Read-only library attribute. Returns the scaling factor used to compute any capacitance value in the library. All capacitance values in Genus are expressed in
femtofarads. Resolution is 1/10.
default_opcond
default_opcond string
Read-only library attribute. Returns the default operating conditions of the library.
default_power_rail
default_power_rail string
Read-only library attribute. Returns the attribute value of the Liberty default_power_rail attribute.
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Library Attributes--library Attributes for Library
default_wireload
default_wireload string
Read-write library attribute. Specifies the default wire-load model for a library. This model can be specified in the library, but you can override it.
files
files string
Read-only library attribute. Returns the full pathname of the specified library.
has_cells_having_power_ground_pins
has_cells_having_power_ground_pins {false | true}
Read-only library attribute. Indicates whether the library has cells with power and ground pins.
input_threshold_pct_fall
input_threshold_pct_fall float
Read-only library attribute. Returns the default value of the threshold point on an input pin signal falling from 1 to 0. If this attribute is not specified in the
library, the value defaults to 50.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
input_threshold_pct_rise
input_threshold_pct_rise float
Read-only library attribute. Returns the default value of the threshold point on an input pin signal rising from 0 to 1. If this attribute is not specified in the library,
the value defaults to 50.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
lib_cells
lib_cells list_of_cells
Read-only library attribute. Returns the list of library cells available in this library. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the ls command by default.
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Library Attributes--library Attributes for Library
Related Information
Related attributes: (base_cell) lib_cells
liberty_attributes
liberty_attributes string
Read-only library attribute. Returns a list of Liberty attributes and values that were specified at the library level.
Related Information
Related attributes: (lib_arc) liberty_attributes
(lib_cell) liberty_attributes
(lib_pin) liberty_attributes
(operating_condition) liberty_attributes
(pg_lib_pin) liberty_attributes
(wireload) liberty_attributes
library_type
library_type string
Read-only library attribute. Indicates whether the library is a target library, a link library, or both.
Related Information
Related attributes: (library_domain) link_library
(library_domain) target_library
max_operating_voltage
max_operating_voltage double
Read-only library attribute. Defines the maximum operating voltage for the library.
Related Information
Related attributes: library
min_operating_voltage
min_operating_voltage double
Read-only library attribute. Defines the minimum operating voltage for the library.
Related Information
Related attributes: library
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Library Attributes--library Attributes for Library
nominal_process
nominal_process float
Read-only library attribute. Returns the nominal process multiplier.
nominal_temperature
nominal_temperature float
Read-only library attribute. Returns the nominal temperature value.
nominal_voltage
nominal_voltage float
Read-only library attribute. Returns the nominal voltage of the library.
operating_conditions
operating_conditions list_of_operating_conditions
Read-only library attribute. Returns a list of operating conditions in the library.
output_threshold_pct_fall
output_threshold_pct_fall float
Read-only library attribute. Returns the default value of the threshold point on an output pin signal falling from 1 to 0. If this attribute is not specified in the
library, the value defaults to 50.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
output_threshold_pct_rise
output_threshold_pct_rise float
Read-only library attribute. Returns the default value of the threshold point on an output pin signal rising from 0 to 1. If this attribute is not specified in the
library, the value defaults to 50.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
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Library Attributes--library Attributes for Library
power_rails
power_rails Tcl_list
Read-only library attribute. Returns a Tcl list of Tcl lists. Each Tcl list contains the power supply name and the corresponding voltage. The number of Tcl lists
corresponds to the number of power_rail attributes in the power_supply group in the .lib file.
Related Information
Affects these commands: report_gates
report_power
Affects this attribute: leakage_power
slew_derate_from_library
slew_derate_from_library float
Read-only library attribute. Returns how the transition times need to be derated to match the transition times between the characterization trip points. If this
attribute is not specified in the library, the value defaults to 1.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
slew_lower_threshold_pct_fall
slew_lower_threshold_pct_fall float
Read-only library attribute. Returns the default value of the lower threshold point used for modeling the delay of a pin falling from 1 to 0. If this attribute is not
specified in the library, the value defaults to 20.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
slew_lower_threshold_pct_rise
slew_lower_threshold_pct_rise float
Read-only library attribute. Returns the default value of the lower threshold point used for modeling the delay of a pin rising from 0 to 1. If this attribute is not
specified in the library, the value defaults to 20.0.
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Library Attributes--library Attributes for Library
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
slew_upper_threshold_pct_fall
slew_upper_threshold_pct_fall float
Read-only library attribute. Returns the default value of the upper threshold point used for modeling the delay of a pin falling from 1 to 0. If this attribute is not
specified in the library, the value defaults to 80.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
slew_upper_threshold_pct_rise
slew_upper_threshold_pct_rise float
Read-only library attribute. Returns the default value of the upper threshold point used for modeling the delay of a pin rising from 0 to 1. If this attribute is not
specified in the library, the value defaults to 80.0.
Related Information
Affects these commands: report_cell_delay_calculation
report_slew_calculation
report_timing
time_scale_in_ps
time_scale_in_ps integer
Read-only library attribute. Returns the scaling factor used to compute any timing value in the library. All timing values in Genus are expressed in
picoseconds.
Related Information
Affects this attribute: library
usable_comb_cells
usable_comb_cells integer
Read-only library attribute. Returns the number of usable combinational cells in the library.
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Library Attributes--operating_condition Attributes for Library
usable_seq_cells
usable_seq_cells integer
Read-only library attribute. Returns the number of usable sequential cells in the library.
usable_timing_models
usable_timing_models integer
Read-only library attribute. Returns the number of library cells of which Genus can understand the timing behavior, but not the combinational or sequential
logic function. Genus will never map to these cells, but if you instantiate these cells, Genus can analyze their timing correctly. A RAM is the most common
example.
version
version string
Read-only library attribute. Returns the version string for the library. The library creator supplies this string, therefore there is no convention for the version of a
library.
wireload_models
wireload_models list_of_wireload_models
Read-only library attribute. Returns a list of wireload models in the library. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the ls command by default.
wireload_selections
wireload_selections list_of_wireload_selections
Read-only library attribute. Returns a list of wireload selection tables in the library. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the ls command by default.
operating_condition Attributes for Library
liberty_attributes
library
process
temperature
tree_type
liberty_attributes
liberty_attributes string
Read-only operating_condition attribute. Returns a list of Liberty attributes and values that were specified for the operating condition in the library.
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Library Attributes--pg_base_pin Attributes for Library
Related Information
Related attributes: (library) liberty_attributes
(lib_arc) liberty_attributes
(lib_cell) liberty_attributes
(lib_pin) liberty_attributes
(pg_lib_pin) liberty_attributes
(wireload) liberty_attributes
library
library library_object
Read-only operating_condition attribute. Returns the name of the library that this operating condition is associated with.
Related Information
Related attributes: (lib_cell) library
(library_domain) library
(wireload) library
(wireload_selection) library
process
process float
Read-write operating_condition attribute. Specifies the process value.
This attribute is useful when tracking down timing discrepancies between different tools. A common source of timing discrepancies is caused by differences in
the technology library files.
temperature
temperature string
Read-write operating_condition attribute. Specifies the operating temperature.
This attribute is useful when tracking down timing discrepancies between different tools. A common source of timing discrepancies is caused by differences in
the technology library files.
tree_type
tree_type {balanced_tree | best_case_tree | worst_case_tree}
Read-write operating_condition attribute. Specifies the wire delay estimation method.
This attribute is useful when tracking down timing discrepancies between different tools. A common source of timing discrepancies is caused by differences in
the technology library files.
pg_base_pin Attributes for Library
base_cell
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Library Attributes--pg_lib_pin Attributes for Library
pg_type
tied_to
base_cell
base_cell object
Read-only pg_base_pin attribute. Returns the base_cell that this pg_base_pin belongs to.
Related Information
Related attributes: (base_pin) base_cell
(lib_cell) base_cell
pg_type
pg_type string
Read-write pg_base_pin attribute. Specifies the pg_type info of the pin. This corresponds to the value of the pg_type Liberty pin attribute.
Related Information
Related attributes: (base_pin) pg_type
(lib_pin) pg_type
(pg_lib_pin) pg_type
tied_to
tied_to string
Read-only pg_base_pin attribute. Returns the value to which the power or ground base pin is tied.
Related Information
Related attribute: (base_pin) tied_to
(lib_pin) tied_to
(pg_lib_pin) tied_to
pg_lib_pin Attributes for Library
all_q_pin_of_d_pin
async_clear_polarity
async_preset_polarity
base_pin
bundle
capacitance
capacitance_max_fall
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Library Attributes--pg_lib_pin Attributes for Library
capacitance_max_rise
capacitance_min_fall
capacitance_min_rise
capacitance_rf
clock_polarity
drive_resistance
driver_type
fanout_load
from_lib_arcs
function
function_type
higher_drive_pin
is_always_on
is_async
is_data
is_generated_clock
is_ground
is_inverted
is_iq_function
is_iqn_function
is_isolated
is_isolation_cell_clock
is_isolation_cell_enable
is_level_shifter_enable
is_pad
is_power
is_scan_out
is_scan_out_inverted
is_std_cell_main_rail
is_tristate
is_unconnected
isolation_enable_condition
isolation_enable_phase
latch_enable_polarity
liberty_attributes
lower_drive_pin
min_capacitance
min_fanout
min_transition
mother_power
non_seq_setup_arc
permit_power_down
pg_function
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Library Attributes--pg_lib_pin Attributes for Library
pg_type
physical_connection
power_gating_class
power_gating_pin_phase
power_gating_polarity
pulse_clock
rail_connection
related_bias_pin
scan_enable_polarity
scan_in_polarity
signal_level
stack_via_list
stack_via_required
sync_clear_polarity
sync_enable_polarity
sync_preset_polarity
tied_to
to_lib_arcs
tristate
use
user_function
voltage_name
voltage_value
x_offset
y_offset
all_q_pin_of_d_pin
all_q_pin_of_d_pin pg_lib_pin
Read-only pg_lib_pin attribute. Returns the output pin(s) that corresponds to the data pin of the sequential cell. Use this for sequential cells with multiple data
pins and output pins.
Related Information
Related attribute: (lib_pin) all_q_pin_of_d_pin
async_clear_polarity
async_clear_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the asynchronous clear pin of a sequential cell.
The value none indicates that the pin is not an asynchronous clear pin.
Related Information
Related attribute: (lib_pin) async_clear_polarity
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Library Attributes--pg_lib_pin Attributes for Library
async_preset_polarity
async_preset_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the asynchronous preset pin of a sequential cell.
The value none indicates that this pin is not an asynchronous preset pin.
Related Information
Related attribute: (lib_pin) async_preset_polarity
base_pin
base_pin base_pin
Read-only pg_lib_pin attribute. Returns the reference base pin of this library pin.
Related Information
Related attribute: (lib_pin) base_pin
bundle
bundle string_list
Read-only pg_lib_pin attribute. Returns for every pin that is part of a bundle, a string of the following format:
bundle bundle_name: bundle_member bundle_member ...
For multi-bit cells, all pins that have similar timing or functionality are grouped in a bundle. The attribute value for all bundle members will be the same.
This attribute has no value for single-bit cells.
Related Information
Related attribute: (lib_pin) bundle
capacitance
capacitance string
Read-write pg_lib_pin attribute. Returns the value of the capacitance attribute from the Liberty library at the pin, cell, or library level depending on the
precedence rules.
Related Information
Related attribute: (lib_pin) capacitance
capacitance_max_fall
capacitance_max_fall max_cap
Read-only pg_lib_pin attribute. Returns the maximum fall capacitance of the pg_lib_pin.
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Library Attributes--pg_lib_pin Attributes for Library
Related Information
Related attributes: (lib_pin) capacitance_max_fall
(lib_pin) capacitance_max_rise
(pg_lib_pin) capacitance_max_rise
capacitance_max_rise
capacitance_max_rise max_cap
Read-only pg_lib_pin attribute. Returns the maximum rise capacitance of the pg_lib_pin.
Related Information
Related attributes: (lib_pin) capacitance_max_rise
(lib_pin) capacitance_max_fall
(pg_lib_pin) capacitance_max_fall
capacitance_min_fall
capacitance_min_fall min_cap
Read-only pg_lib_pin attribute. Returns the maximum fall capacitance of the pg_lib_pin.
Related Information
Related attributes: (lib_pin) capacitance_min_fall
(lib_pin) capacitance_min_rise
(pg_lib_pin) capacitance_min_rise
capacitance_min_rise
capacitance_min_rise min_cap
Read-only pg_lib_pin attribute. Returns the maximum rise capacitance of the pg_lib_pin.
Related Information
Related attributes: (lib_pin) capacitance_min_fall
(lib_pin) capacitance_min_rise
(pg_lib_pin) capacitance_min_fall
capacitance_rf
capacitance_rf string
Read-write pg_lib_pin attribute. Specifies the rise and fall capacitive load of the pin in femtofarads.
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Library Attributes--pg_lib_pin Attributes for Library
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
(lib_pin) capacitance_rf
clock_polarity
clock_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the clock pin of a sequential cell
The value none indicates that this pin is not a clock pin of a sequential cell.
Related Information
Related attribute: (lib_pin) clock_polarity
drive_resistance
drive_resistance int
Read-only pg_lib_pin attribute. Returns the approximate drive resistance of the pin in Ohm.
Related Information
Related attributes: (lib_pin) drive_resistance
driver_type
driver_type {bus_hold | open_drain | open_source | pull_up | pull_down | resistive | resistive_0 | resistive_1}
Read-only pg_lib_pin attribute. Returns the driver type of the output or inout pin.
If the pin is an inout pin, the attribute can have a driver type for the input and output. In this case the following applies:
if pull_up or pull_down is returned with open_drain, the pull_up or pull_down value will be applied to the input, while the open_drain will be applied to the
output
if the value returned is bus_hold, it will be applied to the input and output
if the value returned is not bus_hold, it will be applied to the output.
For output pins only one of the possible values can be returned.
This attribute has no value for input pins.
Related Information
Related attribute: (lib_pin) driver_type
fanout_load
fanout_load float
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Library Attributes--pg_lib_pin Attributes for Library
Read-only pg_lib_pin attribute. Specifies the internal fanout of the input pin. Resolution is 1/1000. Typical units are standard loads or pin count.
Related Information
Related attribute: (lib_pin) fanout_load
from_lib_arcs
from_lib_arcs lib_arc
Read-only pg_lib_pin attribute. Returns a list of outgoing timing arcs.
Related Information
Related attribute: (lib_pin) from_lib_arcs
function
function string
Read-only pg_lib_pin attribute. Specifies the value (Boolean expression) of an output pin as a function of the cell’s input or inout pins.
Related Information
Related attribute: (lib_pin) function
function_type
function_type {none | async_clear | async_preset | clear | clock | clock_gate_enable | data_enable | ground | power | preset | scan_out | scan_in | scan_enable
| scan_enable}
Read-only pg_lib_pin attribute. Returns the function of the pin.
Related Information
Related attribute: (lib_pin) function_type
higher_drive_pin
higher_drive_pin (lib_pin|pg_lib_pin}
Read-only pg_lib_pin attribute. Returns the path to the library pin of a cell that has the same functionality, but has a higher drive strength. If your library
contains several cells with the same functionality, this attribute points to the pin with the next higher drive strength. The attribute value on the pin with the
highest drive strength is an empty string.
Related Information
Related attribute: (pg_lib_pin) higher_drive_pin
(pg_lib_pin) lower_drive_pin
(lib_pin) lower_drive_pin
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Library Attributes--pg_lib_pin Attributes for Library
is_always_on
is_always_on {false | true}
Default: false
Read-write pg_lib_pin attribute. Indicates if this pin is an always-on pin on an always-on cell.
Related Information
Related attributes: (base_pin) is_always_on
(lib_pin) is_always_on
is_async
is_async {false| true}
Read-only pg_lib_pin attribute. Indicates whether this pin is an asynchronous pin.
Related Information
Related attribute: (lib_pin) is_async
is_data
is_data {false | true}
Read-only pg_lib_pin attribute. Indicates if this pin is a data pin.
Related Information
Related attribute: (lib_pin) is_data
is_generated_clock
is_generated_clock string
Read-only pg_lib_pin attribute. Returns the Liberty attributes and corresponding values that were specified in the generated_clock group for the lib_cell to
which this pin belongs.
The following Liberty attributes can be specified in a generated_clock group:
clock_pin
master_pin
divided_by
multipled_by
invert
duty_cycle
edges
shifts
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Related Information
Related attribute: (lib_pin) is_generated_clock
is_ground
is_ground {false | true}
Read-only pg_lib_pin attribute. Indicates if the library pin is a ground pin.
Related Information
Related attribute: (lib_pin) is_ground
is_inverted
is_inverted {false | true}
Read-only pg_lib_pin attribute. Indicates if this pin is an inverted lib pin.
Related Information
Related attribute: (lib_pin) is_inverted
is_iq_function
is_iq_function {true | false}
Read-only pg_lib_pin attribute. Indicates if this pin is an IQ (noninverting output) pin.
Related Information
Related attribute: (lib_pin) is_iq_function
is_iqn_function
is_iqn_function {true | false}
Read-only pg_lib_pin attribute. Indicates if this pin is an IQN (inverting output) pin.
Related Information
Related attribute: (lib_pin) is_iqn_function
is_isolated
is_isolated {false| true}
Read-only pg_lib_pin attribute. Indicates that this library pin is internally isolated and does not require the insertion of an external isolation cell.
Related Information
Related attribute: (lib_pin) is_isolated
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is_isolation_cell_clock
is_isolation_cell_clock {false | true}
Default: false
Read-only pg_lib_pin attribute. Clock pin of a clock isolation cell.
Related Information
Related attributes: (base_pin) is_isolation_cell_clock
(lib_pin) is_isolation_cell_clock
is_isolation_cell_enable
is_isolation_cell_enable {false | true}
Default: false
Read-write pg_lib_pin attribute. Indicates if this pin is the enable pin of an isolation cell.
Related Information
Related attributes: is_isolation_cell
(base_pin) is_isolation_cell_enable
(lib_pin) is_isolation_cell_enable
is_level_shifter_enable
is_level_shifter_enable {false | true}
Default: false
Read-write pg_lib_pin attribute. Indicates if this pin is the enable pin of a level shifter cell.
Related Information
Related attributes: (base_pin) is_level_shifter_enable
(lib_pin) is_level_shifter_enable
is_pad
is_pad {false | true}
Read-only pg_lib_pin attribute. Indicates if the pg_lib_pin is a pad pin.
Related Information
Related attribute: (lib_pin) is_pad
is_power
is_power {false | true}
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Read-only pg_lib_pin attribute. Indicates if the library pin is a power pin.
Related Information
Related attribute: (lib_pin) is_power
is_scan_out
is_scan_out {false| true}
Read-only pg_lib_pin attribute. Indicates whether the pin is a scan data output pin.
Related Information
Related attribute: (lib_pin) is_scan_out
is_scan_out_inverted
is_scan_out_inverted {false| true}
Read-only pg_lib_pin attribute. Indicates whether the pin is a scan data output pin.
Related Information
Related attribute: (lib_pin) is_scan_out_inverted
is_std_cell_main_rail
is_std_cell_main_rail {false | true}
Read-only pg_lib_pin attribute. Indicates whether this pin is a primrary power pin on the main rail in the cell.
Related Information
Related attribute: (libpin) is_std_cell_main_rail
is_tristate
is_tristate {true | false}
Read-only pg_lib_pin attribute. Indicates whetherif the pin is a tristate output.
Related Information
Related attribute: (libpin) is_tristate
is_unconnected
is_unconnected {false| true}
Read-only pg_lib_pin attribute. Indicates whether library pin is connected.
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Related Information
Related attributes: (base_pin) is_unconnected
(lib_pin) is_unconnected
isolation_enable_condition
isolation_enable_condition string
Read-only pg_lib_pin attribute. Specifies the condition of isolation for an internally isolated library pin. The ocndition is specified as a Boolean expression in
terms of input and inout pins.
Related Information
Related attribute: (lib_pin) isolation_enable_condition
isolation_enable_phase
isolation_enable_phase {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the isolation enable pin of an isolation cell.
The value none indicates that this pin is not an isolation enable pin.
Related Information
Related attribute: (lib_pin) isolation_enable_phase
latch_enable_polarity
latch_enable_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the latch enable pin of a sequential cell.
The value none indicates that this pin is not a latch input enable.
Related Information
Related attribute: (lib_pin) latch_enable_polarity
liberty_attributes
liberty_attributes string
Read-only pg_lib_pin attribute. Returns a list of Liberty attributes and values that were specified for this pin in the library.
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Related Information
Related attributes: (library) liberty_attributes
(lib_arc) liberty_attributes
(lib_cell) liberty_attributes
(lib_pin) liberty_attributes
(operating_condition) liberty_attributes
(wireload) liberty_attributes
lower_drive_pin
lower_drive_pin (lib_pin|pg_lib_pin}
Read-only pg_lib_pin attribute. Returns the path to the library pin of a cell that has the same functionality, but has a lower drive strength. If your library contains
several cells with the same functionality, this attribute points to the pin with the next lower drive strength. The attribute value on the pin with the lowest drive
strength is an empty string.
Related Information
Related attribute: (pg_lib_pin) higher_drive_pin
(lib_pin) higher_drive_pin
(lib_pin) lower_drive_pin
min_capacitance
min_capacitance float
Default: 0.0
Read-write pg_lib_pin attribute. Specifies the minimum capacitance in femtofarads that an output pin can drive.
Minimum DRC values are used to ensure the predictability of the timing by ensuring it falls within the characterization range, and to ensure that high drive cells
are only used when needed.
This attribute has no value for input pins.
Related Information
Related attribute: (lib_pin) min_capacitance
min_fanout
min_fanout float
Read-write pg_lib_pin attribute. Specifies the minimum fanout that an output pin of the library cell can drive.
Minimum DRC values are used to ensure the predictability of the timing by ensuring it falls within the characterization range, and to ensure that high drive cells
are only used when needed.
This attribute has no value for input pins.
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Related Information
Related attribute: (lib_pin) min_fanout
min_transition
min_transition float
Default: 0.0
Read-write pg_lib_pin attribute. Specifies the minimum acceptable transition time on the library pin. This attribute applies to input and output pins.
Minimum DRC values are used to ensure the predictability of the timing by ensuring it falls within the characterization range, and to ensure that high drive cells
are only used when needed.
Related Information
Related attribute: (lib_pin) min_transition
mother_power
mother_power {pg_lib_pin|lib_pin}
Read-only pg_lib_pin attribute. Returns the mother pin of the switched power of a power switch cell.
Related Information
Related attribute: (lib_pin) mother_power
non_seq_setup_arc
non_seq_setup_arc {false | true}
Read-only pg_lib_pin attribute.Specifies whether the pin has an enabled non_seq_setup timing arc.
Related Information
Related attributes: (lib_cell) non_seq_setup_arc
(lib_pin) non_seq_setup_arc
permit_power_down
permit_power_down {false | true}
Default: false
Read-write pg_lib_pin attribute. Specifies whether the power pin can bepowered down while in the isolation mode. This corresponds to the value of the
permit_power_down Liberty pin attribute.
pg_function
pg_function string
Read-only pg_lib_pin attribute. Specifies the pg_function info of the pg pin. This corresponds to the value of the pg_function Liberty attribute defined in
pg_pin construct.
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pg_type
pg_type string
Read-write pg_lib_pin attribute. Specifies the pg_type info of the pin. This corresponds to the value of the pg_type Liberty pin attribute.
Related Information
Related attributes: (base_pin) pg_type
(lib_pin) pg_type
(pg_base_pin) pg_type
physical_connection
physical_connection string
Read-only pg_lib_pin attribute. Returns the physical_connection info of the power or ground pin. This corresponds to the value of the physical_connection
Liberty pin attribute.
Related Information
Related attribute: (lib_pin) physical_connection
power_gating_class
power_gating_class string
Read-write pg_lib_pin attribute. Specifies the class of the power gating pin of a state-retention cell. The value is of the form power_pin_x, where x can take an
integer value from 1 through 5.
The value corresponds to the first part of the power_gating_pin pin Liberty attribute value.
Related Information
Related attributes: power_gating_cell
Related attributes: power_gating_cell_type
(lib_pin) power_gating_class
(lib_pin) power_gating_pin_phase
(pg_lib_pin) power_gating_pin_phase
power_gating_pin_phase
power_gating_pin_phase {none | active_low | active_high}
Default: none
Read-write pg_lib_pin attribute. Specifies the active phase of the pin of a state-retention cell.
active_low indicates that an active low signal (0) applied to this pin puts the gate in sleep mode.
active_high indicates that an active high signal (1) applied to this pin puts the gate into sleep mode.
The value of this attribute is the opposite of the value of the power_gating_pin pin Liberty attribute.
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The value none indicates that the pin is not a power gating pin.
Related Information
Related attributes: power_gating_cell
power_gating_cell_type
(pg_lib_pin) power_gating_class
(lib_pin) power_gating_class
(lib_pin) power_gating_pin_phase
power_gating_polarity
power_gating_polarity {none | active_low | active_high}
Default: none
Read-write pg_lib_pin attribute. Specifies the active phase of the pin of a state-retention cell.
active_low indicates that an active low signal (0) applied to this pin puts the gate in sleep mode.
active_high indicates that an active high signal (1) applied to this pin puts the gate into sleep mode.
The value of this attribute is the opposite of the value of the power_gating_pin pin Liberty attribute.
The value none indicates that the pin is not a power gating pin.
Related Information
Related attributes: (lib_pin) power_gating_polarity
pulse_clock
pulse_clock string
Read-only pg_lib_pin attribute. Returns the attribute value of the Liberty pulse_clock pin attribute.
Related Information
Related attributes: (lib_pin) pulse_clock
rail_connection
rail_connection string
Read-write pg_lib_pin attribute. Returns the rail connection of the pin.
Related Information
Related attributes: (lib_pin) rail_connection
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related_bias_pin
related_bias_pin (lib_pins|pg_lib_pins}
Read-only pg_lib_pin attribute. Defines all bias pins associated with this power or ground pin.f
Related Information
Related attribute: (lib_pin) related_bias_pin
scan_enable_polarity
scan_enable_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the scan enable pin of a scan flip-flop.
The value none indicates that the pin is not a scan enable pin.
Related Information
Related attribute: (lib_pin) scan_enable_polarity
scan_in_polarity
scan_in_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the scan data input pin of a scan flip-flop.
The value none indicates that the pin is not a scan data input pin.
Related Information
Related attribute: (lib_pin) scan_in_polarity
signal_level
signal_level string
Read-only pg_lib_pin attribute. Returns the name of the power supply that the pin is connected to. This information is defined in the .lib file through the
input_signal_level (output_signal_level) attribute for an input (output) pin.
Related Information
Related attribute: (lib_pin) signal_level
stack_via_list
stack_via_list string
Read-write pg_lib_pin attribute. Specifies a list of stacked vias (via pillar) to be used for this pin. Set this attribtue before spatial or physical optimization.
Related Information
Related attribute: (lib_pin) stack_via_list
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stack_via_required
stack_via_required {false |true}
Default: false
Read-write pg_lib_pin attribute. Specifies whether a list of stacked vias (via pillar) must be used for all its pins in the design. A list of stacked vias (via pillar)
must be defined for this library pin through the stack_vias_list attribute.
Related Information
Related attribute: (lib_pin) stack_via_required
sync_clear_polarity
sync_clear_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the synchronous clear pin of a sequential cell.
The value none indicates that the pin is not a synchronous clear pin.
Related Information
Related attribute: (lib_pin) sync_clear_polarity
sync_enable_polarity
sync_enable_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the synchronous enable pin of a sequential cell.
The value none indicates that the pin is not a synchronous enable pin.
Related Information
Related attribute: (lib_pin) sync_enable_polarity
sync_preset_polarity
sync_preset_polarity {active_high | active_low | none}
Read-only pg_lib_pin attribute. Returns the active phase of the synchronous preset pin of a sequential cell.
The value none indicates that this pin is not an synchronous preset pin.
Related Information
Related attribute: (lib_pin) sync_preset_polarity
tied_to
tied_to string
Read-only pg_lib_pin attribute. Returns the value to which the power or ground libpin is tied.
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Related Information
Related attribute: (base_pin) tied_to
(lib_pin) tied_to
(pg_base_pin) tied_to
to_lib_arcs
to_lib_arcs lib_arc
Read-only pg_lib_pin attribute. Returns a list of outgoing timing arcs.
Related Information
Related attribute: (lib_pin) to_lib_arcs
tristate
tristate {true | false}
Read-only pg_lib_pin attribute. Indicates if this library pin is a tristate output.
Related Information
Related attributes: (inst) tristate
(lib_cell) tristate
(lib_pin) tristate
use
use {signal | analog | clock | ground | power}
Read-only pg_lib_pin attribute. Returns the use of the pin. If the cell was read from a library in Liberty format, the use will be signal. If a LEF library is read
later, the value of this attribute might change if the pin’s use was defined through the USE statement in the LEF library.
Related Information
Related attributes: lef_library
library
(base_pin) use
(lib_pin) use
user_function
user_function string
Read-write pg_lib_pin attribute. Specifies the user-defined function for the cell on the output pin.
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Related Information
Related attribute: (lib_pin) user_function
voltage_name
voltage_name float
Read-only pg_lib_pin attribute. Returns the attribute value of the Liberty voltage_name attribute in case the library pin is a power or ground pin.
Related Information
Related attribute: (lib_pin) voltage_name
voltage_value
voltage_value float
Read-only pg_lib_pin attribute. Specifies the voltage value of the power or ground pin.
Related Information
Related attribute: (lib_pin) voltage_value
x_offset
x_offset float
Read-only pg_lib_pin attribute. Specifies the x-offset (in microns) of the corresponding LEF cell.
Related Information
Related attribute: (lib_pin) x_offset
y_offset
y_offset float
Read-only pg_lib_pin attribute. Specifies the y-offset (in microns) of the corresponding LEF cell.
Related Information
Related attribute: (lib_pin) y_offset
pin Attribute for Library
is_isolation_cell_data
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is_isolation_cell_data {false | true}
Default: no_value
Read-only pin attribute. Returns a value of true if the pin is isolation data pin type.
Related Information
Related attributes: (lib_pin) is_isolation_cell_data
(base_pin) is_isolation_cell_data
root Attributes for Library
active_operating_conditions allow_invalid_primary_power_pins_libcell allow_multiple_sync_ctrls
aocv_library auto_library_domain auto_library_domain_threshold
bank_based_multibit_inferencing base_cell_sets base_cells
bussed_pin_of_single_bitwidth_as_pin case_analysis_propagation_for_icg case_analysis_sequential_propagation
change_cap_precision convert_rising_falling_arcs_to_combo_arcs disable_when_checks
dummy_scmr_iw_cell_in_all_lds enable_library_pins_sorting_in_mmmc establish_library_during_lef_loading
exact_match_seq_sync_ctrls force_merge_combos_into_multibit_cells force_merge_isos_into_multibit_cells
force_merge_seqs_into_multibit_cells hide_mmmc_lib_clones honor_valid_location
ignore_attribute_check_during_pin_conversion ignore_pin_error_in_test_cell_function ignore_scan_combinational_arcs
ignore_sigma_arc_inconsistency init_design_mmmc_skip_inactive init_mmmc_version
large_cell_arc_threshold lbr_convert_n_piece_cap_to_2_piece lbr_convert_nochange_arcs
lbr_ignore_disable_libarc lbr_infer_cap_range_from_c1cn_dynamic_pincap_model lbr_infer_cap_range_from_dynamic_pincap_m
lbr_mmmc_enable_init_design_speedup lbr_respect_async_controls_priority lbr_seq_in_out_phase_opto
lbr_timing_library_optimize_table_data lbr_use_test_cell_seq level_shifter_groups
lib_avoid_existing_eeq_cell libraries library
library_domains library_sets library_setup_lightweight
limit_lbr_messages link_library load_libraries_of_inactive_views
map_to_master_slave_lssd mark_async_pin_using_timing_arcs mark_inconsistent_cells_as_dont_use
mark_macro_as_power_switch_cell mark_valid_lp_cell_as_usable multibit_allow_async_phase_map
multibit_auto_exclude_registers_with_exceptions multibit_cells_from_different_busses multibit_combo_name_concat_string
multibit_prefix_string multibit_preserve_inferred_instances multibit_preserved_net_check
multibit_seqs_instance_naming_style multibit_seqs_members_naming_style multibit_seqs_name_concat_string
multibit_short_prefix_string multibit_split_string opconds
operating_conditions override_library_max_drc parse_lib_moments_table
rc_corners reload_when_for_macro_cell socv_library
speed_up_read_socv speedup_library_establishment support_3Dtable_power_arc
support_aae_lib_path_change support_appending_libs support_combo_clock
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support_internal_pg_pins support_master_slave_flop support_multi_seq_elements
support_multi_seq_scan_latch support_serial_scanin_multibit_cell support_tlatch_group
suppress_syntech_messages target_library timing_analysis_socv
timing_conditions timing_enable_sr_latch_preset_clear_arcs timing_library_lookup_drv_per_frequency
timing_nsigma_multiplier timing_socv_view_based_nsigma_multiplier_mode treat_non_seq_arc_cell_as_unusable
turbo_lib_loading use_area_from_lef use_compatibility_based_grouping
use_default_related_pg_pin_for_aon use_main_cell_output_function_for_test_cell use_multibit_cells
use_multibit_combo_cells use_multibit_iso_cells use_multibit_seq_and_tristate_cells
use_nextstate_type_only_to_assign_sync_ctrls use_scan_seqs_for_non_dft wireload_mode
wireload_selection
active_operating_conditions
Syntax
active_operating_conditions <string>
Applies to:
root
library_domain
Description
Default:
Data_type: string, read only
Returns the complete path to the operating conditions that were set with the operating_conditions attribute and forces the tool to load the operating conditions
if they were not loaded yet or if they became invalid. Any problems found while loading are reported. If the operating conditions cannot be loaded, then the
attribute returns an empty string.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
report_timing
Affected by these attributes: library
operating_conditions
allow_invalid_primary_power_pins_libcell
allow_invalid_primary_power_pins_libcell {true| false}
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Description
Default: false
Data_type: bool, read/write
Treats cells with invalid primary power pins as unusable for mapping and optimization. This includes:
Cells with more than one primary_power pin with none of them marked as std_cell_main_rail=true.
Cells with more than one primary_power pin and more than one of them marked as std_cell_main_rail=true.
This does not apply to level-shifter cells. Level-shifter cells with invalid primary_power pins are treated as usable.
This attribute must be set before synthesis.
Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
allow_multiple_sync_ctrls
allow_multiple_sync_ctrls {true| false}
Description
Default: false
Data_type: bool, read/write
Allow multiple synchronous clear and preset pins.
Applies to:
root
aocv_library
aocv_library string
Description
Default: ""
Data_type: string, read/write
Specifies the list of advanced on-chip variation (AOCV) libraries.
Applies to:
library_domain
root
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auto_library_domain
Syntax
auto_library_domain {false | true}
Applies to:
root
Description
Default: false
Data_type: string, read/write
Enables automatic library_domain creation. A library domain will be created based on the nominal condition in the .lib. All libraries characterized for the same
nominal condition will than be associated with that library domain. The library domain creation can further be controlled by the auto_library_domain_threshold
attribute.
You must set the attribute before you set the library attribute.
Related Information
Related attribute: auto_library_domain_threshold
library
auto_library_domain_threshold
Syntax
auto_library_domain_threshold <float>
Applies to:
root
Description
Default: 1e-6
Data_type: double, read/write
Specifies the maximum voltage difference allowed between two libraries with the same nominal condition to be part of the same library domain. If the threshold
is exceeded, the libraries must be assigned to different library domains.
Related Information
Related attribute: auto_library_domain
bank_based_multibit_inferencing
bank_based_multibit_inferencing {false | true}
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Description
Default: false
Data_type: bool, read/write
Enables predefined multibit cell inferencing (MBCI) without limiting the multibit mapping to specific multibit library cells. The tool automatically finds a suitable
multibit cell. As this attribute enables predefined multibit cell inferencing, it implies a forced type of mapping and is therefore not QoR-driven.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attribute: map_to_multibit_register
base_cell_sets
Syntax
base_cell_sets <list_of_base_cell_sets>
Applies to:
root
Description
Default:
Data_type: base_cell_set*, read only
Returns the list of all base_cell_sets objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls command by default.
base_cells
Syntax
base_cells <list_of_base_cells>
Applies to:
base_cell_set
root
Description
Default:
Data_type: base_cell *, read only
Returns a list of all base_cell objects or base_cells of the set.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the vls command by default.
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Library Attributes--root Attributes for Library
bussed_pin_of_single_bitwidth_as_pin
Syntax
bussed_pin_of_single_bitwidth_as_pin {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Marks a bussed pin of single bit-width as a normal pin.
case_analysis_propagation_for_icg
Syntax
case_analysis_propagation_for_icg {false | always | is_seq_propagation}
Applies to:
root
Description
Default: false
Data_type: enum, read/write
Indicates whether timing case analysis should propagate logic constants through integrated clock-gating (ICG) cells.
If you set this attribute to always, the logic constants will always be propagated.
If you set this attribute to is_seq_propagation, the logic constants will only be propagated if the case_analysis_sequential_propagation attribute is set to
true.
This attribute applies only to integrated clock-gating cells without statetable group.
This attribute must be set before you load the library.
case_analysis_sequential_propagation
Syntax
case_analysis_sequential_propagation {true | false}
Applies to:
root
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Description
Default: false
Data_type: bool, read/write
Indicates whether timing case analysis should propagate logic constants through sequential cells.
Example
set_db / .case_analysis_sequential_propagation false
change_cap_precision
change_cap_precision {true| false}
Description
Default: false
Data_type: bool, read/write
Changes the default capacitance value to 0.001ff.
Example
set_db / .change_cap_precision true
Applies to:
root
convert_rising_falling_arcs_to_combo_arcs
Syntax
convert_rising_falling_arcs_to_combo_arcs {false| true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether to convert the rising or falling edge arcs of non-clocked pins having no valid setup arc to combinational arcs.
If set to false, the tool will treat the non-clocked pin with the clock-edge arcs as a clock pin, and the cell will be treated as sequential cell.
If set to true, the tool will convert the rising or falling edge arcs of non-clocked pins having no valid setup arc to combinational arcs, and the lib_cell will be
treated as a combinational cell.
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Library Attributes--root Attributes for Library
Related Information
Affects this command: report_timing
Affects these attributes: is_clock
sequential
disable_when_checks
disable_when_checks {true| false}
Default: true
Data_type: bool, read/write
Disables the processing of long when condition having bus operands.
Applies to:
root
dummy_scmr_iw_cell_in_all_lds
Syntax
dummy_scmr_iw_cell_in_all_lds {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Copies dummy std_cell_main_rail IW cell from it's library domain to all other library domains.
enable_library_pins_sorting_in_mmmc
enable_library_pins_sorting_in_mmmc {true| false}
Description
Default: true
Data_type: bool, read/write
Enables library pins sorting in MMMC flow.
Applies to:
root
establish_library_during_lef_loading
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Library Attributes--root Attributes for Library
Syntax
establish_library_during_lef_loading {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Establish the library during LEF loading.
exact_match_seq_sync_ctrls
exact_match_seq_sync_ctrls {true| false}
Description
Default: false
Data_type: bool, read/write
If set to true, the tool will try to force map the synchronous flops inferred from RTL to complex library flip-flops with corresponding synchronous inputs
regardless of QoR. If the library does not have the appropriate synchronous control libcells, simple flip-flops and combinational logic will be used.
It is recommended to set this attribute before reading the libraries to reduce the runtime of processing the libraries.
This attribute may have a positive impact on clock gating coverage due to the explicit enable.
Applies to:
root
Related Information
Set and Reset Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: syn_map
Related attribute exact_match_seq_async_ctrls
force_merge_combos_into_multibit_cells
force_merge_combos_into_multibit_cells {false | true}
Description
Default: false
Data_type: bool, read/write
Merges single-bit combinational instances into an appropriate multibit combinational instance independent of the impact on the QoR. When enabled, multibit
cell inferencing will occur even if it degrades the delay, power, or area QOR of the design. This is useful for increasing multibit coverage but might negatively
impact the QoR.
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Example
Assume two single bit instances g1 and 2 can be merged into a multibit instance. The library has three suitable multibit cells: 2g1x1, 2g1x2, and 2g1x3. Consider
only force_merge_combos_into_multibit_cells enabled:
set_db force_merge_combos_into_multibit_cells true
In this case, the tool computes the total cost with timing for each of the possible multibit lib_cell candidates. The best candidate for multibit cell merging will be
chosen, irrespective of whether it improves or degrades the delay QoR of the design.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Affected by this attribute: use_multibit_cells
Related attributes: dont_merge_multibit
force_merge_isos_into_multibit_cells
force_merge_seqs_into_multibit_cells
merge_multibit
map_to_multibit_register
force_merge_isos_into_multibit_cells
force_merge_isos_into_multibit_cells {true | false}
Description
Default: false
Data_type: bool, read/write
Merges single-bit isolation instances into an appropriate multibit isolation instance independent of the impact on the QoR. When enabled, multibit cell
inferencing will occur even if it degrades the delay, power, or area QOR of the design. This is useful for increasing multibit coverage but might negatively impact
the QoR.
Example
Assume two single bit instances g1 and 2 can be merged into a multibit instance. The library has three suitable multibit cells: 2g1x1, 2g1x2, and 2g1x3. Consider
only force_merge_isos_into_multibit_cells enabled:
set_db force_merge_isos_into_multibit_cells true
In this case, the tool computes the total cost with timing for each of the possible multibit lib_cell candidates. The best candidate for multibit cell merging is
chosen, irrespective of whether it improves or degrades the delay QoR of the design.
Applies to:
root
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Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Affected by this attribute: use_multibit_cells
Related attributes: dont_merge_multibit
force_merge_combos_into_multibit_cells
force_merge_seqs_into_multibit_cells
merge_multibit
map_to_multibit_register
force_merge_seqs_into_multibit_cells
force_merge_seqs_into_multibit_cells {false | true}
Description
Default: false
Data_type: bool, read/write
Merges single-bit sequential instances into an appropriate multibit sequential instance independent of the impact on the QoR. When enabled, multibit cell
inferencing will occur even if it degrades the delay, power, or area QOR of the design. This is useful for increasing multibit coverage but might negatively impact
the QoR.
Example
Assume two single bit instances reg1 and reg2 can be merged into a multibit instance. The library has three suitable multibit cells: dual1, dual2, and dual3 and
force_merge_seqs_into_multibit_cells enabled:
set_db / .force_merge_seqs_into_multibit_cells true
In this case, the tool computes the total cost with timing for each of the possible multibit lib_cell candidates. The best candidate for multibit cell merging will be
chosen irrespective of whether it improves or degrades the delay QoR of the design.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Affected by this attribute: use_multibit_cells
Related attributes: dont_merge_multibit
force_merge_combos_into_multibit_cells
force_merge_isos_into_multibit_cells
merge_multibit
map_to_multibit_register
hide_mmmc_lib_clones
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Library Attributes--root Attributes for Library
Syntax
hide_mmmc_lib_clones {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls whether the cloned MMMC library_sets and timing_conditions are visible in the virtual directory (Vdir).
honor_valid_location
honor_valid_location {true| false}
Description
Default: false
Data_type: bool, read/write
Controls whether or not to honor the valid location defined on the power intent library cells. By default, the valid location defined in the library will be ignored. If
you set this attribute to true, the valid location defined in the library will be honored and passed on to downstream tools.
Applies to:
root
Related Information
Set by this command: commit_power_intent
ignore_attribute_check_during_pin_conversion
ignore_attribute_check_during_pin_conversion {true| false}
Description
Default: true
Data_type: bool, read/write
Ignores the liberty attributes check while converting the library's logical pin defined as power or ground in LEF.
Applies to:
root
ignore_pin_error_in_test_cell_function
ignore_pin_error_in_test_cell_function {true| false}
Description
Default: false
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Data_type: bool, read/write
Controls whether to ignore the pin errors in the test cell function. This attribute must be set before you read in the libraries.
Applies to:
root
Related Information
Affects this command: read_libs
Related attributes: library
lbr_use_test_cell_seq
ignore_scan_combinational_arcs
ignore_scan_combinational_arcs {false | true}
Description
Default: true
Data_type: bool, read/write
Controls whether to ignore the combinational arcs from scan input pins to output pins of scan flip-flops during timing analysis and optimization.
Example
set_db / .ignore_scan_combinational_arcs false
Applies to:
root
Related Information
Affects this command: report_timing
ignore_sigma_arc_inconsistency
Syntax
ignore_sigma_arc_inconsistency {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read only
Indicates whether sigma arc inconsistency is ignored across views during MMMC consistency check.
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init_design_mmmc_skip_inactive
Syntax
init_design_mmmc_skip_inactive {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the establishment of library and skipping the inactive library domain in MMMC flow for init_design speedup.
init_mmmc_version
Syntax
init_mmmc_version <1 | 2>
Applies to:
root
Description
Default: 2
Data_type: int, read/write
Specifies the MMMC version (1 or 2) used by read_mmmc.
In common UI, only version 2 is supported.
In legacy UI, both versions 1 and 2 are supported.
large_cell_arc_threshold
large_cell_arc_threshold integer
Description
Default: 200
Data_type: int, read/write
Specifies the threshold arc count to create a separate binary decision diagram (BDD) for the cell. Cells with leakage arc count greater than this value have a
separate BDD for power computation.
Applies to:
root
lbr_convert_n_piece_cap_to_2_piece
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lbr_convert_n_piece_cap_to_2_piece {true | false}
Description
Default: false
Data_type: bool, read/write
Enables the tool to convert an n-piece capacitance model to a two-piece capacitance model.
Applies to:
root
lbr_convert_nochange_arcs
Syntax
lbr_convert_nochange_arcs (true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Converts nochange arcs to setup/hold arcs.
lbr_ignore_disable_libarc
Syntax
lbr_ignore_disable_libarc {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Ignores the library arcs disabled through 'set_disable_timing' command.
lbr_infer_cap_range_from_c1cn_dynamic_pincap_model
lbr_infer_cap_range_from_c1cn_dynamic_pincap_model {true| false}
Description
Default: false
Data_type: bool, read/write
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Enables Syntech support to infer cap range from n-piece dynamic pincap.
Applies to:
root
lbr_infer_cap_range_from_dynamic_pincap_model
lbr_infer_cap_range_from_dynamic_pincap_model {true| false}
Description
Default: false
Data_type: bool, read/write
Enables the tool to override any static capacitance from the library with an inferred capacitance.
Applies to:
root
lbr_mmmc_enable_init_design_speedup
Syntax
lbr_mmmc_enable_init_design_speedup {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read only
Controls the establishment of library in MMMC flow.
lbr_respect_async_controls_priority
lbr_respect_async_controls_priority {true| false}
Description
Default: true
Data_type: bool, read/write
Instructs the library parser to consider the asynchronous control pins priority description of sequential libcells from the Liberty files. This enables the implicit
implementation of the priority logic by the sequential library cells during mapping.
Set this attribute to false if you want the priority logic to be implemented explicitly by combinational gates. It is recommended to set this attribute before reading
the libraries to reduce the runtime of processing the libraries.
Applies to:
root
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Related Information
Affects this attribute: library
lbr_seq_in_out_phase_opto
lbr_seq_in_out_phase_opto {true| false}
Description
Default: false
Data_type: bool, read/write
Enables the tool to perform the following transformations during synthesis if they result in a QoR improvement.
If the original netlist has no inverters at the d input and the q output, the tool can add inverters at this input and this output during mapping.
A simple flip-flop can be converted to a flop with inversion at the d input and the q output
If the original netlist has an inverter at the d input and the q output, the tool can remove both inverters from this input and this output during mapping.
A flop with inversion at the d input and the q output can be converted to a simple flop by removing the inversions.
If the original netlist has an inverter at the d input, the tool can move the inverter from the d input to the q output of the sequential cell.
This can be referred to as propagating an inverter through the sequential cell, or also bubble pushing.
Verification of these transforms requires compute-expensive phase mapping in Conformal. The affected key points will be reported as inverted
equivalents.
Inverting the d input and q output also inverts the sense of the preset (set) and clear (reset) signals (both synchronous and asynchronous). A clear
sequential libcell with inverted d input and q output becomes a preset libcell. And a preset libcell becomes a clear one. The preset/clear swapping can
only happen if we invert the d and q phases.
This is useful when the RTL functionality requires a preset function but the technology library has only a reset flop (or vice-versa).
It is recommended to set this attribute before reading the libraries to reduce the runtime of processing the libraries.
By default, these operations are not performed because they can impact verification of the design.
Example
module invert_d_q (q, q1, d, clk, rstn, pstn);
input clk, rstn, pstn, d; output q, q1; reg q, q1;
always @(posedge clk)
begin
if (!rstn) q = 1’b0;
else q = d;
if (!pstn) q1 = 1’b1;
else q1 = d;
end
endmodule
By default, this RTL description is synthesized into a reset flop and a preset flop.
If the attribute is set to true and if the library has only reset flops, the preset flop will be mapped to a reset flop.
If the attribute is set to true and if the library has only preset flops, the reset flop will be mapped to a preset flop.
Applies to:
root
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Library Attributes--root Attributes for Library
Related Information
Translating Phase Mapping in Genus Interface to Conformal.
Affects this command: syn_map
write_do_lec
lbr_timing_library_optimize_table_data
lbr_timing_library_optimize_table_data {true | false}
Description
Default: false
Data_type: bool, read/write
Enables Syntech support to optimize table data.
Applies to:
root
lbr_use_test_cell_seq
lbr_use_test_cell_seq {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether or not to use the test cell function if the main cell function is unusable.
This attribute must be set before you read in the libraries.
Applies to:
root
Related Information
Affects this command: read_libs
Related attributes: ignore_pin_error_in_test_cell_function
library
level_shifter_groups
Syntax
level_shifter_groups <list_of_level_shifter_groups>
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Applies to:
root
Description
Default:
Data_type: level_shifter_group*, read only
Returns the list of all level_shifter_group objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
lib_avoid_existing_eeq_cell
Syntax
lib_avoid_existing_eeq_cell {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Set this attribute to true to avoid library defined EEQ cells. When enabled, library EEQ cells will be set to soft avoid. By default, library EEQ cells are not
avoided.
libraries
Syntax
libraries <list_of_libraries>
Applies to:
root
library_set
Description
Default:
Data_type: library*, read only
Returns the list of all library objects.
Example
get_db library_set:wcl_slow .libraries
library:wcl_slow/slow library:wcl_slow/PLL_worst library:wcl_slow/CDK_S128x16 library:wcl_slow/CDK_S256x16 library:wcl_slow/CDK_R512x16
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library
Syntax
library {{lib [lib]...} [{lib [lib]...}]...}
Applies to:
library_domain (read/write)
root (read/write)
lib_cell (read only)
operating_condition (read only)
wireload (read only)
wireload_selection (read only)
Description
Default:
Data_type: string (library_domain, root), library (lib_cell, operating_condition, wireload, wireload_selection)
library_domain Sets the target library for technology mapping for the specified library domain. If you have a multi-voltage design, you must specify
this attribute on the appropriate library domain.
root Sets the target library for technology mapping. If you have a single voltage design, you must specify this attribute on root.
You can specify a single library or a Tcl list of library lists. Each library list is also a Tcl list. Each library must be found in the library search path (specified
through the lib_search_path attribute). The first library in each list is considered the master library to which the content of the other libraries in that list is
appended.
The library attribute also supports libraries that have been compressed with GNU Zip (.gz extension).
The information in the appended libraries overwrites the corresponding information in the master library. However, Genus fails on loading the libraries
if the delay models in the appended libraries differ from the delay models in the master library.
lib_cell Returns the name of the library that this lib_cell belongs to.
operating Returns the name of the library that this operating condition is associated with.
_condition
wireload Returns the name of the library that this wireload model belongs to.
wireload_selection Returns the name of the library that this wireload selection table belongs to.
Related Information
Affected by this command: create_library_domain
Affected by this attribute: init_lib_search_path
Related attribute: support_appending_libs
library_domains
Syntax
library_domains <list_of_library_domains>
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Applies to:
power_domain
root
Description
Default:
Data_type: library_domain*, read only
Returns the list of all library_domain objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
library_sets
Syntax
library_sets <library_sets>
Applies to:
root
timing_condition
Description
Default:
Data_type: library_set*, read only
Returns the list of all library_set objects/timing conditions.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
library_setup_lightweight
Syntax
library_setup_lightweight {ignore_socv | ignore_ccs | ignore_all | none}
Applies to:
root
Description
Default: none
Data_type: enum, read/write
Indicates the groups such as socv/ccs that need to be ignored while loading library. This attribute takes string as an argument and the valid values are:
ignore_socv Load libraries ignoring socv groups.
ignore_ccs Load libraries ignoring ccs groups
ignore_all Load libraries ignoring ccs/socv groups
none Do not load libraries without ignoring ccs/socv
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This attribute must be set before you load the library.
Examples
This loads the libraries by ignoring ccs group:
set_db library_setup_lightweight ignore_ccs
This loads the libraries by ignoring socv group:
set_db library_setup_lightweight ignore_socv
This loads the libraries by ignoring socv and ccs group:
set_db library_setup_lightweight ignore_all
limit_lbr_messages
limit_lbr_messages {true | false}
Description
Default: true
Data_type: bool, read/write
Controls the printing of the LBR messages. By default, each LBR message will be printed maximum twenty times for each library that is being read. If for any
LBR message, the max_print message object attribute has a lower limit, this limit will take precedence. If you set this attribute to false, all LBR messages will
be printed to the logfile.
Applies to:
root
Related Information
Related attribute: max_print
link_library
link_library string
Description
Default: ""
Data_type: string, read/write
Specifies the list of link libraries. Link libraries are technology libraries which the tool uses to resolve cell references. The link libraries contain the descriptions
of cells (macros like RAMS, pads, PLLs, and so on) in a mapped netlist.
Applies to:
library_domain
root
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Library Attributes--root Attributes for Library
Related Information
Related attribute: target_library
load_libraries_of_inactive_views
Syntax
load_libraries_of_inactive_views {0 | 1 | 2}
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Loads libraries of inactive views in different modes depending on value provided with attribute as an argument. This attribute takes integer as an argument and
the valid values are:
0 Do not load libraries of inactive views.
1 Load libraries of inactive views fully.
2 Load libraries of inactive views in light weight.
Examples
This does not load the libraries of inactive views, loads only when a view is made active using command set_analysis_view:
set_db loading_libraries_of_inactive_views 0
This loads the libraries of inactive views in full weight mode, similar to loading of active views:
set_db loading_libraries_of_inactive_views 1
This loads the libraries of inactive views in light weight mode, this mode is used to save memory usage when number of libraries are high in count:
set_db loading_libraries_of_inactive_views 2
map_to_master_slave_lssd
Syntax
map_to_master_slave_lssd {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
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Specifies to recognize master-slave flip-flops as valid sequential cells and not as timing models during library parsing and mapping. You must set this attribute
before reading the libraries. The slave clock, identified by the Liberty clocked_on_also attribute in the ff group of the library cell, will be used as the main
(triggering) clock pin of the cell.
Related Information
Scan Cell Requirements in Genus Library Guide.
Affects these commands: syn_map
syn_opt
Affects this attribute: lssd_master_clock
mark_async_pin_using_timing_arcs
mark_async_pin_using_timing_arcs {true | false}
Description
Default: true
Data_type: bool, read/write
Marks library pin with recovery or removal timing arcs as asynchronous.
Applies to:
root
mark_inconsistent_cells_as_dont_use
Syntax
mark_inconsistent_cells_as_dont_use {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Handle inconsistency by marking the cells as 'dont_use'.
mark_macro_as_power_switch_cell
mark_macro_as_power_switch_cell {true | false}
Description
Default: false
Data_type: bool, read/write
Marks the power switch cell defined as macro as the power switch cell.
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Applies to:
root
mark_valid_lp_cell_as_usable
mark_valid_lp_cell_as_usable {true | false}
Description
Default: false
Data_type: bool, read/write
Marks valid low power cells as usable.
Applies to:
root
multibit_allow_async_phase_map
multibit_allow_async_phase_map {inherited | true | false}
Description
Default: true (root), inherited (inst and module)
Data_type: bool (root), enum (inst and module), read/write
Controls whether asynchronous pins can be interchanged during multibit cell inferencing. By default, asynchronous pin phase mapping will be enabled.
The values are:
inherited Inherits the value from the multibit_allow_async_phase_map root attribute.
false Prevents phase inversion on the module during multibit mapping.
true Allows phase inversion on the module during multibit mapping.
Examples
Consider the following netlist after mapping and before incremental optimization:
module test(resetn, clk, in, out);
input resetn, clk;
input [3:0] in;
output [3:0] out;
DFSF cnt_0_reg[0] (.SDN (resetn), .CP (clk), .D(in[0]), .Q (out[0] ));
DFCF cnt_0_reg[1] (.CDN (resetn), .CP (clk), .D(in[1]), .Q (out[1] ));
DFCF cnt_0_reg[2] (.CDN (resetn), .CP (clk), .D(in[2]), .Q (out[2] ));
DFSF cnt_0_reg[3] (.SDN (resetn), .CP (clk), .D(in[3]), .Q (out[3] ));
endmodule
The netlist contains two clear sequential libcells and two preset sequential libcells.
When the multibit_allow_async_phase_map attribute is set to true (default), you allow the tool to map clear sequential cells to a preset sequential cells
while inverting the D input and Q output if this allows multibit inferencing. For the previous netlist, that means that cells DFSF and DFCF can be combined in
a multibit register DUALDFSF. The D inputs and the Q outputs of the DFCF cell are inverted.
module test(resetn, clk, in, out);
input resetn, clk;
input [3:0] in;
output [3:0] out;
wire resetn, clk;
wire [3:0] in;
wire [3:0] out;
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wire n_31, n_32, n_43, n_44;
DUALDFSF \CDN_MBIT_cnt_0_reg[0_1] (.SDN (resetn), .CP (clk), .D1(in[0]),
.D2 (n_31), .Q1 (out[0]), .Q2 (n_32));
INV g5(.I (in[1]), .ZN (n_31));
INV g6(.I (n_32), .ZN (out[1]));
DUALDFSF \CDN_MBIT_cnt_0_reg[2_3] (.SDN (resetn), .CP (clk), .D1(n_43),
.D2 (in[3]), .Q1 (n_44), .Q2 (out[3]));
INV g23(.I (in[2]), .ZN (n_43));
INV g24(.I (n_44), .ZN (out[2]));
endmodule
When the multibit_allow_async_phase_map attribute is set to false, the clear sequential cells cannot be mapped to preset ones, and consequently the
DFCF cells cannot be replaced with a multibit register in this case, while the two DFSF cells are mapped to a multibit register.
module test(resetn, clk, in, out);
input resetn, clk;
input [3:0] in;
output [3:0] out;
wire resetn, clk;
wire [3:0] in;
wire [3:0] out;
DFCF cnt_0_reg[1] (.CDN (resetn), .CP (clk), .D (in[1]),
.Q (out[1]));
DFCF cnt_0_reg[2] (.CDN (resetn), .CP (clk), .D (in[2]),
.Q (out[2]));
DUALDFSF \CDN_MBIT_cnt_0_reg[0_3] (.SDN (resetn), .CP (clk),
.D1(in[0]), .D2 (in[3]), .Q1 (out[0]), .Q2 (out[3]));
endmodule
Applies to:
inst
module
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attributes: bit_width
multibit_prefix_string
use_multibit_cells
multibit_auto_exclude_registers_with_exceptions
multibit_auto_exclude_registers_with_exceptions {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether timing exception checks should be done on sequential instances to exclude them from multibit merging. By default, the exception checks are
skipped and merging happens for flops with identical exceptions only when all exceptions are transferable to the multibit cell that is created. Enabling this
attribute will automatically apply dont_merge_multibit instance attribute on all sequential instances with exceptions.
Example
Assume two single bit instances reg1 and reg2 have the same timing exceptions. The library has a two-bit multibit cell.
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If multibit_auto_exclude_registers_with_exceptions is set to true, then reg1 and reg2 will not be considered as candidates for multibit merging.
If multibit_auto_exclude_registers_with_exceptions is set to false, then reg1 and reg2 will be merged into a multibit libcell.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
multibit_cells_from_different_busses
multibit_cells_from_different_busses {true | false}
Description
Default: true
Data_type: bool, read/write
If this attribute remains false, only the instances with the same basename are merged together. If this attribute is set to true, the tool can merge single-bit cells
from different banks (also called busses) into a single, multibit cell. For example, four single-bit flops below:
p_reg[4], p_reg[5], q_reg[8] and q_reg[9]
can be merged into one four-bit flop:
p_reg[4_5]_q_reg[8_9]
The single-bit cells affected by this attribute include: flip-flops, latches, tristate buffers, and combinational cells.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Affected by this attribute: multibit_seqs_members_naming_style
Related attributes: bit_width
use_multibit_cells
multibit_combo_name_concat_string
Syntax
multibit_combo_name_concat_string <string>
Applies to:
root
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Library Attributes--root Attributes for Library
Description
Default: _MB_
Data_type: string, read/write
Specifies the separator string to be used in the name of the multibit combinational and special low power cells. The recommended values for the verification
flow are _MB_ and _mb_.
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
multibit_prefix_string
multibit_prefix_string <string>
Description
Default: CDN_MBIT_
Data_type: string, read/write
Specifies the prefix to be used to name multibit instances. The recommended value for the verification flow is CDN_MBIT_.
Example
Consider the following netlist after mapping and before incremental optimization:
module test(resetn, clk, in, out);
input resetn, clk;
input [3:0] in;
output [3:0] out;
DFSF cnt_0_reg[0] (.SDN (resetn), .CP (clk), .D(in[0]), .Q (out[0] ));
DFCF cnt_0_reg[1] (.CDN (resetn), .CP (clk), .D(in[1]), .Q (out[1] ));
DFCF cnt_0_reg[2] (.CDN (resetn), .CP (clk), .D(in[2]), .Q (out[2] ));
DFSF cnt_0_reg[3] (.SDN (resetn), .CP (clk), .D(in[3]), .Q (out[3] ));
endmodule
The netlist contains two clear sequential libcells and two preset sequential libcells.
Assume the multibit_allow_async_phase_map attribute is also set to true. For the previous netlist, that means that cells DFSF and DFCF can be combined in a
multibit register DUALDFSF.The D inputs and the Q outputs of the DFCF cell are inverted. Assume the multibit_prefix_string attribute is set to MBIT_. The
resulting netlist will look like:
module test(resetn, clk, in, out);
input resetn, clk;
input [3:0] in;
output [3:0] out;
wire resetn, clk;
wire [3:0] in;
wire [3:0] out;
wire n_31, n_32, n_43, n_44;
DUALDFSF \MBIT_cnt_0_reg[0_1] (.SDN (resetn), .CP (clk), .D1(in[0]),
.D2 (n_31), .Q1 (out[0]), .Q2 (n_32));
INV g5(.I (in[1]), .ZN (n_31));
INV g6(.I (n_32), .ZN (out[1]));
DUALDFSF \MBIT_cnt_0_reg[2_3] (.SDN (resetn), .CP (clk), .D1(n_43),
.D2 (in[3]), .Q1 (n_44), .Q2 (out[3]));
INV g23(.I (in[2]), .ZN (n_43));
INV g24(.I (n_44), .ZN (out[2]));
endmodule
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Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attributes: bit_width
use_multibit_cells
multibit_seqs_members_naming_style
multibit_preserve_inferred_instances
multibit_preserve_inferred_instances {false | true}
Description
Default: false
Data_type: bool, read/write
Specifies whether to preserve multibit instances that are inferred during incremental optimization. If set to true, the preserve attribute for all multibit instances is
set to size_delete_ok. This preserve setting prevents any optimization step down the flow from breaking the multibit cells. For example, multibit tristate and
combinational cells can get optimized in many places.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
multibit_preserved_net_check
multibit_preserved_net_check {false | true}
Description
Default: false
Data_type: bool, read/write
Controls whether instances can be merged into multibit instances if the connected nets are marked preserved. Set this attribute to true to prevent multibit
merging when any of the nets connected to the instances are marked preserved.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
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multibit_seqs_instance_naming_style
multibit_seqs_instance_naming_style {concat | auto | short}
Description
Default: concat
Data_type: string, read/write
Controls the naming of inferred multibit (flops, latches and tristates) instances.
This attribute can have the following values:
auto Creates the name of the multibit instance based on busses of merged instances.
If the instances belong to the same bus, the name of the multibit instance starts with the bus name followed by the range of the merged bit-
indices.
If the instances belong to different busses, the name of the multibit instance contains each bus name followed by the range of corresponding bit-
indices.
concat Creates the name of the multibit instance by concatenating the names of merged instances.
short Creates the name of the multibit instance by using the bus name for only the first index of a multibit cell if all instances belong to the same bus.
If the multibit instance contains single bits from different busses, the short naming style has no effect and the concat style is followed.
Examples
Consider the following instances:
SCFFQXC1 I3256 (.CLK(CLK), .DATA(D1), .Q(Q1));
SCFFQXC1 I3267 (.CLK(CLK), .DATA(D2), .Q(Q2));
SCFFQXC1 I3312 (.CLK(CLK), .DATA(D3), .Q(Q3));
SCFFQXC1 I3439 (.CLK(CLK), .DATA(D4), .Q(Q4));
SCFFQXC1 I3572 (.CLK(CLK), .DATA(D5), .Q(Q5));
SCFFQXC1 I4188 (.CLK(CLK), .DATA(D6), .Q(Q6));
SCFFQXC1 I4357 (.CLK(CLK), .DATA(D7), .Q(Q7));
SCFFQXC1 I4567 (.CLK(CLK), .DATA(D8), .Q(Q8));
Using the auto setting:
set_db / .multibit_seqs_instance_naming_style auto
The multibit instances are named as follows:
SCCSGFF4QXC1 I3256_3439(.CLK (CLK), .DATA0 (D1), .DATA1 (D2),
.DATA2 (D3), .DATA3 (D4), .Q0 (Q1), .Q1 (Q2), .Q2 (Q3), .Q3 (Q4));
SCCSGFF4QXC1 I3572_4567(.CLK (CLK), .DATA0 (D5), .DATA1 (D6),
.DATA2 (D7), .DATA3 (D8), .Q0 (Q5), .Q1 (Q6), .Q2 (Q7), .Q3 (Q8));
Using the concat setting:
set_db / .multibit_seqs_instance_naming_style concat
The multibit instances are named as follows:
SCCSGFF4QXC1 I3256_I3267_I3312_I3439(.CLK (CLK), .DATA0 (D1), .DATA1 (D2),
.DATA2 (D3), .DATA3 (D4), .Q0 (Q1), .Q1 (Q2), .Q2 (Q3), .Q3 (Q4));
SCCSGFF4QXC1 I3572_I4188_I4357_I4567(.CLK (CLK), .DATA0 (D5), .DATA1 (D6),
.DATA2 (D7), .DATA3 (D8), .Q0 (Q5), .Q1 (Q6), .Q2 (Q7), .Q3 (Q8))
Consider the following instances:
a_reg[2]
a_reg[1]
b_reg[2]
b_reg[1]
a_reg[0]
b_reg[0]
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Using the short setting:
set_db / .multibit_seqs_instance_naming_style short
The multibit instances are named as follows:
CDN_MBIT_a_reg[0]_MB_a_reg[1]_MB_a_reg[2]_MB_b_reg[0]
CDN_MBIT_b_reg[1]_MB_[2]
The short naming style was not used for the first multibit instance because it contains single bits from two different busses. The short naming style
was used for the second multibit instance because both single bits belong to the same bus. The bus name is only shown for the first bit.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attribute: multibit_seqs_name_concat_string
multibit_seqs_members_naming_style
multibit_seqs_members_naming_style {list_of_strings}
Description
Default: "%s%d" "%s%d_reg" "%s_%d_" "%s_%d_reg" {"%s[%d]} {%s[%d]_reg}
Data_type: string, read/write
Controls which single-bit sequential instances can be merged into a multibit sequential instance during synthesis. The attribute value can contain a list of
naming styles of the single-bit instances for which merging can be done.
Examples
To combine the single bit cells a1 and a2, the following naming style must be part of the attribute value:
set_db / .multibit_seqs_members_naming_style "%s%d"
To combine the single bit cells a1_reg and a2_reg, the following naming style must be part of the attribute value:
set_db / .multibit_seqs_members_naming_style "%s%d_reg"
To combine the single bit cells a[1] and a[2], the following naming style must be part of the attribute value:
set_db / .multibit_seqs_members_naming_style {%s[%d]}
To combine the single bit cells, a[1]_reg and a[2]_reg, the following naming style must be part of the attribute value:
set_db / .multibit_seqs_members_naming_style {%s[%d]_reg}
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Affects this attribute: multibit_cells_from_different_busses
multibit_seqs_name_concat_string
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multibit_seqs_name_concat_string <string>
Description
Default: _MB_
Data_type: string, read/write
Specifies the separator string to be used in the name of the multibit sequential instance created by concatenating the names of merged instances. The
recommended values for the verification flow are _MB_ and _mb_.
Example
set_db / .multibit_seqs_name_concat_string _mb_
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Affects this attribute: multibit_seqs_instance_naming_style
multibit_short_prefix_string
multibit_short_prefix_string string
Description
Default: _CDN_CPX_
Data_type: string, read/write
Specifies the string to separate the base name from the indexes of the multibit instances in those cases where the merged instances were created from the
same bus, and the multibit instance name was created using the short naming style. The default value is recommended for the verification flow.
Example
Consider the following instances:
a_reg[0]
a_reg[1]
a_reg[2]
If the following attribute settings are used:
set_db / .multibit_seqs_instance_naming_style short
set_db / .multibit_short_prefix_string _CDN_CPX_
The multibit instance will be named as follows:
CDN_MBIT_a_reg_CDN_CPX_[0]_MB_[1]_MB_[2]
Applies to:
root
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Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Affects this attribute: multibit_seqs_instance_naming_style
multibit_split_string
multibit_split_string string
Description
Default: _split_
Data_type: string, read/write
Specifies the string to be used to name single bit instances when the netlist that was read in already contains multibit cells.
When the tool merges single bit instances into a multibit instance, it keeps track of the original names during the current session. If the tool splits the multibit cell
back into single bits in the same session, it can reuse the original names. If the merging and splitting occur in different sessions, the original names are not
stored and the tool uses this attribute value to create the single bit names.
Example
Assume the following netlist was read in during the current session:
module PIPO_REGISTER_REGDIMENSION9(CLK, RSN, Inpbus, Outbus);
input CLK, RSN;
input [9:0] Inpbus;
output [9:0] Outbus;
HS65V_GSH_4SDFPQX18 \OutbusintCK_reg[0_3] (.CP (CLK), .\D[0]
(Inpbus[0]), .\D[1] (Inpbus[1]), .\D[2] (Inpbus[2]), .\D[3]
(Inpbus[3]), .TI (Outbus[0]), .TE (1’b0), .\Q[0] (Outbus[0]),
.\Q[1] (Outbus[1]), .\Q[2] (Outbus[2]), .\Q[3] (Outbus[3]));
endmodule
While performing incremental optimization, the multibit cell is split again into single bit instances. The tool uses the value of the multibit_split_string attribute
to create the single bit names. Assume the attribute was set to _user_, the netlist written out would look as follows:
module PIPO_REGISTER_REGDIMENSION9(CLK, RSN, Inpbus, Outbus);
input CLK, RSN;
input [9:0] Inpbus;
output [9:0] Outbus;
wire CLK, RSN;
wire [9:0] Inpbus;
wire [9:0] Outbus;
wire UNCONNECTED, UNCONNECTED0, UNCONNECTED1, UNCONNECTED2;
SDFFX4 \OutbusintCK_reg[0_3]_user_0 (.CK (CLK), .D (Inpbus[0]), .SI
(Outbus[0]), .SE (1’b0), .Q (Outbus[0]), .QN (UNCONNECTED));
SDFFX4 \OutbusintCK_reg[0_3]_user_1 (.CK (CLK), .D (Inpbus[1]), .SI
(Outbus[1]), .SE (1’b0), .Q (Outbus[1]), .QN (UNCONNECTED0));
SDFFX4 \OutbusintCK_reg[0_3]_user_2 (.CK (CLK), .D (Inpbus[2]), .SI
(Outbus[2]), .SE (1’b0), .Q (Outbus[2]), .QN (UNCONNECTED1));
SDFFX4 \OutbusintCK_reg[0_3]_user_3 (.CK (CLK), .D (Inpbus[3]), .SI
(Outbus[3]), .SE (1’b0), .Q (Outbus[3]), .QN (UNCONNECTED2));
endmodule
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
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Library Attributes--root Attributes for Library
Affects this command: elaborate
Related attributes: bit_width
use_multibit_cells
multibit_seqs_members_naming_style
opconds
Syntax
opconds <list_of_opconds>
Applies to:
root
Description
Default:
Data_type: opcond*, read only
Returns the list of all opcond objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
operating_conditions
operating_conditions operating_conditions
Description
Default: ""
Data_type: string, library (read only) library_domain and root (read/write)
Specifies the operating conditions to use for timing. You must specify the path to an operating_conditions object in the library. The operating_conditions
attribute does not need to have a value if you want to use the default operating conditions.
Specify this attribute before you use the libraries in the design.
Examples
The following command sets the operating condition for library domain srpg to 1p08:
set_db library_domains/srpg .operating_condition 1p08
The following command sets the operating conditions to worst_case:
set_db operating_conditions worst_case
Applies to:
library
library_domain
root
override_library_max_drc
override_library_max_drc {true | false}
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Description
Default: false
Data_type: bool, read/write
Specifies whether you can relax the design rule constraints set on the library. Set this attribute to true to relax the max_capacitance, max_fanout, and
max_transition constraints. By default, you can only tighten the constraint values.
Applies to:
root
Related Information
Affects these commands: report_design_rules
syn_opt
Affects these attributes: max_capacitance
max_fanout
max_transition
parse_lib_moments_table
parse_lib_moments_table {true | false}
Description
Default: false
Data_type: bool, read/write
Parses the library moments table while loading the library file.
Applies to:
root
rc_corners
Syntax
rc_corners <list_of_rc_corners>
Applies to:
root
Description
Default:
Data_type: rc_corner*, read only
Returns the list of rc_corner objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
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reload_when_for_macro_cell
reload_when_for_macro_cell {false | true}
Description
Default: true
Data_type: bool, read/write
Disables the processing of the when condition redundantly for the macro library cell during library characterization.
Applies to:
root
socv_library
socv_library string
Description
Default:
Data_type: string, read/write
Specifies the list of Statistical On-Chip Variation (SOCV) libraries.
Applies to:
library_domain
root
Related Information
Related command: read_libs
speed_up_read_socv
Syntax
speed_up_read_socv {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enables the fastest way to populate the library cells required in object spec of SOCV file. The attribute must be set before reading SOCV files.
speedup_library_establishment
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Library Attributes--root Attributes for Library
Syntax
speedup_library_establishment {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the establishment of library calls during library loading stages to speedup.
support_3Dtable_power_arc
support_3Dtable_power_arc {true| false}
Description
Default: false
Data_type: bool, read/write
Controls support for three-dimensional power arc.
Applies to:
root
support_aae_lib_path_change
Syntax
support_aae_lib_path_change {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the flow for iSpatial to initiate the AAE when soft link path of loaded library has been changed between the on-going flow/tool running.
You must set this attribute before reading the libraries.
Related Information
Affects this attribute: library
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support_appending_libs
support_appending_libs {true| false}
Description
Default: false
Data_type: bool, read/write
Controls whether or not you can append two or more libraries that are defined in different .lib files and that have the same library name and the same PVT
conditions but contain different libcells.
Applies to:
root
Related Information
Affects this attribute: library
support_combo_clock
support_combo_clock {true | false}
Description
Default: false
Data_type: bool, read/write
When you set this attribute to true, non-sequential cells that have a clock attribute set to true on one of the input pins will be treated as sequential cells.
Applies to:
root
Related Information
Affects these attributes: is_combinational
is_sequential
is_usable
support_internal_pg_pins
support_internal_pg_pins {true| false}
Description
Default: true
Data_type: bool, read/write
Supports internal power and ground pins.
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Applies to:
root
support_master_slave_flop
support_master_slave_flop {true| false}
Description
Default: false
Data_type: bool, read/write
Support master-slave flop library cell.
Applies to:
root
support_multi_seq_elements
support_multi_seq_elements {true| false}
Description
Default: true
Data_type: bool, read/write
Controls the conversion of a state-retention cell with multiple sequential elements, such as multiple ff or latch groups, into a single ff or latch function.
Any outgoing timing arcs on the power gating pin of the state-retention cell are enabled by default.
You must set this attribute before you read the libraries.
Applies to:
root
Related Information
Affects this attribute: library
support_multi_seq_scan_latch
support_multi_seq_scan_latch {true| false}
Description
Default: false
Data_type: bool, read/write
Supports scan latch library cell defined using two latches.
Applies to:
root
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support_serial_scanin_multibit_cell
support_serial_scanin_multibit_cell {true| false}
Description
Default: true
Data_type: bool, read/write
Determines whether to support a multi-bit serial scan cell as multi-bit cell when only the scan input of the first bit is specified as a scan input pin (test_scan_in)
while the scan input of all other bits are internal nodes.
Applies to:
root
support_tlatch_group
support_tlatch_group {true| false}
Description
Default: true
Data_type: bool, read/write
Supports library cells having the transparent latch (tlatch) group.
Applies to:
root
suppress_syntech_messages
suppress_syntech_messages {true| false}
Description
Default: false
Data_type: bool, read/write
Controls the printing of the LBR parse messages.
Applies to:
root
target_library
target_library string
Description
Default:
Data_type: string, read/write
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Specifies the list of target libraries. Target libraries are technology libraries that are used by the Synthesis engine during mapping and optimization. The target
libraries contain the cells used to generate the netlist and definitions for the design’s operating conditions.
Applies to:
library_domain
root
Related Information
Related attribute: link_library
timing_analysis_socv
Syntax
timing_analysis_socv {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls SOCV analysis.
Related Information
Related commands: syn_opt
setAnalysisMode in the Innovus Text Command Reference
getAnalysisMode in the Innovus Text Command Reference
timing_conditions
Syntax
timing_conditions <list_of_timing_conditions>
Applies to:
root
Description
Default:
Data_type: timing_condition*, read only
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Returns the list of timing_condition objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
timing_enable_sr_latch_preset_clear_arcs
Syntax
timing_enable_sr_latch_preset_clear_arcs {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the enabling of the timing arcs through clear and preset pins of set-reset (SR) latches.
Related Information
Effects these commands: syn_generic
syn_map
syn_opt
report_timing
timing_library_lookup_drv_per_frequency
timing_library_lookup_drv_per_frequency {worst | linear}
Description
Default: worst
Data_type: enum, read/write
When max_cap lookup tables are present in the library, this attribute determines whether the maximum capacitance values used for design rule verification
during incremental optimization should be the worst value for all frequencies or the interpolated value for the maximum frequency.
In the library, the maximum capacitance can be specified as follows:
at the library level using the default_max_capacitance attribute
at the pin level using the max_capacitance attribute
at the pin level using the max_cap group (a table which specifies the maximum capacitance in function of the frequency and the input transition time).
Currently, the tool only supports one dimensional max_cap lookup tables in function of the frequency.
If you set this attribute to linear, the tool always determines the maximum pin capacitance by doing a linear interpolation of the pin’ s max_cap lookup table in
function of the maximum frequency constraint that the timing engine returns across all paths through the given pin.
If you set this attribute to worst, the tool uses a worst value for all frequencies determined as following:
default_max_capacitance max_capacitance max_cap group Action if attribute set to worst
(lib level) (pin level (pin level)
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yes yes yes Selects the worst of the max_capacitance pin attribute and the interpolated value
of the max_cap group.
no yes yes Selects the worst of the max_capacitance pin attribute and the interpolated value
of the max_cap group.
yes no yes Selects the worst of the default_max_capacitance lib level attribute and the
interpolated value of the max_cap group.
no no yes Interpolates the value of the max_cap group.
This attribute is taken into account only if the use_max_cap_lut attribute is set to true.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
report_timing
report_design_rules
Affected by this attribute: use_max_cap_lut
timing_nsigma_multiplier
Syntax
timing_nsigma_multiplier <float>
Applies to:
root
Description
Default: 3.0
Data_type: double, read/write
Specifies the multiplier factor used in SOCV analysis. This multiplier indicates how much variation for delays, slews, and arrival times to consider around a
mean value.
The default value is 3. Assuming a mean value of µ and sigma variation of σ, this means that for a given quantity (delay, slew, arrival time)
µ + 3∗σ is the worst case value
µ – 3∗σ is the best case value
This attribute affects timing analysis and optimization.
Related Information
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timing_socv_view_based_nsigma_multiplier_mode
Syntax
timing_socv_view_based_nsigma_multiplier_mode {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Enables setting of view-based separate setup and hold sigma multipliers.
Related Information
Related commands: syn_opt
set_global in the Innovus Text Command Reference
treat_non_seq_arc_cell_as_unusable
treat_non_seq_arc_cell_as_unusable {true| false}
Description
Default: true
Data_type: bool, read/write
Treats the lib cells having non sequential setup arc as unusable if timing_disable_non_sequential_checks is set to false.
Applies to:
root
turbo_lib_loading
turbo_lib_loading {0 | 1 | 2}
Description
Default: 1
Data_type: int, read/write
Populates timing arcs, power arcs, and library establishment data only on need basis for runtime speedup.
Applies to:
root
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use_area_from_lef
use_area_from_lef {false | true | auto}
Description
Default: false
Data_type: enum, read/write
Specifies whether to use the cell area from the LEF libraries. If you set this attribute to auto, the cell area will be read from the technology area unless the LEF
library is available and it has at least one macro definition. By default, the cell area will not be read from the LEF library.
0 and false are equivalent, and 1 and true are equivalent.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
use_compatibility_based_grouping
use_compatibility_based_grouping {false | true}
Description
Default: true
Data_type: bool, read/write
Controls the mapping of single-bit sequential, combinational, and tristate cells into multibit cells based on common control signals.
By default, the tool will create groups of compatible single-bit cells that have common control signals. Merging is only done within a group of compatible cells.
Applies to:
root
Related Information
Affects this command: syn_opt
Affects these attributes: force_merge_combos_into_multibit_cells
force_merge_seqs_into_multibit_cells
use_multibit_combo_cells
use_multibit_seq_and_tristate_cells
Affected by this attribute: multibit_seqs_members_naming_style
Related attribute: bit_width
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use_default_related_pg_pin_for_aon
use_default_related_pg_pin_for_aon {true| false}
Description
Default: true
Data_type: bool, read/write
Specifies whether to use the default power or ground pin for the input or output pin's related_power_pin or related_ground_pin of always-on buffer or inverter
cell, respectively.
Applies to:
root
use_main_cell_output_function_for_test_cell
use_main_cell_output_function_for_test_cell {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether or not to ignore the test_cell functionality and use the main cell functionality for DFT sequential cells when there is a discrepancy between the
main-cell function and the test_cell function or when the test_cell function is missing. When the attribute is disabled and the test_cell group has no function, only
the main-cell function is used and the cell is treated as a non-scan cell.
Applies to:
root
use_multibit_cells
use_multibit_cells {false | true}
Description
Default: false
Data_type: bool, read/write
If set to true, single-bit cells are mapped to an appropriate multibit cell from the technology library.
For example, the following four single-bit flops:
ff_reg[0] ff_reg[1] ff_reg[2] ff_reg[3]
can be merged into one four-bit flop as shown below:
ff_reg[0_3]
Single-bit cells that can be merged include: flip-flops, latches, tristate buffers, combinatorial cells, isolation cells and level-shifter cells.
When merging flops, the shared input is the clock line.
When merging latches, the shared input is the gate line.
When merging tri-state cells, the shared input is the enable line.
Multibit cell inferencing is performed during the mapping stage. While cells that are marked unusable by the tool cannot be used during mapping, they
can be used during incremental optimization.
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This attribute controls both logical and physical-aware multibit mapping. If the design is placed, physical-aware multibit mapping is performed, otherwise logical
multibit mapping is performed.
Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
Affects these attributes: force_merge_combos_into_multibit_cells
force_merge_seqs_into_multibit_cells
use_multibit_combo_cells
use_multibit_seq_and_tristate_cells
Affected by this attribute: multibit_seqs_members_naming_style
Related attributes: bit_width
multibit_cells_from_different_busses
use_multibit_combo_cells
use_multibit_combo_cells {false | true}
Description
Default: false
Data_type: bool, read/write
Controls the mapping of single-bit combinational cells to appropriate multibit combinational cells from the technology library.
By default, this attribute inherits the last setting of the use_multibit_cells attribute, but you can explicitly override this setting to enable or disable
combinational cell mapping.
Multibit cell inferencing is performed during incremental optimization rather than during the mapping stage. While cells that are marked unusable by the
tool cannot be used during mapping, they can be used during incremental optimization.
Applies to:
root
Related Information
Affects this command: syn_opt
Affected by this attribute: use_multibit_cells
Related attribute: bit_width
use_multibit_iso_cells
use_multibit_iso_cells {true | false}
Description
Default: false
Data_type: bool, read/write
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Controls the mapping of single-bit isolation cells to appropriate multibit isolation cells from the technology library.
By default, this attribute inherits the last setting of the use_multibit_cells attribute, but you can explicitly override this setting to enable or disable isolation cell
mapping.
Multibit cell inferencing is performed during incremental optimization rather than during the mapping stage. While cells that are marked unusable by the
tool cannot be used during mapping, they can be used during incremental optimization.
Examples
get_db use_multibit_cells
false
get_db use_multibit_iso_cells
false
set_db use_multibit_cells true
Setting attribute of root '/': 'use_multibit_cells' = true
get_db use_multibit_iso_cells
true
set_db use_multibit_iso_cells false
Setting attribute of root '/': 'use_multibit_iso_cells' = false
set_db use_multibit_cells true
Setting attribute of root '/': 'use_multibit_cells' = true
get_db use_multibit_iso_cells
true
Applies to:
root
Related Information
Affects this command: syn_opt
Affected by this attribute: use_multibit_cells
Related attribute: bit_width
use_multibit_seq_and_tristate_cells
use_multibit_seq_and_tristate_cells {true | false}
Description
Default: false
Data_type: bool, read/write
Controls the mapping of single-bit sequential and tristate cells to appropriate multibit cells from the technology library.
By default, this attribute inherits the last setting of the use_multibit_cells attribute, but you can explicitly override this setting to enable or disable sequential
and tristate cell mapping.
Multibit cell inferencing is performed during incremental optimization rather than during the mapping stage. While cells that are marked unusable by the
tool cannot be used during mapping, they can be used during incremental optimization.
Applies to:
root
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Related Information
Affects this command: syn_opt
Affected by this attribute: use_multibit_cells
Related attribute: bit_width
use_nextstate_type_only_to_assign_sync_ctrls
use_nextstate_type_only_to_assign_sync_ctrls {true| false}
Description
Default: false
Data_type: bool, read/write
Forces the tool to use the nextstate_type .lib pin attribute (when available in the library) to assign synchronous control pins.
By default, the tool uses the nextstate_type .lib pin attribute along with some heuristics based on pin names to assign synchronous control pins.
Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
Affects this attribute: sync_clear_pins
use_scan_seqs_for_non_dft
use_scan_seqs_for_non_dft {true | false | degenerated_only}
Description
Default: true
Data_type: enum, read/write
Controls the mapping of registers to scan flip-flops for functional purposes.
This attribute can have the following values:
degenerated_only Allows mapping to scan flip-flops with the scan-related pins tied off (also known as degenerated scan flops).
This value is typically used when only scan flop library cells are available for use during technology mapping.
false Avoids mapping to scan flip-flops for functional use.
This value is typically used when the flip-flops will be mapped to scan for DFT by setting the dft_scan_map_mode design object attribute
to either force_all or tdrc_pass.
true Allows registers not targeted for DFT to be mapped to scan flip-flops for functional use.
A flop can only be mapped to scan for DFT if you run the check_dft_rules command and the flop passes the DFT rules check or if prior to mapping, you
set the dft_scan_map_mode design attribute to force_all.
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Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
Related attributes: dft_mapped
dft_scan_map_mode
wireload_mode
wireload_mode {top | enclosed | segmented | none}
Description
Default: none
Data_type: enum, read/write
Allows you to override the computing net load method that is normally specified in the technology library. The wire-load modes are:
enclosed Uses the wire-load model of the smallest block that fully encloses the net to compute the load of the net. The hierarchical boundary pins are not
counted as fanouts.
segmented Divides the nets that cross hierarchical boundaries into segments with one segment for each level of hierarchy. Separate load values are
computed for each segment (counting the hierarchical boundary pins as individual fanouts) and the load values are added together.
top Uses the wire-load model of the top-level design for all nets in all sub-designs. The hierarchical boundary pins are not counted as fanouts.
By default, this attribute is set to the value of the default_wire_load_mode Liberty attribute of the library that was read in. If the default_wire_load_mode attribute
was not set in the library, the wireload_mode attribute defaults to none.
If multiple libraries are read in, the tool checks for a library that has the default_wire_load_mode attribute set and the wireload_mode attribute is set to that value.
If multiple libraries have this attribute set, the wireload_mode attribute is set to the value defined in the library that was read in first. If the default_wire_load_mode
attribute is not found in any of the libraries, the wireload_mode attribute defaults to none.
When the interconnect_mode attribute is set to ple, the wireload_mode attribute is set to none. In this case, the tool uses physical layout estimators (PLEs)
instead of wire-load models during synthesis.
Applies to:
root
Related Information
Affected by this attribute: interconnect_mode
Related attributes: force_wireload
wireload_selection
wireload_selection
wireload_selection {default | table | none}
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Description
Default: ""
Data_type: string, read/write
Indicates whether to use a wire-load selection table to choose default wire-load models for blocks based on their cell areas.
default Reverts the environment to the default settings. The tool behaves as if the attribute had never been set.
none Specifies not to perform automatic wire-load selection by area. The only wire-load models that will be used are the ones that are set with the
force_wireload attribute on individual modules or the default wireload model specified in the library.
table Specifies the hierarchical path to the wire-load selection table to be used.
Examples
Some libraries contain multiple selection tables (such as for different numbers of metal layers), and in such cases you can indicate which
wireload_selection table should be used:
set_db [find /libraries/ -library_domain my_dom] .wireload_selection \
[find /*/my_dom -wireload_selection ALUMINUM]
Some libraries contain multiple selection tables (such as for different numbers of metal layers), and in such cases you can indicate which
wireload_selection table should be used:
set_db wireload_selection \
==> [vfind / -wireload_selection "4_layer"]
The following example chooses a different selection group:
set_db wireload_selection wc_group
Applies to:
library_domain
root
Related Information
Related attributes: force_wireload
wireload_mode
seq_function Attribute for Library
d_function
d_function
d_function string
Read-only seq_function attribute. Returns the function of the sequential cell.
wireload_selection Attribute for Library
library
library library_object
Read-only wireload attribute. Returns the name of the library that this wireload selection table belongs to.
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Related Information
Related attributes: (lib_cell) library
(library_domain) library
(operating_condition) library
(wireload) library
wireload Attributes for Library
fanout_cap
liberty_attributes
library
fanout_cap
fanout_cap string
Read-write wireload attribute. Sets the capacitance per fanout for the wire-load model.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
report_area
report_design_rules
report_gates
report_summary
report_timing
liberty_attributes
liberty_attributes string
Read-only wireload attribute. Returns a list of Liberty attributes and values that were specified for the wireload_model in the library.
Related Information
Related attributes: (library) liberty_attributes
(lib_arc) liberty_attributes
(lib_cell) liberty_attributes
(lib_pin) liberty_attributes
(operating_condition) liberty_attributes
(pg_lib_pin) liberty_attributes
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library
library library_object
Read-only wireload attribute. Returns the name of the library that this wire-load model belongs to.
Related Information
Related attributes: (lib_cell) library
(library_domain) library
(operating_condition) library
(wireload_selection) library
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Input and Output (IO)
12
Input and Output (IO)
The chapter describes the attributes of the following object types:
hdl_architecture Attribute for IO hdl_component Attribute for IO
hdl_parameter Attribute for IO
hdl_architecture Attribute for IO
hdl_flatten_complex_port_in_bottom_up_flow
hdl_flatten_complex_port_in_bottom_up_flow {1 | 0 | true | false}
Default: true
Read-write hdl_architecture attribute. When set to true, creates one-dimensional packed version
of complex ports in bottom up flow.
hdl_component Attribute for IO
sim_model
sim_model {{hdl_format list_of_unix_paths}...}
Read-write hdl_component attribute. Specifies the UNIX location of the simulation model for the
specified ChipWare component. This attribute takes a Tcl list of Tcl lists: each sub-list represents a
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Input and Output (IO)--hdl_architecture Attribute for IO
simulation model of the ChipWare component and a pair of strings in the following format:
{hdl_format list_of_unix_paths}
The possible values for hdl_format are:
v1995 (for Verilog-1995 simulation models)
v2001 (for Verilog-2001 simulation models)
sv (for SystemVerilog simulation models)
vhdl1987 (for VHDL-1987 simulation models)
vhdl1993 (for VHDL-1993 simulation models)
The list_of_paths is a UNIX path pointing to the simulation model.
Examples
If the simulation model is not hierarchical, the sim_model attribute values can look like the following
example:
{ { v1995 $path/CW_complete.v } \
{ v2001 $path/CW_complete.v } \
{ vhdl1987 $path/CW_complete.vhdl } \
{ vhdl1993 $path/CW_complete.vhdl } }
If the simulation model is hierarchical, the sim_model attribute values can look like the following
example:
{ { v1995 { $path/CW_top.v $path/CW_leaf.v } } \
{ v2001 { $path/CW_top.v $path/CW_leaf.v } } \
{ vhdl1987 { $path/CW_top.vhdl $path/CW_leaf.vhdl } } \
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{ vhdl1993 { $path/CW_top.vhdl $path/CW_leaf.vhdl } } }
Related Information
Affects this command: elaborate
hdl_parameter Attribute for IO
current_value
current_value integer
Read-write hdl_parameter attribute. Specifies the value currently assigned to this parameter.
You can use this attribute in pre-elaboration scripts that are attached to hdl_implementation objects
via the pre_elab_script attribute.
Related Information
Related command: create_component_parameter
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Physical
13
Physical
The chapter describes the attributes of the following object types:
All Attributes for Physical base_cell Attributes for Physical blockage Attributes for Physical
bump Attributes for Physical def_pin Attributes for Physical design Attributes for Physical
fill Attributes for Physical gcell_grid Attribute for Physical gcell Attributes for Physical
group Attributes for Physical Ispatial Flow layer Attributes for Physical
net Attributes for Physical pcell Attributes for Physical pdomain Attributes for Physical
place_blockage Attributes for Physical pnet Attributes for Physical power_domain Attributes for Physical
region Attributes for Physical root Attributes for Physical route_blockage Attributes for Physical
route_rule Attributes for Physical route_type Attributes for Physical row Attributes for Physical
sdp_column Attributes for Physical sdp_group Attributes for Physical sdp_instance Attributes for Physical
sdp_row Attributes for Physical site Attributes for Physical slot Attributes for Physical
specialnet Attributes for Physical style Attributes for Physical track_pattern Attributes for Physical
track Attributes for Physical via Attributes for Physical
See also:
direction
group
instances
pins
slack
type
voltage
All Attributes for Physical
index
is_fixed_mask
is_no_flop
is_spare
layer
location
location_x
location_y
orient
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place_status
skip_in_write_def
index
Syntax
index <integer>
Applies to:
gcell
jtag_port
sdp_column
sdp_instance
sdp_row
style
test_bus_port
test_signal
Description
Object Default Data_type Description
gcell int, Returns the X and Y index values into the gcell array.
read_only
jtag_port -1 int, Specifies the index value of the port. The index value is used to determine the order in which the boundary cells
read/write are stitched together in the boundary-scan register.
A value of -1 indicates that the information was not provided in an IOspeclist.
sdp_column 0 int, read- Returns the index or position of this column in the row it belongs to.
only
sdp_instance 0 int, read- Returns the index or position of the instance in the row or column to which the instance belongs.
only
sdp_row 0 int, read- Returns the index or position of this row in the column it belongs to.
only
style 0 int, read- Returns the style index value (number following a STYLE statement).
only
test_bus_port 0 int, read- Returns the index of the test bus port.
only
Test bus ports with the same function have an index to distinguish them. For example, the ports of an n-bit scan
data input bus have an index between 0 and n-1.
test_signal 0 int, read- Returns the index of the test signal.
only
Test signals with the same function have an index to distinguish them. For example, the ports of an n-bit scan
data input bus have an index between 0 and n-1.
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Related Information
Set by these commands: add_jtag_boundary_scan
read_def
read_sdp_file
Set by these constraints: define_test_bus_port
define_test_signal
is_fixed_mask
Syntax
is_fixed_mask {true | false}
Applies to:
base_cell
hinst
inst
lib_cell
Description
Default: false
Data_type: book, read only
Indicates whether the instance lib_cell /cell has FIXEDMASK keymask in LEF.
is_no_flop
Syntax
is_no_flop {false | true}
Applies to:
blockage
place_blockage
Description
Default: false
Data_type: bool, read/write
Placement blockage attribute, which indicates if the blockage excludes flip-flops.
Related Information
Set by this command: read_def
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is_spare
is_spare {1 | 0 | false| true}
Default: false
Read-write inst attribute. Indicates that the instance is a spare instance. These are used by post-mask ECO flows.
layer
Syntax
layer <string>
Applies to:
Object Data_type
blockage layer, read only
fill layer, read only
hpin string, read/write
pin string, read/write
port string, read/write
route_bloc string, read/write
kage
slot layer, read only
track_patt layer, read only
ern
Description
Default:
Returns the name of the layer.
Related Information
Set by this command: read_def
Related attributes: rects
polygons
location
Syntax 1
location <pathname>
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Applies to:
Object Data_type Description
hdl_architecture string, Returns the name and physical location of the source file that contains the specified entity (in VHDL) or module (in
read only Verilog).
hdl_component string, Specifies the physical location of the source file that contains the VHDL entity declaration for the specified component.
read only
hdl_configuration string, Returns the location of the VHDL source file that contains the specified VHDL configuration.
read only
hdl_implementation string, Specifies the physical location of the source file containing the RTL code of the specified component implementation. If
read only the source file is Verilog, it specifies the location of the entire synthesis model. If the source file is in VHDL, it specifies
the location of the VHDL architecture.
hdl_package string, Returns the name and physical location of the source file that contains the specified VHDL package.
read only
This attribute is supported only in the RTL flow.
Related Information
Related attribute: default_location
Syntax 2
location <float | point>
Applies to:
Object Data_type Description
bump point, read only Returns the x and y coordinates of the lower left corner of the bump.
hinst point, read only Returns the physical coordinates of the lower left hand corner of the hierarchical instance in microns.
hpin point, read only Returns the physical coordinates of the hierarchical pin in microns.
inst point, read only Returns the physical coordinates of the lower left hand corner of the hierarchical instance in microns.
pcell point, read only Returns the x and y coordinates of the lower left corner of the pcell.
pg_pin point, read only Returns the physical coordinates of the lower left hand corner of the pg_pin in microns.
pin point, read only Returns the physical coordinates of the lower left hand corner of the pin in microns.
port point, read only Returns the physical coordinates of the lower left hand corner of the port in microns.
Related Information
Set by this command: read_def
Related attributes: location_x
location_y
Syntax 3
location {pin | port | bus}
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Applies to:
Object Data_type Description
opcg_domain hpin | pin | constant | pg_pin | hport | Returns where the domain macro will be inserted, which was specified using the -location option of
port, read only the define_opcg_domain command.
Related Information
Set by this command: define_opcg_domain
Syntax 4
location {from | to | auto | self | other | fanin | fanout | faninout | parent | sibling | any}
Applies to:
Object Default Data_type Description
isolation_rule to enum, Specifies the location of the isolation cells.
read/write
To change the location, you need to remove the isolation rule.
level_shifter_rule to enum, Returns the location that was specified with the -location option of the update_level_shifter_rules
read/write CPF command.
Related Information
Affected by this command: read_power_intent
location_x
Syntax
location_x <float>
Applies to:
Object Default Data_type
blockage 0.000 double, read only
region 0.000
def_pin
pcell
hinst coord, read only
hpin
inst
pg_pin
pin
port
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Description
Object Details
blockage Returns the physical x-coordinate of the lower left hand corner of the blockage in microns. The location_x value is derived from the DEF.
def_pin Returns the x-coordinate of the physical pin if the pin was placed.
hinst Returns the physical x-coordinate of the lower left hand corner of the hierarchical instance in microns. The location_x value is derived from
the DEF.
hpin Returns the physical x-coordinate of the hierarchical pin in microns.
inst Returns the physical x-coordinate of the lower left hand corner of the instance in microns. The location_x value is derived from the DEF.
pcell Returns the x-coordinate of the lower left corner of the pcell
pg_pin Returns the physical x-coordinate of the pg_pin in microns.
pin Returns the physical x-coordinate of the pin in microns. The location_x value is derived from the DEF.
port Returns the physical x-coordinate of the port in microns. The location_x value is derived from the DEF.
region Returns the physical x-coordinate of the lower left hand corner of the region in microns. The location_x value is derived from the DEF.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by this command: read_def
Related attribute: location_y
location_y
Syntax
location_y <float>
Applies to:
Object Default Data_type
blockage 0.000 double, read only
region 0.000
def_pin
pcell
row
hinst coord, read only
hpin
inst
pg_pin
pin
port
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Description
Object Details
blockage Returns the physical y-coordinate of the lower left hand corner of the blockage in microns. The location_y value is derived from the DEF.
def_pin Returns the y-coordinate of the physical pin if the pin was placed.
hinst Returns the physical y-coordinate of the lower left hand corner of the hierarchical instance in microns. The location_y value is derived from
the DEF.
hpin Returns the physical y-coordinate of the hierarchical pin in microns.
inst Returns the physical y-coordinate of the lower left hand corner of the instance in microns. The location_y value is derived from the DEF.
pcell Returns the y-coordinate of the lower left corner of the pcell
pg_pin Returns the physical y-coordinate of the pg_pin in microns.
pin Returns the physical y-coordinate of the pin in microns. The location_y value is derived from the DEF.
port Returns the physical y-coordinate of the port in microns. The location_y value is derived from the DEF.
region Returns the physical y-coordinate of the lower left hand corner of the region in microns. The location_y value is derived from the DEF.
row Returns the y-coordinate of the lower left corner of the row.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by these commands: create_row
read_def
Related attribute: location_x
orient
orient {r0|r90|r180|r270|mx|mx90|my|my90|unknown}
Default: R0
Read-write inst attribute. Specifies the instance placement orientation.
place_status
Syntax 1
place_status {unplaced | placed | fixed | cover}
Applies to:
pcell
Description
Default:
Data_type: string, read only
Returns the placement status of the pcell. The possible values are:
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Value Details
cover has a location, is part of the cover macro and cannot be moved by automatic tools.
fixed has a location and cannot be moved by automatic tools.
placed has a location and can be moved by automatic tools.
unplaced has no location
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Syntax 2
place_status {unplaced | placed | fixed | cover | soft_fixed}
Applies to:
bump
hpin
inst
pg_pin
pin
port
Description
Default: unplaced
Data_type: enum, read/write (all except bump)
Returns the placement status of the bump/hpin/instance/pg_pin/pin/port. The possible values are:
Value Details
cover has a location, is part of the cover macro and cannot be moved by automatic tools.
fixed has a location and cannot be moved by automatic tools.
placed has a location and can be moved by automatic tools.
soft_fixed has a location and cannot be moved during global placement, but can be moved for legalization.
unplaced has no location
bump cells are usually placed with + cover placement status.
Related Information
Set by this command: read_def
skip_in_write_def
Syntax
skip_in_write_def {false | true}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
Controls whether to skip the content of this instance when writing out the DEF file.
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Applies only to hierarchical instances.
You can use this attribute in a hierarchical DEF flow to create a top-level DEF file that does not contain the content of the hierarchical instances. Content of
these hierarchical instances can be added later.
Related Information
Affects this command: write_def
base_cell Attributes for Physical
keep_as_physical
keep_as_physical {1 | 0 | true | false}
Default: false
Read-only base_cell attribute. When set to true, retains the physical cell during read_def -keep_all_physical_cells execution.
site
site site
Read-only base_cell attribute. Returns the physical lib_cell site.
blockage Attributes for Physical
component
def_name
density
has_fills
has_slots
is_exceptpgnet
is_exclude_flops
is_partial
is_pushdown
is_soft
mask
max_layer
min_layer
polygons
properties
rects
spacing
user_created
user_name
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visible
width
component
component string
Read-only blockage attribute. Returns a component name if the blockage is associated with a component.
Related Information
Set by this command: read_def
def_name
def_name string
Read-only blockage attribute. Returns the DEF name of the blockage.
Related Information
Set by this command: read_def
density
density float
Read-only blockage attribute. Returns the percentage of the blockage area that can be used for standard cells during initial placement if the blockage was
marked partial.
Related Information
Set by this command: read_def
Related attribute: is_partial
has_fills
has_fills {false |true}
Default: false
Read-write blockage attribute. Specifies whether the blockage has metal fills.
Related Information
Set by this command: read_def
has_slots
has_slots {false |true}
Read-write blockage attribute. Specifies whether the blockage has slots.
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Related Information
Set by this command: read_def
is_exceptpgnet
is_exceptpgnet {false |true}
Read-only blockage attribute. Indicates whether the blockage only blocks signal net routing, and does not block power or ground net routing.
Related Information
Set by this command: read_def
is_exclude_flops
is_exclude_flops {false |true}
Default: false
Read-only blockage attribute. Indicates whether the blockage excludes flip-flops.
Related Information
Set by this command: read_def
is_partial
is_partial {false |true}
Read-only blockage attribute. Indicates whether the blockage can be partially used for initial placement.
Related Information
Set by this command: read_def
Related attribute: density
is_pushdown
is_pushdown {false |true}
Read-write blockage attribute. Specifies whether the blockage was pushed down into the block from the top level of the design.
Related Information
Set by this command: read_def
is_soft
is_soft {false |true}
Read-only blockage attribute. Indicates whether the blockage area can be used in phases of the design after initial placement.
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Related Information
Set by this command: read_def
mask
mask integer
Read-only blockage attribute. Returns the mask number used for double- or triple-patterning lithography.
Related Information
Set by this command: read_def
max_layer
max_layer string
Read-only blockage attribute. Defines the top layer of a range of metal layers to which this blockage applies
This attribute applies only to routing halo blockages.
Related Information
Set by this command: read_def
min_layer
min_layer string
Read-only blockage attribute. Defines the bottom layer of a range of metal layers to which this blockage applies.
This attribute applies only to routing halo blockages.
Related Information
Set by this command: read_def
polygons
polygons string
Read-only blockage attribute. Returns a Tcl list of coordinates of at least three points if the blockage has a polygon geometry.
Example
genus:/designs/DTMF_CHIP> get_db [get_db blockages */5_routing_Metal6] .polygons
{{555.945 290.93} {555.945 323.32} {616.1 323.32}} {{616.1 323.32} {616.1 290.93} {555.945 290.93}}
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Related Information
Set by this command: read_def
properties
properties string
Read-only blockage attribute. Returns the properties associated with the blockage.
Related Information
Set by this command: read_def
rects
rects {rect...}
Read-write blockage attribute. Returns a Tcl list with the lower left and upper right coordinates of each rectangular-shaped box that is part of this blockage.
Related Information
Set by this command: read_def
spacing
spacing float
Read-only blockage attribute. Returns the minimum spacing allowed between the blockage and any other routing shape. For a routing blockage either the
spacing or the width is specified.
Related Information
Set by this command: read_def
Related attribute: (blockage) width
user_created
user_created {false | true}
Read-only blockage attribute. Indicates whether the blockage was created by the user in Genus. The attribute returns false if the blockage was defined in the
DEF file.
Related Information
Set by these commands: create_place_blockage
create_place_halo
create_route_blockage
create_route_halo
read_def
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user_name
user_name string
Read-only blockage attribute. Returns the blockage name assigned by the user.
visible
visible {false | true}
Default: false
Read-write blockage attribute. Indicates whether this blockage is visible in the GUI.
width
width float
Read-only blockage attribute. Returns the effective width that must be used for the purposes of spacing calculations. For a routing blockage either the spacing
or the width is specified.
Related Information
Affected by this command: read_def
Related attribute: spacing
bump Attributes for Physical
base_cell
center
def_name
model
net
orient
port
properties
urx
ury
weight
base_cell
base_cell base_cell
Read-only bump attribute. Returns the base_cell name of the bump.
center
center point
Read-only bump attribute. Returns the coordinates of the center of the bump in microns.
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def_name
def_name string
Read-only bump attribute. Returns the DEF name of the bump.
Related Information
Set by this command: read_def
model
model string
Read-only bump attribute. Returns the model of which this bump is an instance. The model refers to a MACRO defined in the LEF library.
Related Information
Set by this command: read_def
net
net net_name
Read-only bump attribute. Returns the net associated with the bump.
orient
orient string
Read-only bump attribute. Returns the orientation of the bump. Following are the possible orientations: N, S, E, W, FN, FS, FE, or FW.
Related Information
Set by this command: read_def
Related attribute: (row) orientation
port
port port
Read-only bump attribute. Returns the port associated with the bum.
properties
properties string
Read-only bump attribute. Returns the properties associated with the bump.
Related Information
Set by this command: read_def
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urx
urx float
Read-only bump attribute. Returns the x-coordinate of the upper right corner of the bump.
Related Information
Set by this command: read_def
ury
ury float
Read-only bump attribute. Returns the y-coordinate of the upper right corner of the bump.
Related Information
Set by this command: read_def
weight
weight integer
Read-only bump attribute. Returns the weight assigned to the bump, which determines whether or not automatic placement attempts to keep the bump near the
location specified in the DEF file. The weight is only meaningful when the bump is placed.
Related Information
Set by this command: read_def
def_pin Attributes for Physical
layers
net_expr
net_name
orientation
placement_status
polygons
ports
properties
special
use
vias
visible
layers
layers {layer minspacing designrulewidth {llx lly urx ury}} ...
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Read-only def_pin attribute. Returns one or more lists with the layer information of the physical pin if the pin was placed. Each list contains the layer name, the
minimum spacing allowed between this pin and any other routing shape, the effective layer width, and the lower left and upper right coordinates for each pin
location.
In the DEF file, you can only specify the minimum spacing or the effective width. The attribute, however, lists two numbers after the layer name, one of
which will be 0. The non-zero value corresponds to the information that was specified in the DEF file.
This attribute will be empty is the pin has no PORT statements and no LAYER statements.
Related Information
Set by this command: read_def
net_expr
net_expr "netExprPropName defaultNetName"
Read-only def_pin attribute. Returns the net expression associated with the physical pin.
Related Information
Set by this command: read_def
net_name
net_name string
Read-only def_pin attribute. Returns the internal net name associated with the physical pin. This net name is defined in the NETS or SPECIALNETS statement.
Related Information
Set by this command: read_def
orientation
orientation string
Read-only def_pin attribute. Returns the orientation of the physical pin if the pin was placed.
Related Information
Set by this command: read_def
placement_status
placement_status string
Read-only def_pin attribute. Returns the placement status of physical pin. Possible values are:
COVER—Pin is part of the cover macro and cannot be moved
FIXED—Pin cannot be moved by automatic tools, but can be moved by interactive commands.
PLACED—Pin can be moved by automatic tools.
UNPLACED—Pin has not been placed.
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Related Information
Set by this command: read_def
polygons
polygons {layer minspacing designrulewidth {pt pt pt [pt] }} ...
Read-only def_pin attribute. Returns one or more lists with polygon information of the physical pin if the pin was placed. Each list contains the layer name, the
minimum spacing allowed between this pin and any other routing shape, the effective layer width, and a list of coordinates of at least 3 points. A polygon is
generated by connecting each successive point, and then the first and last points.
In the DEF file, you can only specify the minimum spacing or the effective width. The attribute, however, lists two numbers after the layer name, one of
which will be 0. The non-zero value corresponds to the information that was specified in the DEF file.
This attribute will be empty is the pin has no PORT statements and no POLYGON statements.
Related Information
Set by this command: read_def
ports
ports { placementStatus location_x location_y orientation
{{layer minspacing designrulewidth {llx lly urx ury}} ...}
{{layer minspacing designrulewidth {pt pt pt [pt]}} ...}
{{vianame location_x location_y}...} }...
Read-only def_pin attribute. Returns one or more lists if the DEF file contains PORT statement(s) for the physical pin . Each list contains
placement status
location of the physical pin
orientation
a list with layer information (corresponding to the LAYER statements for the PORT)
a list with polygon information (corresponding to the POLYGON statements for the PORT)
a list with via information (corresponding to the VIA statements for the PORT)
If the DEF did not contain a LAYER, POLYGON or VIA statement for the PORT, the corresponding list will be empty.
Related Information
Set by this command: read_def
properties
properties string
Read-only def_pin attribute. Returns the properties associated with the def_pin.
Related Information
Set by this command: read_def
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special
special {false | true}
Read-only def_pin attribute. Indicates whether the pin is a special pin. In the place and route tool, a special router routes special wiring to special pins.
Related Information
Set by this command: read_def
use
use string
Read-only def_pin attribute. Returns the use of the pin. Following are the possible values:
ANALOG—Used for analog connectivity
CLOCK—Used for clock net connectivity
GROUND—Used for connectivity to the chip-level ground distribution network
POWER—Used for connectivity to the chip-level power distribution network
RESET—Used as a reset pin
SCAN—Used as a scan pin
SIGNAL—Used for regular net connectivity
TIEOFF—Used as a tie-high or tie-low pin
Related Information
Set by this command: read_def
vias
vias {vianame location_x location_y}...
Read-only def_pin attribute. Returns one or more lists with via information of the physical pin if the pin was placed. Each list contains the name of a previously
defined via (in the DEF or LEF) and the location of the via.
This attribute will be empty is the pin has no PORT statements and no VIA statements.
Related Information
Set by this command: read_def
(route_rule) vias
visible
visible {true | false}
Default: true
Read-write def_pin attribute. Specifies whether this physical pin is visible in the GUI.
design Attributes for Physical
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aspect_ratio avoid_no_row_libcell bbox
blockages boundary bumps
def_component_mask_shift def_extension def_file
def_history def_technology def_version
die_area floorplan_default_row_pattern_site floorplan_first_row_site_index
floorplan_last_row_site_index gcells groups
num_phys_insts obstruction_routing_layer pcells
phys_ignore_nets phys_ignore_special_nets phys_insts
phys_skip_and_copy_special_nets regions rows
sdp_files sdp_groups sdp_type
small_blocked_box_count track_count utilization
utilization_threshold
aspect_ratio
Syntax
aspect_ratio <float>
Applies to:
design
Description
Default: 1.0000
Data_type: double, read/write
Specifies the aspect ratio for the physical layout estimator (PLE). The ratio is specified as height divided by width.
avoid_no_row_libcell
Syntax
avoid_no_row_libcell {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Prevents the use of lib_cells for which no rows have been defined in the DEF file. A lib_cell site must match that of a defined row, otherwise the cell is
unplaceable.
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Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related command: read_def
bbox
Syntax
bbox <rect>
Applies to:
base_cell
bump
design
hinst
inst
lib_cell
net
pcell
Description
Default:
Data_type: rect, read only
Returns the coordinates of the physical boundary of the base_cell/bump/design/hierarchical instance/instance/net/pcell.
blockages
Syntax
bbox <string>
Applies to:
design
hinst
inst
Description
Default:
Data_type: string, read only
Returns information about all blockages specified for the design/hierarchical instance/instance in the DEF file.
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This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by this command: read_def
Related attributes: blockage Attributes
boundary
Syntax
boundary <polygon>
Applies to:
design
pdomain
Description
Default:
Data_type: polygon (design) string (pdomain), read only
Returns the coordinates of the physical boundary of the design/power domain.
Related Information
Set by this command: read_def
bumps
Syntax
bumps <string>
Applies to:
design
Description
Default:
Data_type: bump*, read only
Returns information about all bump cells specified for the design in the DEF file.
def_component_mask_shift
Syntax
def_component_mask_shift <string>
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Applies to:
design
Description
Default:
Data_type: string, read only
Returns the imported DEF component mask shift information. The COMPONENTMASKSHIFT statement in the DEF file defines which layers of a component are
allowed to be shifted from the original mask colors in the LEF. This can be useful to shift all the layers of a specific component in order to align the masks with
other component or router mask settings to increase routing density. This definition allows a specific component to compactly describe the mask shifting for that
component.
Related Information
Set by this command: read_def
def_extension
Syntax
def_extension <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns one or more strings each containing the tag and the extension specified between the BEGINEXT and ENDEXT statements in the imported DEF file.
Related Information
Set by this command: read_def
def_file
Syntax
def_file <def_filename>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns the name of the loaded DEF file.
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Related Information
Set by this command: read_def
def_history
Syntax
def_history <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns one or more strings each containing a historical record (content of a HISTORY statement) specified in the imported DEF file.
Related Information
Set by this command: read_def
def_technology
Syntax
def_technology <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns the technology name specified in the TECHNOLOGY statement of the imported DEF file.
Related Information
Set by this command: read_def
def_version
Syntax
def_version <string>
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Applies to:
design
Description
Default:
Data_type: string, read only
Returns the version of the loaded DEF file.
Related Information
Set by this command: read_def
die_area
Syntax
die_area <float>
Applies to:
design
Description
Default:
Data_type: double, read only
Returns the die area, in square microns.
Related Information
Set by this command: read_def
floorplan_default_row_pattern_site
Syntax
floorplan_default_row_pattern_site <site>
Applies to:
design
Description
Default:
Data_type: site, read/write
Specifies the row pattern site for creation of hybrid rows.
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Related Information
Related commands: create_floorplan
create_row
floorplan_first_row_site_index
Syntax
floorplan_first_row_site_index <integer>
Applies to:
design
Description
Default: 0
Data_type: integer, read/write
Specifies the first site index of a hybrid row pattern site.
Related Information
Related commands: create_floorplan
create_row
floorplan_last_row_site_index
Syntax
floorplan_last_row_site_index <integer>
Applies to:
design
Description
Default: -1
Data_type: integer, read/write
Specifies the last site index of a hybrid row pattern site.
Related Information
Related commands: create_floorplan
create_row
gcells
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Syntax
gcells <list of gcells>
Applies to:
design
Description
Default:
Data_type: gcell *, read only
Returns all gcells for a design.
groups
Syntax
groups <string>
Applies to:
design
group
Description
Default:
Data_type: group*, read only
Returns information such as the members, the region, and properties for all groups defined for the design in the DEF file and the groups this group belongs to.
Related Information
Set by this command: read_def
Related attributes: group Attributes
num_phys_insts
Syntax
num_phys_insts <integer>
Applies to:
design
Description
Default: 0
Data_type: int, read only
Returns the number of physical instance objects in the design.
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obstruction_routing_layer
Syntax
obstruction_routing_layer <integer>
Applies to:
design
Description
Default: 2
Data_type: int, read/write
Specifies the maximum (top) layer index that the tool should look at to derive (create) placement blockages from existing routing blockages.
The layers are defined in the LEF file in process order from bottom to top.
Related Information
Related attributes: cap_table_file
lef_library
pcells
Syntax
pcells <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns physical cell (pcell) information. A physical cell is a cell that is instantiated in the DEF COMPONENTS section but is not instantiated in the netlist. These
cells have neither logical functions or timing arcs. This type of cell is often used to fill gaps in a power grid. Examples include I/O pad corner cells, I/O power
supply pads, filler cells, and decoupling caps.
The pcell attribute returns the following physical cell data: The cell name (instance name), macro name (library cell name), placement status (unplaced, placed
and moveable or placed and not movable), origin (placement location), orientation (how the cell is flipped and rotated), halo, and properties. The halo specifies
a placement blockage that is tied to the instance and will therefore move with the instance. The halo is specified relative to the boundary of the cell starting from
left, bottom, right and top, in that order. The properties come from the DEF mechanism to track user defined instance properties.
The output is of the form:
{cellname macroname placement_status {origin} orientation {halo} {properties}}
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
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Related command: read_def
phys_ignore_nets
Syntax
phys_ignore_nets {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Controls processing of the NETS section in the DEF file by the read_def or write_def commands. By default, the NETS section is processed.
Related Information
Affects these commands: read_def
write_def
phys_ignore_special_nets
Syntax
phys_ignore_special_nets {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Controls processing of the SPECIALNETS section in the DEF file by the read_def or write_def commands.
Related Information
Affects these commands: read_def
write_def
phys_insts
Syntax
phys_insts <list_of_phys_instances>
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Applies to:
design
Description
Default:
Data_type: pcell *, read only
Returns the list of physical instance objects in the design.
phys_skip_and_copy_special_nets
Syntax
phys_skip_and_copy_special_nets {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Specifies whether to skip SPECIALNETS during read_def execution and copy them from original during write_def.
Related Information
Affects these commands: read_def
write_def
regions
Syntax
regions <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns information for all regions defined for the design in the DEF file.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
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Related Information
Related command: read_def
Related attributes: region Attributes
rows
Syntax
rows <list_of_rows>
Applies to:
design
Description
Default:
Data_type: row *, read only
Returns the list of rows in the design.
Related Information
Related command: read_def
sdp_files
Syntax
sdp_files <sdp_files>
Applies to:
design
Description
Default:
Data_type: string*, read only
Returns the SDP relative placement file that has been read in.
Related Information
Related command: read_sdp_file
sdp_groups
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Syntax
sdp_groups <list_of_sdp_groups>
Applies to:
design
Description
Default:
Data_type: sdp_group*, read only
Returns the list of sdp_group objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
sdp_type
Syntax
sdp_type {no_value | datapath | ff_column | both}
Applies to:
design
Description
Default: no_value
Data_type: string, read/write
Specifies the type of the SDP relative placement file read in for the design to create SDP constraints.
Related Information
Set by this command: read_sdp_file
small_blocked_box_count
Syntax
small_blocked_box_count <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Extracts the count of small pcell, fixed, and place boxes used for blocked point.
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Related Information
Related command: read_def
track_count
Syntax
track_count <string>
Applies to:
design
Description
Default:
Data_type: string, read only
Returns the total track count per layer.
utilization
Syntax
utilization <float>
Applies to:
design
gcell
layer
Description
Default: 0.00 (design and gcell), 1.0 (layer)
Data_type: double, read only (design and gcell), read/write (layer)
Returns the actual utilization of the design/gcell/layer.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by this command (gcell): read_def
Set by this attribute (layer): lef_library
utilization_threshold
Syntax
utilization_threshold <float>
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Physical--fill Attributes for Physical
Applies to:
design
Description
Default: 0.95
Data_type: double, read/write
Specifies the maximum value that the design can reach for utilization during synthesis.
The specified value must be in the range of [0.0, 1.0] where a value of 1.0 corresponds to100% utilization for the design.
Example
set_db designs .utilization_threshold 0.8
set_db [get_db designs *] .utilization_threshold 0.8
Related Information
Affects this command: syn_opt -spatial
fill Attributes for Physical
mask
opc
polygons
properties
rects
via
via_mask
via_opc
via_points
mask
mask integer
Read-only fill attribute. Returns the mask number used for the layer of this fill in case double- or triple-patterning lithography is used.
Related Information
Set by this command: read_def
opc
opc {false | true}
Read-only fill attribute. Indicates whether the fill shape requires OPC correction during mask generation.
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Related Information
Set by this command: read_def
polygons
polygons {{pt pt pt [pt]} ...}
Read-only fill attribute. Returns one or more lists. Each list contains the coordinates of at least 3 points of a polygon that is part of this fill. The polygon is
generated by connecting each successive point, and then the first and last points.
Related Information
Set by this command: read_def
Related attributes: rects
layer
properties
properties string
Read-only fill attribute. Returns the properties associated with the fill.
Related Information
Set by this command: read_def
rects
rects {rect...}
Read-only fill attribute. Returns one or more lists. Each list contains the lower left and upper right coordinates of a rectangular-shaped box that is part of this
fill.
Related Information
Set by this command: read_def
Related attributes: layer
polygons
via
via string
Read-only fill attribute. Returns the name of the via associated with this fill.
Related Information
Set by this command: read_def
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Physical--gcell_grid Attribute for Physical
via_mask
via_mask integer
Read-only fill attribute. Returns the mask number associated with the fill via in case double or triple patterning lithography is used.
Related Information
Set by this command: read_def
via_opc
via_opc {false | true}
Read-only fill attribute. Indicates whether the fill via requires OPC correction during mask generation.
Related Information
Set by this command: read_def
via_points
via_points {pt pt pt [pt]}
Read-only fill attribute. Returns the polygon geometry for the fill via.
Related Information
Set by this command: read_def
gcell_grid Attribute for Physical
num_grids
num_grids integer
Default: 0
Read-only gcell_grid attribute. Returns the number of columns or rows in the grid.
gcell Attributes for Physical
demand
horizontal_demand
horizontal_remaining
horizontal_supply
instance_count
pin_count
pin_density
rect
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remaining
supply
utilization
vertical_demand
vertical_remaining
vertical_supply
demand
demand integer
Default: no_value
Read-only gcell attribute. Returns the number of routing tracks used in the preferred routing direction for the layer.
horizontal_demand
horizontal_demand integer
Default: no_value
Read-only gcell attribute. Returns the number of used horizontal routing tracks used in the preferred routing direction for the layer.
horizontal_remaining
horizontal_remaining integer
Read-only gcell attribute. Returns the number of horizontal tracks that are not required for horizontal routing.
Related Information
Set by this command: read_def
horizontal_supply
horizontal_supply integer
Default: no_value
Read-only gcell attribute. Returns the number of total horizontal routing tracks in the preferred routing direction for the layer.
instance_count
instance_count integer
Read-only gcell attribute. Lists the number of instances that the gcell contains.
Related Information
Set by this command: read_def
pin_count
pin_count integer
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Read-only gcell attribute. Returns the number of instance pins that can be accessed within the gcell. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
Related Information
Set by this command: read_def
pin_density
pin_density float
Read-only gcell attribute. Returns the number of pins in the gcell divided by the gcell area. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
Related Information
Set by this command: read_def
rect
rect {{llx lly} {urx ury}}
Read-only gcell attribute. Returns the lower left and upper right coordinates of the gcell. The coordinates can be floating numbers.
Related Information
Set by this command: read_def
remaining
remaining integer
Default: no_value
Read-only gcell attribute. Returns the number of routing tracks remaining in the preferred routing direction for the layer.
supply
supply integer
Default: no_value
Read-only gcell attribute. Returns the total routing tracks in the preferred routing direction for the layer.
utilization
utilization float
Read-only gcell attribute. Returns the actual utilization of the gcell.
Related Information
Set by this command: read_def
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Physical--group Attributes for Physical
vertical_demand
vertical_demand integer
Default: no_value
Read-only gcell attribute. Returns number of vertical routing tracks used in the preferred routing direction for the layer.
vertical_remaining
vertical_remaining integer
Read-only gcell attribute. Returns the number of vertical tracks that are not required for vertical routing.
Related Information
Set by this command: read_def
vertical_supply
vertical_supply integer
Default: no_value
Read-only gcell attribute. Returns total vertical routing tracks in the preferred routing direction for the layer.
group Attributes for Physical
components
constraint_type
def_name
is_floating
members
properties
region
user_created
components
components {<componentName pinName >{0|1} }...
Read-only group attribute. Returns a list of instance belonging to group.
Related Information
Set by this command: read_def
constraint_type
constraint_type string
Read-only group attribute. Returns the group constraint type.
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def_name
def_name string
Read-only group attribute. Returns either the original DEF group name if the group was defined in the DEF file, or the user-defined name in case the group was
created in Genus.
Related Information
Set by these commands: create_group
read_def
is_floating
is_floating {false | true}
Read-only group attribute. Indicates whether the group is floating.
Related Information
Set by this command: create_group
members
members string
Read-only group attribute. Lists the members associated with the group. This is a computed attribute. Computed attributes are potentially very time consuming
to process and not listed by the ls command by default.
Related Information
Set by these commands: create_group
read_def
properties
properties string
Read-only group attribute. Lists the properties (names and values) that are associated with the group.
Related Information
Affected by this command: read_def
region
region string
Read-write group attribute. Specifies the name of the region that is associated with the group.
All instances assigned to this group must be placed within the specified region but other instances not belonging to the group can also be placed within
the region.
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Physical--Ispatial Flow
Related Information
Set by these commands: create_group
read_def
user_created
user_created {false | true}
Read-only group attribute. Indicates whether the group was created by the user in Genus. The attribute returns false if the group was defined in the DEF file.
Related Information
Set by these commands: create_group
read_def
Ispatial Flow
innovus_executable invs_add_io_buffers invs_add_io_buffers_base_name
invs_add_io_buffers_exclude_clock_net invs_add_io_buffers_exclude_nets invs_add_io_buffers_honor_dont_touch
invs_add_io_buffers_in_cells invs_add_io_buffers_include_nets invs_add_io_buffers_out_cells
invs_add_io_buffers_port invs_add_io_buffers_pre_place invs_add_io_buffers_skip_refine_place
invs_add_io_buffers_status invs_add_io_buffers_suffix invs_assign_buffer
invs_assign_removal invs_clk_gate_recloning invs_enable_useful_skew
invs_init_core_row invs_launch_servers invs_memory_usage
invs_opt_leakage invs_opt_leakage_options invs_place_opt_design
invs_postexport_report_script invs_postload_script invs_power_library_flow
invs_pre_place_opt invs_preload_script invs_scanreorder_keepport
invs_set_lib_unit invs_spatial_place_connected invs_temp_dir
invs_timing_driven_place invs_to_genus_colorized_lef_path invs_write_path_groups
invs_write_scandef_options
innovus_executable
innovus_executable path
Default: default_search_order
Read-write root attribute. Specifies the Innovus executable that should be used for the syn_opt command. It overrides the default search order, which first
examines the environment variable ENCOUNTER, next the PATH environment variable, then the CDS_SYNTH_ROOT environment variable. Includes checking to assure
that the specified executable is reachable.
To ensure that Genus uses the proper Innovus executable from the user’s PATH when using the default setting of the attribute, set the following
environment variable before you start Genus:
setenv genus_USE_PATH 1
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Example
The following example takes the Innvovus executable from the specified directory:
set_attribute innovus_executable /path/soce/bin/innovus /
Related Information
Related attribute: phys_checkout_innovus_license
invs_add_io_buffers
Syntax
invs_add_io_buffers {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
This is the main control to enable all add_io_buffer attributes.
invs_add_io_buffers_base_name
invs_add_io_buffers_base_name string
Read-write root attribute. Specifies the base name of the added buffer and net.
invs_add_io_buffers_exclude_clock_net
invs_add_io_buffers_exclude_clock_net {1 | 0 | true | false}
Read-write root attribute. Specifies not to connect the buffer on clock nets. You need to run time_design to check clock net.
invs_add_io_buffers_exclude_nets
invs_add_io_buffers_exclude_nets string
Read-write root attribute. Specifies the of the file that contains the names of the nets to exclude from the buffer attachment operation.
invs_add_io_buffers_honor_dont_touch
invs_add_io_buffers_honor_dont_touch {1 | 0 | true | false}
Read-write root attribute. Specifies to exclude dont touch nets while buffering.
invs_add_io_buffers_in_cells
invs_add_io_buffers_in_cells string
Read-write root attribute. Specifies the cell name or cell names of the input cell buffer. If the specified cell is an inverter, invs_add_io_buffers inserts an inverter
pair.
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invs_add_io_buffers_include_nets
invs_add_io_buffers_include_nets string
Read-write root attribute. Specifies the of the file that contains the names of the nets to include in the buffer attachment operation.
invs_add_io_buffers_out_cells
invs_add_io_buffers_out_cells string
Read-write root attribute. Specifies the cell name or cell names of the output cell buffer. If the specified cell is an inverter, invs_add_io_buffers inserts an
inverter pair.
invs_add_io_buffers_port
invs_add_io_buffers_port {1 | 0 | true | false}
Read-write root attribute. Specifies whether to prepend the port name to the buffer and net names when base name is not given.
invs_add_io_buffers_pre_place
invs_add_io_buffers_port {1 | 0 | true | false}
Read-write root attribute. Specifies if the inverter connected to the port is legally placed and the other inverter is left unplaced.
invs_add_io_buffers_skip_refine_place
invs_add_io_buffers_port {1 | 0 | true | false}
Read-write root attribute. Specifies to skip legalization of the new buffer/inverter. Incremental placement needs to be run later to legalize it.
invs_add_io_buffers_status
invs_add_io_buffers_port {placed | fixed | softfixed}
Read-write root attribute. Specifies the placement status of the added buffer as placed/fixed/softfixed.
invs_add_io_buffers_suffix
invs_add_io_buffers_port string
Read-write root attribute. Specifies the suffix to use in buffer and net names.
invs_assign_buffer
invs_assign_buffer string
Read-write root attribute. Specifies the buffer to use for assign removal in the Innovus® tool. If you set the attribute value to auto, the tool will automatically
select the buffer type. If you set the attribute value to none, the tool will use virtual buffers.
invs_assign_removal
invs_assign_removal {false | true}
Default: false
Read-write root attribute. Specifies whether to perform assign removal in the Innovus® Implementation System.
invs_clk_gate_recloning
invs_clk_gate_recloning {false | true}
Default: false
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Read-write root attribute. Specifies whether to perform clock-gating recloning in the Innovus Implementation System (that is, use the -clkGateRecloning option
of the Innovus placeDesign command during placement).
invs_enable_useful_skew
invs_enable_useful_skew {true | false}
Default: true
Read-write root attribute. Controls whether to use the useful skew information—dumped by the Innovus Implementation System in the latency.sdc file—during
placement optimization in Genus.
Related Information
Affects this command: syn_opt -physical
invs_init_core_row
Syntax
invs_init_core_row {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies that Innovus based Genus flows should force application of init_core_row after loading of the exchange DB. One potential need for this is to clean
up a third-party generated DEF file to meet Innovus standards.
Specify this attribute before you issue the syn_opt -spatial command.
Related Information
Affects this command: syn_opt -spatial
invs_launch_servers
invs_launch_servers string
Read-write root attribute. Specifies a list of servers that can be used to launch an Innovus batch process. The tool first tries to launch the batch job on the first
specified. server. If this attempt fails, the tool will try to launch on the next server, and so on.
The batch job is used to run placement in the physical flow.
The process uses the same controls as for Genus’s super-threading capability and has the same license requirements as super-threading.
You can use other servers than those specified with the super_thread_servers attribute.
Example
The following command specifies to run the placement job on servers linux21 and linux24.
set_attr invs_launch_servers {linux21 linux24} /
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Related Information
Reducing Runtime Using Super-Threading in Genus User Guide.
Related attributes: super_thread_batch_command
super_thread_kill_command
super_thread_status_command
invs_memory_usage
invs_memory_usage double
Default: no_value
Read-only root attribute. Specifies the peak memory usage by Innovus during execution of syn_opt command.
invs_opt_leakage
invs_opt_leakage {false| true}
Default: false
Read-write root attribute. Controls whether to enable the optLeakagePower command after the place_opt_design command in the Innovus Implementation
System.
invs_opt_leakage_options
invs_opt_leakage_options string
Read-write root attribute. Specifies any options to be used with the optLeakagePower command in the Innovus Implementation System.
Example
set_attribute invs_opt_leakage_options ’-allowResizing’ /
invs_place_opt_design
invs_place_opt_design {true| false}
Default: true
Read-write root attribute. Enables concurrent placement and optimization in the Innovus Implementation System.
invs_postexport_report_script
invs_postexport_report_script string
Default: no_value
Read-write root attribute. Specifies the path of the script to enable reporting only after design has been exported from Innovus.
invs_postload_script
Syntax
invs_postload_script <string>
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Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the script to include in the Innovus setup file after the setup steps (after the libraries, design, user constraints, and user modes are loaded) and before
placement is started. The script will be sourced after the genus2invs.invs_setup.tcl file.
Example
The following is an example of such a script:
timeDesign -prePlace outDir ./ zwlm
Related Information
Related commands: syn_opt -spatial
invs_power_library_flow
invs_power_library_flow {false | true}
Read-write root attribute. Specifies whether to pass the power library and power analysis view to Innovus through the multi-mode file.
The script will be sourced after the genus2invs.invs_setup.tcl file.
Example
Following is an example of such a script:
timeDesign -prePlace outDir ./ zwlm
invs_pre_place_opt
invs_pre_place_opt {true | false}
Default: true
Read-write root attribute. Specifies whether to perform buffer and inverter pair removal during placement. This pre-placement optimization occurs when using
the syn_opt command.
invs_preload_script
invs_preload_script string
Read-write root attribute. Specifies the script to include in the Innovus setup file prior to the setup steps (before the libraries and the design are loaded).
Example
Following is an example of such a script:
set_global report_timing_format {hpin cell fanout load slew delay arrival} set_table_style -name report_timing -max_widths {256} suppressMessage SOCLF 200
invs_scanreorder_keepport
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invs_scanreorder_keepport {false | true}
Default: false
Read-write root attribute. Controls whether to include the setScanReorderMode -keepPort file command in the Innovus setup file.
invs_set_lib_unit
invs_set_lib_unit {false | true}
Default: true
Read-write root attribute. Controls whether to include the timing and capacitance units in the Innovus setup file.
Set this attribute when you read in multiple libraries with inconsistent units.
invs_spatial_place_connected
Syntax
invs_spatial_place_connected <string>
Applies to:
root
Default:
Data_type: string. read/write
Description
Specifies 'place_connected' calls to be made in Innovus after loading iSpatial design, before place_opt_design.
invs_temp_dir
invs_temp_dir string
Read-write root attribute. Specifies the directory in which the Innovus interface files (such as, .conf, .def, .sdc, netlist, and so on) generated during syn_opt
must be stored.
Files with the genus2invs prefix can be used to transfer data from Genus to the Innovus™ Implementation System tool. Files with the invs2genus prefix can be
used to transfer data from Innovus to Genus.
The directory also contains setup files to reload the design in Innovus and Genus. The setup files allow the user to reload the state of the design before and
after placement.
genus2invs.genus_setup.tcl —reloads the design in Genus before placement.
genus2invs.invs_setup.tcl—reloads the design in Innovus before placement.
invs2genus.genus_setup.tcl—reloads the design in Genus after placement.
invs2genus.invs_setup.tcl—reloads the design in Innovus after placement.
invs_timing_driven_place
invs_timing_driven_place {true | false}
Default: true
Read-write root attribute. Specifies whether to activate Innovus timing-driven placement to generate the silicon virtual prototype when using the syn_opt
command. Timing-driven placement balances the importance of meeting setup timing constraints with routability, resulting in placement that is better suited for
timing closure.
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Physical--layer Attributes for Physical
Using this attribute can cause an increase in run time.
invs_to_genus_colorized_lef_path
invs_to_genus_colorized_lef_path string
Read-write root attribute. Specifies the directory path for storing a copy of the colorized LEF file generated by Innovus.
invs_write_path_groups
Syntax
invs_write_path_groups {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether to write out all path groups to use internally within Ispatial.
If the path-groups are fully compatible with Innovus they will be exchanged on return from iSpatial. Fully compatible groups are those created with 'group_path'
and not 'path_group'. Additionally, some groups need to be marked as high-effort through 'set_path_group_options'.
If the groups are not fully compatible, they can be sent to Innovus to guide optimization but will not be returned from Innovus.
Related Information
Related Commands: group_path
path_group
set_path_group_options
invs_write_scandef_options
invs_write_scandef_options string
Read-write root attribute. Specifies the options of the write_scandef command used to write the scanDEF for Innovus.
layer Attributes for Physical
area
cap_multiplier
cap_table_name
capacitance
color
eol_keepout
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eol_spacing
first_column_cut_spacing
layer_index
mask
max_adjacent_spacing
max_cut_spacing
max_width
min_spacing
min_width
offset
offset_x
offset_y
pitch
pitch_x
pitch_y
resistance
route_index
same_mask_spacing
smallest_min_spacing
used
utilization
via_length
via_width
visible
width
area
area float
Read-only layer attribute. Returns the minimum required area for polygons on this metal layer.
cap_multiplier
cap_multiplier float
Read-only layer attribute. Returns the multiplier for the interconnect capacitance that accounts for increases in capacitance caused by nearby wires.
Related Information
Set by this attribute: lef_library
cap_table_name
cap_table_name string
Read-only layer attribute. Returns the corresponding layer name in the capacitance table file.
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Related Information
Set by this attribute: cap_table_file
capacitance
capacitance float
Read-only layer attribute. Returns the capacitance for each square unit, in picofarads per square micron.
Related Information
Set by this attribute: lef_library
Related attribute: (lib_pin) capacitance
color
color string
Read-write layer attribute. Specifies the color of the layer in the GUI.
eol_keepout
eol_keepout string
Read-only layer attribute. Returns the layer end-of-line KEEPOUT rule that is applied when the EXCEPTEOL condition is met.
For more information refer to the LEF/DEF 5.8 Language Reference
eol_spacing
eol_spacing float
Read-only layer attribute. Returns the layer end-of-line spacing value (in micron) that is applied when the EXCEPTEOL condition is met.
For more information refer to the LEF/DEF 5.8 Language Reference
first_column_cut_spacing
first_column_cut_spacing double
Default: 0.0
Read-only layer attribute. Returns the first column cut spacing for via bottom layer.
layer_index
layer_index integer
Read-only layer attribute. Returns the index for this layer. The first routing layer in the process has index 0.
The layers are defined in the LEF file in process order from bottom to top.
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Related Information
Set by this attribute: cap_table_file
mask
mask integer
Read-only layer attribute. Returns the number of masks that will be used for double- or triple-patterning for this layer.
max_adjacent_spacing
max_adjacent_spacing float
Read-only layer attribute. Returns the maximum adjacent spacing for the via bottom layer.
max_cut_spacing
max_cut_spacing float
Read-only layer attribute. Returns the maximum spacing for the via bottom layer.
max_width
max_width float
Read-only layer attribute. Returns the maximum width of a track on the layer.
min_spacing
min_spacing float
Read-only layer attribute. Returns the minimum spacing between tracks on the layer.
min_width
min_width float
Read-only layer attribute. Returns the minimum width of a track on the layer.
offset
offset float
Read-only layer attribute. Returns the offset from the design origin for the preferred direction routing tracks of the layer.
offset_x
offset_x float
Read-only layer attribute. Returns the x offset from the design origin for the vertical routing tracks of the layer.
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offset_y
offset_y float
Read-only layer attribute. Returns the y offset from the design origin for the horizontal routing tracks of the layer.
pitch
pitch float
Read-only layer attribute. Returns the required routing pitch (in microns) for the layer. The pitch for a given routing layer specifies the distance between routing
tracks in the preferred direction for that layer.
Related Information
Set by this attribute: lef_library
pitch_x
pitch_x float
Read-only layer attribute. Returns the required x routing pitch (in microns) for the layer. The x pitch specifies the distance between the vertical routing tracks for
that layer.
Related Information
Set by this attribute: lef_library
pitch_y
pitch_y float
Read-only layer attribute. Returns the required y routing pitch (in microns) for the layer. The y pitch specifies the distance between the horizonatl tracks for that
layer.
Related Information
Set by this attribute: lef_library
resistance
resistance float
Read-only layer attribute. Returns the resistance for a square of wire, in ohms per square.
Related Information
Set by this attribute: lef_library
route_index
route_index integer
Default: 0
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Read-only layer attribute. Returns the route index value for the layer.
same_mask_spacing
same_mask_spacing double
Default: 0.0
Read-only layer attribute. Returns the smallest same mask spacing for the layer.
smallest_min_spacing
smallest_min_spacing double
Read-only layer attribute. Specifies the minimum spacing for the layer.
Default: 0.0
Related Information
Set by this attribute: lef_library
used
used {false | true}
Read-only layer attribute. Indicates whether this layer is used in PLE calculations.
utilization
utilization float
Read-write layer attribute. Specifies the layer utilization.
Each metal layer has a fixed number of tracks that can be used for routing. This attribute lets you define the percentage of tracks that the router can use for this
layer.
Related Information
Set by this attribute: lef_library
via_length
via_length double
Default: 0.0
Read-only layer attribute. Returns via length for via bottom layer.
via_width
via_width double
Default: 0.0
Read-only layer attribute. Returns via width for via bottom layer.
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Physical--net Attributes for Physical
visible
visible {false | true}
Default: false
Read-write layer attribute. Indicates whether this layer is visible in the GUI.
width
width float
Read-only layer attribute. Returns the default routing width (in microns) to use for all regular wiring on the layer.
Related Information
Set by this attribute: lef_library
net Attributes for Physical
annotated_capacitance_max
annotated_capacitance_max float
Read-write net attribute. Specifies the capacitance from the parasitic annotation.
physical_cap
physical_cap float
Read-write net attribute. Specifies the capacitance, in femtofarads, from the parasitic annotation.
pcell Attributes for Physical
def_name
height
is_spare
model
orient
orientation
placement_status
properties
urx
ury
weight
width
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Physical--net Attributes for Physical
def_name
def_name string
Read-only pcell attribute. Returns the DEF name of the pcell.
Related Information
Set by this command: read_def
height
height float
Read-only pcell attribute. Returns the height, in microns, of the object based on the information from the physical library.
Related Information
Set by this command: read_def
Related attribute: (pcell) width
is_spare
is_spare {1 | 0 | false| true}
Default: false
Read-write pcell attribute. Indicates that the instance is a spare instance. These are used by post-mask ECO flows.
model
model string
Read-only pcell attribute. Returns the model of which this pcell is an instance. The model refers to a MACRO defined in the LEF library.
Related Information
Set by this command: read_def
orient
orient string
Read-only pcell attribute. Returns the orientation of the pcell. Following are the possible orientations: N, S, E, W, FN, FS, FE, or FW.
Related Information
Set by this command: read_def
orientation
orientation string
Read-only pcell attribute. Returns the orientation of the pcell. Following are the possible orientations: N, S, E, W, FN, FS, FE, or FW.
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Related Information
Set by this command: read_def
Related attribute: (row) orientation
placement_status
placement_status string
Read-only pcell attribute. Returns the placement status of the pcell. Possible values are:
cover—pcell has a location, is part of the cover macro and cannot be moved by automatic tools
fixed—pcell has a location and cannot be moved by automatic tools
placed—pcell has a location and can be moved by automatic tools
unplaced—pcell has no location
Related Information
Set by this command: read_def
properties
properties string
Read-only pcell attribute. Returns the properties associated with the pcell.
Related Information
Set by this command: read_def
urx
urx float
Read-only pcell attribute. Returns the x-coordinate of the upper right corner of the pcell.
Related Information
Set by this command: read_def
ury
ury float
Example
genus:/designs/rct/physical> [get_db pcells *foo2] .ury28000.000
Read-only pcell attribute. Returns the y-coordinate of the upper right corner of the pcell.
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Physical--pdomain Attributes for Physical
Related Information
Set by this command: read_def
weight
weight integer
Read-only pcell attribute. Returns the weight assigned to the pcell, which determines whether or not automatic placement attempts to keep the pcell near the
location specified in the DEF file. The weight is only meaningful when the pcell is placed.
Related Information
Set by this command: read_def
width
width float
Read-only pcell attribute. Returns the width of the pcell.
Related Information
Set by this command: read_def
Related attribute: (pcell) height
pdomain Attributes for Physical
boundary
cutouts
mingap
rects
rsext
boundary
boundary string
Read-only pdomain attribute. Returns the coordinates of the physical boundary of the power domain.
Related Information
Set by this command: read_def
cutouts
cutouts string
Read-only pdomain attribute. Returns the list of power domain region cutouts. For example, if a square region boundary is defined, you can remove a corner by
specifying a cutout.
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Physical--place_blockage Attributes for Physical
Related Information
Set by this command: read_def
mingap
mingap string
Read-only pdomain attribute. Returns the top, bottom, left, and right distance, in microns, that must be reserved from the power domain boundary edges for
power routing.
Related Information
Set by this command: read_def
rects
rects {rect...}
Read-only pdomain attribute. Returns a Tcl list of power domain region rectangles after cutout processing.
Related Information
Set by this command: read_def
rsext
rsext string
Read-only pdomain attribute. Returns the top, bottom, left, and right boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
Related Information
Set by this command: read_def
place_blockage Attributes for Physical
def_name
def_name string
Read-only place_blockage attribute. Returns the DEF name of the place_blockage.
Related Information
Set by this command: read_def
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Physical--pnet Attributes for Physical
properties
properties string
Read-only place_blockage attribute. Returns the properties associated with the place_blockage.
Related Information
Set by this command: read_def
pnet Attributes for Physical
capacitance
components
def_name
fixedbump
frequency
original_name
path_count
path_index
path_value
pattern
properties
rc_name
route_rule
shieldnet
source
use
visible
weight
xtalk
capacitance
capacitance float
Read-only pnet attribute. Returns the estimated wire capacitance. This is the value specified for the ESTCAP keyword in the DEF file.
Related Information
Set by this command: read_def
components
components {componentName pinName {0|1} }...
Read-only pnet attribute. Returns one or more lists. Each list contains the regular component pin on a net or a subnet, its corresponding component, and an
indication whether the pin is part of a synthesized scan chain.
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Related Information
Set by this command: read_def
def_name
def_name string
Read-only pnet attribute. Returns the name of the DEF net.
Related Information
Set by this command: read_def
fixedbump
fixedbump {false | true}
Read-only pnet attribute. Indicates whether the bump net in the net can be reassigned to a different pin.
Related Information
Set by this command: read_def
frequency
frequency float
Read-only pnet attribute. Returns the frequency of the net in Hertz. The frequency value is used by the router to choose the correct number of via cuts required
for a given net.
Related Information
Set by this command: read_def
original_name
original_name string
Read-only pnet attribute. Returns the name of the original net that was partitioned and that includes this net. This name was specified with the ORIGINAL
keyword in the DEF file.
Related Information
Set by this command: read_def
path_count
path_count integer
Read-only pnet attribute. Returns the number of paths for this net.
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Related Information
Set by this command: read_def
path_index
path_index integer
Default: 0
Read-write pnet attribute. Specifies the index of the path of the net for which you want to get more information through the path_value attribute.
Related Information
Sets this attribute: path_value
path_value
path_value string
Read-only pnet attribute. Returns the information for the path identified through the path_index attribute.
Related Information
Set by this attribute: path_index
pattern
pattern string
Read-only pnet attribute. Returns the routing pattern used for this net. The routing pattern can be one of the following:
BALANCED—Used to minimize skews in timing delays for clock nets.
STEINER—Used to minimize net length.
TRUNK—Used to minimize delay for global nets.
WIREDLOGIC—Used in ECL designs to connect output and must join pins before routing to the remaining pins.
Related Information
Set by this command: read_def
properties
properties {propertyName propertyValue}...
Read-only pnet attribute. Returns one or more lists. Each list contains a property defined for this net, that is, a property name followed by its value.
Related Information
Set by this command: read_def
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Physical--pnet Attributes for Physical
rc_name
rc_name string
Read-only pnet attribute. Returns the name that Genus gave to this net.
route_rule
route_rule string
Read-only pnet attribute. Returns the LEF-defined route_rule name that is used when creating the net and wiring.
Related Information
Set by this command: read_def
shieldnet
shieldnet string
Read-only pnet attribute. Returns the name of a special net that shields this net.
Related Information
Set by this command: read_def
source
source string
Read-only pnet attribute. Returns how the net was created.
DIST—Net is the result of adding physical components (that is, components that only connect to power or ground nets), such as filler cells, well-taps, tie-
high and tie-low cells, and decoupling caps.
NETLIST—Net is defined in the original netlist. This is the default value, and is not normally written out in the DEF file.
TEST—Net is part of a scan chain.
TIMING—Net represents a logical rather than physical change to netlist, and is used typically as a buffer for a clock-tree, or to improve timing on long nets.
USER—Net is user defined.
Related Information
Set by this command: read_def
use
use string
Read-only pnet attribute. Returns the use of the net.
ANALOG—Used as an analog signal net.
CLOCK—Used as a clock net.
GROUND—Used as a ground net.
POWER—Used as a power net.
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Physical--power_domain Attributes for Physical
RESET—Used as a reset net.
SCAN—Used as a scan net.
SIGNAL—Used as a digital signal net.
TIEOFF—Used as a tie-high or tie-low net.
Related Information
Set by this command: read_def
visible
visible {false | true}
Read-only pnet attribute. Indicates whether this net is visible in the GUI.
weight
weight integer
Read-only pnet attribute. Returns the weight assigned to the net. Automatic layout tools attempt to shorten the lengths of nets with high weights. A value of 0
indicates that the net length for that net can be ignored. The value of 1 specifies that the net should be treated normally. A larger weight specifies that the tool
should try harder to minimize the net length of that net.
Related Information
Set by this command: read_def
xtalk
xtalk integer
Read-only pnet attribute. Returns the crosstalk class number for the net. The value ranges between 0 and 200.
Related Information
Set by this command: read_def
power_domain Attributes for Physical
disjoint_hinst_box_list
ext_bottom
ext_edges
ext_left
ext_right
ext_top
extend_power_bottom
extend_power_left
extend_power_right
extend_power_top
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Physical--power_domain Attributes for Physical
first_row_site_index
gap_bottom
gap_edges
gap_left
gap_right
gap_top
last_row_site_index
min_gaps
rects
row_pattern_site
row_space_type
row_spacing
rs_exts
disjoint_hinst_box_list
disjoint_hinst_box_list string
Read-write power_domain attribute. Returns a list of hierarchcial instances and disjoint boxes that define the power domain boundary.
ext_bottom
ext_bottom coordinate
Read-only power_domain attribute. Returns the bottom edge of the boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
ext_edges
ext_edges list_of_coordinates
Read-only power_domain attribute. Returns the top, bottom, left, and right edges of the boundary for legal targets to be used by the power planning and routing
commands, in conjunction with the power domain boundary.
ext_left
ext_left coordinate
Read-only power_domain attribute. Returns the left edge of the boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
ext_right
ext_right coordinate
Read-only power_domain attribute. Returns the right edge of the boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
ext_top
ext_top coordinate
Read-only power_domain attribute. Returns the top edge of the boundary for legal targets to be used by the power planning and routing commands, in
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conjunction with the power domain boundary.
extend_power_bottom
extend_power_bottom coordinate
Read-write power_domain attribute. Returns the bottom edge of the boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
extend_power_left
extend_power_left coordinate
Read-write power_domain attribute. Returns the left edge of the boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
extend_power_right
extend_power_right coordinate
Read-write power_domain attribute. Returns the right edge of the boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
extend_power_top
extend_power_top coordinate
Read-write power_domain attribute. Returns the top edge of the boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
first_row_site_index
first_row_site_index int
Read-write power_domain attribute. Specifies the first row site index value.
gap_bottom
gap_bottom coordinate
Read-write power_domain attribute. Returns the distance, in microns, that must be reserved from the bottom edge of the power domain boundary for power
routing.
gap_edges
gap_edges list_of_coordinates
Read-only power_domain attribute. Returns the top, bottom, left, and right distance, in microns, that must be reserved from the power domain boundary edges for
power routing.
gap_left
gap_left coordinate
Read-write power_domain attribute. Returns the distance, in microns, that must be reserved from the left edge of the power domain boundary for power routing.
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Physical--power_domain Attributes for Physical
gap_right
gap_right coordinate
Read-write power_domain attribute. Returns the distance, in microns, that must be reserved from the right edge of the power domain boundary for power routing.
gap_top
gap_top coordinate
Read-write power_domain attribute. Returns the distance, in microns, that must be reserved from the top edge of the power domain boundary for power routing.
last_row_site_index
last_row_site_index int
Read-write power_domain attribute. Specifies the last row site index value.
min_gaps
min_gaps string
Read-only power_domain attribute. Returns the top, bottom, left, and right distance, in microns, that must be reserved from the power domain boundary edges for
power routing.
rects
rects {rect...}
Read-write power_domain attribute. Returns a Tcl list of boxes that define the power domain boundary.
row_pattern_site
row_pattern_site site
Read-write power_domain attribute. Specifies the site name of the row pattern for power domain.
row_space_type
row_space_type {0 | 1 | 2}
Default: 2
Read-write power_domain attribute. Determines whether the row spacing value applies between no row (0), each row (1), or each pair of rows (2).
row_spacing
row_spacing double
Read-write power_domain attribute. Specifies the row spacing between each row (1) or each pair of rows (2) as specified in row_space_type.
rs_exts
rs_exts string
Read-write power_domain attribute. Returns the top, bottom, left, and right boundary for legal targets to be used by the power planning and routing commands, in
conjunction with the power domain boundary.
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Physical--region Attributes for Physical
region Attributes for Physical
def_name
derived_from_power_domain
properties
rects
user_created
def_name
def_name string
Read-only region attribute. Returns either the original DEF region name if the region was defined in the DEF file, or the user-defined name in case the region
was created in Genus.
Related Information
Set by these commands: create_region
read_def
derived_from_power_domain
derived_from_power_domain {false | true}
Read-only region attribute. Indicates whether this region was created when the power domain physical boundary was created.
properties
properties string
Read-only region attribute. Lists the properties that are associated with the region.
Related Information
Set by this command: read_def
rects
rects {rect}...
Read-only region attribute. Returns one or more lists. Each list contains the lower left and upper right coordinates of a rectangular area in the region. The
coordinates can be floating numbers.
Related Information
Set by these commands: create_region
read_def
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Physical--root Attributes for Physical
user_created
user_created {false | true}
Read-only region attribute. Indicates whether the region was created by the user in Genus. The attribute returns false if the region was defined in the DEF file.
Related Information
Set by these commands: create_region
read_def
root Attributes for Physical
cap_table_file congestion_effort db_units
def_output_escape_multibit def_output_version delaycal_enable_high_fanout
design_bottom_routing_layer design_process_node design_top_routing_layer
extract_rc_lef_tech_file_map force_via_resistance highlighted
init_lef_files init_lib_phys_consistency_checks interconnect_mode
layers lef_library lef_manufacturing_grid
lef_stop_on_error lef_units oa_def_file
opt_spatial_common_db opt_spatial_early_clock opt_spatial_merge_flops
opt_spatial_useful_skew phys_annotate_ndr_nets phys_assume_met_fill
phys_checkout_innovus_license phys_density_based_balancing_max_area_ratio phys_density_based_balancing_min_area_ratio
phys_extra_vias_length_factor phys_fix_multi_height_cells phys_flow_effort
phys_pre_place_iopt phys_premorph_density phys_read_script_large_file_source
phys_refresh_power_intent_1801 phys_scan_def_file phys_summary_table_print_negative_tns
phys_update_preannotation_script physical_aware_multibit_mapping physical_force_predict_floorplan
pqos_ignore_msv pqos_ignore_scan_chains pqos_placement_effort
predict_floorplan_allow_core_reshape predict_floorplan_allow_illegal_macro predict_floorplan_constraints
predict_floorplan_enable_cpg predict_floorplan_invs_post_resize_script predict_floorplan_keep_fences
predict_floorplan_keep_fixed_macros predict_floorplan_script predict_floorplan_skip_propagate_activity
predict_floorplan_use_innovus qos_report_power qrc_tech_file
read_def_fuzzy_name_match read_def_keep_net_property read_def_libcell_mismatch_error
read_qrc_tech_file_rc_corner report_logic_levels_histogram_fixed_depth report_ndr_min_layer_count
route_early_global_horizontal_supply_scale_factor route_early_global_num_tracks_per_clock_wire route_early_global_secondary_pg
route_early_global_vertical_supply_scale_factor route_rules scale_of_cap_per_unit_length
scale_of_res_per_unit_length selected shrink_factor
sites source_of_via_resistance via_resistance
vias
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Physical--root Attributes for Physical
cap_table_file
cap_table_file capacitance_table_file
Read-write root attribute. Specifies the capacitance table file for technology mapping. You can specify only one file. This file can be encrypted. Genus uses the
capacitance table to derive the capacitance unit per length, resistance unit per length, and area unit per length.
The LEF file can contain the same information but in all cases, Genus will use the latest specification.
Read-only rc_corner attribute. Returns the capacitance table file for this rc_corner.
You must specify the LEF files before the capacitance table file.
Example
genus@root:> get_db rc_corner:rc_corner .cap_table_file
../Captable/cln28hpl_1p10m+alrdl_5x2yu2yz_typical.capTbl
Related Information
Set by this command: create_rc_corner
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: lef_library
scale_of_cap_per_unit_length
scale_of_res_per_unit_length
congestion_effort
congestion_effort {off | low | medium | high)
Default: off
Read-write root attribute. Specifies the effort that the incremental optimization engine should use to optimize congestion. By default, congestion is not taken
into account.
Related Information
Affects this command: syn_opt -incr
db_units
db_units integer
Read-only root attribute. Returns the number of database units used per micron in either the LEF file or the Open Access (OA) technology file.
def_output_escape_multibit
def_output_escape_multibit {true | false}
Default: true
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Physical--root Attributes for Physical
Read-write root attribute. Specifies whether to add an escape character (\) before the brackets in component names and before bit blasted ports and nets.
Example
By default, reg_out[1] is written as reg_out\[1\].
def_output_version
def_output_version string
Default: 5.8
Read-write root attribute. Specifies the DEF version to use for DEF export. Supported versions are 5.3 and up. The default for the attribute is the latest
supported version.
Related Information
Affects these commands: syn_generic -physical
syn_opt -physical
write_def
write_design
write_design -innovus
delaycal_enable_high_fanout
Syntax
delaycal_enable_high_fanout {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enables the default net delay which will be annotated on high fanout nets.
Related Information
Related commands: syn_opt
setDelayCalMode
getDelayCalMode
design_bottom_routing_layer
design_bottom_routing_layer string
Read-write root attribute. Specifies the lowest LEF layer name for global and detail routing.
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design_process_node
design_process_node integer
Default: no_value
Read-write root attribute. Specifies the value for the setDesignMode -process command of the Innovus™ Implementation System. This command option
specifies the process technology value (in nanometers). Valid values are in the range of 3 to 250.
This attribute is set by you or is derived from design_mode_node.
design_top_routing_layer
Syntax
design_top_routing_layer <layerName>
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the highest LEF layer name for global and detail routing.
extract_rc_lef_tech_file_map
Syntax
extract_rc_lef_tech_file_map <string>
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the layer mapping file to map LEF file layers to QRC tech file layers. If used, the layer map file can be in any of the following formats:
Cadence format as shown below:
M0 M0 \
M1 M1 \
M2 M2 \
...
QRC (Common Command Language (CCL)) format as shown below:
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extraction_setup \
-technology_layer_map \
M0 m0 \
V0 via0 \
M1 m1 \
V1S via1 \
...
Related Information
Affects these commands: syn_generic
syn_map
force_via_resistance
force_via_resistance float
Default: no_value
Read-write root attribute. When specified, overrides the via resistance value read from the capacitance table file or the LEF library. Specify the new value in
ohm. A warning is given when the specified value is set too high or too low. For example, you can use this attribute to account for double via routing.
Example
legacy_genus:/> get_attr via_resistance /4.0legacy_genus:/> set_attr force_via_resistance 8 /Forced via resistance is too large. Single via resistance is
’4.000’. Setting attribute of root ’/’: ’force_via_resistance’ = 8.0legacy_genus:/> set_attr force_via_resistance 1.5 /Forced via resistance is too small.
Single via resistance is ’4.000’. Setting attribute of root ’/’: ’force_via_resistance’ = 1.5legacy_genus:/> set_attr force_via_resistance 2.5 / Setting
attribute of root ’/’: ’force_via_resistance’ = 2.5legacy_genus:/> set_attr force_via_resistance 5.5 / Setting attribute of root ’/’: ’force_via_resistance’ =
5.5
Related Information
Related attributes: cap_table_file
lef_library
via_resistance
highlighted
highlighted string
Read-only root attribute. Returns the list of all highlighted objects in the GUI.
init_lef_files
init_lef_files string
Read-only root attribute. Returns the list of LEF files that have been read in.
init_lib_phys_consistency_checks
init_lib_phys_consistency_checks {true | false}
Default: true
Read-write root attribute. Specifies whether to perform a consistency check between the timing and physical library.
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interconnect_mode
Syntax
interconnect_mode {wireload | ple}
Applies to:
root
Description
Default: wireload
Data_type: enum, read/write
Determines whether Genus should use the wire-load models or physical layout estimators (PLEs) during synthesis.
When you read in LEF libraries, the interconnect_mode attribute is automatically set to ple. In this case, Genus will use the physical information from the LEF
and capacitance table file during synthesis instead of the wire-load model from the technology library.
In ple mode the cell area defined in the LEF will be used in place of those in the timing library (.lib) area. The timing library area will be used if the physical
libraries do not contain any cell definitions.
layers
layers list_of_layers
Read-only root attribute. Returns the list of all layer objects. This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the ls command by default.
lef_library
lef_library lef_library
Read-write root attribute. Specifies the LEF libraries for technology mapping. Specifically, Genus will use the wire resistance, capacitance, area, and site size
information in the LEF library. The capacitance table file can contain the same information but in all cases, Genus will use the latest specification. You must
specify the LEF libraries before the capacitance table file for the best synthesis results.
Cells that are found in the timing library but not in the LEF library will be marked as avoid. That is, the avoid attribute will be set to true. on those cells that are in
the .lib file but not in the LEF file.
When you read in LEF libraries, the cell area defined in the LEF libraries will be used instead of the cell area specified in the timing library (.lib). The timing
library area will be used if the physical libraries do not contain any cell definitions.
Reading in LEF libraries, sets the interconnect_mode root attribute to ple.
Genus supports LEF 5.3 and above.
You must import all LEF libraries, not just the technology LEF. You must specify the technology LEF file first.
Example
The following example specifies two LEF libraries, tech.lef and cell.lef:
legacy_genus:/> set_attribute lef_library {tech.lef cell.lef}
The following example differs from the above example: it replaces the existing LEF file because it specifies the files separately with two set_attribute
commands as opposed to a Tcl list with one set_attribute command.
legacy_genus:/> set_attribute lef_library tech.lef
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legacy_genus:/> set_attribute lef_library cell.lef
Related Information
Related attributes: avoid
cap_table_file
interconnect_mode
scale_of_cap_per_unit_length
scale_of_res_per_unit_length
lef_manufacturing_grid
lef_manufacturing_grid float
Read-only root attribute. Returns the MANUFACTURINGGRID value defined in the LEF library in microns.
Related Information
Related attribute: lef_library
lef_stop_on_error
lef_stop_on_error {false | true}
Default: false
Read-write root attribute. Specifies whether the tool should stop when it encounters an error in the LEF file. By default, the tool ignores the LEF parse errors.
Related Information
Related attribute: lef_library
lef_units
lef_units integer
Read-only root attribute. Returns the units specified in the LEF file.
Related Information
Related attribute: lef_library
oa_def_file
oa_def_file string
Read-write root attribute. Returns the DEF file created by the import_oa_db command.
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opt_spatial_common_db
opt_spatial_common_db string
Read-write root attribute. Path of final common DB from iSpatial flow. This attribute is applicable only valid for MMMC designs in Stylus UI.
opt_spatial_early_clock
opt_spatial_early_clock {0 | 1 | true | false}
Default: false
Read-write root attribute. Use early clock flow within Innovus for executing opt_spatial_effort -extreme.
opt_spatial_merge_flops
opt_spatial_merge_flops {false | true | mergeOnly | splitOnly}
Default: false
Read-write root attribute. Use flop merging within Innovus for executing opt_spatial_effort -extreme.
opt_spatial_useful_skew
opt_spatial_useful_skew {0 | 1 | true | false}
Default: true
Read-write root attribute. Use useful-skew optimization within Innovus for executing opt_spatial_effort -extreme.
phys_annotate_ndr_nets
phys_annotate_ndr_nets {true | false}
Default: true
Read-write root attribute. Annotates SPEF data for non-default routes (NDRs) and for nets assigned to higher metal layers. Using the SPEF data improves
correlation with the Innovus System and improves QoS by focusing on the correct timing paths.
Genus Physical does not natively use higher metal layers or NDRs for route estimation. By using Innovus SPEF, Genus Physical can accurately model the R/C
for these special routes and ensure good correlation.
If you want to enable NDRs for optimization, you need to specify the appropriate settings in the script passed to Innovus using using the
enc_postload_script root attribute.
phys_assume_met_fill
phys_assume_met_fill float
Read-write root attribute. Takes into account the metal fill in the design during extraction.
For preroute extraction, when calculating the capacitance of a wire segment on layer N , the tool assumes layer N-1 and layer N+1 to be filled. You can specify
one of the following values:
0 : Assumes no metal fill in layer N .
When you do not specify this parameter, the software assumes no metal fill in layer N. This is equivalent to setting the scalevalue parameter to 0 .
1 : Assumes full metal fill at minimum spacing distance.
Where there is a minimum of signal-to-signal spacing, the cross-coupling capacitance will be extracted and reported.
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Where there is no wire within the minimum spacing, a capacitance to ground will mimic minimum-spaced metal fill in that location.
x: Capacitance value is calculated once with full metal fill and once without metal fill. The user-specified scale value (decimal value between 0 and 1)
determines the interpolation point between the two calculated values, for example, 0.5
phys_checkout_innovus_license
phys_checkout_innovus_license {false | true}
Default: false
Read-write root attribute. Controls whether the Innovus™ Implementation System can check out the appropriate Innovus license(s) for the requested features.
By default, Genus Physical uses the basic placement capabilities available in Innovus without using any Innovus license. Set this attribute to true to force the
Innovus™ Implementation System to check out the appropriate Innovus license(s) needed for the features that you use in your script. You will get an error if you
do not have access to the required licenses.
phys_density_based_balancing_max_area_ratio
phys_density_based_balancing_max_area_ratio double
Default: 1.444
Read-write root attribute. Specifies the area ratio limit on tall base cell set.
phys_density_based_balancing_min_area_ratio
phys_density_based_balancing_min_area_ratio double
Default: 0.0
Read-write root attribute. Specifies the area ratio limit on short base cell set.
phys_extra_vias_length_factor
Syntax
phys_extra_vias_length_factor <double>
Applies to:
root
Description
Default: 0.0
Data_type: double, read/write
Controls the pessimism added for post route correlation by adding higher costs to longer wire segments.
phys_fix_multi_height_cells
phys_fix_multi_height_cells {false |true}
Default: false
Read-write root attribute. Controls whether to consider the placement of instances of multiple-height cells (multiple of the standard cell height) fixed during
incremental placement.
Multiple-height cells commonly have routing blockages on a particular metal layer in the LEF library. These metal layers usually have power routes.
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Related Information
Affects this command: syn_opt [-incr]
phys_flow_effort
phys_flow_effort {medium| high | none}
Default: medium
Read-write root attribute. Controls the placement and optimization steps in the Genus Physical flow.
High effort provides the best QoR at the cost of runtime.
Medium effort offers the best trade-off between the runtime and QoR and turns legalization off by default.
None will result in the best runtime.
This flow does not require an Innovus license.
Related Information
Affects this command: syn_opt [-incr]
phys_pre_place_iopt
phys_pre_place_iopt {auto | true | false}
Default: auto
Read-write root attribute. Controls whether to run fast parallel optimization before placement in the physical flow.
This attribute can have the following values:
auto Automatically runs fast parallel optimization before placement during syn_opt.
false Prevents fast parallel optimization before placement.
true Runs fast parallel optimization before placement.
phys_premorph_density
phys_premorph_density float
Default: 0.96
Read-write root attribute. Specifies the target maximum density during the placement spreading step before legalization. Set this to a lower number for designs
with large timing jumps during legalization. The recommended value is between 0.85 and 0.96.
Related Information
Affects this command: syn_opt [-incr]
phys_read_script_large_file_source
phys_read_script_large_file_source {0 | 1 | true | false}
Default: true
Read-write root attribute. Specifies whether Genus setup file loading in physical flows use special large file support to bypass Tcl file size limits.
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phys_refresh_power_intent_1801
Syntax
phys_refresh_power_intent_1801 {false | true}
Applies to:
root
Description
Default: false
Data_type: boolean, read/write
Refreshes the power intent 1801 settings if the design is removed/updated in the Ispatial flow.
Related Information
Affects this command: syn_opt -spatial
phys_scan_def_file
phys_scan_def_file string
Read-write root attribute. Specifies the scanDEF file to use in the physical flow.
phys_summary_table_print_negative_tns
phys_summary_table_print_negative_tns {false | true}
Default: true
Read-write root attribute. Enables Genus to report TNS values as negative values in the summary report.
Related Information
Affects this command: report_summary
phys_update_preannotation_script
phys_update_preannotation_script string
Read-write root attribute. Specifies the script to source in Genus after loading the physical database from Innovus and before the parasitic annotation step in
Genus.
Related Information
Affects this command: write_design
physical_aware_multibit_mapping
physical_aware_multibit_mapping {auto | false | true}
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Default: auto
Read-write root attribute. Enables placement-based (or physical-aware) multibit merging when placement information is available.
This attribute can have following values:
auto Performs multibit merging when placement information is available, otherwise logical multibit merging is performed.
false Ignores placement information and does multibit merging bsed on logical grouping.
true Only performs multibit merging when placement information is available. So if no placement information is available, multibit merging is skipped.
Related Information
Affects by these commands syn_generic -physical
syn_opt
physical_force_predict_floorplan
physical_force_predict_floorplan {0 | 1 | false | true}
Default: auto
Read-write root attribute. Force predict_floorplan in generic stage.
Related Information
Affects this command: predict_floorplan
pqos_ignore_msv
pqos_ignore_msv {false | true}
Default: false
Read-write root attribute. Specifies whether to pass library or power domain information to the Innovus place and route tool.
Related Information
Affects this command: syn_opt
pqos_ignore_scan_chains
pqos_ignore_scan_chains {false | true}
Default: false
Read-write root attribute. Specifies whether to ignore scan chains during placement estimation. Set this to true to disable the placement-based reordering in
the Innovus™ Implementation System.
Related Information
Affects this command: syn_opt
pqos_placement_effort
pqos_placement_effort {no_value | low | medium | high}
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Default: no_value
Read-write root attribute. Specifies the effort level to be used for congestion optimization during placement in Encounter® place and route. Sets the value of
the -congEffort option of the Encounter® setPlaceMode command.
Related Information
Affects this command: syn_opt
predict_floorplan_allow_core_reshape
Syntax
predict_floorplan_allow_core_reshape {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enables the reshape flow in Innovus predict_floorplan in generic stage.
Related Information
Affects this command: predict_floorplan
predict_floorplan_allow_illegal_macro
predict_floorplan_allow_illegal_macro {0 | 1 | true | false}
Default: false
Read-write root attribute. Allow illegal placed macros and continue the Innovus predict_floorplan in generic stage.
Related Information
Affects this command: predict_floorplan
predict_floorplan_constraints
Syntax
predict_floorplan_constraints <string>
Applies to:
root
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Description
Default:
Data_type: string, read/write
Specifies the name of the Automatic Floorplan Synthesis constraint file that can be used by the Innovus planDesign command to guide the floorplan estimation.
Related Information
Affects this command: predict_floorplan
predict_floorplan_enable_cpg
predict_floorplan_enable_cpg {0 | 1 | true | false}
Default: false
Read-write root attribute. Enable Cadence Placement Guidence (CPG) flow in Innovus predict_floorplan in generic stage.
Related Information
Affects this command: predict_floorplan
predict_floorplan_invs_post_resize_script
predict_floorplan_invs_post_resize_script string
Default: no_value
Read-write root attribute. Specifies the name of the script to be sourced after the floorplan is auto-resized.
Related Information
Affects this command: predict_floorplan
predict_floorplan_keep_fences
predict_floorplan_keep_fences {0 | 1 | true | false}
Default: false
Read-write root attribute. Keeps fences in Innovus predict_floorplan in generic stage.
Related Information
Affects this command: predict_floorplan
predict_floorplan_keep_fixed_macros
predict_floorplan_keep_fixed_macros {1 | 0| true| false}
Default: false
Read-write root attribute. Transfer option "-keep_fixed_macros" to Innovus predict_floorplan.
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Related Information
Affects this command: predict_floorplan
predict_floorplan_script
predict_floorplan_script string
Default: no_value
Read-write root attribute.Specifies the name of the Master Floorplan script to guide the floorplan estimation.
Related Information
Affects this command: predict_floorplan
predict_floorplan_skip_propagate_activity
predict_floorplan_skip_propagate_activity {1 | 0| true| false}
Default: false
Read-write root attribute. Skip activity propagation in Innovus predict_floorplan in generic stage.
Related Information
Affects this command: predict_floorplan
predict_floorplan_use_innovus
predict_floorplan_use_innovus {0 | 1 | false | true}
Default: false
Read-write root attribute. Enable the Innovus predict_floorplan flow in generic stage.
Related Information
Affects this command: predict_floorplan
qos_report_power
qos_report_power {auto | false | true}
Default: auto
Read-write root attribute. Specifies whether to include leakage and dynamic power in QoS statistics table.
Related Information
Affects these commands: write_reports
report_summary
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qrc_tech_file
qrc_tech_file string
Read-write root attribute. Specifies the QRC technology file from where the process and extraction information must be read.
If you read in both a QRC technology file and a capacitance table file, the QRC technology file will take precedence.
You must read in the LEF files before you can read in the QRC technology file.
For technologies below 28nm, the Encounter® Digital Implementation System requires a QRC technology file instead of a capacitance table file.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related attribute: cap_table_file
read_def_fuzzy_name_match
read_def_fuzzy_name_match {false | true}
Default: false
Read-write root attribute. Specify to enable fuzzy name matching during execution of read_def command.
Fuzzy match matches: /[]_
Examples:
netist U1/g7 - DEF U1_g7
netlist U1_g7 - DEF U1/g7
netlist U1_g365 - DEF U1g365
netlist U1_ptr1_reg[6] - DEF U1/ptr1_reg
Related Information
Affects this command: read_def
read_def_keep_net_property
read_def_keep_net_property string
Default:
Read-write root attribute. Keeps the DEF NETs with the specified property name when reading the DEF file.
Related Information
Affects this command: read_def
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read_def_libcell_mismatch_error
read_def_libcell_mismatch_error {true| false}
Default: true
Read-write root attribute. Controls whether the read_def command should fail if the library cell instantiation for an instance in the DEF file does not match the
netlist. By default, an error will be issued when there is a mismatch.
Related Information
Affects this command: read_def
read_qrc_tech_file_rc_corner
read_qrc_tech_file_rc_corner {false | true}
Default: false
Read-write root attribute. Specifies to replace the capacitance table file with the technology file.
report_logic_levels_histogram_fixed_depth
report_logic_levels_histogram_fixed_depth integer
Default: 0
Read-write root attribute. Controls the depth in the report_logic_levels_histogram command. If you set this attribute, the -bar option of the
report_logic_levels_histogram command is ignored.
report_ndr_min_layer_count
report_ndr_min_layer_count {false| true}
Default: false
Read-write root attribute. Controls whether the number of non-default routes and nets assigned to higher metal layers by Innovus is reported in all subsequent
QoR and summary reports.
Enabling this attribute affects the runtime of these report command.s
Related Attributes
Affects this command report_qor
route_early_global_horizontal_supply_scale_factor
route_early_global_horizontal_supply_scale_factor float
Default: 1.0
Read-write root attribute. Specifies the Scale H supply by a specified ratio.
route_early_global_num_tracks_per_clock_wire
route_early_global_num_tracks_per_clock_wire integer
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Default: 0
Read-write root attribute. Specifies the special width for clock wires.
route_early_global_secondary_pg
route_early_global_secondary_pg {1 | 0 | true | false}
Default: false
Read-write root attribute. Specifies whether secondary PG pins needs to be routed.
route_early_global_vertical_supply_scale_factor
route_early_global_vertical_supply_scale_factor float
Default: 1.0
Read-write root attribute. Specifies the Scale V supply by a specified ratio.
route_rules
Syntax
route_rules <string>
Applies to:
design
root
Description
Default:
Data_type: route_rule*, read only
Returns the list of routing rules and the list of all 'route_rule' objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
scale_of_cap_per_unit_length
Syntax
scale_of_cap_per_unit_length <float>
Applies to:
root
Description
Default: 1.0
Data_type: double, read/write
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Specifies the scale for the wire capacitance value. This attribute is used as multiplier to modify the capacitance values to resolve minor discrepancies between
the default, detail, and sign-off extractors in the Innovus Implementation System.
Example
The following example sets the scale factor to 1.2:
set_db / .scale_of_cap_per_unit_length 1.2
1.2
Related Attributes
Related attribute: scale_of_res_per_unit_length
scale_of_res_per_unit_length
Syntax
scale_of_res_per_unit_length <float>
Applies to:
root
Description
Default: 1.0
Data_type: double, read/write
Specifies the scale for the wire resistance value. This attribute is used as multiplier to modify the resistance values to resolve minor discrepancies between the
default, detail, and sign-off extractors in the Innovus.
Example
The following example sets the scale factor to 1.2:
set_db / .scale_of_res_per_unit_length 1.2
S1.2
Related Information
Related attribute: scale_of_cap_per_unit_length
selected
Syntax
selected <string>
Applies to:
root
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Description
Default:
Data_type: Tcl List, read/write
Returns the list of all selected objects in the GUI (Layout Viewer).
shrink_factor
Syntax
shrink_factor <float>
Applies to:
root
Description
Default:
Data_type: double, read/write
Specifies (as a floating point number less than 1.0) how much to shrink the LEF geometries for timing purposes. Geometries in a LEF and DEF can be defined
much larger than what will actually be scribed on the silicon. In such cases, a process shrink factor is used. Values above 1.0 are not valid.
The shrink factor affects the layer widths. Since the layer widths are used to pick the resistance and capacitance values from the captable, this attribute affect
the resistance and capacitance calculation.
Example
The following example sets the shrink factor to 65%:
set_db / .shrink_factor 0.65
0.65
Related Information
Affects this command: report_area
sites
Syntax
sites {list_sites}
Applies to:
root
Description
Default:
Data_type: sites*, read only
Returns the list of site objects. This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
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Physical--route_blockage Attributes for Physical
source_of_via_resistance
Syntax
source_of_via_resistance <string>
Applies to:
root
Description
Default:
Data_type: string, read only
Returns the source of the via resistance. This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
via_resistance
via_resistance float
Read-only root attribute. Returns the average resistance of vias between metal1 and metal2 layers and betwen metal2 and metal3 layers. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the ls command by default.
Related Information
Related attributes: cap_table_file
lef_library
force_via_resistance
vias
vias list_of_vias
Read-only root attribute. Returns the list of via objects. This is a computed attribute. Computed attributes are potentially very time consuming to process and
not listed by the ls command by default.
route_blockage Attributes for Physical
def_name
def_name string
Read-only route_blockage attribute. Returns the DEF name of the route_blockage.
Related Information
Set by this command: read_def
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Physical--route_rule Attributes for Physical
properties
properties string
Read-only route_blockage attribute. Returns the properties associated with the route_blockage.
Related Information
Set by this command: read_def
route_rule Attributes for Physical
from_lef
hardspacing
layers
mincuts
properties
viarules
vias
from_lef
from_lef {false | true}
Read-only route_rule attribute. Indicates whether the nondefault rule was specified in the LEF file. If false, the route_rule was specified in the DEF file.
Related Information
Set by this command: read_def
hardspacing
hardspacing {false | true}
Read-only route_rule attribute. Specifies whether any spacing values that exceed the LEF LAYER ROUTING spacing requirements are hard rules instead of
soft rules. By default, routers treat extra spacing requirements as soft rules.
Related Information
Set by this command: read_def
layers
layers {layer layername width minwidth diagwidth diagWidth spacing minspacing wireext wireext} ...
Read-only route_rule attribute. Returns one or more lists. Each list contains the name of a routing layer and various width and spacing values to be used for
this nondefault rule.
Related Information
Set by this command: read_def
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Physical--route_type Attributes for Physical
mincuts
mincuts {layer cutLayerName numCuts}...
Read-only route_rule attribute. Returns one or more lists. Each list contains the layer name, the cutlayer name and the minimum number of cuts required for
this non-default rule.
Related Information
Set by this command: read_def
properties
properties {propertyName propertyValue}...
Read-only route_rule attribute. Returns one or more lists. Each list contains a property defined for this non-default rule, that is, a property name followed by its
value.
Related Information
Set by this command: read_def
viarules
viarules viarulename ...
Read-only route_rule attribute. Returns the viarule(s) to be used with this nondefault rule previously defined in a LEF VIARULE GENERATE statement.
Related Information
Set by this command: read_def
vias
vias vianame...
Read-only route_rule attribute. Returns previously defined LEF or DEF vias to be used with this nondefault rule.
Related Information
Set by this command: read_def
Related attribute: (def_pin) vias
route_type Attributes for Physical
bottom_mask_layer_num
bottom_one_side_layer_num
bottom_preferred_layer
driver_use_multi_cut_via
em_route_rule
em_route_rule_distance
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input_stack_via_rule
mask
min_stack_layer
non_default_rule
output_stack_via_rule
preferred_routing_layer_effort
shield_net
shield_side
stack_distance
top_mask_layer_num
top_one_side_layer_num
top_preferred_layer
bottom_mask_layer_num
bottom_mask_layer_num int
Default: -1
Read-only route_type attribute. Specify the bottom layer number that the mask constraint should be applied.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
bottom_one_side_layer_num
bottom_one_side_layer_num int
Default: -1
Read-only route_type attribute. Specify the bottom layer number that one side spacing constraint should be applied on.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
bottom_preferred_layer
bottom_preferred_layer string
Read-only route_type attribute. Specify the preferred lowest routing layer.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
driver_use_multi_cut_via
driver_use_multi_cut_via {0 | 1 | false | true}
Default: False
Read-only route_type attribute. If true, then driver pins will use multi-cut vias.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
em_route_rule
em_route_rule string
Read-only route_type attribute. Specifies the EM route_rule to associate with this route type.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
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em_route_rule_distance
em_route_rule double
Read-only route_type attribute. Specifies the distance from the output pin, when the em_route_rule is applied to the net.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
input_stack_via_rule
input_stack_via_rule double
Read-only route_type attribute. Specify a stacked via rule name, which must match one of the LEF STACKVIARULE names.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
mask
mask int
Default: 1
Read-only route_type attribute. Indicates mask number for multiple mask layer usage.
min_stack_layer
min_stack_layer string
Read-only route_type attribute. The net should use a stacked via from output pins up to the given layer before starting normal routing.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
non_default_rule
non_default_rule string
Read-only route_type attribute. Specify the non-default routing rule.
output_stack_via_rule
output_stack_via_rule string
Read-only route_type attribute. Specify a stacked via rule name, which must match one of the LEF STACKVIARULE names.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
preferred_routing_layer_effort
preferred_routing_layer_effort string
Read-only route_type attribute. Effort for honoring top and bottom preferred routing layer.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
shield_net
shield_net string
Read-only route_type attribute. Net to be used as a shield.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
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Physical--row Attributes for Physical
shield_side
shield_side {unstated | one_side | both_side}
Default: both_side
Read-only route_type attribute. Specifies whether to perform one sided or two sided shielding.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
stack_distance
stack_distance double
Read-only route_type attribute. Specifies that the cut distance of cuts on adjacent layers in the stacked vias are defined in min_stack_layer.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
top_mask_layer_num
top_mask_layer_num int
Default: -1
Read-only route_type attribute. Specify the top layer number that the mask constraint should be applied.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
top_one_side_layer_num
top_one_side_layer_num int
Default: -1
Read-only route_type attribute. Specify the top layer number that one side spacing constraint should be applied.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
top_preferred_layer
top_preferred_layer string
Read-only route_type attribute. Preferred highest routing layer.
Not used by Genus internally, exists only for Innovus Common DB exchanges.
row Attributes for Physical
height
is_horizontal
macro
num_x
num_y
orientation
selectable
site
step_x
step_y
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Physical--row Attributes for Physical
user_created
visible
width
height
height float
Read-only row attribute. Returns the height of the row.
Related Information
Set by these commands: create_row
read_def
Related attribute: width
is_horizontal
is_horizontal {true | false }
Default: true
Read-only row attribute. Indicates whether the row is horizontal or vertical.
Related Information
Set by this command: read_def
macro
macro string
Read-only row attribute. Returns the name of the LEF site used for the row.
Related Information
Set by these commands: create_row
read_def
num_x
num_x integer
Default: 0
Read-only row attribute. Returns the repetition of row for site X.
num_y
num_y integer
Default: 0
Read-only row attribute. Returns the repetition of row for site Y.
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orientation
orientation string
Read-only row attribute. Returns the orientation of all sites in the row. Following are the possible orientations: N, S, E, W, FN, FS, FE, or FW.
Related Information
Set by this command: read_def
selectable
selectable {true | false}
Default: true
Read-only row attribute. Indicates whether the row is selectable in the GUI.
site
site site
Default: no value
Read-only row attribute. Returns the site associated with row.
step_x
step_x double
Default: no value
Read-only row attribute. Returns the spacing of row in microns for site X.
step_y
step_y double
Default: no value
Read-only row attribute. Returns the spacing of row in microns for site Y.
user_created
user_created {false | true}
Read-only row attribute. Indicates whether the row was created by the user in Genus. The attribute returns false if the row was defined in the DEF file.
Related Information
Set by these commands: create_row
read_def
visible
visible {true | false}
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Physical--sdp_column Attributes for Physical
Default: true
Read-write row attribute. Indicates whether the row is displayed in the GUI.
Related Information
Set by these commands: create_row
read_def
width
width float
Read-only row attribute. Returns the physical width of the row.
Related Information
Set by these commands: create_row
read_def
Related attribute: height
sdp_column Attributes for Physical
flip
justify_by
orient
sdp_group
sdp_instances
sdp_row
sdp_rows
size_same
skip_value
flip
flip {X | Y | XY}
Read-only sdp_column attribute. Indicates whether the column is flipped. If no flip value was specified for the column in the SDP relative placement file, the
attribute has no value.
Related Information
Set by this command: read_sdp_file
justify_by
justify_by {SW | NW | SE | NE | W | E | N | S | MID}
Default: SW
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Physical--sdp_column Attributes for Physical
Read-only sdp_column attribute. Returns the justifyBY constraint of the column. If no constraint value was specified for the column in the SDP relative
placement file, the value defaults to SW.
Related Information
Set by this command: read_sdp_file
orient
orient {R0|R90|R180|R270|MX|MY|MY90|MX90}
Default: RO
Read-only sdp_column attribute. Returns the orientation of the SDP column. If no orientation value was specified for the column in the SDP relative placement
file, the value defaults to R0.
Related Information
Set by this command: read_sdp_file
sdp_group
sdp_group string
Read-only sdp_column attribute. Returns the SDP group that this column belongs to.
sdp_instances
sdp_instances list_of_sdp_instances
Read-only sdp_column attribute. Returns the list of SDP instances associated with this SDP column.
sdp_row
sdp_row string
Read-only sdp_column attribute. Returns the SDP row that this column belongs to.
sdp_rows
sdp_rows list_of_sdp_rows
Read-only sdp_column attribute. Returns the list of SDP rows associated with this SDP column.
size_same
size_same {false | true}
Default: false
Read-write sdp_column attribute. Specifies whether all instances in the column have the same width as the widest instance in the column.
Related Information
Set by this command: read_sdp_file
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Physical--sdp_group Attributes for Physical
skip_value
skip_value integer
Read-only sdp_column attribute. Specifies the number of columns to skip. This attribute can only have a non-zero value for a column called skip_column_x.
Related Information
Set by this command: read_sdp_file
sdp_group Attributes for Physical
hier_path
orient
origin
sdp_columns
sdp_rows
hier_path
hier_path string
Read-only sdp_group attribute. Returns the hierarchical path name of the SDP group (or datapath structure).
Related Information
Set by this command: read_sdp_file
orient
orient {R0|R90|R180|R270|MX|MY|MY90|MX90}
Default: RO
Read-only sdp_group attribute. Returns the orientation of the SDP group (or datapath structure). If no orientation value was specified for the SDP group in the
SDP relative placement file, the value defaults to R0.
Related Information
Set by this command: read_sdp_file
origin
origin x y
Read-only sdp_group attribute. Returns the coordinates of the origin of the SDP group (or datapath structure).
Related Information
Set by this command: read_sdp_file
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Physical--sdp_instance Attributes for Physical
sdp_columns
sdp_columns list_of_sdp_columns
Read-only sdp_group attribute. Returns the list of SDP columns in this SDP group.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the ls command by default.
sdp_rows
sdp_rows list_of_sdp_rows
Read-only sdp_group attribute. Returns the list of SDP rows in this SDP group.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the ls command by default.
sdp_instance Attributes for Physical
flip
instance
justify_by
orient
sdp_column
sdp_row
size_fixed
skip_value
flip
flip {X | Y | XY}
Read-only sdp_instance attribute. Indicates whether the instance is flipped. If no flip value was specified for the instance in the SDP file, the attribute has no
value.
Related Information
Set by this command: read_sdp_file
instance
instance string
Read-only sdp_instance attribute. Returns the full path name of the instance.
Related Information
Set by this command: read_sdp_file
justify_by
justify_by {SW | NW | SE | NE | W | E | N | S | MID}
Default: SW
Read-only sdp_instance attribute. Returns the justifyBY constraint of the instance. If no constraint value was specified for the instance in the SDP file, the value
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Physical--sdp_row Attributes for Physical
defaults to SW.
Related Information
Set by this command: read_sdp_file
orient
orient {R0|R90|R180|R270|MX|MY|MY90|MX90}
Default: RO
Read-only sdp_instance attribute. Returns the orientation of the SDP instance. If no orientation value was specified for the instance in the SDP file, the value
defaults to R0.
Related Information
Set by this command: read_sdp_file
sdp_column
sdp_column sdp_column
Read-only sdp_instance attribute. Returns the SDP column that this SDP instance belongs to.
sdp_row
sdp_row sdp_row
Read-only sdp_instance attribute. Returns the SDP row that this SDP instance belongs to.
size_fixed
size_fixed {false | true}
Default: false
Read-write sdp_instance attribute. Specifies whether the size of the instance can be modified during incremental optimization. By default, the size can be
modified.
Related Information
Set by this command: read_sdp_file
skip_value
skip_value integer
Default: 0
Read-only sdp_instance attribute. Specifies the number of rows or columns to skip between two instances. This attribute can only have a non-zero value for an
instance called skip_instance_x.
sdp_row Attributes for Physical
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Physical--sdp_row Attributes for Physical
flip
justify_by
orient
sdp_column
sdp_columns
sdp_group
sdp_instances
size_same
skip_value
flip
flip {X | Y | XY}
Read-only sdp_row attribute. Indicates whether the SDP row is flipped. If no flip value was specified for the row in the SDP file, the attribute has no value.
Related Information
Set by this command: read_sdp_file
justify_by
justify_by {SW | NW | SE | NE | W | E | N | S | MID}
Default: SW
Read-only sdp_row attribute. Returns the justifyBY constraint of the row. If no constraint value was specified for the row in the SDP file, the value defaults to SW.
Related Information
Set by this command: read_sdp_file
orient
orient {R0|R90|R180|R270|MX|MY|MY90|MX90}
Default: RO
Read-only sdp_row attribute. Returns the orientation of the SDP row. If no orientation value was specified for the row in the SDP file, the value defaults to R0.
Related Information
Set by this command: read_sdp_file
sdp_column
sdp_column sdp_column
Read-only sdp_row attribute. Returns the SDP column that this SDP row belongs to.
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Physical--site Attributes for Physical
sdp_columns
sdp_columns list_of_sdp_columns
Read-only sdp_row attribute. Returns the list of SDP columns associated with this SDP row. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
sdp_group
sdp_group sdp_group
Read-only sdp_row attribute. Returns the SDP group that this SDP row belongs to.
sdp_instances
sdp_instances list_of_sdp_instances
Read-only sdp_row attribute. Returns the list of SDP instances associated with this SDP row. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
size_same
size_same {false | true}
Default: false
Read-write sdp_row attribute. Specifies whether all instances in the row have the same width as the widest instance in the row.
Related Information
Set by this command: read_sdp_file
skip_value
skip_value integer
Default: 0
Read-only sdp_row attribute. Specifies the number of rows to skip. This attribute can only have a non-zero value for a column called skip_row_x.
site Attributes for Physical
class
height
row_pattern
size
symmetry
width
class
class string
Read-only site attribute. Returns the site class name.
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Physical--slot Attributes for Physical
Related Information
Set by this attribute: lef_library
height
height float
Default: 0.000
Read-only site attribute. Returns the site height in microns.
Related Information
Set by this attribute: lef_library
row_pattern
row_pattern string
Read-only site attribute. Returns the row pattern of the site object based on the information from the physical library.
size
size point
Read-only site attribute. Returns the site size.
symmetry
symmetry {X | Y | R90}
Read-only site attribute. Returns the site symmetry.
Related Information
Set by this attribute: lef_library
width
width float
Read-only site attribute. Returns the site width in microns.
Related Information
Set by this attribute: lef_library
slot Attributes for Physical
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Physical--specialnet Attributes for Physical
polygons
polygons {{pt pt pt [pt]} ...}
Read-only slot attribute. Returns one or more lists. Each list contains a list of coordinates of at least three points of a polygon that defines a slot. The polygon
is generated by connecting each successive point, and then the first and last points.
Related Information
Set by this command: read_def
Related attributes: rects
layer
rects
rects {rect...}
Read-only slot attribute. Returns one or more lists. Each list contains the lower left and upper right coordinates of a rectangular-shaped slot.
Related Information
Set by this command: read_def
Related attributes: layer
polygons
specialnet Attributes for Physical
components
def_name
fixedbump
original_name
path_count
path_index
path_value
pattern
polygons
properties
rc_name
rectangles
source
style
use
weight
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Physical--specialnet Attributes for Physical
components
components {componentName pinName {0|1} }...
Read-only specialnet attribute. Returns one or more lists. Each list contains the special pin on the net, its corresponding component, and an indication
whether the pin is part of a synthesized scan chain.
Related Information
Set by this command: read_def
def_name
def_name string
Read-only specialnet attribute. Returns the DEF name of the special net.
Related Information
Set by this command: read_def
fixedbump
fixedbump {false | true}
Read-only specialnet attribute. Indicates whether the bump net in the special net can be reassigned.
Related Information
Set by this command: read_def
original_name
original_name string
Read-only specialnet attribute. Returns the name of the original net that was partitioned and that includes this special net.
Related Information
Set by this command: read_def
path_count
path_count integer
Read-only specialnet attribute. Returns the number of paths for this special net. Paths contain the routing point data in the special wiring statement of the
special net that are not part of the POLYGON or RECT statements.
Related Information
Set by this command: read_def
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Physical--specialnet Attributes for Physical
path_index
path_index integer
Default: 0
Read-write specialnet attribute. Specifies the index of the path of the special net for which you want to get more information through the path_value attribute.
Related Information
Sets this attribute: path_value
path_value
path_value string
Read-only specialnet attribute. Returns the information for the path identified though the path_index attribute.
Related Information
Set by this attribute: path_index
pattern
pattern string
Read-only specialnet attribute. Returns the routing pattern used for this special net. The routing pattern can be one of the following:
BALANCED—Used to minimize skews in timing delays for clock nets.
STEINER—Used to minimize net length.
TRUNK—Used to minimize delay for global nets.
WIREDLOGIC—Used in ECL designs to connect output and must join pins before routing to the remaining pins.
Related Information
Set by this command: read_def
polygons
polygons {{layer {pt pt pt [pt]} ...}
Read-only specialnet attribute. Returns one or more lists. Each list defines a polygon on the specified layer that is part of the routing of this special net.
Related Information
Set by this command: read_def
properties
properties {propertyName propertyValue}...
Read-only specialnet attribute. Returns one or more lists. Each list contains a property defined for this specialnet, that is, a property name followed by its
value.
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Physical--specialnet Attributes for Physical
Related Information
Set by this command: read_def
rc_name
rc_name string
Read-only specialnet attribute. Returns the name that Genus gave to this specialnet.
rectangles
rectangles {layer llx lly urx ury} ...
Read-only specialnet attribute. Returns one or more lists. Each list defines a rectangle on the specified layer that is part of the routing of this special net.
Related Information
Set by this command: read_def
source
source string
Read-only specialnet attribute. Returns how the net was created. The source can be one of the following:
DIST—Net is the result of adding physical components (that is, components that only connect to power or ground nets), such as filler cells, well-taps, tie-
high and tie-low cells, and decoupling caps.
NETLIST—Net is defined in the original netlist. This is the default value, and is not normally written out in the DEF file.
TEST—Net is part of a scan chain.
TIMING—Net represents a logical rather than physical change to netlist, and is used typically as a buffer for a clock-tree, or to improve timing on long nets.
USER—Net is user defined.
Related Information
Set by this command: read_def
style
style {no_value | integer }
Read-only specialnet attribute. Returns the index of the style that defines the outer boundary for this special net wire. The no_value value indicates that the
special net does not use a style.
Related Information
Set by this command: read_def
use
use string
Read-only specialnet attribute. Returns the use of the specialnet. Following are the possible values:
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Physical--style Attributes for Physical
ANALOG—Used as an analog signal net.
CLOCK—Used as a clock net.
GROUND—Used as a ground net.
POWER—Used as a power net.
RESET—Used as a reset net.
SCAN—Used as a scan net.
SIGNAL—Used as a digital signal net.
TIEOFF—Used as a tie-high or tie-low net.
Related Information
Set by this command: read_def
weight
weight integer
Read-only specialnet attribute. Returns the weight assigned to the special net.
Related Information
Set by this command: read_def
style Attributes for Physical
polygon
polygon polygon
Read-only style attribute. Returns a list of coordinates from which the style polygon can be generated.
Related Information
Set by this command: read_def
track_pattern Attributes for Physical
num_tracks
num_tracks integer
Default: 0
Read-only track_pattern attribute. Returns the number of tracks.
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Physical--track Attributes for Physical
properties
properties string
Read-only attribute. Returns the properties associated with the track_pattern.
Related Information
Set by this command: read_def
track Attributes for Physical
count
is_horizontal
is_used
layer
layer_number
macro
mask
multiple
same_mask
start
step
count
count integer
Read-only track attribute. Returns the number of tracks for the layer identified by the layer attribute in the routing direction identified by the is_horizontal
attribute. This number corresponds to the value specified for the DO keyword in the TRACKS statement in the DEF file.
Related Information
Set by this command: read_def
is_horizontal
is_horizontal {false | true}
Read-only track attribute. Indicates for which direction the track information applies. The direction is determined by the X or Y specification following the
TRACKS statement.
Related Information
Set by this command: read_def
is_used
is_used {false | true}
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Physical--track Attributes for Physical
Read-only track attribute. Indicates whether the track is used during the physical layout estimation.
layer
layer string
Read-only track attribute. Returns the layer to which the track information applies.
Related Information
Set by this command: read_def
layer_number
layer_number integer
Read-only track attribute. Returns the track layer number.
Related Information
Set by this command: read_def
macro
macro string
Read-only track attribute. Returns the macro associated with these tracks.
Related Information
Set by this command: read_def
mask
mask integer
Read-only track attribute. Returns the mask number used for the first routing track.in case double- or triple-patterning lithography is used.
Related Information
Set by this command: read_def
multiple
multiple {false | true}
Read-only track attribute. Indicates whether there are multiple track definitions for the same layer.
same_mask
same_mask {false | true}
Read-only track attribute. Indicates whether all routing tracks use the same mask as the first track in case double- or triple-patterning lithography is used.
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Physical--via Attributes for Physical
start
start float
Read-only track attribute. Returns the X or Y coordinate of the first line. The value will be an X (Y) coordinate if the is_horizontal attribute is set to false
(true).
Related Information
Set by this command: read_def
step
step float
Read-only track attribute. Returns the spacing between the tracks.
Related Information
Set by this command: read_def
via Attributes for Physical
bottom_layer
cut_cols
cut_layer
cut_pattern
cut_rows
height
lef_name
min_route_layer
polygons
properties
rects
top_layer
viarule_name
width
xbottom_enclosure
xbottom_offset
xcut_size
xcut_spacing
xorigin_offset
xtop_enclosure
xtop_offset
ybottom_enclosure
ybottom_offset
ycut_size
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Physical--via Attributes for Physical
ycut_spacing
yorigin_offset
ytop_enclosure
ytop_offset
bottom_layer
bottom_layer string
Read-only via attribute. Returns the name of the bottom routing layer associated with the via.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
cut_cols
cut_cols integer
Read-only via attribute. Returns the number of cut columns that make up the via array.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
cut_layer
cut_layer string
Read-only via attribute. Returns the name of the cut layer associated with the via.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
cut_pattern
cut_pattern string
Read-only via attribute. Returns an ASCII string that represents the cut pattern associated with the via. A cut pattern is used when some of the cuts are missing
from the array of cuts. When no cut pattern is available, all cuts are assumed to be present.
This attribute has no value for fixed vias.
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Physical--via Attributes for Physical
Related Information
Set by this command: read_def
cut_rows
cut_rows integer
Read-only via attribute. Returns the number of cut rows that make up the via array.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
height
height float
Read-only via attribute. Returns the height of the via.
Related Information
Set by this command: read_def
lef_name
lef_name string
Read-only via attribute. Returns the LEF name associated with the via.
min_route_layer
min_route_layer integer
Read-only via attribute. Returns the index value of the bottom routing layer.
polygons
polygons {{layer mask {pt pt pt [pt]} ...}
Read-only via attribute. Returns one or more lists. Each list contains a layer name, which mask for double- or triple-patterning lithography is to be applied to the
defined shape, and a list of coordinates of at least 3 points. A polygon is generated by connecting each successive point, and then the first and last points.
Related Information
Set by this command: read_def
properties
properties string
Read-only via attribute. Returns the properties associated with the via.
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Physical--via Attributes for Physical
Related Information
Set by this command: read_def
rects
rects {{layer mask llx lly urx ury} ...}
Read-only via attribute. Returns one or more lists. Each list defines the via geometry for the specified layer: it contains the layer name, which mask for double-
or triple-patterning lithography is to be applied to the defined shape, and the lower left and upper right coordinates of the via shape. The coordinates are
specified in microns and can be floating numbers.
Related Information
Set by this command: read_def
top_layer
top_layer string
Read-only via attribute. Returns the name of the top routing layer associated with the via.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
viarule_name
viarule_name string
Read-only via attribute. Returns the name of the LEF VIARULE that produced this via.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
width
width float
Read-only via attribute. Returns the width of the via.
Related Information
Set by this command: read_def
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Physical--via Attributes for Physical
xbottom_enclosure
xbottom_enclosure float
Read-only via attribute. Returns the required x enclosure (in micron) for the bottom layer. This enclosure measures the distance in the horizontal direction from
the edge of the cut array to the edge of the bottom metal layer that encloses the cut array.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
xbottom_offset
xbottom_offset float
Read-only via attribute. Returns the xoffset of the bottom layer (in micron).
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
xcut_size
xcut_size float
Read-only via attribute. Returns the required width of the cut layer rectangle (in micron).
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
xcut_spacing
xcut_spacing float
Read-only via attribute. Returns the required spacing between cuts in the horizontal direction. The spacing is measured from one cut edge to the next cut edge
and is specified in microns.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
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Genus Attribute Reference
Physical--via Attributes for Physical
xorigin_offset
xorigin_offset float
Read-only via attribute. Returns the x offset of the origin of the via shapes (in micron). By default, the 0,0 origin of the via is the center of the cut array and the
enclosing metal rectangles.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
xtop_enclosure
xtop_enclosure float
Read-only via attribute. Returns the required x enclosure for the top layer (in micron). This enclosure measures the distance in the horizontal direction from the
edge of the cut array to the edge of the top metal layer that encloses the cut array.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
xtop_offset
xtop_offset float
Read-only via attribute. Returns the x offset of the top layer (in micron).
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
ybottom_enclosure
ybottom_enclosure float
Read-only via attribute. Returns the required y enclosure for the bottom layer (in micron). This enclosure measures the distance in the vertical direction from
the edge of the cut array to the edge of the bottom metal layer that encloses the cut array.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
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Physical--via Attributes for Physical
ybottom_offset
ybottom_offset float
Read-only via attribute. Returns the y offset of the bottom layer (in micron).
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
ycut_size
ycut_size float
Read-only via attribute. Returns the required height of the cut layer rectangle (in micron).
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
ycut_spacing
ycut_spacing float
Read-only via attribute. Returns the required spacing between cuts in the vertical direction. The spacing is measured from one cut edge to the next cut edge
and is specified in microns.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
yorigin_offset
yorigin_offset float
Read-only via attribute. Returns they offset of the origin of the via shapes (in micron). By default, the 0,0 origin of the via is the center of the cut array and the
enclosing metal rectangles.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
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Physical--via Attributes for Physical
ytop_enclosure
ytop_enclosure float
Read-only via attribute. Returns the required y enclosure for the top layer (in micron). This enclosure measures the distance in the vertical direction from the
edge of the cut array to the edge of the top metal layer that encloses the cut array.
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
ytop_offset
ytop_offset float
Read-only via attribute. Returns the y offset of the top layer (in micron).
This attribute has no value for fixed vias.
Related Information
Set by this command: read_def
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Formal Verification
14
Formal Verification
clp_enable_1801_hierarchical_bbox clp_ignore_ls_high_to_low clp_treat_errors_as_warnings
lec_executable sim_model verification_directory
verification_directory_naming_style wcdc_clock_dom_comb_propagation wcdc_synchronizer_type
wclp_lib_statetable wlec_add_noblack_box_retime_subdesign wlec_analyze_abort
wlec_analyze_setup wlec_auto_analyze wlec_black_box_ilm_modules
wlec_compare_threads wlec_composite_compare wlec_dft_constraint_file
wlec_gzip_fv_json wlec_hier_append_string wlec_hier_comp_threshold
wlec_hier_compare_string wlec_hier_prepend_string wlec_lib_statetable
wlec_low_power_analysis wlec_multithread_license_list wlec_no_dft_constraints
wlec_parallel_threads wlec_post_add_notranslate_modules wlec_run_hier_check_noneq
wlec_set_cdn_synth_root wlec_uniquify wlec_use_lec_model
wlec_use_smart_lec wlec_verbose write_verification_files
clp_enable_1801_hierarchical_bbox
clp_enable_1801_hierarchical_bbox {false | true}
Description
Default: false
Data_type: bool, read/write
Determines whether to enable the 1801 hierarchical black-boxed block flow in Conformal Low Power (CLP).
Applies to:
root
clp_ignore_ls_high_to_low
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Genus Attribute Reference
Formal Verification--clp_treat_errors_as_warnings
clp_ignore_ls_high_to_low {false | true}
Description
Default: false
Data_type: bool, read/write
Determines whether Conformal Low Power (CLP) should check for high to low voltage level shifting.
Applies to:
root
clp_treat_errors_as_warnings
clp_treat_errors_as_warnings <error_message_list>
Description
Default:
Data_type: string, read/write
Forces Conformal Low Power (CLP) to treat the specified error message IDs as warnings.
Applies to:
root
lec_executable
Syntax
lec_executable <path>
Applies to:
root
Description
Default:
Data_type: string, read/write
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Formal Verification--sim_model
Specifies the Conformal ® Low Power (CLP) executable that should be used for the check_power_structure and check_cpf
commands.
sim_model
Syntax
sim_model {{hdl_format list_of_unix_paths}...}
Applies to:
hdl_component
Description
Default:
Data_type: string, read/write
Specifies the UNIX location of the simulation model for the specified ChipWare component. This attribute takes a Tcl list of Tcl
lists: each sub-list represents a simulation model of the ChipWare component and a pair of strings in the following format:
{hdl_format list_of_unix_paths}
where:
The possible values for hdl_format are:
v1995 (for Verilog-1995 simulation models)
v2001 (for Verilog-2001 simulation models)
sv (for SystemVerilog simulation models)
vhdl1987 (for VHDL-1987 simulation models)
vhdl1993 (for VHDL-1993 simulation models)
The list_of_paths is a UNIX path pointing to the simulation model.
Examples
If the simulation model is not hierarchical, the sim_model attribute values can look like the following example:
{ { v1995 $path/CW_complete.v } \
{ v2001 $path/CW_complete.v } \
{ vhdl1987 $path/CW_complete.vhdl } \
{ vhdl1993 $path/CW_complete.vhdl } }
If the simulation model is hierarchical, the sim_model attribute values can look like the following example:
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Formal Verification--verification_directory
{ { v1995 { $path/CW_top.v $path/CW_leaf.v } } \
{ v2001 { $path/CW_top.v $path/CW_leaf.v } } \
{ vhdl1987 { $path/CW_top.vhdl $path/CW_leaf.vhdl } } \
{ vhdl1993 { $path/CW_top.vhdl $path/CW_leaf.vhdl } } }
Related Information
Affects this command: elaborate
verification_directory
Syntax
verification_directory <string>
Applies to:
design
Description
Default:
Data_type: string, read/write
Specifies the directory to which the verification files are written. The directory will be created if it did not already exist.
If no directory name is specified, the default directory name will be based on the verification_directory_naming_style
attribute value.
Related Information
Affected by this attribute: verification_directory_naming_style
verification_directory_naming_style
verification_directory_naming_style string
Description
Default: fv/%s
Data_type: string, read/write
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Formal Verification--wcdc_clock_dom_comb_propagation
Specifies the format to be used to name the directory to which the verification files are written when the
write_verification_files attribute is set to true.
The attribute value can contain an arbitrary string, zero or one %s representing the design name, and zero or one %d representing
the number of the session.
If the value contains neither %s nor %d, each elaboration run writes the files in the same directory, overwriting the existing
ones.
If the value contains %d, each elaboration run creates a new directory.
If the value contains %s but no %d, a new directory is created only if elaboration is given a different top design.
By default, the verification directory will be overwritten each time you run a new session of the tool.
The following files will be written to this directory:
fv_map.v.gz: Intermediate netlist generated during syn_map
rtl_to_fv_map.do: A do file for comparison between RTL and the intermediate netlist generated during syn_map
fv_map.fv.json: Auxiliary information
If you want to change the attribute setting, do so before you elaborate the design.
Applies to:
root
Related Information
Affects these commands: elaborate
syn_generic
syn_map
syn_opt
wcdc_clock_dom_comb_propagation
wcdc_clock_dom_comb_propagation {logic_nophase | exact_phase | either_phase | wire | logic_phase}
Description
Default: logic_nophase
Data_type: string, read/write
Controls clock domain propagation through combinational elements in the Conformal® Extended Checks software.
Applies to:
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Formal Verification--wcdc_synchronizer_type
root
wcdc_synchronizer_type
Syntax
wcdc_synchronizer_type {dff | mux | module} ...
Applies to:
design
Description
Default: {dff mux}
Data_type: string, read/write
Specifies the type of synchronizer circuit used in the design. You can specify multiple values.
wclp_lib_statetable
wclp_lib_statetable {true | false}
Description
Default: true
Data_type: bool, read/write
Affects the read library -liberty command in the generated dofile. If set to true, that command is equipped with a -
statetable option. If set to false, that command will not have -statetable.
Applies to:
root
Related Information
Affects this command check_cpf
check_power_structure
write_clp_script
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Formal Verification--wlec_add_noblack_box_retime_subdesign
wlec_add_noblack_box_retime_subdesign
wlec_add_noblack_box_retime_subdesign {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether to add the Conformal LEC command that excludes the specified retimed modules from the hierarchical dofile
script generation. Specify this attribute before writing out the intermediate netlist.
The default value is the recommended value for retiming verification.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_analyze_abort
wlec_analyze_abort {true | false}
Description
Default: false
Data_type: bool, read/write
Adds the Conformal LEC command that analyzes the abort points to the dofile. The command works on the abort points in the
design and tries to resolve them by adding partition points, increasing the compare effort, and more. Specify this attribute before
writing out the intermediate netlist.
If the attribute is set to true in a hierarchical compare, the following commands are added in the dofile:
write hier_compare dofile <dofile name> -noexact_pin_match -constraint -usage
-replace -run_hier -prepend_string
"remodel -seq_constant -repeat"
run hier_compare <dofile name> -analyze_abort
If the attribute is set to true in a flat compare, the following commands are added in the dofile:
set system mode lec
remodel -seq_constant -repeat
map key points
report mapped points
report unmapped points -summary
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Formal Verification--wlec_analyze_setup
report unmapped points -extra -unreachable -notmapped
add compared points -all
compare
usage
// if seeing abort, please try ’analyze abort -compare’
report compare data
Applies to:
root
Related Information
Affects this command write_do_lec
Affected by this attribute: wlec_auto_analyze
wlec_analyze_setup
wlec_analyze_setup {true | false}
Description
Default: false
Data_type: bool, read/write
Adds the Conformal LEC command analyze setup -verbose to the dofile. The command analyzes setup related issues and tries
to correct any key point mapping related issues before starting the comparison. Specify this attribute before writing out the
intermediate netlist.
If the attribute is set to true in a hierarchical compare, the following commands will be added in the dofile:
write hier_compare dofile <dofile name> -noexact_pin_match -constraint \
-usage -replace -run_hier -prepend_string
"remodel -seq_constant -repeat;analyze setup -verbose; map key points"
If the attribute is set to true in a flat compare, the following commands are added:
set system mode lec
remodel -seq_constant -repeat
analyze setup -verbose
map key points
Applies to:
root
Related Information
Affects this command write_do_lec
Affected by this attribute: wlec_auto_analyze
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Formal Verification--wlec_auto_analyze
wlec_auto_analyze
wlec_auto_analyze {true | false}
Description
Default: true
Data_type: bool, read/write
Adds the Conformal LEC command set analyze option -auto to the dofile. This command handles both setup related issues
as well as abort points (if any). This attribute is a superset of the wlec_analyze_abort and wlec_analyze_setup attributes. Hence,
if you keep this attribute at its default value of true, you do not need to specify neither wlec_analyze_setup nor
wlec_analyze_abort.
By default the hierarchical compare will have the following commands in the dofile:
set flatten model -seq_constant -seq_constant_x_to 0
set flatten model -nodff_to_dlat_zero -nodff_to_dlat_feedback
set analyze option -auto
write hier_compare dofile <dofile name> -noexact_pin_match -constraint -usage \
-replace -run_hier -prepend_string "remodel -seq_constant -repeat"
run hier_compare <dofile name>
By default, the flat compare will have the following commands in the dofile:
set flatten model -seq_constant -seq_constant_x_to 0set flatten model -nodff_to_dlat_zero -
nodff_to_dlat_feedbackset analyze option -autoset system mode lecremodel -seq_constant -repeat
If all of the wlec_auto_analyze, wlec_analyze_setup, and wlec_analyze_abort attributes are set to true, the wlec_auto_analyze
will take precedence.
Applies to:
root
Related Information
Affects this command write_do_lec
Affects these attributes: wlec_analyze_abort
wlec_analyze_setup
wlec_black_box_ilm_modules
wlec_black_box_ilm_modules {true | false}
Description
Default: false
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Formal Verification--wlec_compare_threads
Data_type: bool, read/write
When true, Conformal LEC treats ILM modules as black boxes.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_compare_threads
wlec_compare_threads <integer>
Description
Default: 4
Data_type: int, read/write
Adds the Conformal® LEC command set compare options with the -threads option to the dofile. The attribute value specifies
the number of compare threads.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_composite_compare
wlec_composite_compare {true | false}
Description
Default: true
Data_type: bool, read/write
Specifies that the generated .do file include two compare operations: rtl-to-fv_map and fv_map-to-revised. The 'fv_map' netlist
is automatically written in the verification directory during mapping (syn_map). When disabled, the generated .do file contains only
one compare operation: golden-to-revised.
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Formal Verification--wlec_dft_constraint_file
Only applicable when you execute the write_do_lec command after the syn_map command with the -golden_design
defaulting to the RTL.
This attribute has no effect when root attribute one_pass_formal_verification is true.
Applies to:
root
Related Information
Affects this command: write_do_lec
Related attributes verification_directory
verification_directory_naming_style
wlec_dft_constraint_file
wlec_dft_constraint_file <file>
Description
Default:
Data_type: string, read/write
Specifies a TCL script to be sourced from the generated .do dofile. This provides a method to apply additional DFT constraints
during formal verification when a third-party DFT tool is used. This file must exist when verification is performed.
Applies to:
root
Related Information
Affects this command: write_do_lec
wlec_gzip_fv_json
wlec_gzip_fv_json {true | false}
Description
Default: false
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Formal Verification--wlec_hier_append_string
Data_type: bool, read/write
When set to true, compresses the verification information files, <name>.fv.json.gz, written by write_do_lec to the verification
directory.
Conformal 19.10-s300 or higher version is required to support compressed .fv.json.gz files.
Applies to:
root
Related Information
Affects this command: write_do_lec
wlec_hier_append_string
wlec_hier_append_string <file>
Description
Default:
Data_type: string, read/write
When specified, the value is used as the -append_string argument to the Conformal LEC write_hier_compare_dofile
command written to the dofile by write_do_lec command.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_hier_comp_threshold
wlec_hier_comp_threshold <integer>
Description
Default: 50
Data_type: int, read/write
Specifies the minimum number of instances required in a module to perform a hierarchical comparison on that module with the
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Formal Verification--wlec_hier_compare_string
Conformal® Logical Equivalence Checker.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_hier_compare_string
wlec_hier_compare_string <file>
Description
Default:
Data_type: string, read/write
When specified, the value is used as the -compare_string argument to the Conformal LEC write_hier_compare_dofile
command written to the dofile by write_do_lec command.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_hier_prepend_string
wlec_hier_prepend_string <file>
Description
Default:
Data_type: string, read/write
When specified, the value is used as the -prepend_string argument to the Conformal LEC write_hier_compare_dofile
command written to the dofile by write_do_lec command.
Applies to:
root
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Formal Verification--wlec_lib_statetable
Related Information
Affects this command write_do_lec
wlec_lib_statetable
wlec_lib_statetable {true | false}
Description
Default: true
Data_type: bool, read/write
Affects the read library -liberty command in the generated dofile. If set to true, that command is equipped with a -
statetable option. If set to false, that command will not have -statetable.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_low_power_analysis
wlec_low_power_analysis {true | false}
Description
Default: false
Data_type: bool, read/write
When enabled, adds the Conformal Low Power commands to compare the power domains between the golden and revised
designs. The design needs to have power intent information.
This attribute controls the following the Conformal Low Power commands: check_lowpower_cells (CPF) and
compare_power_consistency (1801 flow), and compare_power_intent.
Applies to:
root
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Formal Verification--wlec_multithread_license_list
Related Information
Affects this command: write_do_lec
wlec_multithread_license_list
wlec_multithread_license_list <string>
Description
Default:
Data_type: string, read/write
Specifies the Conformal license or list of Conformal licenses to use for multi-threaded processing. If the list is empty, the
Conformal default list will be used.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_no_dft_constraints
wlec_no_dft_constraints {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, specifies that automatically generated DFT constraints not be included in the Conformal LEC dofile written by
write_do_lec command.
Applies to:
root
Related Information
Affects this command write_do_lec
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Formal Verification--wlec_parallel_threads
wlec_parallel_threads
wlec_parallel_threads <integer>
Description
Default: 4
Data_type: int, read/write
Adds the Conformal LEC command set parallel option with the -threads option to the dofile. The attribute value specifies the
number of parallel threads.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_post_add_notranslate_modules
wlec_post_add_notranslate_modules <string>
Description
Default:
Data_type: string, read/write
Specifies a Tcl script to be sourced after any add_no_translate_modules command execution and before read_library
command in the .do script generated by write_do_lec. Use add_no_translate_modules commands in the
wlec_post_add_notranslate_modules script to overwrite any automatically-generated add_no_translate_modules commands.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_run_hier_check_noneq
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Formal Verification--wlec_set_cdn_synth_root
wlec_run_hier_check_noneq {true | false}
Description
Default: false
Data_type: bool, read/write
Adds -check_noneq option to the run_hier_compare command in the dofile, which results in Conformal LEC to skip the
analyze_datapath command if a quick compare operation first determines that the submodule is not equivalent. This option
reduces Conformal LEC runtime for designs that require dynamic flattening.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_set_cdn_synth_root
wlec_set_cdn_synth_root {true | false}
Description
Default: false
Data_type: bool, read/write
This attribute only applies if the design contains ChipWare or third party libraries. By default, the CDN_SYNTH_ROOT environment
variable will not be set in the generated dofile. This allows you the flexibility to manually set CDN_SYNTH_ROOT.
If this attribute is set to true, the CDN_SYNTH_ROOT is set to the directory in which the tool is installed. This ensures that the
ChipWare/third party library components are picked from the same tool session that was used during synthesis.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_uniquify
wlec_uniquify {true | false}
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Formal Verification--wlec_use_lec_model
Description
Default: true
Data_type: bool, read/write
Controls uniquification of all modules in the design. If this attribute is set to true, the write_do_lec command adds the following
LEC command to the generated dofile:
uniquify -all -nolib
This attribute is only effective if the generated dofile performs a hierarchical Conformal comparison.
If the RTL has instantiated ChipWare components, the uniquify command will be generated in the dofile regardless of the
value of the wlec_uniquify attribute. This is to prevent these modules from getting skipped during hierarchical compare.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_use_lec_model
wlec_use_lec_model {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether all ChipWare simulation models should be included.
If this attribute is set to false, the simulation for all ChipWare components will be loaded.
If set to true, the simulation model for all ChipWare components will be loaded except the following two:
CW_mult
DW02_mult
The generated dofile uses the Conformal built-in models instead. For these two components, the write_do_lec command
Assumes the existence of LEC built-in models if
set_db wlec_use_lec_model true
Adds the tool provided models into the dofile if
set_db wlec_use_lec_model false
This attribute is effective only if the golden design is the RTL code that was loaded into the tool.
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Formal Verification--wlec_use_smart_lec
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_use_smart_lec
wlec_use_smart_lec {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether to add adaptive-proof commands and information on massively parallel hierarchical compare to the dofile.
A Conformal Smart LEC license is required.
Applies to:
root
Related Information
Affects this command write_do_lec
wlec_verbose
wlec_verbose {true | false}
Description
Default: false
Data_type: bool, read/write
Generates a dofile with verbose reporting. Alternatively, use the -verbose option of the write_do_lec command.
Applies to:
root
Related Information
Affects this command write_do_lec
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Formal Verification--write_verification_files
write_verification_files
write_verification_files {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether or not to write intermediate files to the verification directory, specified by the
verification_directory_naming_style attribute.
Applies to:
root
Related Information
Affects these commands: elaborate
syn_generic
syn_map
syn_opt
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Netlist Export
15
Netlist Export
error_on_lib_lef_pin_inconsistency gen_module_prefix hdl_keep_wand_wor_type
lef_add_logical_pins lef_add_power_and_ground_pins use_power_ground_pin_from_lef
write_sv_port_wrapper write_vlog_bit_blast_bus_connections write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports write_vlog_bit_blast_tech_cell write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires write_vlog_empty_module_for_black_box write_vlog_empty_module_for_logic_abstract
write_vlog_empty_module_for_subdesign write_vlog_generic_gate_define write_vlog_line_wrap_limit
write_vlog_no_negative_index write_vlog_port_association_style write_vlog_preserve_net_name
write_vlog_simplify_constant write_vlog_skip_ilm_modules write_vlog_skip_subdesign
write_vlog_top_module_first write_vlog_unconnected_port_style write_vlog_wor_wand
error_on_lib_lef_pin_inconsistency
Syntax
error_on_lib_lef_pin_inconsistency {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
If enabled, the tool will issue an error message if a library pin of a logical cell is not found in the corresponding physical cell.
You must set this attribute before reading the libraries.
Related Information
Affects this attribute: library
gen_module_prefix
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Netlist Export--hdl_keep_wand_wor_type
Syntax
gen_module_prefix <string>
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the prefix to be used for internally generated module names (arithmetic, logic, register-file modules, and so on).
This attribute is supported only in the RTL flow.
Related Information
Affects this command: read_hdl
hdl_keep_wand_wor_type
hdl_keep_wand_wor_type integer
Description
Default: 0
Data_type: int, read/write
Specifies the wand and wor nets in the netlist. When set to 1, it will retain wand and wor nets in the netlist.
Applies to:
root
lef_add_logical_pins
lef_add_logical_pins {true | false}
Description
Default: true
Data_type: bool, read/write
Controls the addition of LEF logical pins (pins other than ANALOG, GROUND, or POWER) that are not part of the lib_cell definition in the Liberty file. By
default, these pins are added to the lib_cell definition.
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Netlist Export--lef_add_power_and_ground_pins
Applies to:
root
lef_add_power_and_ground_pins
lef_add_power_and_ground_pins {true | false}
Description
Default: true
Data_type: bool, read/write
Controls the addition of LEF POWER and GROUND pins that are not part of the lib_cell definition in the Liberty file. By default, these pins are added to
the lib_cell definition.
Applies to:
root
use_power_ground_pin_from_lef
use_power_ground_pin_from_lef {true | false}
Description
Default: true
Data_type: bool, read/write
Specifies whether or not to ignore the inconsistency in the use definition of power and ground pins between .lib and LEF libraries. By default, the
definition from LEF is used when an inconsistency is detected.
When this attribute is enabled, you must read in the LEF libraries before reading the design information.
Applies to:
root
write_sv_port_wrapper
write_sv_port_wrapper {false | true}
Description
Default: false
Data_type: bool, read/write
Determines if the write_hdl command should write out a wrapper to connect the original I/O interfaces to the port names in the Verilog it writes out.
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Netlist Export--lef_add_power_and_ground_pins
This attribute applies only to RTL using System Verilog interfaces. By default, the I/O ports in the Verilog netlist written by the write_hdl
command do not match the test bench because interfaces were used.
Example
RTL
interface ffbus (input logic c, d, output logic q);
endinterface: ffbus
module ff (ffbus a);
always @(posedge a.c) a.q <= a.d;
endmodule
Script
# Set the 'write_sv_port_wrapper' attribute to true:
set_db / .library tutorial.lib
set_db / .write_sv_port_wrapper true
read_hdl -sv 1.v
elab
write_hdl
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Netlist Export--write_vlog_bit_blast_bus_connections
Netlist
# The 'write_hdl' command writes out the following netlist:
module ff(.a({a_q, a_d, a_c}));
input a_c, a_d;
output a_q;
wire a_c, a_d;
wire a_q;
CDN_flop a_q_reg(.clk (a_c), .d (a_d), .sena (1’b1), .aclr (1’b0),
.apre (1’b0), .srl (1’b0), .srd (1’b0), .q (a_q));
endmodule
`ifdef SYNTHESIS
`else
module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
input clk, d, sena, aclr, apre, srl, srd;
output q;
wire clk, d, sena, aclr, apre, srl, srd;
wire q;
reg qi;
assign #1 q = qi;
always
@(posedge clk or posedge apre or posedge aclr)
if (aclr)
qi = 0;
else if (apre)
qi = 1;
else if (srl)
qi = srd;
else begin
if (sena)
qi = d;
end
initial
qi = 1’b0;
endmodule
`endif
Applies to:
root
Related Information
Affects this command: write_hdl
write_vlog_bit_blast_bus_connections
Syntax
write_vlog_bit_blast_bus_connections {false | true}
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Netlist Export--write_vlog_bit_blast_constants
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Determines if the write_hdl command will write out the busses connected to the instance pins as individual bits (in a bit-blasted style).
Example
If the default value of false is maintained, the bus connection style for instance pins is the merged style. In the following example, a and b are each
four bit busses:
sub sub(.a ({a[3], 1’b0, a[1:0]}), .b (b));
If the attribute is set to true, the instance pins will be bit-blasted:
sub sub(.a ({a[3],1’b0,a[1],a[0]}), .b ({b[3],b[2],b[1],b[0]}));
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_bit_blast_constants
write_vlog_bit_blast_constants {false | true}
Default: false
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Netlist Export--write_vlog_bit_blast_constants
Read-write root attribute. Determines if the write_hdl command will write out constants as individual bits (in a bit-blasted style).
Example
For the following example RTL:
// filename: test.v
module leaf (y, a, b);
input [7:0] a, b;
output [7:0] y;
assign y = a + b;
endmodule
module top (y, a, b);
input [7:0] a;
input [3:0] b;
output [7:0] y;
leaf u1 (y, a, {4’b0110, b});
endmodule
If you set the write_vlog_bit_blast_constants attribute to false as follows:
legacy_genus:/> set_attribute library tutorial.lib
legacy_genus:/> read_hdl test.v
legacy_genus:/> elaborate
legacy_genus:/> set_attribute write_vlog_bit_blast_constants false
legacy_genus:/> write_hdl
Then the write_hdl command writes out the following output:
module leaf (y, a, b);
...
endmodule
module top (y, a, b);
input [7:0] a;
input [3:0] b;
output [7:0] y;
leaf u1 (y, a, {4’b0110, b});
endmodule
If you set the write_vlog_bit_blast_constants attribute to true, the write_hdl command writes out the following netlist:
module leaf (y, a, b);
...
endmodule
module top (y, a, b);
input [7:0] a;
input [3:0] b;
output [7:0] y;
leaf u1 (y, a, {1’b0, 1’b1, 1’b1, 1’b0, b});
endmodule
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Netlist Export--write_vlog_bit_blast_mapped_ports
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_mapped_ports {false | true}
Default: false
Read-write root attribute. Indicates if mapped ports are separated into bits (bit blasted).
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Netlist Export--write_vlog_bit_blast_mapped_ports
Example
For the following example RTL:
// filename: test.v
module leaf (y, a, b);
input [5:0] a, b;
output [5:0] y;
assign y = a + b;
endmodule
module top (y, a, b);
input [5:0] a;
input [2:0] b;
output [5:0] y;
leaf u1 (y, a, {3’b010, b});
endmodule
If you use the following script:
set_attribute library tutorial.lib
read_hdl test.v
elaborate
set_attribute false
write_hdl
Then the write_hdl command writes out the following netlist:
module leaf (y, a, b);
input [5:0] a, b;
output [5:0] y;
...
endmodule
module top (y, a, b);
input [5:0] a;
input [2:0] b;
output [5:0] y;
leaf u1 (y, a, {3’b010, b});
endmodule
If you set the attribute to true, then the write_hdl command writes out the following netlist:
module leaf (y_5, y_4, y_3, y_2, y_1, y_0, a_5, a_4, a_3, a_2, a_1, a_0, b_5,
b_4, b_3, b_2, b_1, b_0);
input a_5, a_4, a_3, a_2, a_1, a_0;
input b_5, b_4, b_3, b_2, b_1, b_0;
output y_5, y_4, y_3, y_2, y_1, y_0;
...
endmodule
module top (y_5, y_4, y_3, y_2, y_1, y_0, a_5, a_4, a_3, a_2, a_1, a_0,
b_2, b_1, b_0);
input a_5, a_4, a_3, a_2, a_1, a_0;
input b_2, b_1, b_0;
output y_5, y_4, y_3, y_2, y_1, y_0;
leaf u1 (y_5, y_4, y_3, y_2, y_1, y_0,
a_5, a_4, a_3, a_2, a_1, a_0,
1’b0, 1’b1, 1’b0, b_2, b_1, b_0);
endmodule
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Genus Attribute Reference
Netlist Export--write_vlog_bit_blast_tech_cell
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_bit_blast_tech_cell
write_vlog_bit_blast_tech_cell {false | true}
Default: false
Read-write root attribute. Determines if the write_hdl command will write out ports of technology cells that are explicitly instantiated in the netlist as
individual bits (in a bit-blasted style).
Examples
Consider the following RTL code:
module lte_modem_fft_s3_ram256x38_1_fft (sin, we_n, \din[5] , \din[4] , \din[3] ,\din[2] , \din[1] , \din[0] , sout, clk, \addr[7] , \addr[6] ,
\addr[5] , \addr[4] ,\addr[3] , \addr[2] , \addr[1] , \addr[0] , \dout[5] , \dout[4] , \dout[3] , \dout[2] , \dout[1] , \dout[0] , slp_ret_n,
shift_n, slp_nret_n, scan_n, cs_n);
input sin; input we_n; input \din[5] , \din[4] , \din[3] , \din[2] , \din[1] , \din[0] ; output sout; input clk; input \addr[7] , \addr[6] ,
\addr[5] , \addr[4] , \addr[3] , \addr[2] , \addr[1] , \addr[0] ; output \dout[5] , \dout[4] , \dout[3] , \dout[2] , \dout[1] , \dout[0] ; input
slp_ret_n; input shift_n; input slp_nret_n; input scan_n; input cs_n;
// Internal wires
wire FE_OFN200_s2_b_im_p_2__5_;
wire FE_OFN199_s2_b_im_p_2__1_;
qcsram1111_22rwdng00_256x38_4_stdsp_rhrf M1 (
.\dout[5] (\dout[5] ), .\dout[4] (\dout[4] ), .\dout[3] (\dout[3] ),
.\dout[2] (\dout[2] ), .\dout[1] (\dout[1] ), .\dout[0] (\dout[0] ),
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Netlist Export--write_vlog_bit_blast_tech_cell
.\din[5] (FE_OFN200_s2_b_im_p_2__5_), .\din[4] (\din[4] ),
.\din[3] (\din[3] ), .\din[2] (\din[2] ),
.\din[1] (FE_OFN199_s2_b_im_p_2__1_), .\din[0] (\din[0] ),
.\addr[7] (\addr[7] ), .\addr[6] (\addr[6] ), .\addr[5] (\addr[5] ),
.\addr[4] (\addr[4] ), .\addr[3] (\addr[3] ), .\addr[2] (\addr[2] ),
.\addr[1] (\addr[1] ), .\addr[0] (\addr[0] ),
.we_n(we_n),
.sout(sout),
.slp_ret_n(slp_ret_n),
.slp_nret_n(slp_nret_n),
.sin(sin),
.shift_n(shift_n),
.scan_n(scan_n),
.cs_n(cs_n),
.clk(clk));endmodule
The following examples show how the setting of the write_vlog_bit_blast_tech_cell attribute affect the generated netlist. You can compare the
bolded text in both examples to see the effect.
Assume you use the following script:
set_attribute library lte_modem_ram_0.99v_ss_m30_cmax_m30_1.0.lib.gz
read_netlist write_vlog_bit_blast_tech_cell.v
set_attribute write_vlog_bit_blast_tech_cell false
write_hdl
Then the write_hdl command writes out the following netlist:
module lte_modem_fft_s3_ram256x38_1_fft(sin, we_n, \din[5] , \din[4] ,
\din[3] , \din[2] , \din[1] , \din[0] , sout, clk, \addr[7] , \addr[6] ,
\addr[5] , \addr[4] , \addr[3] , \addr[2] , \addr[1] , \addr[0] , \dout[5] ,
\dout[4] , \dout[3] , \dout[2] , \dout[1] , \dout[0] , slp_ret_n, shift_n,
slp_nret_n, scan_n, cs_n);
input sin, we_n, \din[5] , \din[4] , \din[3] , \din[2] , \din[1] ,
\din[0] , clk, \addr[7] , \addr[6] , \addr[5] , \addr[4] , \addr[3] ,
\addr[2] , \addr[1] , \addr[0] , slp_ret_n, shift_n, slp_nret_n,
scan_n, cs_n;
output sout, \dout[5] , \dout[4] , \dout[3] , \dout[2] , \dout[1] ,
\dout[0] ;
wire sin, we_n, \din[5] , \din[4] , \din[3] , \din[2] , \din[1] ,
\din[0] , clk, \addr[7] , \addr[6] , \addr[5] , \addr[4] , \addr[3] ,
\addr[2] , \addr[1] , \addr[0] , slp_ret_n, shift_n, slp_nret_n,
scan_n, cs_n;
wire sout, \dout[5] , \dout[4] , \dout[3] , \dout[2] , \dout[1] , \dout[0] ;
wire FE_OFN199_s2_b_im_p_2__1_, FE_OFN200_s2_b_im_p_2__5_;
qcsram1111_22rwdng00_256x38_4_stdsp_rhrf M1(.clk (clk), .sin (sin),
.we_n (we_n), .din ({FE_OFN200_s2_b_im_p_2__5_, \din[4] , \din[3] ,
\din[2] , FE_OFN199_s2_b_im_p_2__1_, \din[0]}), .addr ({\addr[7] ,
\addr[6] , \addr[5] , \addr[4] , \addr[3] , \addr[2] , \addr[1] ,
\addr[0] }), .shift_n (shift_n), .slp_ret_n (slp_ret_n),
.slp_nret_n (slp_nret_n), .scan_n (scan_n), .cs_n (cs_n),
.sout (sout), .dout ({\dout[5] , \dout[4] , \dout[3] , \dout[2] ,
\dout[1] , \dout[0] }));
endmodule
If you set the write_vlog_bit_blast_tech_cell attribute to true, then the write_hdl command writes out the following netlist.
module lte_modem_fft_s3_ram256x38_1_fft(sin, we_n, \din[5] , \din[4] ,
\din[3] , \din[2] , \din[1] , \din[0] , sout, clk, \addr[7] , \addr[6] ,
\addr[5] , \addr[4] , \addr[3] , \addr[2] , \addr[1] , \addr[0] , \dout[5] ,
\dout[4] , \dout[3] , \dout[2] , \dout[1] , \dout[0] , slp_ret_n, shift_n,
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Netlist Export--write_vlog_bit_blast_tech_cell
slp_nret_n, scan_n, cs_n);
input sin, we_n, \din[5] , \din[4] , \din[3] , \din[2] , \din[1] ,
\din[0] , clk, \addr[7] , \addr[6] , \addr[5] , \addr[4] , \addr[3] ,
\addr[2] , \addr[1] , \addr[0] , slp_ret_n, shift_n, slp_nret_n,
scan_n, cs_n;
output sout, \dout[5] , \dout[4] , \dout[3] , \dout[2] , \dout[1] ,
\dout[0] ;
wire sin, we_n, \din[5] , \din[4] , \din[3] , \din[2] , \din[1] ,
\din[0] , clk, \addr[7] , \addr[6] , \addr[5] , \addr[4] , \addr[3] ,
\addr[2] , \addr[1] , \addr[0] , slp_ret_n, shift_n, slp_nret_n,
scan_n, cs_n;
wire sout, \dout[5] , \dout[4] , \dout[3] , \dout[2] , \dout[1] , \dout[0]
wire FE_OFN199_s2_b_im_p_2__1_, FE_OFN200_s2_b_im_p_2__5_;
qcsram1111_22rwdng00_256x38_4_stdsp_rhrf M1(.clk (clk), .sin (sin),
.we_n (we_n), .\din[5] (FE_OFN200_s2_b_im_p_2__5_),
.\din[4] (\din[4] ), .\din[3] (\din[3] ), .\din[2] (\din[2] ),
.\din[1] (FE_OFN199_s2_b_im_p_2__1_), .\din[0] (\din[0] ),
.\addr[7] (\addr[7] ), .\addr[6] (\addr[6] ), .\addr[5] (\addr[5] ),
.\addr[4] (\addr[4] ), .\addr[3] (\addr[3] ), .\addr[2] (\addr[2] ),
.\addr[1] (\addr[1] ), .\addr[0] (\addr[0] ), .shift_n (shift_n),
.slp_ret_n (slp_ret_n), .slp_nret_n (slp_nret_n), .scan_n (scan_n),
.cs_n (cs_n), .sout (sout), .\dout[5] (\dout[5] ),
.\dout[4] (\dout[4] ), .\dout[3] (\dout[3] ), .\dout[2] (\dout[2] ),
.\dout[1] (\dout[1] ), .\dout[0] (\dout[0] ));
endmodule
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
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Netlist Export--write_vlog_convert_onebit_vector_to_scalar
write_vlog_convert_onebit_vector_to_scalar
write_vlog_convert_onebit_vector_to_scalar {false | true}
Default: false
Read-write root attribute. Specifies whether to write out one bit vectors present in RTL as scalars in the generated netlist.
Example
Consider the following RTL code:
module x(X, A1, A2);
input [0:0] A1 ;
input [0:0] A2 ;
output X ;
and U$1(X, A1, A2);endmodule
If you use the default value, the netlist written out will be similar to:
module x(X, A1, A2);
input [0:0] A1, A2;
wire [0:0] A1, A2;
wire X;
and U$1 (X, A1, A2);
endmodule
If you set this attribute to true, the generated netlist will be similar to:
module x(X, A1, A2);
input A1, A2;
output X;
wire A1, A2;
wire X;
and U$1 (X, A1, A2);
endmodule
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Netlist Export--write_vlog_declare_wires
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_declare_wires
write_vlog_declare_wires {true | false}
Default: true
Read-write root attribute. Specifies whether to generate a netlist with or without implicit wires. When set to false, Genus suppresses the
declarations of implicit wires.
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Netlist Export--write_vlog_declare_wires
Example
For the following example RTL:
// filename: test.v
module test (y, a, b, c);
input [3:0] a, b, c;
output [3:0] y;
assign y = a & b & c;
endmodule
If you set the write_vlog_declare_wires to true as follows:
legacy_genus:/> set_attribute library tutorial.lib
legacy_genus:/> read_hdl test.v
legacy_genus:/> elaborate
legacy_genus:/> set_attribute write_vlog_declare_wires true
legacy_genus:/> write_hdl
Then the write_hdl command writes out the following netlist:
module test (y, a, b, c);
input [3:0] a, b, c;
output [3:0] y;
wire [3:0] a, b, c;
wire [3:0] y;
wire n_9, n_10, n_11, n_12;
and g1 (n_9, a[0], b[0]);
and g3 (n_10, a[1], b[1]);
and g4 (n_11, a[2], b[2]);
and g5 (n_12, a[3], b[3]);
and g6 (y[0], n_9, c[0]);
and g2 (y[1], n_10, c[1]);
and g7 (y[2], n_11, c[2]);
and g8 (y[3], n_12, c[3]);
endmodule
If you set the write_vlog_declare_wires to false, then the write_hdl command writes out the following netlist:
module test (y, a, b, c);
input [3:0] a, b, c;
output [3:0] y;
and g1 (n_9, a[0], b[0]);
and g3 (n_10, a[1], b[1]);
and g4 (n_11, a[2], b[2]);
and g5 (n_12, a[3], b[3]);
and g6 (y[0], n_9, c[0]);
and g2 (y[1], n_10, c[1]);
and g7 (y[2], n_11, c[2]);
and g8 (y[3], n_12, c[3]);
endmodule
Related Information
Affects this command: write_hdl
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Genus Attribute Reference
Netlist Export--write_vlog_empty_module_for_black_box
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_black_box {false | true}
Default: false
Read-write root attribute: Controls whether an empty module will be written out for an unresolved black box. If set to true, the unresolved black box
is written as an empty module. If set to false, the unresolved black box model remains unresolved in the netlist.
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Netlist Export--write_vlog_empty_module_for_logic_abstract
Related Information
Logic Abstract Modeling in Genus HDL Modeling Guide.
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_empty_module_for_logic_abstract
write_vlog_empty_module_for_logic_abstract {true | false}
Default: true
Read-write root attribute: Controls how an unresolved logic abstract model is written out in a Verilog netlist. If set to true, the unresolved logic
abstract model is written as an empty module. If set to false, the unresolved logic abstract model remains unresolved in the netlist.
Example
For the following example RTL:
// filename: test.vhd
library ieee;
use ieee.std_logic_1164.all;
entity my_top is
generic (w : integer := 4);
port (a, b, c : in std_logic_vector (w-1 downto 0);
y : out std_logic_vector (w-1 downto 0) );
end my_top;
architecture rtl of my_top is
signal t : std_logic_vector (w-1 downto 0);
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Netlist Export--write_vlog_empty_module_for_logic_abstract
component my_sub
generic (w : integer := 4);
port (p, q : in std_logic_vector (w-1 downto 0);
x : out std_logic_vector (w-1 downto 0) );
end component;
begin
u1: my_sub generic map (w => w)
port map (p => a, q => b, x => t);
y <= t or c;
end rtl;
If you set the write_vlog_empty_module_for_logic_abstract attribute to true:
legacy_genus:/> set_attribute library tutorial.lib
legacy_genus:/> read_hdl -vhdl test.vhd
legacy_genus:/> elaborate
legacy_genus:/> set_attribute write_vlog_empty_module_for_logic_abstract true
legacy_genus:/> write_hdl
Then the write_hdl command writes out the following netlist:
module my_sub_w4 (p, q, x); // an empty module
input [3:0] p, q;
output [3:0] x;
endmodule
module my_top (a, b, c, y);
input [3:0] a, b, c;
output [3:0] y;
wire t0, t1, t2, t3;
my_sub_w4 u1 (.p(a), .q(b), .x({t3, t2, t1, t0}));
or g1 (y[0], t0, c[0]);
or g2 (y[1], t1, c[1]);
or g3 (y[2], t2, c[2]);
or g4 (y[3], t3, c[3]);
endmodule
If you set the write_vlog_empty_module_for_logic_abstract attribute to false, then the write_hdl command writes out the following netlist:
module my_top (a, b, c, y);
input [3:0] a, b, c;
output [3:0] y;
wire t0, t1, t2, t3;
my_sub_w4 u1 (.p(a), .q(b), .x({t3, t2, t1, t0}));
or g1 (y[0], t0, c[0]);
or g2 (y[1], t1, c[1]);
or g3 (y[2], t2, c[2]);
or g4 (y[3], t3, c[3]);
endmodule
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Netlist Export--write_vlog_empty_module_for_subdesign
Related Information
Logic Abstract Modeling in Genus HDL Modeling Guide.
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_empty_module_for_subdesign
Syntax
write_vlog_empty_module_for_subdesign {false | true}
Applies to:
module
Description
Default: false
Data_type: bool, read/write
Controls how a module is written out in a Verilog netlist. If set to true, the module is written as an empty module.
Example
Consider the following design:
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Netlist Export--write_vlog_generic_gate_define
module sub(in, out);
input in;
output out;
assign out = in;
endmodule
module WRTV(in, out);
input in;
output [4:0]out;
sub s0(in, out[4]);
endmodule
Set the write_vlog_empty_module_for_subdesign to true to write out the sub module as an empty module:
module sub(in, out);
input in;
output out;
endmodule
module WRTV(in, out);
input in;
output [4:0]out;
sub s0(in, out[4]);
endmodule
Using the default setting for write_vlog_empty_module_for_subdesign, will result in the following netlist:
module sub(in, out);
input in;
output out;
wire in;
wire out;
assign out = in;
endmodule
module WRTV(in, out);
input in;
output [4:0]out;
sub s0(in, out[4]);
endmodule
Related Information
Affects this command: write_hdl
write_vlog_generic_gate_define
write_vlog_generic_gate_define string
Default: RC_CDN_GENERIC_GATE
Read-write root attribute. Specifies the Verilog macro name that is written in the output Verilog netlist to enclose module descriptions of Genus built-
in generic gates within ’ifdef and ’endif Verilog compiler directives.
A netlist written after elaborate can have the following module description:
`ifdef RC_CDN_GENERIC_GATE`elsemodule CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);....`endif
You must include module descriptions of generic gates in the output netlist to simulate the design, but the module descriptions are not needed to
read in the netlist in Genus.
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Netlist Export--write_vlog_line_wrap_limit
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_line_wrap_limit
write_vlog_line_wrap_limit integer
Default: 72
Read-write root attribute. Specifies the number of printable characters on a single line in the written netlist.
This attribute is not supported for writing out encrypted modules.
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Netlist Export--write_vlog_no_negative_index
Related Information
Affects these commands: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_no_negative_index
write_vlog_no_negative_index {false | true}
Default: false
Read-write root attribute. When set to true, Genus converts negative ranges to the standard (normalized) range and keeps the direction unchanged
as follows:
input a[-4:0] --> input a[0:4]
input b[0:-4] --> input b[4:0]
This attribute also applies to internal bus wires.
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Netlist Export--write_vlog_port_association_style
Related Information
Affects these commands: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_port_association_style
Syntax
write_vlog_port_association_style {default | positional | named}
Applies to:
hinst
inst
Description
Default: default
Data_type: string, read/write
Determines the style for writing port connections of an instance. The style can be default, which specifies that the instance is written out the same as
the original design input, positional, which specifies that the instance is written out as a positional instance, or named, which specifies that the
instance is written out as a named instance.
This attribute is supported only for hierarchical and blackbox instances.
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Netlist Export--write_vlog_preserve_net_name
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_preserve_net_name
write_vlog_preserve_net_name {true | false}
Default: false
Read-write root attribute. When set to true, Genus preserves the wire names present in the input design. This will result in an increase in the
number of assign statements in the output netlist.
This attribute is supported in both RTL and Structural flows.
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Netlist Export--write_vlog_simplify_constant
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_simplify_constant
Syntax
write_vlog_simplify_constant {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Determines whether or not to simplify constants when writing them out.
Example
If the attribute is set to true, consecutive 0s from MSB are skipped when writing the netlist:
sub sub(.a (4'b0), .b (4'b10));
If the attribute is set to false, consecutive 0s from MSB are kept when writing the netlist:
sub sub(.a (4'b0000), .b (4'b0010));
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Genus Attribute Reference
Netlist Export--write_vlog_skip_ilm_modules
Related Information
Affects this command: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
write_vlog_skip_ilm_modules
write_vlog_skip_ilm_modules {false | true}
Default: false
Read-write root attribute. Specifies whether to skip writing out Verilog for ILM modules.
write_vlog_skip_subdesign
Syntax
write_vlog_skip_subdesign {false | true}
Applies to:
module
Description
Default: false
Data_type: bool, read/write
Prevents that the subdesign is written out as a Verilog module in the netlist.
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Netlist Export--write_vlog_top_module_first
Example
Consider the following example RTL:
module sub(a, b);
input [3:0] a;
output [3:0] b;
inv1 g0(.A (a[0]), .Y (b[0]));
inv1 g1(.A (a[1]), .Y (b[1]));
inv1 g2(.A (a[2]), .Y (b[2]));
inv1 g3(.A (a[3]), .Y (b[3]));
endmodule
module test(a, b);
input [3:0] a;
output [3:0] b;
sub sub1(.a ({2'b10,a[1:0]}), .b ({b[3:2],1'b0, b[1]}));
sub sub2(.a (a), .b ({b[3], b[2:0]}));
sub sub3(.a ({a[3:2],2'b10}), .b (b));
sub1 sub13(.a ({2'b10,a[3:2],3'b101,a[1]}), .b (b));
endmodule
If you set the write_vlog_skip_subdesign attribute to true on the sub module, the following netlist will be generated:
module test(a, b);
input [3:0] a;
output [3:0] b;
wire [3:0] a;
wire [3:0] b;
wire n_6, n_14, n_15, n_16, n_17, n_18;
assign n_14 = 1'b1;
assign n_15 = 1'b0;
assign n_16 = 1'b1;
assign n_17 = 1'b0;
assign n_18 = 1'b1;
assign n_6 = 1'b0;
sub sub1(.a ({2'b10, a[1:0]}), .b ({b[3:2], n_6, b[1]}));
sub sub2(.a (a), .b (b));
sub sub3(.a ({a[3:2], 2'b10}), .b (b));
sub1 sub13(.a ({n_18, n_17, a[3:2], n_16, n_15, n_14, a[1]}), .b (b));
endmodule
Related Information
Affects this command: write_hdl
write_vlog_top_module_first
write_vlog_top_module_first {false | true}
Default: false
Read-write root attribute. Indicates if the top module is written first in the Verilog output.
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Netlist Export--write_vlog_top_module_first
Example
For the following example RTL:
module top(in, out);
input in;
output out;
sub a1(.in(in), .out(out));
endmodule
module sub(in, out);
input in;
output out;
assign out = in;
endmodule
If you set the write_vlog_top_module_first attribute to true, the write_hdl command writes out the netlist with the top module first. The
default behavior is shown below:
module sub(in, out);
input in;
output out;
assign out = in;
endmodule
module top(in, out);
input in;
output out;
sub a1(.in(in), .out(out));
endmodule
Related Information
Affects these commands: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_unconnected_port_style
write_vlog_wor_wand
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Netlist Export--write_vlog_unconnected_port_style
write_vlog_unconnected_port_style
write_vlog_unconnected_port_style {full | none | partial}
Default: full
Read-write root attribute. Selects the Verilog style for unconnected instance pins. By default, the write_hdl command writes out dummy wires for
unconnected instance pins.
This attribute does not apply to Verilog gate primitives.
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Netlist Export--write_vlog_unconnected_port_style
Examples
Consider the following RTL example:
module test1 (A1,A2,Y1,Y2);
input A1,A2;
output Y1,Y2;
DELAY1 DL (.A(A2));
endmodule
Genus generates the following Verilog netlists depending upon the value of the write_vlog_unconnected_port_style attribute:
write_vlog_unconnected_port_style full
module test1(A1, A2, Y1, Y2);
input A1, A2;
output Y1, Y2;
wire A1, A2;
wire Y1, Y2;
wire UNCONNECTED;
DELAY1 DL(.A (A2), .Z (UNCONNECTED));
endmodule
write_vlog_unconnected_port_style partial
module test1(A1, A2, Y1, Y2);
input A1, A2;
output Y1, Y2;
wire A1, A2;
wire Y1, Y2;
DELAY1 DL(.A (A2), .Z ());
endmodule
write_vlog_unconnected_port_style none
module test1(A1, A2, Y1, Y2);
input A1, A2;
output Y1, Y2;
wire A1, A2;
wire Y1, Y2;
DELAY1 DL(.A (A2));
endmodule
Consider the following basic gate:
module test(in1,ou1);
input in1;
output out1;
not n1(w,in1);
endmodule
Genus generates the following Verilog netlist, independent of the setting of the attribute:
module test(in1,ou1);
input in1;
output out1;
not n1(w,in1);
endmodule
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Netlist Export--write_vlog_wor_wand
Related Information
Affects these commands: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_wor_wand
write_vlog_wor_wand
write_vlog_wor_wand {true | false}
Default: true
Read-write root attribute. When set to false, a wor (wand) wire is declared as a wire rather than a wor (wand).
Examples
By default, Genus does not synthesize wor/wand logic, even if it is present in the HDL read into Genus. However, if a signal is originally declared as
a wor signal, then the write_hdl command writes it out in the synthesized netlist.
The following command prevents signals from being declared as wor/wand in the Genus generated netlist:
legacy_genus:/> set_attribute write_vlog_wor_wand false
For example, for the following RTL:
module leaf (y, a, b);
parameter w = 4;
input [w-1:0] a, b;
output [w-1:0] y;
assign y = a & b;
endmodule
module top (y, data_0, data_1, sel_0, sel_1);
parameter w = 4;
input [w-1:0] data_0, data_1, sel_0, sel_1;
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Netlist Export--write_vlog_wor_wand
output [w-1:0] y;
wor [w-1:0] y;
leaf #(w) u0 (y, data_0, sel_0);
leaf #(w) u1 (y, data_1, sel_1);
endmodule
Genus generates the following Verilog netlists depending upon the value of the write_vlog_wor_wand attribute:
write_vlog_wor_wand true (default)
module leaf_w4(y, a, b);
....
endmodule
module top(y, data_0, data_1, sel_0, sel_1);
input [3:0] data_0, data_1, sel_0, sel_1;
output [3:0] y;
wire [3:0] data_0, data_1, sel_0, sel_1, y;
wor n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8; // <== wor
leaf_w4 u0({n_7, n_5, n_3, n_1}, data_0, sel_0);
leaf_w4 u1({n_8, n_6, n_4, n_2}, data_1, sel_1);
or g1 (y[0], n_1, n_2);
or g2 (y[1], n_3, n_4);
or g3 (y[2], n_5, n_6);
or g4 (y[3], n_7, n_8);
endmodule
write_vlog_wor_wand false
module leaf_w4(y, a, b);
....
endmodule
module top(y, data_0, data_1, sel_0, sel_1);
input [3:0] data_0, data_1, sel_0, sel_1;
output [3:0] y;
wire [3:0] data_0, data_1, sel_0, sel_1, y;
wire n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8; // <== wire
leaf_w4 u0({n_7, n_5, n_3, n_1}, data_0, sel_0);
leaf_w4 u1({n_8, n_6, n_4, n_2}, data_1, sel_1);
or g1 (y[0], n_1, n_2);
or g2 (y[1], n_3, n_4);
or g3 (y[2], n_5, n_6);
or g4 (y[3], n_7, n_8);
endmodule
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Netlist Export--write_vlog_wor_wand
Related Information
Affects these commands: write_hdl
Related Attributes: write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_top_module_first
write_vlog_unconnected_port_style
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Constraints
16
Constraints
The chapter describes the attributes of the following object types:
arc Attributes for Constraints clock Attributes for Constraints
cost_group Attribute for Constraints exception Attributes for Constraints
external_delay Attributes for Constraints hnet Attributes for Constraints
hpin Attributes for Constraints net Attribute for Constraints
pin Attributes for Constraints port Attributes for Constraints
arc Attributes for Constraints
from_pin
from_pin {hpin | pin | constant | pg_pin | hport | port}
Default: no value
Read-only arc attribute. Returns the beginning pin of this timing arc.
is_cellarc
is_cellarc {1 | 0 | true | false}
Default: no value
Read-only arc attribute. Indicates whether the arc is a libcell arc.
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Constraints--clock Attributes for Constraints
to_pin
to_pin {hpin | pin | constant | pg_pin | hport | port}
Default: no value
Read-only arc attribute. Returns the terminating pin of this timing arc.
clock Attributes for Constraints
active_clock
comment
hold_uncertainty
ideal_transition_max_fall
ideal_transition_max_rise
ideal_transition_min_fall
ideal_transition_min_rise
inverted_sources
is_combinational_source_path
max_capacitance_clock_path_fall
max_capacitance_clock_path_rise
max_capacitance_data_path_fall
max_capacitance_data_path_rise
max_transition_clock_path_fall
max_transition_clock_path_rise
max_transition_data_path_fall
max_transition_data_path_rise
min_capacitance_clock_path_fall
min_capacitance_clock_path_rise
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Constraints--clock Attributes for Constraints
min_capacitance_data_path_fall
min_capacitance_data_path_rise
min_transition_clock_path_fall
min_transition_clock_path_rise
min_transition_data_path_fall
min_transition_data_path_rise
network_latency_fall_max
network_latency_fall_min
network_latency_rise_max
network_latency_rise_min
non_inverted_sources
setup_uncertainty
source_latency_early_fall_max
source_latency_early_fall_min
source_latency_early_rise_max
source_latency_early_rise_min
source_latency_late_fall_max
source_latency_late_fall_min
source_latency_late_rise_max
source_latency_late_rise_min
active_clock
active_clock {1 | 0 | true | false}
Default: false
Read-write clock attribute. Controls the active clocks.
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Constraints--clock Attributes for Constraints
comment
comment string
Read-write clock attribute. Specifies the comment tagged to this clock.
Related Information
Set by one of these commands: create_clock
create_generated_clock
Related attribute: (exception) comment
hold_uncertainty
hold_uncertainty delay
Default: 0.0
Read-write clock attribute. Specifies the uncertainty in the arrival times of capturing edges (in
picoseconds) for the clock in early-mode (hold) timing analysis.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
Related Information
Related attributes: (hpin) hold_uncertainty
(pin) hold_uncertainty
(port) hold_uncertainty
(clock) setup_uncertainty
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Constraints--clock Attributes for Constraints
ideal_transition_max_fall
ideal_transition_max_fall float
Default: 0.0
Read-write clock attribute. Specifies the maximum fall slew value in picoseconds. The slew can
affect both the delay through the sequential devices and the setup requirements within them.
Related Information
Related attributes: (hpin) slew
(pin) slew
ideal_transition_max_rise
ideal_transition_max_rise float
Default: 0.0
Read-write clock attribute. Specifies the maximum rise slew value in picoseconds. The slew can
affect both the delay through the sequential devices and the setup requirements within them.
Related Information
Related attributes: (hpin) slew
(pin) slew
ideal_transition_min_fall
ideal_transition_min_fall float
Default: 0.0
Read-write clock attribute. Specifies the minimum fall slew value in picoseconds. Genus ignores
(does not use) the minimum values but they can be passed to downstream tools. The slew can
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Constraints--clock Attributes for Constraints
affect both the delay through the sequential devices and the setup requirements within them.
Related Information
Related attributes: (hpin) slew
(pin) slew
ideal_transition_min_rise
ideal_transition_min_rise float
Default: 0.0
Read-write clock attribute. Specifies the minimum rise slew value in picoseconds. Genus ignores
(does not use) the minimum values but they can be passed to downstream tools. The slew can
affect both the delay through the sequential devices and the setup requirements within them.
Related Information
Related attributes: (hpin) slew
(pin) slew
inverted_sources
inverted_sources string
Read-write clock attribute. Specifies a Tcl list of the ports and pins that are inverted sources of the
clock waveform.
Related Information
Related attribute: non_inverted_sources
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Constraints--clock Attributes for Constraints
is_combinational_source_path
is_combinational_source_path {false | true}
Read-write clock attribute. Indicates whether the generated clock was created with the -
combinational option. This information is only used by the write_sdc command.
max_capacitance_clock_path_fall
max_capacitance_clock_path_fall {inf | float}
Read-write clock attribute. Returns the fall max_capacitance value on clock paths.
max_capacitance_clock_path_rise
max_capacitance_clock_path_rise {inf | float}
Read-write clock attribute. Returns the rise max_capacitance value on clock paths.
max_capacitance_data_path_fall
max_capacitance_data_path_fall {inf | float}
Read-write clock attribute. Returns the fall max_capacitance value on data paths.
max_capacitance_data_path_rise
max_capacitance_data_path_rise {inf | float}
Read-write clock attribute. Returns the rise max_capacitance value on data paths.
max_transition_clock_path_fall
max_transition_clock_path_fall {inf | float}
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Constraints--clock Attributes for Constraints
Read-write clock attribute. Returns the fall max_transition value on clock paths.
max_transition_clock_path_rise
max_transition_clock_path_rise {inf | float}
Read-write clock attribute. Returns the rise max_transition value on clock paths.
max_transition_data_path_fall
max_transition_data_path_fall {inf | float}
Read-write clock attribute. Returns the fall max_transition value on data paths.
max_transition_data_path_rise
max_transition_data_path_rise {inf | float}
Read-write clock attribute. Returns the rise max_transition value on data paths.
min_capacitance_clock_path_fall
min_capacitance_clock_path_fall {inf | float}
Read-write clock attribute. Returns the fall min_capacitance value on clock paths.
min_capacitance_clock_path_rise
min_capacitance_clock_path_rise {inf | float}
Read-write clock attribute. Returns the rise min_capacitance value on clock paths.
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Constraints--clock Attributes for Constraints
min_capacitance_data_path_fall
min_capacitance_data_path_fall {inf | float}
Read-write clock attribute. Returns the fall min_capacitance value on data paths.
min_capacitance_data_path_rise
min_capacitance_data_path_rise {inf | float}
Read-write clock attribute. Returns the rise min_capacitance value on data paths.
min_transition_clock_path_fall
min_transition_clock_path_fall {inf | float}
Read-write clock attribute. Returns the fall min_transition value on clock paths.
min_transition_clock_path_rise
min_transition_clock_path_rise {inf | float}
Read-write clock attribute. Returns the rise min_transition value on clock paths.
min_transition_data_path_fall
min_transition_data_path_fall {inf | float}
Read-write clock attribute. Returns the fall min_transition value on data paths.
min_transition_data_path_rise
min_transition_data_path_rise {inf | float}
Read-write clock attribute. Returns the rise min_transition value on data paths.
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Genus Attribute Reference
Constraints--clock Attributes for Constraints
network_latency_fall_max
network_latency_fall_max float
Default: 0.0
Read-write clock attribute. Specifies the maximum (launch) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
Related Information
Related attributes: (hpin) network_latency_fall_max
(pin) network_latency_fall_max
(port) network_latency_fall_max
(clock) network_latency_fall_min
(clock) network_latency_rise_max
(clock) network_latency_rise_min
network_latency_fall_min
network_latency_fall_min float
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Constraints--clock Attributes for Constraints
Default: 0.0
Read-write clock attribute. Specifies the minimum (capture) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
Related Information
Related attributes: (hpin) network_latency_fall_min
(pin) network_latency_fall_min
(port) network_latency_fall_min
(clock) network_latency_fall_max
(clock) network_latency_rise_max
(clock) network_latency_rise_min
network_latency_rise_max
network_latency_rise_max float
Default: 0.0
Read-write clock attribute. Specifies the maximum (launch) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
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Constraints--clock Attributes for Constraints
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
Related Information
Related attributes: (hpin) network_latency_rise_max
(pin) network_latency_rise_max
(port) network_latency_rise_max
(clock) network_latency_fall_max
(clock) network_latency_fall_min
(clock) network_latency_rise_min
network_latency_rise_min
network_latency_rise_min float
Default: 0.0
Read-write clock attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
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Genus Attribute Reference
Constraints--clock Attributes for Constraints
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
Related Information
Related attributes: (hpin) network_latency_rise_min
(pin) network_latency_rise_min
(port) network_latency_rise_min
(clock) network_latency_fall_max
(clock) network_latency_fall_min
(clock) network_latency_rise_max
non_inverted_sources
non_inverted_sources Tcl_list
Read-write clock attribute. Specifies a Tcl list of the ports and pins that are sources of the clock
waveform.
Related Information
Related attribute: inverted_sources
setup_uncertainty
setup_uncertainty delay
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Genus Attribute Reference
Constraints--clock Attributes for Constraints
Default: 0.0
Read-write clock attribute. Specifies the uncertainty of the ideal clock waveform edges (in
picoseconds) in late-mode (setup) timing analysis.
Related Information
Related attributes: (hpin) setup_uncertainty
(pin) setup_uncertainty
(port) setup_uncertainty
(clock) hold_uncertainty
source_latency_early_fall_max
source_latency_early_fall_max float
Default: 0.0
Read-write clock attribute. Specifies the maximum (launch) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
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Genus Attribute Reference
Constraints--clock Attributes for Constraints
Related Information
Related attributes: (hpin) source_latency_early_fall_max
(pin) source_latency_early_fall_max
(port) source_latency_early_fall_max
(clock) source_latency_early_fall_min
(clock) source_latency_early_rise_max
(clock) source_latency_early_rise_min
source_latency_early_fall_min
source_latency_early_fall_min float
Default: 0.0
Read-write clock attribute. Specifies the minimum (capture) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
March 2025 702 Product Version 23.1
Genus Attribute Reference
Constraints--clock Attributes for Constraints
Related Information
Related attributes: (hpin) source_latency_early_fall_min
(pin) source_latency_early_fall_min
(port) source_latency_early_fall_min
(clock) source_latency_early_fall_max
(clock) source_latency_early_rise_max
(clock) source_latency_early_rise_min
source_latency_early_rise_max
source_latency_early_rise_max float
Default: 0.0
Read-write clock attribute. Specifies the maximum (launch) latency (in picoseconds) between the
rise edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
March 2025 703 Product Version 23.1
Genus Attribute Reference
Constraints--clock Attributes for Constraints
Related Information
Related attributes: (hpin) source_latency_early_rise_max
(pin) source_latency_early_rise_max
(port) source_latency_early_rise_max
(clock) source_latency_early_fall_max
(clock) source_latency_early_fall_min
(clock) source_latency_early_rise_min
source_latency_early_rise_min
source_latency_early_rise_min float
Default: 0.0
Read-write clock attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rise edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis. You can specify a Tcl list of four delay values.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
March 2025 704 Product Version 23.1
Genus Attribute Reference
Constraints--clock Attributes for Constraints
Related Information
Related attributes: (hpin) source_latency_early_rise_min
(pin) source_latency_early_rise_min
(port) source_latency_early_rise_min
(clock) source_latency_early_fall_max
(clock) source_latency_early_fall_min
(clock) source_latency_early_rise_max
source_latency_late_fall_max
source_latency_late_fall_max float
Default: 0.0
Read-write clock attribute. Specifies the maximum (launch) latency between the falling edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
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Genus Attribute Reference
Constraints--clock Attributes for Constraints
Related Information
Related attributes: (hpin) source_latency_late_fall_max
(pin) source_latency_late_fall_max
(port) source_latency_late_fall_max
(clock) source_latency_late_fall_min
(clock) source_latency_late_rise_max
(clock) source_latency_late_rise_min
source_latency_late_fall_min
source_latency_late_fall_min float
Default: 0.0
Read-write clock attribute. Specifies the minimum (capture) latency between the fall edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
March 2025 706 Product Version 23.1
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Constraints--clock Attributes for Constraints
Related Information
Related attributes: (hpin) source_latency_late_fall_min
(pin) source_latency_late_fall_min
(port) source_latency_late_fall_min
(clock) source_latency_late_fall_max
(clock) source_latency_late_rise_max
(clock) source_latency_late_rise_min
source_latency_late_rise_max
source_latency_late_rise_max float
Default: 0.0
Read-write clock attribute. Specifies the maximum (launch) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
March 2025 707 Product Version 23.1
Genus Attribute Reference
Constraints--clock Attributes for Constraints
Related Information
Related attributes: (hpin) source_latency_late_rise_max
(pin) source_latency_late_rise_max
(port) source_latency_late_rise_max
(clock) source_latency_late_fall_max
(clock) source_latency_late_fall_min
(clock) source_latency_late_rise_min
source_latency_late_rise_min
source_latency_late_rise_min float
Default: 0.0
Read-write clock attribute. Specifies the minimum (capture) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
March 2025 708 Product Version 23.1
Genus Attribute Reference
Constraints--cost_group Attribute for Constraints
Related Information
Related attributes: (hpin) source_latency_late_rise_min
(pin) source_latency_late_rise_min
(port) source_latency_late_rise_min
(clock) source_latency_late_fall_max
(clock) source_latency_late_fall_min
(clock) source_latency_late_rise_max
cost_group Attribute for Constraints
weight
weight float
Default: 1.0
Read-write cost_group attribute. Specifies the weight value specified using the -weight option of
the define_cost_group command. You can override this value using the set_db command.
Related Information
Set by this command: define_cost_group
exception Attributes for Constraints
comment
cost_group
March 2025 709 Product Version 23.1
Genus Attribute Reference
Constraints--cost_group Attribute for Constraints
max
no_compress
user_priority
comment
comment string
Read-write exception attribute. Specifies the comment tagged to this exception.
Related Information
Set by one of these commands: group_path
set_clock_groups
set_false_path
set_max_delay
set_min_delay
set_multicycle_path
Related attribute: (clock) comment
cost_group
cost_group string
Read-write exception attribute. Specifies the cost group to which a path_group exception belongs.
Related Information
Set by this command: define_cost_group
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Constraints--cost_group Attribute for Constraints
max
max {true | false}
Default: true
Read-write exception attribute. Indicates if the exception was created for a MAX delay analysis.
This attribute is set when you read in SDC constraints.
Genus always performs a MAX delay analysis.
no_compress
no_compress {false | true}
Default: false
Read-write exception attribute. Add control over compression of exceptions. By default, the
exceptions are compressed.
user_priority
user_priority integer
Default: 0
Read-write exception attribute. Specifies the user priority associated with a timing exception.
A timing path can meet the criteria of from-points, through-points, and to-points for a number of
timing exceptions. However, only one exception can be applied to the path. Also, only one
exception of type path_group can be applied to a path.
This attribute is a read-only attribute for path_adjust exceptions. It does not make sense to
associate a priority with path_adjust exceptions because multiple path_adjust exceptions
can be applied to a single path.
March 2025 711 Product Version 23.1
Genus Attribute Reference
Constraints--external_delay Attributes for Constraints
Related Information
Related attribute: priority
external_delay Attributes for Constraints
clock_network_latency_included
clock_network_latency_included {false | true}
Default: false
Read-write external_delay attribute. When set to true, the external_delay delay value (in ps)
includes the clock latency values (in ps).
Normally, Genus constrains paths with both the external_delay value (in ps) and the clock network
latency values (in ps). If this attribute is set to true, Genus ignores the clock network latency values
if an external_delay on the path is already adjusting for the clock latency values.
clock_source_latency_included
clock_source_latency_included {false | true}
Default: false
Read-only external_delay attribute. When set to true, the external_delay delay value (in p.s.)
includes the clock source latency values (in p.s.).
Normally, Genus constrains paths with both the external_delay value (in p.s.) and the clock source
latency values (in p.s.). If this attribute is set to true, Genus ignores the clock source latency values
if an external_delay on the path is already adjusting for the clock latency values.
delay
delay integer_list
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Genus Attribute Reference
Constraints--hnet Attributes for Constraints
Read-write external_delay attribute. Specifies the minimum and maximum rise and fall delay
values of the external_delay constraint.
Genus does not use the minimum values, but storing the minimum values allows Genus to
write out the SDC constraints correctly.
Related Information
Set by these commands: set_input_delay
set_output_delay
hnet Attributes for Constraints
hdl_type
hdl_type {wire | wand | wor | supply0 | supply1}
Default: wire
Read-write hnet attribute. Specifies the type of the net.
resistance
resistance float [float]
Default: no_value no_value
Read-write hnet attribute. Specifies the wire resistance of the hnet in kohms. You can specify two
values: falling and rising resistance values.
March 2025 713 Product Version 23.1
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Constraints--hpin Attributes for Constraints
Related Information
Set by this command: set_resistance
Related attribute: (net) resistance
hpin Attributes for Constraints
break_timing_paths
from_arcs
hold_uncertainty
ideal_driver
ideal_network
is_ideal_network
network_latency_fall_max
network_latency_fall_min
network_latency_rise_max
network_latency_rise_min
setup_uncertainty
slew_max_fall
slew_max_rise
slew_min_fall
slew_min_rise
source_latency_early_fall_max
source_latency_early_fall_min
source_latency_early_rise_max
source_latency_early_rise_min
source_latency_late_fall_max
March 2025 714 Product Version 23.1
Genus Attribute Reference
Constraints--hpin Attributes for Constraints
source_latency_late_fall_min
source_latency_late_rise_max
source_latency_late_rise_min
timing_case_logic_value
to_arcs
break_timing_paths
break_timing_paths {false | true | clock_gating | propagate_slews | set_data_check | set_dont_time |
set_max_delay}
Default: false
Read-write hpin attribute. Controls whether to break the timing path at the specified pin. By default
the timing path is not broken.
Some values are set by the tool.
clock_gating Set by the tool when a set_clock_gating_check constraint is set at the
specified pin.
false Prevents that the timing path is broken at the specified pin and allows the
slew values to propagate through the pin.
propagate_slews Allows the timing path to be broken at the specified pin but does allow slews
to propagate through the pin.
set_data_check Set by the tool when a set_data_check constraint is set at the specified pin.
set_dont_time Set by the tool when a set_dont_time constraint is set at the specified pin.
set_max_delay Set by the tool when a set_max_delay constraint is set from or to the
specified pin.
true Allows the timing path is broken at the specified pin and does not allow
slews to propagate through the pin.
Can be set by the tool when reading SDC constraints.
March 2025 715 Product Version 23.1
Genus Attribute Reference
Constraints--hpin Attributes for Constraints
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_sdc
Related commands: path_adjust
set_path_specification
Related attributes: (pin) break_timing_paths
(port) break_timing_paths
from_arcs
from_arcs arc
Default: no value
Read-only hpin attribute. Returns list of arc objects for which this pin is the starting pin of the timing
arc.
hold_uncertainty
hold_uncertainty { {no_value no_value} | Tcl_list}
Default: no_value no_value
Read-write hpin attribute. Specifies the uncertainty in the arrival times of capturing edges (in
picoseconds) for the clock in early-mode (hold) timing analysis. Genus ignores (does not use) this
value in optimization and timing analysis, but can pass it to downstream tools.
If you specify a single value, then both the rising and falling edge are set to that single value. If you
specify a Tcl list containing two values, then the two values are interpreted as the rising and falling
edge.
March 2025 716 Product Version 23.1
Genus Attribute Reference
Constraints--hpin Attributes for Constraints
Related Information
Related attributes: (clock) hold_uncertainty
(pin) hold_uncertainty
(port) hold_uncertainty
(hpin) setup_uncertainty
ideal_driver
ideal_driver {false | true}
Default: false
Read-write hpin attribute. Indicates if the pin is to be considered an ideal driver.
If the pin is an ideal driver, the timer and optimizer will not attempt to optimize any net driven by this
pin. Therefore, transitions, connect delay, and design rule constraints of this pin are ignored. This
attribute is available on both mapped and unmapped netlists.
Related Information
Affected by this attribute: ideal_seq_async_pins
Related attributes: (pin) ideal_driver
(port) ideal_driver
ideal_network
ideal_network {false | true}
Default: false
Read-write hpin attribute. Sets the network of the specified driver pin to an ideal network. The pin
must be a driving pin. This attribute propagates through combinational gates, and hierarchical
boundaries, unlike the ideal_driver attribute.
March 2025 717 Product Version 23.1
Genus Attribute Reference
Constraints--hpin Attributes for Constraints
Propagation Rules
The propagation of the ideal_network attribute follows these rules:
A pin is treated as ideal if it is either
A pin specified in the object list of the ideal_network attribute.
A driver pin and its cell is ideal.
A load pin attached to an ideal net.
A net is treated as ideal if all its driving cells are ideal.
A combinational cell is treated as ideal if all its input pins are ideal.
A hierarchical pin can propagate the ideal_network attribute.
Propagation stops at the pins where these conditions are not met. These pins are referred to as
network boundary pins, and they are ideal pins.
Related Information
Related attributes: (pin) ideal_network
(port) ideal_network
(hpin) ideal_driver
(pin) ideal_driver
(port) ideal_driver
is_ideal_network
is_ideal_network {false | true}
Default: false
Read-write hpin attribute. Sets the network of the specified driver pin to an ideal network. The pin
must be a driving pin. This attribute propagates through combinational gates, and hierarchical
boundaries, unlike the ideal_driver attribute.
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Constraints--hpin Attributes for Constraints
Propagation Rules
The propagation of the ideal_network attribute follows these rules:
A pin is treated as ideal if it is either
A pin specified in the object list of the ideal_network attribute.
A driver pin and its cell is ideal.
A load pin attached to an ideal net.
A net is treated as ideal if all its driving cells are ideal.
A combinational cell is treated as ideal if all its input pins are ideal.
A hierarchical pin can propagate the ideal_network attribute.
Propagation stops at the pins where these conditions are not met. These pins are referred to as
network boundary pins, and they are ideal pins.
Related Information
Related attributes: (pin) is_ideal_network
(port) is_ideal_network
(hpin) ideal_driver
(pin) ideal_driver
(port) ideal_driver
network_latency_fall_max
network_latency_fall_max float
Default: no_value
Read-write hpin attribute. Specifies the maximum (launch) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
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The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) network_latency_fall_max
(pin) network_latency_fall_max
(port) network_latency_fall_max
(hpin) network_latency_fall_min
(hpin) network_latency_rise_max
(hpin) network_latency_rise_min
network_latency_fall_min
network_latency_fall_min float
Default: no_value
Read-write hpin attribute. Specifies the minimum (capture) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
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Constraints--hpin Attributes for Constraints
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) network_latency_fall_min
(pin) network_latency_fall_min
(port) network_latency_fall_min
(hpin) network_latency_fall_max
(hpin) network_latency_rise_max
(hpin) network_latency_rise_min
network_latency_rise_max
network_latency_rise_max float
Default: no_value
Read-write hpin attribute. Specifies the maximum (launch) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
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Constraints--hpin Attributes for Constraints
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) network_latency_rise_max
(pin) network_latency_rise_max
(port) network_latency_rise_max
(hpin) network_latency_fall_max
(hpin) network_latency_fall_min
(hpin) network_latency_rise_min
network_latency_rise_min
network_latency_rise_min float
Default: no_value
Read-write hpin attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
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Constraints--hpin Attributes for Constraints
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) network_latency_rise_min
(pin) network_latency_rise_min
(port) network_latency_rise_min
(hpin) network_latency_fall_max
(hpin) network_latency_fall_min
(hpin) network_latency_rise_max
setup_uncertainty
setup_uncertainty delay
Default: no_value
Read-write hpin attribute. Specifies the uncertainty of the ideal clock waveform edges (in
picoseconds) in late-mode (setup) timing analysis.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the uncertainty.
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Constraints--hpin Attributes for Constraints
Related Information
Related attributes: (clock) setup_uncertainty
(pin) setup_uncertainty
(port) setup_uncertainty
(hpin) hold_uncertainty
slew_max_fall
slew_max_fall delay
Default: no_value
Read-only hpin attribute. Returns the fall transition time for the hierarchical pin.
slew_max_rise
slew_max_rise delay
Default: no_value
Read-only hpin attribute. Returns the rise transition time for the hierarchical pin.
slew_min_fall
slew_min_fall delay
Default: no_value
Read-only hpin attribute. Returns the minimum fall transition time for the hierarchical pin.
slew_min_rise
slew_min_rise delay
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Constraints--hpin Attributes for Constraints
Default: no_value
Read-only hpin attribute. Returns the minimum rise transition time for the hierarchical pin.
source_latency_early_fall_max
source_latency_early_fall_max float
Default: no_value
Read-write hpin attribute. Specifies the maximum (launch) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_fall_max
(pin) source_latency_early_fall_max
(port) source_latency_early_fall_max
(hpin) source_latency_early_fall_min
(hpin) source_latency_early_rise_max
(hpin) source_latency_early_rise_min
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Constraints--hpin Attributes for Constraints
source_latency_early_fall_min
source_latency_early_fall_min float
Default: no_value
Read-write hpin attribute. Specifies the minimum (capture) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_fall_min
(pin) source_latency_early_fall_min
(port) source_latency_early_fall_min
(hpin) source_latency_early_fall_max
(hpin) source_latency_early_rise_max
(hpin) source_latency_early_rise_min
source_latency_early_rise_max
source_latency_early_rise_max float
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Constraints--hpin Attributes for Constraints
Default: no_value
Read-write hpin attribute. Specifies the maximum (launch) latency (in picoseconds) between the
rise edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_rise_max
(pin) source_latency_early_rise_max
(port) source_latency_early_rise_max
(hpin) source_latency_early_fall_max
(hpin) source_latency_early_fall_min
(hpin) source_latency_early_rise_min
source_latency_early_rise_min
source_latency_early_rise_min float
Default: no_value
Read-write hpin attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rise edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis. You can specify a Tcl list of four delay values.
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Constraints--hpin Attributes for Constraints
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_rise_min
(pin) source_latency_early_rise_min
(port) source_latency_early_rise_min
(hpin) source_latency_early_fall_max
(hpin) source_latency_early_fall_min
(hpin) source_latency_early_rise_max
source_latency_late_fall_max
source_latency_late_fall_max float
Default: no_value
Read-write hpin attribute. Specifies the maximum (launch) latency between the falling edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
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Constraints--hpin Attributes for Constraints
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_late_fall_max
(pin) source_latency_late_fall_max
(port) source_latency_late_fall_max
(hpin) source_latency_early_fall_min
(hpin) source_latency_late_rise_max
(hpin) source_latency_late_rise_min
source_latency_late_fall_min
source_latency_late_fall_min float
Default: no_value
Read-write hpin attribute. Specifies the minimum (capture) latency between the fall edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
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Constraints--hpin Attributes for Constraints
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_late_fall_min
(pin) source_latency_late_fall_min
(port) source_latency_late_fall_min
(hpin) source_latency_early_fall_max
(hpin) source_latency_late_rise_max
(hpin) source_latency_late_rise_min
source_latency_late_rise_max
source_latency_late_rise_max float
Default: no_value
Read-write hpin attribute. Specifies the maximum (launch) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
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Constraints--hpin Attributes for Constraints
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_late_rise_max
(pin) source_latency_late_rise_max
(port) source_latency_late_rise_max
(hpin) source_latency_early_fall_max
(hpin) source_latency_late_fall_min
(hpin) source_latency_late_rise_min
source_latency_late_rise_min
source_latency_late_rise_min float
Default: no_value
Read-write hpin attribute. Specifies the minimum (capture) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
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Constraints--hpin Attributes for Constraints
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_late_rise_min
(pin) source_latency_late_rise_min
(port) source_latency_late_rise_min
(hpin) source_latency_early_fall_max
(hpin) source_latency_late_fall_min
(hpin) source_latency_late_rise_max
timing_case_logic_value
timing_case_logic_value {no_value | 0 | 1 | rise | fall}
Default: no_value
Read-write hpin attribute. Forces the pin to assume the specified logic value or transition value for
timing analysis purposes. You can set this attribute on mapped leaf (combinational) instance pins,
hierarchical boundary pins or outputs pins of sequential cells. The timer automatically sets the logic
constants to their appropriate value.
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Constraints--net Attribute for Constraints
Related Information
Affects these commands: report_timing
syn_generic
syn_map
syn_opt
Related attributes: (pin) timing_case_logic_value
(port) timing_case_logic_value
to_arcs
to arcs arc
Read-only hpin attribute. Returns list of arc objects where the current pin is the termination point of
the arc.
net Attribute for Constraints
resistance
resistance float [float]
Default: no_value no_value
Read-write net attribute. Specifies the wire resistance of the net in kohms. You can specify two
values: falling and rising resistance values.
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Constraints--pin Attributes for Constraints
Related Information
Set by this command: set_resistance
Related attribute: (hnet) resistance
pin Attributes for Constraints
break_timing_paths
from_arcs
hold_uncertainty
ideal_driver
ideal_network
is_ideal_network
network_latency_fall_max
network_latency_fall_min
network_latency_rise_max
network_latency_rise_min
setup_uncertainty
slew_max_fall
slew_max_rise
slew_min_fall
slew_min_rise
source_latency_early_fall_max
source_latency_early_fall_min
source_latency_early_rise_max
source_latency_early_rise_min
source_latency_late_fall_max
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Constraints--pin Attributes for Constraints
source_latency_late_fall_min
source_latency_late_rise_max
source_latency_late_rise_min
timing_case_logic_value
to_arcs
break_timing_paths
break_timing_paths {false | true | clock_gating | propagate_slews | set_data_check | set_dont_time |
set_max_delay}
Default: false
Read-write pin attribute. Controls whether to break the timing path at the specified pin. By default
the timing path is not broken.
Some values are set by the tool.
clock_gating Set by the tool when a set_clock_gating_check constraint is set at the
specified pin.
false Prevents that the timing path is broken at the specified pin and allows the
slew values to propagate through the pin.
propagate_slews Allows the timing path to be broken at the specified pin but does allow slews
to propagate through the pin.
set_data_check Set by the tool when a set_data_check constraint is set at the specified pin.
set_dont_time Set by the tool when a set_dont_time constraint is set at the specified pin.
set_max_delay Set by the tool when a set_max_delay constraint is set from or to the
specified pin.
true Allows the timing path is broken at the specified pin and does not allow
slews to propagate through the pin.
Can be set by the tool when reading SDC constraints.
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Constraints--pin Attributes for Constraints
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_sdc
Related commands: path_adjust
set_path_specification
Related attributes: (hpin) break_timing_paths
(port) break_timing_paths
from_arcs
from_arcs arc
Default: no value
Read-only pin attribute. Returns list of arc objects for which this pin is the starting pin of the timing
arc.
Examples
get_db pin:top/buf1/A .from_arcs
get_db port:top/inc .from_arcs
hold_uncertainty
hold_uncertainty delay
Default: 0.0
Read-write pin attribute. Specifies the uncertainty in the arrival times of capturing edges (in
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Constraints--pin Attributes for Constraints
picoseconds) for the clock in early-mode (hold) timing analysis. Genus ignores (does not use) this
value in optimization and timing analysis, but can pass it to downstream tools.
Related Information
Affected by this attribute: (pin) ideal_driver
Related attributes: (clock) hold_uncertainty
(hpin) hold_uncertainty
(port) hold_uncertainty
(pin) setup_uncertainty
(pin) source_latency_early_fall_max
ideal_driver
ideal_driver {false | true}
Default: false
Read-write pin attribute. Indicates if the pin is to be considered an ideal driver.
If the pin is an ideal driver, the timer and optimizer will not attempt to optimize any net driven by this
pin. Therefore, transitions, connect delay, and design rule constraints of this pin are ignored. This
attribute is available on both mapped and unmapped netlists.
Related Information
Affected by this attribute: ideal_seq_async_pins
Related attributes: (hpin) ideal_driver
(port) ideal_driver
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Constraints--pin Attributes for Constraints
ideal_network
ideal_network {false | true}
Default: false
Read-write pin attribute. Sets the network of the specified driver pin to an ideal network. The pin
must be a driving pin. This attribute propagates through combinational gates, and hierarchical
boundaries, unlike the ideal_driver attribute.
Propagation Rules
The propagation of the ideal_network attribute follows these rules:
A pin is treated as ideal if it is either
A pin specified in the object list of the ideal_network attribute.
A driver pin and its cell is ideal.
A load pin attached to an ideal net.
A net is treated as ideal if all its driving cells are ideal.
A combinational cell is treated as ideal if all its input pins are ideal.
A hierarchical pin can propagate the ideal_network attribute.
Propagation stops at the pins where these conditions are not met. These pins are referred to as
network boundary pins, and they are ideal pins.
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Constraints--pin Attributes for Constraints
Related Information
Affects this attribute: (hpin) propagated_ideal_network
Related attributes: (pin) ideal_network
(port) ideal_network
(hpin) ideal_driver
(pin) ideal_driver
(port) ideal_driver
is_ideal_network
is_ideal_network {false | true}
Default: false
Read-write pin attribute. Sets the network of the specified driver pin to an ideal network. The pin
must be a driving pin. This attribute propagates through combinational gates, and hierarchical
boundaries, unlike the ideal_driver attribute.
Propagation Rules
The propagation of the is_ideal_network attribute follows these rules:
A pin is treated as ideal if it is either
A pin specified in the object list of the ideal_network attribute.
A driver pin and its cell is ideal.
A load pin attached to an ideal net.
A net is treated as ideal if all its driving cells are ideal.
A combinational cell is treated as ideal if all its input pins are ideal.
A hierarchical pin can propagate the ideal_network attribute.
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Constraints--pin Attributes for Constraints
Propagation stops at the pins where these conditions are not met. These pins are referred to as
network boundary pins, and they are ideal pins.
Related Information
Affects this attribute: (hpin) propagated_ideal_network
Related attributes: (pin) is_ideal_network
(port) is_ideal_network
(hpin) ideal_driver
(pin) ideal_driver
(port) ideal_driver
network_latency_fall_max
network_latency_fall_max float
Default: no_value
Read-write pin attribute. Specifies the maximum (launch) latency (in picoseconds) between the fall
edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup checking)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Constraints--pin Attributes for Constraints
Related Information
Related attributes: (clock) network_latency_fall_max
(hpin) network_latency_fall_max
(port) network_latency_fall_max
(pin) network_latency_fall_min
(pin) network_latency_rise_max
(pin) network_latency_rise_min
network_latency_fall_min
network_latency_fall_min float
Default: no_value
Read-write pin attribute. Specifies the minimum (capture) latency (in picoseconds) between the fall
edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup checking)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Related Information
Related attributes: (clock) network_latency_fall_min
(hpin) network_latency_fall_min
(port) network_latency_fall_min
(pin) network_latency_fall_max
(pin) network_latency_rise_max
(pin) network_latency_rise_min
network_latency_rise_max
network_latency_rise_max float
Default: no_value
Read-write pin attribute. Specifies the maximum (launch) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Related Information
Related attributes: (clock) network_latency_rise_max
(hpin) network_latency_rise_max
(port) network_latency_rise_max
(pin) network_latency_fall_max
(pin) network_latency_fall_min
(pin) network_latency_rise_min
network_latency_rise_min
network_latency_rise_min float
Default: no_value
Read-write pin attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Related Information
Related attributes: (clock) network_latency_rise_min
(hpin) network_latency_rise_min
(port) network_latency_rise_min
(pin) network_latency_fall_max
(pin) network_latency_fall_min
(pin) network_latency_rise_max
setup_uncertainty
setup_uncertainty delay
Default: no_value
Read-write pin attribute. Specifies the uncertainty of the ideal clock waveform edges (in
picoseconds) in late-mode (setup) timing analysis.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the uncertainty.
Related Information
Related attributes: (clock) setup_uncertainty
(hpin) setup_uncertainty
(port) setup_uncertainty
(pin) hold_uncertainty
slew_max_fall
slew_max_fall delay
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Default: no_value
Read-only pin attribute. Returns the fall transition time for the pin.
slew_max_rise
slew_max_rise delay
Default: no_value
Read-only pin attribute.Returns the rise transition time for the pin.
slew_min_fall
slew_min_fall delay
Default: no_value
Read-only pin attribute. Returns the minimum fall transition time for the pin.
slew_min_rise
slew_min_rise delay
Default: no_value
Read-only pin attribute. Returns the minimum rise transition time for the pin.
source_latency_early_fall_max
source_latency_early_fall_max float
Default: no_value
Read-write pin attribute. Specifies the maximum (launch) latency (in picoseconds) between the fall
edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
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source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_fall_max
(hpin) source_latency_early_fall_max
(port) source_latency_early_fall_max
(pin) source_latency_early_fall_min
(pin) source_latency_early_rise_max
(pin) source_latency_early_rise_min
source_latency_early_fall_min
source_latency_early_fall_min float
Default: no_value
Read-write pin attribute. Specifies the minimum (capture) latency (in picoseconds) between the fall
edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
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Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_fall_min
(hpin) source_latency_early_fall_min
(port) source_latency_early_fall_min
(pin) source_latency_early_fall_max
(pin) source_latency_early_rise_max
(pin) source_latency_early_rise_min
source_latency_early_rise_max
source_latency_early_rise_max float
Default: no_value
Read-write pin attribute. Specifies the maximum (launch) latency (in picoseconds) between the rise
edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
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no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_rise_max
(hpin) source_latency_early_rise_max
(port) source_latency_early_rise_max
(pin) source_latency_early_fall_max
(pin) source_latency_early_fall_min
(pin) source_latency_early_rise_min
source_latency_early_rise_min
source_latency_early_rise_min float
Default: no_value
Read-write pin attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rise edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis. You can specify a Tcl list of four delay values.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_early_rise_min
(hpin) source_latency_early_rise_min
(port) source_latency_early_rise_min
(pin) source_latency_early_fall_max
(pin) source_latency_early_fall_min
(pin) source_latency_early_rise_max
source_latency_late_fall_max
source_latency_late_fall_max float
Default: no_value
Read-write pin attribute. Specifies the maximum (launch) latency between the falling edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_fall_max
(hpin) source_latency_late_fall_max
(port) source_latency_late_fall_max
(pin) source_latency_late_fall_min
(pin) source_latency_late_rise_max
(pin) source_latency_late_rise_min
source_latency_late_fall_min
source_latency_late_fall_min float
Default: no_value
Read-write pin attribute. Specifies the minimum (capture) latency between the fall edge of the ideal
waveform and the sequential elements in the circuit for late-mode (setup checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_fall_min
(hpin) source_latency_late_fall_min
(port) source_latency_late_fall_min
(pin) source_latency_late_fall_max
(pin) source_latency_late_rise_max
(pin) source_latency_late_rise_min
source_latency_late_rise_max
source_latency_late_rise_max float
Default: no_value
Read-write pin attribute. Specifies the maximum (launch) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_rise_max
(hpin) source_latency_late_rise_max
(port) source_latency_late_rise_max
(pin) source_latency_late_fall_max
(pin) source_latency_late_fall_min
(pin) source_latency_late_rise_min
source_latency_late_rise_min
source_latency_late_rise_min float
Default: no_value
Read-write pin attribute. Specifies the minimum (capture) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_rise_min
(hpin) source_latency_late_rise_min
(port) source_latency_late_rise_min
(pin) source_latency_late_fall_max
(pin) source_latency_late_fall_min
(pin) source_latency_late_rise_max
timing_case_logic_value
timing_case_logic_value {no_value | 0 | 1 | rise | fall}
Default: no_value
Read-write pin attribute. Forces the pin to assume the specified logic value or transition value for
timing analysis purposes. You can set this attribute on mapped leaf (combinational) instance pins,
hierarchical boundary pins or outputs pins of sequential cells. The timer automatically sets the logic
constants to their appropriate value.
Related Information
Affects these commands: report_timing
syn_generic
syn_map
syn_opt
Related attributes: (hpin) timing_case_logic_value
(port) timing_case_logic_value
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to_arcs
to arcs arc
Read-only pin attribute. Returns list of arc objects where the current pin is the termination point of
the arc.
Examples
get_db pin:top/flop6/D .to_arcs
get_db pin:top/scenario4_fnout_brkn_by_mux_select_case_analysis/SE .to_arcs
port Attributes for Constraints
break_timing_paths
drive_resistance_fall_max
drive_resistance_fall_min
drive_resistance_rise_max
drive_resistance_rise_min
driver_from_pin_fall_max
driver_from_pin_fall_min
driver_from_pin_rise_max
driver_from_pin_rise_min
driver_ignore_drc
driver_ignore_drc_by_mode
driver_input_slew_fall_to_fall_max
driver_input_slew_fall_to_fall_min
driver_input_slew_fall_to_rise_max
driver_input_slew_fall_to_rise_min
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driver_input_slew_rise_to_fall_max
driver_input_slew_rise_to_fall_min
driver_input_slew_rise_to_rise_max
driver_input_slew_rise_to_rise_min
driver_pin_fall_max
driver_pin_fall_min
driver_pin_rise_max
driver_pin_rise_min
external_capacitance_max
external_capacitance_min
external_driven_pin_fall
external_driven_pin_rise
external_fanout_load
external_pin_cap
external_resistance
external_wire_cap
external_wire_res
external_wireload_fanout
external_wireload_model
from_arcs
hold_uncertainty
ideal_driver
ideal_network
input_slew_max_fall
input_slew_max_rise
input_slew_min_fall
input_slew_min_rise
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is_ideal_network
min_capacitance
network_latency_fall_max
network_latency_fall_min
network_latency_rise_max
network_latency_rise_min
setup_uncertainty
slew_max_fall
slew_max_rise
slew_min_fall
slew_min_rise
source_latency_early_fall_max
source_latency_early_fall_min
source_latency_early_rise_max
source_latency_early_rise_min
source_latency_late_fall_max
source_latency_late_fall_min
source_latency_late_rise_max
source_latency_late_rise_min
timing_case_logic_value
to_arcs
break_timing_paths
break_timing_paths {false | true | clock_gating | propagate_slews | set_data_check | set_dont_time |
set_max_delay}
Default: false
Read-write port attribute. Controls whether to break the timing path at the specified port. By default
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the timing path is not broken.
Some values are set by the tool.
clock_gating Set by the tool when a set_clock_gating_check constraint is set at the
specified pin.
false Prevents that the timing path is broken at the specified pin and allows the
slew values to propagate through the pin.
propagate_slews Allows the timing path to be broken at the specified pin but does allow slews
to propagate through the pin.
set_data_check Set by the tool when a set_data_check constraint is set at the specified pin.
set_dont_time Set by the tool when a set_dont_time constraint is set at the specified pin.
set_max_delay Set by the tool when a set_max_delay constraint is set from or to the
specified pin.
true Allows the timing path is broken at the specified pin and does not allow
slews to propagate through the pin.
Can be set by the tool when reading SDC constraints.
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_sdc
Related commands: path_adjust
set_path_specification
Related attributes: (hpin) break_timing_paths
(pin) break_timing_paths
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drive_resistance_fall_max
drive_resistance_fall_max float
Default: no_value
Read-write port attribute. Specifies the maximum driving resistance (in kilo Ohms) on the port for
falling transitions.
drive_resistance_fall_min
drive_resistance_fall_min float
Default: no_value
Read-write port attribute. Specifies the minimum driving resistance (in kilo Ohms) on the port for
falling transitions.
drive_resistance_rise_max
drive_resistance_rise_max float
Default: no_value
Read-write port attribute. Specifies the maximum driving resistance (in kilo Ohms) on the port for
rising transitions.
drive_resistance_rise_min
drive_resistance_rise_min float
Default: no_value
Read-write port attribute. Specifies the minimum driving resistance (in kilo Ohms) on the port for
rising transitions.
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driver_from_pin_fall_max
driver_from_pin_fall_max libpin
Read-write port attribute. Returns the driving cell input pin specified for maximim falling delays at
the port.
driver_from_pin_fall_min
driver_from_pin_fall_min libpin
Read-write port attribute. Returns the driving cell input pin specified for minimum falling delays at
the port.
driver_from_pin_rise_max
driver_from_pin_rise_max libpin
Read-write port attribute. Returns the driving cell input pin specified for maximim rising delays at
the port.
driver_from_pin_rise_min
driver_from_pin_rise_min libpin
Read-write port attribute. Returns the driving cell input pin specified for minimum rising delays at
the port.
driver_ignore_drc
driver_ignore_drc {false | true}
Default: false
Read-write port attribute. Controls whether to use design constraints of the external driver.
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driver_ignore_drc_by_mode
driver_ignore_drc_by_mode { {mode_1 {false | true}} {mode_2 {false | true}} ...}
Read-write port attribute. Specifies for each mode whether to use the design constraints of the
external driver.
driver_input_slew_fall_to_fall_max
driver_input_slew_fall_to_fall_max delay
Default: no_value
Read-write port attribute. Specifies the falling input transition for the from_pin of the driving cell,
which is used for the maximum falling delay and transition calculations at the port.
driver_input_slew_fall_to_fall_min
driver_input_slew_fall_to_fall_min delay
Default: no_value
Read-write port attribute. Specifies the falling input transition for the from_pin of the driving cell,
which is used for the minimum falling delay and transition calculations at the port.
driver_input_slew_fall_to_rise_max
driver_input_slew_fall_to_rise_max delay
Default: no_value
Read-write port attribute. Specifies the falling input transition for the from_pin of the driving cell,
which is used for the maximum rising delay and transition calculations at the port.
driver_input_slew_fall_to_rise_min
driver_input_slew_fall_to_rise_min delay
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Default: no_value
Read-write port attribute. Specifies the falling input transition for the from_pin of the driving cell,
which is used for the minimum rising delay and transition calculations at the port.
driver_input_slew_rise_to_fall_max
driver_input_slew_rise_to_fall_max delay
Default: no_value
Read-write port attribute. Specifies the rising input transition for the from_pin of the driving cell,
which is used for the maximum falling delay and transition calculations at the port.
driver_input_slew_rise_to_fall_min
driver_input_slew_rise_to_fall_min delay
Default: no_value
Read-write port attribute. Specifies the rising input transition for the from_pin of the driving cell,
which is used for the minimum falling delay and transition calculations at the port.
driver_input_slew_rise_to_rise_max
driver_input_slew_rise_to_rise_max delay
Default: no_value
Read-write port attribute. Specifies the rising input transition for the from_pin of the driving cell,
which is used for the maximum rising delay and transition calculations at the port.
driver_input_slew_rise_to_rise_min
driver_input_slew_rise_to_rise_min delay
Default: no_value
Read-write port attribute. Specifies the rising input transition for the from_pin of the driving cell,
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which is used for the minimum rising delay and transition calculations at the port.
driver_pin_fall_max
driver_pin_fall_max libpin
Read-write port attribute. Specifies a library pin object for the maximum fall timing mode. The
indicated library pin is assumed to be driving the port externally for the purposes of timing
calculation and design rule checking in this timing mode.
This attribute applies only to input ports.
driver_pin_fall_min
driver_pin_fall_min libpin
Read-write port attribute. Specifies a library pin object for the minimum fall timing mode. The
indicated library pin is assumed to be driving the port externally for the purposes of timing
calculation and design rule checking in this timing mode.
This attribute applies only to input ports. Genus ignores (does not use) the minimum values
in optimization and timing analysis, but can pass them to downstream tools.
driver_pin_rise_max
driver_pin_rise_max libpin
Read-write port attribute. Specifies a library pin object for the maximum rise timing mode. The
indicated library pin is assumed to be driving the port externally for the purposes of timing
calculation and design rule checking in this timing mode.
This attribute applies only to input ports.
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driver_pin_rise_min
driver_pin_rise_min libpin
Read-write port attribute. Specifies a library pin object for the minimum rise timing mode. The
indicated library pin is assumed to be driving the port externally for the purposes of timing
calculation and design rule checking in this timing mode.
This attribute applies only to input ports. Genus ignores (does not use) the minimum values
in optimization and timing analysis, but can pass them to downstream tools.
external_capacitance_max
external_capacitance_max rise_capacitance fall_capacitance
Read-write port attribute. Specifies the maximum allowed external capacitance (in femtoFarad) for
a rise transition and fall transistion at this port, respectively.
external_capacitance_min
external_capacitance_min rise_capacitance fall_capacitance
Read-write port attribute. Specifies the minimum allowed external capacitance (in femtoFarad) for
a rise transition and fall transistion at this port, respectively.
external_driven_pin_fall
external_driven_pin_fall string
Read-write port attribute. Specifies the input pin of the external object that is driven in case of a fall
transition. This information is useful for fall slope sensitivity modeling on output ports. You must
specify a library pin object.
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Constraints--port Attributes for Constraints
Related information
Related attribute: external_driven_pin_rise
external_driven_pin_rise
external_driven_pin_rise string
Read-write port attribute. Specifies the input pin of the external object that is driven in case of a
rise transition. This information is useful for rise slope sensitivity modeling on output ports. You
must specify a library pin object.
Related information
Related attribute: external_driven_pin_fall
external_fanout_load
external_fanout_load {no_value | float}
Default: no_value
Read-write port attribute. Indicates the fanout load seen by the port outside the design. This
information is used by the maximum and minimum fanout design rules. The resolution is 1/1000.
Related information
Related attributes: max_fanout
external_pin_cap
external_pin_cap rise_capacitance fall_capacitance
Default: no_value no_value
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Read-write port attribute. Indicates the external capacitive load (in femtofarad) due to pins that are
connected to this port.
Related information
Related attributes: external_wire_cap
external_wire_res
external_wireload_fanout
external_wireload_model
external_resistance
external_resistance { {no_value no_value no_value no_value} | Tcl_list}
Default: {no_value no_value no_value no_value}
Read-write port attribute. Specifies the resistance of the external driver in kilo ohm for a minimum
rise, minimum fall, maximum rise and maximum fall transition. The resolution is 1/1000.
If you specify different resistance values, you must do so as a Tcl list (within braces).
Genus ignores (does not use) the minimum values in optimization and timing analysis, but
they can be passed to downstream tools.
external_wire_cap
external_wire_cap {no_value | float}
Default: no_value
Read-write port attribute. Specifies the capacitance (in femtofarads) of the external wire connected
to this port. The resolution is 1/10.
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Related information
Related attributes: external_pin_cap
external_wire_res
external_wireload_fanout
external_wireload_model
external_wire_res
external_wire_res {no_value | float}
Default: no_value
Read-write port attribute. Specifies the resistance of the external wire connected to this port in kilo
ohm. The resolution is 1/1000.
Related information
Related attributes: external_pin_cap
external_wire_cap
external_wireload_fanout
external_wireload_model
external_wireload_fanout
external_wireload_fanout {no_value | integer}
Default: no_value
Read-write port attribute. Specifies the number of fanouts for this port outside the design.
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Related information
Related attributes: external_pin_cap
external_wire_cap
external_wire_res
external_wireload_model
external_wireload_model
external_wireload_model string
Read-write port attribute. Specifies the wire-load model to use for this port.
Related information
Affected by these attributes: force_wireload
Related attributes: external_pin_cap
external_resistance
external_wire_cap
external_wire_res
external_wireload_fanout
from_arcs
from_arcs arc
Default: no value
Read-only port attribute. Returns list of arc objects for which this pin is the starting pin of the timing
arc.
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Examples
get_db pin:top/buf1/A .from_arcs
get_db port:top/inc .from_arcs
hold_uncertainty
hold_uncertainty delay
Default: 0.o
Read-write port attribute. Specifies the uncertainty in the arrival times of capturing edges (in
picoseconds) for the clock in early-mode (hold) timing analysis.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
Related Information
Affected by this attribute: (port) ideal_driver
Related attributes: (clock) hold_uncertainty
(hpin) hold_uncertainty
(pin) hold_uncertainty
(port) setup_uncertainty
ideal_driver
ideal_driver {false | true}
Default: false
Read-write port attribute. Indicates if the port is to be considered an ideal driver. If the port is an
ideal driver, the timer and optimizer will not attempt to optimize any net driven by this pin. Therefore,
transitions, connect delay, and design rule constraints for this pin are ignored.
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This attribute is available on both mapped and unmapped netlists.
This attribute does not propagate to the fanout drivers.
Related Information
Affected by this attribute: ideal_seq_async_pins
Related attributes: (hpin) ideal_driver
(pin) ideal_driver
ideal_network
ideal_network {false | true}
Default: false
Read-write port attribute. Sets the network of the specified driver port to an ideal network. The port
must be a driving port. This attribute propagates through combinational gates, and hierarchical
boundaries, unlike the ideal_driver attribute.
If an ideal signal arrives at a multi-input instance, the output of that instance is considered ideal if all
inputs of the instance are ideal.
Related Information
Affects this attribute: (pin) propagated_ideal_network
Related attributes: (hpin) ideal_network
(pin) ideal_driver
(hpin) ideal_driver
(pin) ideal_driver
(port) ideal_driver
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input_slew_max_fall
input_slew_max_fall float
Default: no_value
Read-write port attribute. Specifies the maximum falling slew for the input port.
Related Information
Set by this command: set_input_transition
input_slew_max_rise
input_slew_max_rise float
Default: no_value
Read-write port attribute. Specifies the maximum rising slew for the input port.
Related Information
Set by this command: set_input_transition
input_slew_min_fall
input_slew_min_fall float
Default: no_value
Read-write port attribute. Specifies the minimum falling slew for the input port.
Related Information
Set by this command: set_input_transition
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input_slew_min_rise
input_slew_rise_min float
Default: no_value
Read-write port attribute. Specifies the minimum rising slew for the input port.
Related Information
Set by this command: set_input_transition
is_ideal_network
is_ideal_network {false | true}
Default: false
Read-write port attribute. Sets the network of the specified driver port to an ideal network. The port
must be a driving port. This attribute propagates through combinational gates, and hierarchical
boundaries, unlike the ideal_driver attribute.
If an ideal signal arrives at a multi-input instance, the output of that instance is considered ideal if all
inputs of the instance are ideal.
Related Information
Affects this attribute: (pin) propagated_ideal_network
Related attributes: (hpin) is_ideal_network
(pin) is_ideal_network
(hpin) ideal_driver
(pin) ideal_driver
(port) ideal_driver
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min_capacitance
min_capacitance float
Default: no_value
Read-write port attribute. Specifies the minimum capacitance in femtofarads that an output port can
drive.
network_latency_fall_max
network_latency_fall_max float
Default: no_value
Read-write port attribute. Specifies the maximum (launch) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Related Information
Related attributes: (clock) network_latency_fall_max
(hpin) network_latency_fall_max
(pin) network_latency_fall_max
(port) network_latency_fall_min
(port) network_latency_rise_max
(port) network_latency_rise_min
network_latency_fall_min
network_latency_fall_min float
Default: no_value
Read-write port attribute. Specifies the minimum (capture) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Related Information
Related attributes: (clock) network_latency_fall_min
(hpin) network_latency_fall_min
(pin) network_latency_fall_min
(port) network_latency_fall_max
(port) network_latency_rise_max
(port) network_latency_rise_min
network_latency_rise_max
network_latency_rise_max float
Default: no_value
Read-write port attribute. Specifies the maximum (launch) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Related Information
Related attributes: (clock) network_latency_rise_max
(hpin) network_latency_rise_max
(pin) network_latency_rise_max
(port) network_latency_fall_max
(port) network_latency_fall_min
(port) network_latency_rise_min
network_latency_rise_min
network_latency_rise_min float
Default: no_value
Read-write port attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rising edge of the ideal waveform and the sequential elements in the circuit for late-mode (setup
checking) timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
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Constraints--port Attributes for Constraints
Related Information
Related attributes: (clock) network_latency_rise_min
(hpin) network_latency_rise_min
(pin) network_latency_rise_min
(port) network_latency_fall_max
(port) network_latency_fall_min
(port) network_latency_rise_max
setup_uncertainty
setup_uncertainty delay
Default: no_value
Read-write port attribute. Specifies the uncertainty of the ideal clock waveform edges (in
picoseconds) in late-mode (setup) timing analysis.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the uncertainty.
Related Information
Related attributes: (clock) setup_uncertainty
(hpin) setup_uncertainty
(pin) setup_uncertainty
(port) hold_uncertainty
(port) ideal_driver
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slew_max_fall
slew_max_fall delay
Default: no_value
Read-only port attribute. Returns the fall transition time for the port.
slew_max_rise
slew_max_rise delay
Default: no_value
Read-only port attribute. Returns the rise transition time for the port.
slew_min_fall
slew_min_fall delay
Default: no_value
Read-only port attribute.Returns the minimum fall transition time for the port.
slew_min_rise
slew_min_rise delay
Default: no_value
Read-only port attribute. Returns the minimum rise transition time for the port.
source_latency_early_fall_max
source_latency_early_fall_max float
Default: no_value
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Read-write port attribute. Specifies the maximum (launch) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_fall_max
(hpin) source_latency_early_fall_max
(pin) source_latency_early_fall_max
(port) source_latency_early_fall_min
(port) source_latency_early_rise_max
(port) source_latency_early_rise_min
source_latency_early_fall_min
source_latency_early_fall_min float
Default: no_value
Read-write port attribute. Specifies the minimum (capture) latency (in picoseconds) between the
fall edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
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source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_fall_min
(hpin) source_latency_early_fall_min
(pin) source_latency_early_fall_min
(port) source_latency_early_fall_max
(port) source_latency_early_rise_max
(port) source_latency_early_rise_min
source_latency_early_rise_max
source_latency_early_rise_max float
Default: no_value
Read-write port attribute. Specifies the maximum (launch) latency (in picoseconds) between the
rise edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
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Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_rise_max
(hpin) source_latency_early_rise_max
(pin) source_latency_early_rise_max
(port) source_latency_early_fall_max
(port) source_latency_early_fall_min
(port) source_latency_early_rise_min
source_latency_early_rise_min
source_latency_early_rise_min float
Default: no_value
Read-write port attribute. Specifies the minimum (capture) latency (in picoseconds) between the
rise edge of the ideal waveform and the sequential elements in the circuit for early-mode (hold)
timing analysis. You can specify a Tcl list of four delay values.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus ignores this value in optimization and timing analysis, but can pass it to downstream
tools.
In addition to numeric delay values, this attribute accepts the special string no_value to indicate that
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no change should be made to the latency.
Related Information
Related attributes: (clock) source_latency_early_rise_min
(hpin) source_latency_early_rise_min
(pin) source_latency_early_rise_min
(port) source_latency_early_fall_max
(port) source_latency_early_fall_min
(port) source_latency_early_rise_max
source_latency_late_fall_max
source_latency_late_fall_max float
Default: no_value
Read-write port attribute. Specifies the maximum (launch) latency between the falling edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_fall_max
(hpin) source_latency_late_fall_max
(pin) source_latency_late_fall_max
(port) source_latency_late_fall_min
(port) source_latency_late_rise_max
(port) source_latency_late_rise_min
source_latency_late_fall_min
source_latency_late_fall_min float
Default: no_value
Read-write port attribute. Specifies the minimum (capture) latency between the fall edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_fall_min
(hpin) source_latency_late_fall_min
(pin) source_latency_late_fall_min
(port) source_latency_late_fall_max
(port) source_latency_late_rise_max
(port) source_latency_late_rise_min
source_latency_late_rise_max
source_latency_late_rise_max float
Default: no_value
Read-write port attribute. Specifies the maximum (launch) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_rise_max
(hpin) source_latency_late_rise_max
(pin) source_latency_late_rise_max
(port) source_latency_late_fall_max
(port) source_latency_late_fall_min
(port) source_latency_late_rise_min
source_latency_late_rise_min
source_latency_late_rise_min float
Default: no_value
Read-write port attribute. Specifies the minimum (capture) latency between the rising edge of the
ideal waveform and the sequential elements in the circuit for late-mode (setup checking) timing
analysis.
The total latency (or delay) for a clock edge is the sum of the "network" and "source" latencies. The
source latency is the delay between the ideal clock waveform and the point in the circuit where the
clock waveform is applied (such as the clock input port of the design). The network latency is the
delay of the clock network between the point where the clock has been defined and an actual
sequential element.
Genus computes timing constraints for a path using the maximum clock latency at the launching
clock edge and the minimum clock latency at the capturing clock edge. This produces the tightest
possible timing constraints.
Positive values for latency indicate that the edge arrives later in time. For minimum (capture) latency
edges, positive latency values produce looser timing constraints. For maximum (capture) latency
edges, positive latency values produce tighter timing constraints.
In addition to a numeric delay value, this attribute accepts the special string no_value to indicate
that no change should be made to the latency.
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Related Information
Related attributes: (clock) source_latency_late_rise_min
(hpin) source_latency_late_rise_min
(pin) source_latency_late_rise_min
(port) source_latency_late_fall_max
(port) source_latency_late_fall_min
(port) source_latency_late_rise_max
timing_case_logic_value
timing_case_logic_value {no_value | 0 | 1 | rise | fall}
Default: no_value
Read-write port attribute. Forces the port to assume the specified logic value or transition value for
timing analysis purposes. You can set this attribute on input ports.
Related Information
Affects these commands: report_timing
syn_generic
syn_map
syn_opt
Related attributes: (hpin) timing_case_logic_value
(pin) timing_case_logic_value
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to_arcs
to arcs arc
Read-only port attribute. Returns list of arc objects where the current pin is the termination point of
the arc.
Examples
get_db pin:top/flop6/D .to_arcs
get_db pin:top/scenario4_fnout_brkn_by_mux_select_case_analysis/SE .to_arcs
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Multi-Mode Multi-Corner (MMMC) Flow
17
Multi-Mode Multi-Corner (MMMC) Flow
The chapter describes the attributes of the following object types:
analysis_view Attributes for MMMC Flow
constraint_mode Attributes for MMMC Flow
delay_corner Attributes for MMMC Flow
library_set Attributes for MMMC Flow
opcond Attributes for MMMC Flow
rc_corner Attributes for MMMC Flow
timing_condition Attributes for MMMC Flow
analysis_view Attributes for MMMC Flow
constraint_mode
delay_corner
design
is_active
is_dynamic
is_hold
is_hold_default
is_leakage
is_setup
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is_setup_default
latency_file
path_adjust_file
constraint_mode
constraint_mode constraint_mode
Read-only analysis_view attribute. Returns the timing constraint mode for this analysis_view.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow
.constraint_modeconstraint_mode:dtmf_recvr_core/functional_wcl_slow
delay_corner
delay_corner delay_corner
Read-only analysis_view attribute. Returns the delay_corner for this analysis_view.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow
.delay_cornerdelay_corner:dtmf_recvr_core/delay_corner_wcl_slow
design
design design
Read-only analysis_view attribute. Returns the design that this analysis_view belongs.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .designdesign:dtmf_recvr_core
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Multi-Mode Multi-Corner (MMMC) Flow--analysis_view Attributes for MMMC Flow
is_active
is_active {false | true}
Default: false
Read-only analysis_view attribute. Indicates whether the analysis view is active for setup or hold
analysis.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .is_activetrue
is_dynamic
is_dynamic {false | true}
Read-only analysis_view attribute. Indicates whether the analysis_view is for dynamic power
analysis.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .is_dynamicfalse
is_hold
is_hold {false | true}
Read-only analysis_view attribute. Indicates whether the analysis_view is active for hold analysis.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .is_holdfalse
March 2025 789 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--analysis_view Attributes for MMMC Flow
is_hold_default
is_hold_default {false | true}
Read-only analysis_view attribute. Indicates whether the analysis_view is the default view for hold
analysis.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .is_hold_defaultfalse
is_leakage
is_leakage {false | true}
Read-only analysis_view attribute. Indicates whether the analysis view is for leakage power
analysis.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .is_leakagefalse
is_setup
is_setup {false | true}
Read-only analysis_view attribute. Indicates whether the analysis view is active for setup analysis.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .is_setuptrue
is_setup_default
is_setup_default {false | true}
March 2025 790 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--constraint_mode Attributes for MMMC Flow
Read-only analysis_view attribute. Indicates whether the analysis view is the default view for setup
analysis.
Example
genus@root:> get_db analysis_view:dtmf_recvr_core/view_wcl_slow .is_setup_defaulttrue
latency_file
latency_file string
Read-only analysis_view attribute. Returns the file that contains the clock latency constraints for
this analysis view.
path_adjust_file
path_adjust_file string
Read-only analysis_view attribute. Returns the file that contains the path_adjust constraints for this
analysis view.
constraint_mode Attributes for MMMC Flow
design
ilm_sdc_files
is_active
is_dynamic
is_hold
is_leakage
is_setup
sdc_files
tcl_vars
March 2025 791 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--constraint_mode Attributes for MMMC Flow
design
design design
Read-only constraint_mode attribute. Returns the design to which this constraint_mode belongs.
Example
genus@root:> get_db constraint_mode:dtmf_recvr_core/funct_wcl_slow .designdesign:dtmf_recvr_core
ilm_sdc_files
ilm_sdc_files list_of_sdc_files
Read-only constraint_mode attribute. Returns the list of ILM SDC files associated with this
constraint mode.
Related Information
Set by this command: create_constraint_mode
is_active
is_active {false | true}
Default: false
Read-only constraint_mode attribute. Specifies whether constraint mode is used by a setup or hold
active analysis view.
Example
genus@root:> get_db constraint_mode:dtmf_recvr_core/functional_wcl_slow .is_activetrue
March 2025 792 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--constraint_mode Attributes for MMMC Flow
is_dynamic
is_dynamic {false | true}
Default: false
Read-only constraint_mode attribute. Indicates whether the constraint mode is used by a power
dynamic active analysis_view.
is_hold
is_hold {false | true}
Read-only constraint_mode attribute. Indicates whether the constraint_mode is used by a hold
active analysis view.
Example
genus@root:> get_db constraint_mode:dtmf_recvr_core/funct_wcl_slow .is_hold false
is_leakage
is_leakage {false | true}
Default: false
Read-only constraint_mode attribute. Indicates whether the constraint mode is used by a power
leakage active analysis_view.
is_setup
is_setup {false | true}
Read-only constraint_mode attribute. Indicates whether the constraint_mode is used by a setup
active analysis view.
March 2025 793 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--delay_corner Attributes for MMMC Flow
Example
genus@root:> get_db constraint_mode:dtmf_recvr_core/functional_wcl_slow .is_setup true
sdc_files
sdc_files list_of_sdc_files
Read-only constraint_mode attribute. Returns the list of SDC files associated with this constraint
mode.
Example
genus@root:> get_db constraint_mode:dtmf_recvr_core/funct_wcl_slow .sdc_files
../Constraints/mmmc/dtmf_recvr_core_gate_slow.sdc
Related Information
Set by this command: create_constraint_mode
tcl_vars
tcl_vars list_of_variables
Read-only constraint_mode attribute. Returns the list of Tcl variables set for this constraint mode.
delay_corner Attributes for MMMC Flow
design
early_irdrop_files
early_rc_corner
early_temperature_files
March 2025 794 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--delay_corner Attributes for MMMC Flow
early_timing_condition
early_timing_condition_string
is_dynamic
is_hold
is_leakage
is_setup
is_si_enabled
late_irdrop_files
late_rc_corner
late_temperature_files
late_timing_condition
late_timing_condition_string
mmmc_design
design
design design
Read-only delay_corner attribute. Returns the design to which this delay_corner belongs.
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow .designdesign:dtmf_recvr_core
early_irdrop_files
early_irdrop_files files
Read-only delay_corner attribute. Returns the name of the IR drop file to apply for the early delay
calculation for this delay corner.
March 2025 795 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--delay_corner Attributes for MMMC Flow
Related Information
Set by this command: create_delay_corner
early_rc_corner
early_rc_corner rc_corner
Read-only delay_corner attribute. Returns the RC corner object to associate with the early delay
corner.
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow
.early_rc_cornerrc_corner:rc_corner
Related Information
Set by this command: create_delay_corner
early_temperature_files
early_temperature_files file
Read-only delay_corner attribute. Returns the name of the temperature file for temperature-aware
delay calculation for an early corner.
Related Information
Set by this command: create_delay_corner
March 2025 796 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--delay_corner Attributes for MMMC Flow
early_timing_condition
early_timing_condition timing_condition
Read-only delay_corner attribute. Returns the early timing conditions associated with the specified
power index.
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow .late_timing_condition
timing_condition:timing_cond_wcl_slow
Related Information
Set by this command: create_delay_corner
early_timing_condition_string
early_timing_condition_string list_of_condition_pairs
Read-only delay_corner attribute. Returns the early timing conditions for each power domain using
the following format for each pair:
(power_domain, timing_condition)
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow
.early_timing_condition_string
timing_cond_wcl_slow
Related Information
Set by this command: create_delay_corner
March 2025 797 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--delay_corner Attributes for MMMC Flow
is_dynamic
is_dynamic {false | true}
Default: false
Read-only delay_corner attribute. Indicates whether the constraint mode is used by a power
dynamic active analysis_view.
is_hold
is_hold {false | true}
Read-write delay_corner attribute. Indicates whether the delay_corner is used by a hold active
analysis view.
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow .is_hold
false
is_leakage
is_leakage {false | true}
Default: false
Read-only delay_corner attribute. Indicates whether the delay corner is used by a power leakage
active analysis_view.
is_setup
is_setup {false | true}
Read-write delay_corner attribute. Indicates whether the delay_corner is used by a setup active
analysis view.
March 2025 798 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--delay_corner Attributes for MMMC Flow
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow .is_setup
true
is_si_enabled
is_si_enabled string
Read-only delay_corner attribute. Indicates whethre SI analysis was performed on the
delay_corner.
Related Information
Set by this command: create_delay_corner
late_irdrop_files
late_irdrop_files files
Read-only delay_corner attribute. Returns the name of the IR drop files to apply for the late delay
calculation for this delay corner.
Related Information
Set by this command: create_delay_corner
late_rc_corner
late_rc_corner rc_corner
Read-only delay_corner attribute. Returns the RC corner object to associate with the late delay
corner.
March 2025 799 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--delay_corner Attributes for MMMC Flow
Example
get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow .late_rc_corner rc_corner:rc_corner
Related Information
Set by this command: create_delay_corner
late_temperature_files
late_temperature_files files
Read-only delay_corner attribute. Returns the name of the temperature files for temperature-aware
delay calculation for an late corner.
Related Information
Set by this command: create_delay_corner
late_timing_condition
late_timing_condition timing_condition
Read-only delay_corner attribute. Returns the late timing conditions associated with the specified
power index.
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow .late_timing_condition
timing_condition:timing_cond_wcl_slow
Related Information
Set by this command: create_delay_corner
March 2025 800 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--library_set Attributes for MMMC Flow
late_timing_condition_string
late_timing_condition_string list_of_condition_pairs
Read-only delay_corner attribute. Returns the late timing conditions for each power domain using
the following format for each pair:
(power_domain, timing_condition)
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Example
genus@root:> get_db delay_corner:dtmf_recvr_core/delay_corner_wcl_slow .late_timing_condition_string
timing_cond_wcl_slow
Related Information
Set by this command: create_delay_corner
mmmc_design
mmmc_design mmmc_design
Read-only delay_corner attribute. Returns the mmmc design that this constraint_mode belongs to.
library_set Attributes for MMMC Flow
aocv_files
libraries
library_files
si_files
March 2025 801 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--library_set Attributes for MMMC Flow
socv_files
aocv_files
aocv_files list_of_files
Read-only library_set attribute. Returns the list of Advanced On-Chip Variation (AOCV) files that
were read in.
Related Information
Set by this command: create_library_set
libraries
libraries list_of_library_objects
Read-only library_set attribute. Returns the list of library objects created after the libraries were
read in.
Example
genus@root:> get_db library_set:wcl_slow .libraries
library:wcl_slow/slow library:wcl_slow/PLL_worst library:wcl_slow/CDK_S128x16
library:wcl_slow/CDK_S256x16 library:wcl_slow/CDK_R512x16
library_files
library_files list_of_files
Read-only library_set attribute. Returns the names of the libraries specified with the -timing
option of the create_library_set command.
March 2025 802 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--library_set Attributes for MMMC Flow
Example
genus@root:> get_db library_set:wcl_slow .library_files
../LIB/gsclib045_v3.5/timing/slow.lib ../LIB/macro_libs/pllclk_slow.lib
../LIB/macro_libs/CDK_S128x16.lib ../LIB/macro_libs/CDK_S256x16.lib
../LIB/macro_libs/CDK_R512x16.lib
Related Information
Set by this command: create_library_set
si_files
si_files list_of_files
Read-only library_set attribute. Returns the list of Signal Integrity (SI) library files that were read
in.
Related Information
Set by this command: create_library_set
socv_files
socv_files list_of_files
Read-only library_set attribute. Returns the list of Statistical On-Chip Variation (SOCV) files that
were read in.
Related Information
Set by this command: create_library_set
March 2025 803 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--opcond Attributes for MMMC Flow
opcond Attributes for MMMC Flow
is_hold
is_setup
is_virtual
library_file
process
temperature
tree_type
is_hold
is_hold {false | true}
Read-only opcond attribute. Indicates whether the opcond is used by a hold active analysis view.
is_setup
is_setup {false | true}
Read-only opcond attribute. Indicates whether the opcond is used by a setup active analysis view.
is_virtual
is_virtual {true | false}
Read-only opcond attribute. Indicates whether the opcond is created by the user.
library_file
library_file file
March 2025 804 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--opcond Attributes for MMMC Flow
Read-only opcond attribute. Returns the name of the library specified with the -library_file option
of the create_op_cond command.
Related Information
Set by this command: create_opcond
process
process float
Read-only opcond attribute. Specifies the process value of the opcond.
Related Information
Set by this command: create_opcond
temperature
temperature string
Read-only opcond attribute. Specifies the temperature of the opcond.
Related Information
Set by this command: create_opcond
tree_type
tree_type {best_case | balanced_case | worst_case | binary_case}
Read-only opcond attribute. Specifies the tree_type of the opcond.
March 2025 805 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--rc_corner Attributes for MMMC Flow
rc_corner Attributes for MMMC Flow
post_route_cap
post_route_clock_cap
post_route_clock_cross_cap
post_route_clock_res
post_route_cross_cap
post_route_res
pre_route_cap
pre_route_clock_cap
pre_route_clock_res
pre_route_res
qrc_tech_file
temperature
post_route_cap
post_route_cap {capFactor1 capFactor2 capFactor3}
Read-only rc_corner attribute. Returns the capacitance scale factor(s) for RC extraction in post-
route mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
March 2025 806 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--rc_corner Attributes for MMMC Flow
Example
genus@root:> get_db rc_corner:rc_corner .post_route_cap
1.0 1.0 1.0
Related Information
Set by this command: create_rc_corner
post_route_clock_cap
post_route_clock_cap {capFactor1 capFactor2 capFactor3}
Read-only rc_corner attribute. Returns the scale factor(s) for the capacitance of clock nets for RC
extraction in post-route mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Example
genus@root:> get_db rc_corner:rc_corner .post_route_clock_cap
1.0 1.0 1.0
Related Information
Set by this command: create_rc_corner
March 2025 807 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--rc_corner Attributes for MMMC Flow
post_route_clock_cross_cap
post_route_clock_cross_cap {<capFactor1 capFactor2 capFactor3>}
Read-only rc_corner attribute. Returns the scale factor(s) for the coupling capacitance of clock
nets for RC extraction in post-route mode. The attribute value can contain one, two, or three
numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
post_route_clock_res
post_route_clock_res {resFactor1 resFactor2 resFactor3}
Read-only rc_corner attribute. Returns the scale factor(s) for the resistance of clock nets for RC
extraction in post-route mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Example
genus@root:> get_db rc_corner:rc_corner .post_route_clock_res
1.0 1.0 1.0
March 2025 808 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--rc_corner Attributes for MMMC Flow
Related Information
Set by this command: create_rc_corner
post_route_cross_cap
post_route_cross_cap {capFactor1 capFactor2 capFactor3
Read-only rc_corner attribute. Returns the scale factor(s) for coupling capacitances for RC
extraction in post-route mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Example
genus@root:> get_db rc_corner:rc_corner .post_route_cross_cap
1.0 1.0 1.0
Related Information
Set by this command: create_rc_corner
post_route_res
post_route_res {resFactor1 resFactor2 resFactor3}
Read-only rc_corner attribute. Returns the resistance scale factor(s) for RC extraction in post-route
mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
March 2025 809 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--rc_corner Attributes for MMMC Flow
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Related Information
Set by this command: create_rc_corner
pre_route_cap
pre_route_cap {capFactor1 capFactor2 capFactor3}
Read-only rc_corner attribute. Returns the capacitance scale factor(s) for RC extraction in pre-
route mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Related Information
Set by this command: create_rc_corner
pre_route_clock_cap
pre_route_clock_cap {capFactor1 capFactor2 capFactor3}
Read-only rc_corner attribute. Returns the scale factor(s) for the capacitance of clock nets for RC
extraction in pre-route mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
March 2025 810 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--rc_corner Attributes for MMMC Flow
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Related Information
Set by this command: create_rc_corner
pre_route_clock_res
pre_route_clock_res {resFactor1 resFactor2 resFactor3}
Read-only rc_corner attribute. Returns the scale factor(s) for the resistance of clock nets for RC
extraction in pre-route mode. The attribute value can contain one, two, or three numbers.
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Related Information
Set by this command: create_rc_corner
pre_route_res
pre_route_res {resFactor1 resFactor2 resFactor3}
Read-only rc_corner attribute. Returns the resistance scale factor(s) for RC extraction in pre-route
mode. The attribute value can contain one, two, or three numbers.
March 2025 811 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--rc_corner Attributes for MMMC Flow
If one value was returned, the scale factor applies to the low-level effort. A scale factor value
of 1 is used for the medium and high-level efforts by default.
If two values are returned, the first value is used for the low-level effort and the second value is
used for medium-level effort. Scale factor value of 1 is used for the high-level effort by default.
If three values were returned, the first value is used for the low-level effort, the second value is
used for the medium-level effort, and the third value is used for the high-level effort.
Related Information
Set by this command: create_rc_corner
qrc_tech_file
qrc_tech_file file
Read-only rc_corner attribute. Returns the QRC tech file of the rc_corner.
Related Information
Set by this command: create_rc_corner
temperature
temperature string
Read-only rc_corner attribute. Returns the temperature of the rc_corner.
Related Information
Set by this command: create_rc_corner
March 2025 812 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--timing_condition Attributes for MMMC Flow
timing_condition Attributes for MMMC Flow
library_sets
library_sets library_sets
Read-only timing_condition attribute. Returns the library sets for this timing condition.
Example
genus@root:> get_db timing_condition:timing_cond_wcl_slow .library_sets
library_set:wcl_slow
Related Information
Set by this command: create_timing_condition
opcond
opcond opcond_object
Read-only timing_condition attribute. Returns the opcond object created for the operating
condition of this timing condition.
Example
genus@root:> get_db timing_condition:timing_cond_wcl_slow .opcond
opcond:op_cond_wcl_slow
March 2025 813 Product Version 23.1
Genus Attribute Reference
Multi-Mode Multi-Corner (MMMC) Flow--timing_condition Attributes for MMMC Flow
Related Information
Set by this command: create_timing_condition
opcond_library
opcond_library library_name
Read-only timing_condition attribute. Returns the name of the library in which the operating
condition for this timing condition is defined.
Related Information
Set by this command: create_timing_condition
March 2025 814 Product Version 23.1
Genus Attribute Reference
Clock Gating
18
Clock Gating
clock_gate_enable_pin clock_gate_enable_polarity clock_gating_integrated_cell
is_clock_gate_clock is_clock_gate_enable is_clock_gate_obs
is_clock_gate_out is_clock_gate_reset is_clock_gate_test
is_integrated_clock_gating is_synthesis_clock_gate lp_clock_gating_method
lp_clock_gating_add_obs_port lp_clock_gating_auto_cost_group_initial_target lp_clock_gating_auto_cost_gro
lp_clock_gating_auto_path_adjust lp_clock_gating_auto_path_adjust_fixed_delay lp_clock_gating_auto_path_adj
lp_clock_gating_auto_path_adjust_multiplier lp_clock_gating_cell lp_clock_gating_connect_test_c
lp_clock_gating_connect_test_consider_constant_enabled_as_connected lp_clock_gating_control_point lp_clock_gating_coverage_effo
lp_clock_gating_exceptions_aware lp_clock_gating_exclude lp_clock_gating_extract_commo
lp_clock_gating_gated_clock_gates lp_clock_gating_gated_flops lp_clock_gating_hierarchical
lp_clock_gating_infer_enable lp_clock_gating_is_flop_rc_gated lp_clock_gating_is_flop_user_g
lp_clock_gating_is_leaf_clock_gate lp_clock_gating_max_flops lp_clock_gating_min_flops
lp_clock_gating_module lp_clock_gating_prefix lp_clock_gating_stage
lp_clock_gating_style lp_clock_gating_test_signal lp_insert_clock_gating
report_clock_from_different_views lp_clock_gating_exclude_signal
clock_gate_enable_pin
Syntax
clock_gate_enable_pin {true | false}
Applies to:
lib_pin
pg_lib_pin
Description
Default: false
Data_type: bool, read only
Indicates if this pin is an enable pin on a clock-gating cell.
Related Information
Affects this command: syn_generic
March 2025 815 Product Version 23.1
Genus Attribute Reference
Clock Gating--clock_gate_enable_polarity
clock_gate_enable_polarity
Syntax
clock_gate_enable_polarity {high | low}
Applies to:
lib_pin
pg_lib_pin
Description
Default: high
Data_type: enum, read/write
Returns the active phase of the enable pin of a clock-gating cell.
clock_gating_integrated_cell
Syntax
clock_gating_integrated_cell <string>
Applies to:
base_cell
lib_cell
Description
Default:
Data_type: string, read only
Describes the functionality of the integrated clock-gating cell:
type of sequential cell,
whether the cell is appropriate for positive or negative-edge triggered registers,
whether the test control logic is located before or after the latch or flip-flop, or does not exist,
whether the cell contains observability logic or not.
An empty string indicates that the cell is not an integrated clock-gating cell.
March 2025 816 Product Version 23.1
Genus Attribute Reference
Clock Gating--is_clock_gate_clock
Related Information
Clock-Gating Cell Specification in the Genus Library Guide.
Affects this command: syn_generic
syn_map
syn_opt
Related attributes: lp_clock_gating_add_obs_port
is_clock_gate_reset
lp_clock_gating_control_point
lp_clock_gating_style
is_clock_gate_clock
Syntax
is_clock_gate_clock {false | true}
Applies to:
lib_pin
pg_lib_pin
Description
Default: false
Data_type: bool, read only
Indicates if this pin is a clock pin on a clock-gating cell.
Related Information
Affects this command: syn_generic
is_clock_gate_enable
Syntax
is_clock_gate_enable {false | true}
Applies to:
lib_pin
pg_lib_pin
Description
Default: false
March 2025 817 Product Version 23.1
Genus Attribute Reference
Clock Gating--is_clock_gate_obs
Data_type: bool, read only
Indicates if this pin is an enable pin on a clock-gating cell.
Related Information
Affects this command: syn_generic
is_clock_gate_obs
Syntax
is_clock_gate_obs {false | true}
Applies to:
lib_pin
pg_lib_pin
Description
Default: false
Data_type: bool, read only
Indicates if this pin is an observable pin on a clock-gating cell.
Related Information
Affects this command: syn_generic
is_clock_gate_out
Syntax
is_clock_gate_out {false | true}
Applies to:
lib_pin
pg_lib_pin
Description
Default: false
Data_type: bool, read only
Indicates if this pin is an output pin on a clock-gating cell.
Related Information
Affects this command: syn_generic
March 2025 818 Product Version 23.1
Genus Attribute Reference
Clock Gating--is_clock_gate_reset
is_clock_gate_reset
Syntax
is_clock_gate_reset {false | true}
Applies to:
lib_pin
pg_lib_pin
Description
Default: false
Data_type: bool, read only
Indicates if this pin is an asynchronous reset pin on a clock-gating cell.
Related Information
Affects this command: syn_generic
is_clock_gate_test
Syntax
is_clock_gate_test {false | true}
Applies to:
lib_pin
pg_lib_pin
Description
Default: false
Data_type: bool, read only
Indicates if this pin is a test pin on a clock-gating cell.
Related Information
Affects this command: syn_generic
is_integrated_clock_gating
March 2025 819 Product Version 23.1
Genus Attribute Reference
Clock Gating--is_integrated_clock_gating
Syntax
is_integrated_clock_gating {false | true}
Applies to:
base_cell
inst
lib_cell
Description
Default: false
Data_type: bool, read only
Indicates whether the base_cell / instance / lib_cell is an integrated clock_gating cell.
is_synthesis_clock_gate
Syntax
is_synthesis_clock_gate {false | true}
Applies to:
inst
Description
Default: false
Data_type: bool, read/write
Indicates if the instance is a clock-gating cell inserted by Genus.
Related Information
Related attributes: lp_insert_clock_gating
clock_gating_integrated_cell
lp_clock_gating_method
Syntax
lp_clock_gating_method {sena | feedback | sena_and_feedback | common_enable_extraction | combine | other | ungated}
Applies to:
inst
March 2025 820 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_add_obs_port
Description
Default: ungated
Data_type: enum, read only
Indicates the method used in Genus to find a clock gate enable condition for the flop.
This attribute applies only to flops.
lp_clock_gating_add_obs_port
Syntax
lp_clock_gating_add_obs_port {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Specifies whether the integrated clock-gating cell must contain observability logic.
If you set this attribute to true, the low power (RC-LP) engine only uses integrated clock-gating cells that have a clock_gating_integrated_cell attribute
that contains obs in the fourth substring.
The RC-LP engine adds an obs port to the clock-gating module and connects this port to the pin of the integrated clock-gating cell that has the
clock_gate_obs_pin attribute.
If you set this attribute to false, the RC-LP engine only uses integrated clock-gating cells that have a clock_gating_integrated_cell attribute that has no
entry for the fourth substring.
Related Information
Clock-Gating Cell Specification in the Genus Library Guide.
Affects these commands: add_clock_gates_obs
syn_generic
report_clock_gates
lp_clock_gating_auto_cost_group_initial_target
Syntax
lp_clock_gating_auto_cost_group_initial_target <float>
Applies to:
design
March 2025 821 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_auto_cost_grouping
Description
Default:
Data_type: delay, read/write
Specifies the initial target slack for automatic clock gate cost groups in picoseconds. This attribute will set the initial target for all newly generated clock-gating
logic.
When no value is specified, the tool will generate the initial target for these cost groups during mapping.
Related Information
Affects these commands: report_timing
syn_map
lp_clock_gating_auto_cost_grouping
Syntax
lp_clock_gating_auto_cost_grouping {true | false}
Applies to:
design
Description
Default: true
Data_type: bool, read/write
Controls whether to automatically create a cost group for the paths going through clock gate enable pins. The cost groups are defined after clock gating is
inserted and have the following name:
cg_enable_group_XXX
where XXX is the name of the clock.
Related Information
Affects these commands: report_timing
syn_map
lp_clock_gating_auto_path_adjust
Syntax
lp_clock_gating_auto_path_adjust {none | fixed | variable | inherited}
Applies to:
design
module
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Genus Attribute Reference
Clock Gating--lp_clock_gating_auto_path_adjust_fixed_delay
Description
Default: none (design), inherited (clock/module)
Data_type: enum, read/write
Controls the automatic timing adjustment on the clock gate enable paths in the design/module.
You can specify any of the following values:
none Prevents the automatic timing adjustment.
fixed Uses the user-defined path adjust value.
variable Scales the tool-calculated path adjust values.
inherited Inherits the value from the design attribute.
Related Information
Affects these commands: report_timing
syn_map
Affects these attributes: lp_clock_gating_auto_path_adjust_fixed_delay
lp_clock_gating_auto_path_adjust_multiplier
lp_clock_gating_auto_path_adjust_fixed_delay
Syntax
lp_clock_gating_auto_path_adjust_fixed_delay <no_value | float>
Applies to:
design
module
Description
Default: 0.0 (design), no_value (clock/module)
Data_type: delay, read/write
Specifies a user-defined path adjust value (in picoseconds) for the enable pins of all clock-gating instances in the design. This value overrides the tool-
calculated path adjust values. You must specify a positive value. A negative or null value does not affect the path constraints.
The path_adjust timing exceptions are stored in the following directory:
/designs/top/timing/exceptions/path_adjusts/
The tool-computed path_adjust timing exceptions are calculated based on information in the libraries and have the following name:
_auto_XXps_cg_path_adjust
where XX is the user-provided delay value.
Related Information
Affects these commands: report_timing
syn_map
Affected by this attribute: lp_clock_gating_auto_path_adjust
March 2025 823 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_auto_path_adjust_modes
lp_clock_gating_auto_path_adjust_modes
Syntax
lp_clock_gating_auto_path_adjust_modes <modes>
Applies to:
design
Description
Default: no_value
Data_type: mode*, read/write
Specifies the timing constraint modes in which automatic timing adjustment on the clock gate enable paths will be applied. By default, the path adjust is applied
in all modes.
Related Information
Affects these commands: report_timing
syn_map
lp_clock_gating_auto_path_adjust_multiplier
Syntax
lp_clock_gating_auto_path_adjust_multiplier <float>
Applies to:
design
module
Description
Default: 1.0 (design), no_value (clock and module)
Data_type: double, read/write
Scales the tool-calculated path adjust values added to the enable pins of all clock-gating instances in the design. Specify a real number between 0.0 and
infinity.
The path_adjust timing exceptions are stored in the following directory:
/designs/top/timing/exceptions/path_adjusts/
The tool-computed path_adjust timing exceptions are calculated based on information in the libraries and have the following name:
_auto_XXps_cg_path_adjust
where XX is the magnitude of the adjustment.
March 2025 824 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_cell
Related Information
Affects these commands: report_timing
syn_map
Affected by this attribute: lp_clock_gating_auto_path_adjust
lp_clock_gating_cell
Syntax
lp_clock_gating_cell <path_name_for_cell>
Applies to:
object Default Data_type
design {} string, read/write
module {} string, read/write
hinst no_value lib_cell, read only
inst no_value lib_cell, read only
Description
design Specifies the path name of the cell to be used for clock-gating insertion. The path name can contain the wildcard character (*). This attribute
overrides the following attributes:
lp_clock_gating_add_obs_port, lp_clock_gating_control_point, and lp_clock_gating_style.
If the specified cell does not exist in any of the libraries, the auto clock-gating insertion will fail. If multiple cells are found, the attribute is not set and
the tool reports an error.
module Specifies the path name of the cell to be used for clock-gating insertion. The path name can contain the wildcard character (*). This attribute
overrides the following attributes:
lp_clock_gating_add_obs_port, lp_clock_gating_control_point, and lp_clock_gating_style.
If the specified cell does not exist in any of the libraries, the auto clock-gating insertion will fail. If multiple cells are found, the attribute is not set and
the tool reports an error.
This attribute applies to all instances of this module.
hinst Returns the path name of the cell (to be) used for clock-gating insertion. This attribute will return no value if the attribute was not set either on the
module corresponding to this instance (or its parent) or on the design.
Example
set_db design:cpu_10bit .lp_clock_gating_cell TLATNTSCAX2
inst Returns the path name of the cell (to be) used for clock-gating insertion. This attribute can be queried on leaf sequential instances. This attribute
will return no value if the attribute was not set either on the module corresponding to this instance (or its parent) or on the design.
Example
set_db design:cpu_10bit .lp_clock_gating_cell TLATNTSCAX2
March 2025 825 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_connect_test_clock_gate_types
Related Information
Affects these commands: report_clock_gates
syn_generic
Affects these attributes: lp_clock_gating_add_obs_port
lp_clock_gating_hierarchical
lp_clock_gating_control_point
lp_clock_gating_style
lp_clock_gating_connect_test_clock_gate_types
lp_clock_gating_connect_test_clock_gate_types {all | synthesis | user}
Description
Sets the types of clock gates that are considered for test connection.
You can specify one of these values:
synthesis Consider only tool-inserted clock gates for test connection.
user Consider only RTL-instantiated clock gates for test connection.
all Consider both tool-inserted and RTL-instantiated clock gates for test connection.
Default: synthesis
Data_type: enum, read/write
Applies to:
root
lp_clock_gating_connect_test_consider_constant_enabled_as_connected
lp_clock_gating_connect_test_consider_constant_enabled_as_connected {true | false}
Description
Clock gating test connection will consider a constant enabled clock gate as already connected.
Default: false
Data_type: bool, read/write
Applies to:
root
lp_clock_gating_control_point
March 2025 826 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_connect_test_consider_constant_enabled_as_connected
Syntax
lp_clock_gating_control_point {precontrol | postcontrol | none}
Applies to:
design
Description
Default: precontrol
Data_type: enum, read/write
If a user-defined clock-gating module is used, specifies whether the module contains test logic. If no user-defined clock gating module or special library cell is
specified for clock gating, the attribute controls whether the integrated clock-gating cell (to be selected) must contain test control logic, and specifies where the
test logic must be located—before or after the latch or flip-flop in the integrated clock-gating cell.
The attribute can have the following values:
none If a user-defined clock-gating module is used, specifies that the module has no test logic. If an integrated clock-gating cell must be selected,
specifies that only cells that have a clock_gating_integrated_cell attribute that has no entry for the third substring can be used.
precontrol If a user-defined clock-gating module is used, specifies that the module has test logic. If an integrated clock-gating cell must be selected,
specifies to only use cells whose clock_gating_integrated_cell (.lib) attribute contains precontrol in the third substring. The test port of the
clock-gating cell will be connected to the pin with the clock_gate_test_pin attribute.
postcontrol If a user-defined clock-gating module is used, specifies that the the module has a test port. If an integrated clock-gating cell must be selected,
specifies to only use cells whose clock_gating_integrated_cell (.lib) attribute contains postcontrol in the third substring. The test port of
the clock-gating cell will be connected to the pin with the clock_gate_test_pin attribute.
To select a clock-gating cell that contains test control logic without a latch or flip-flop, set the lp_clock_gating_control_point attribute to either
precontrol or postcontrol, and set the lp_clock_gating_style attribute to none. The RC-LP engine then looks for a clock-gating cell in the library with the
value none_posedge_control or none_negedge_control for the clock_gating_integrated_cell attribute.
Related Information
Clock-Gating Cell Specification in the Genus Library Guide.
Affects these commands: report_clock_gates
syn_generic
lp_clock_gating_coverage_effort
lp_clock_gating_coverage_effort {standard | high}
Description
Sets the effort level to find clock gate enables of clock gated registers. Possible values are standard and high.
High effort algorithms may find clock gate enables that are difficult to understand structurally.
Default: standard
Data_type: bool, read/write
March 2025 827 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_coverage_effort
Applies to:
root
Related Information
Affects this command: syn_generic
Related attribute: lp_insert_clock_gating
lp_clock_gating_exceptions_aware
lp_clock_gating_exceptions_aware {true | false}
Description
Specifies whether or not to take timing exceptions set on flop instances or on their clock, enable, and reset pins into account during clock gating.
Default: true
Data_type: bool, read/write
Applies to:
root
Related Information
Affects these commands: syn_generic
report_clock_gates
lp_clock_gating_exclude
Syntax
lp_clock_gating_exclude {false | true}
Applies to:
design
hinst
inst
module
Description
Default: false
Data_type: bool, read/write
design Controls whether to insert clock-gating logic for this design. If you set this attribute to true, no clock-gating logic is added to the design.
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Genus Attribute Reference
Clock Gating--lp_clock_gating_exclude
hinst Determines whether to insert clock-gating logic for this instance. If you set this attribute to true on a hierarchical instance, no clock-gating logic is
added to any of the registers in that instance and the hierarchy below that instance.
You can only set this attribute on a unique hierarchical instance. Otherwise, the tool issues an error message and the attribute is ignored. If
a hierarchical instance is instantiated multiple times, first use the dedicate_module command to uniquify the instance that you want to
exclude from clock-gating.
inst Determines whether to insert clock-gating logic for this instance. If you set this attribute to true on a register, no clock-gating logic is added to this
register even when it is possible. If you set this attribute to true on a hierarchical instance, no clock-gating logic is added to any of the registers in
that instance and the hierarchy below that instance.
You can only set this attribute on a unique instance. Otherwise, the tool issues an error message and the attribute is ignored. If a
hierarchical instance is instantiated multiple times, first use the dedicate_module command to uniquify the instance that you want to exclude
from clock-gating.
module Determines whether to insert clock-gating logic for this module. If you set this attribute to true, no clock-gating logic is added to this module and all
its submodules.
This attribute applies to all instances of this module.
Related Information
Affects this command: syn_generic
Related command: dedicate_module
lp_clock_gating_extract_common_enable
Syntax
lp_clock_gating_extract_common_enable {true | false}
Applies to:
design
Description
Default: true
Data_type: bool, read/write
Controls whether to extract the common enable from the enable logic of the registers to be clock gated.
Register banks can sometimes not be considered for clock-gating insertion because their bit width is smaller than the minimum number of registers required for
clock-gating insertion. If the flops that were not gated—because of this minimum bit width requirement—have a complex enable logic, common enable
extraction can extract a common function in the enable logic of those registers. By considering this common function as the enable signal, the minimum bit width
requirement can be satisfied and the registers can be gated.
Related Information
Affects this command: syn_generic
Related attribute: lp_clock_gating_min_flops
March 2025 829 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_extract_common_enable
lp_clock_gating_gated_clock_gates
Syntax
lp_clock_gating_gated_clock_gates <string>
Applies to:
hinst
inst
Description
Default:
Data_type: string, read only
Returns the clock gates gated by this clock-gating instance.
This attribute applies only to clock-gating instances.
Related Information
Affected by this command: syn_generic
lp_clock_gating_gated_flops
Syntax
lp_clock_gating_gated_flops <string>
Applies to:
hinst
inst
Description
Default:
Data_type: string, read only
Returns the flops gated by this clock-gating instance.
This attribute applies only to clock-gating instances.
Related Information
Affected by this command: syn_generic
March 2025 830 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_gated_flops
lp_clock_gating_hierarchical
Syntax
lp_clock_gating_hierarchical {auto | false | true}
Applies to:
design
module
Description
Default: false (design), auto (module)
Data_type: bool (design), enum (module), read/write
Controls insertion of clock-gating logic across logical design/module. Ports will be punched for the clock signals which cross hierarchical boundaries. This is
expected to result in a reduction in the total number of clock gates inserted and an improvement in clock gating coverage.
Related Information
Clock-Gating Cell Specification in the Genus Library Guide.
Affects these commands: syn_generic
lp_clock_gating_infer_enable
lp_clock_gating_infer_enable {true | false | set_reset_flops_only}
Description
When clock-gating insertion is enabled, enabling this attribute will invoke an advanced algorithm that identifies additional clock-gating opportunities—even in
the absence of a feedback loop—that cannot be identified using the basic algorithm.
true Performs the advanced algorithm without restrictions.
false Does not invoke the advanced algorithm.
set_reset_flops_only Only invokes the advanced algorithm for set and reset flops.
This attribute is ignored if you use the syn_generic command with the -effort option set to low, because the low-effort synthesis always disables
infer_enable.
Default: true
Data_type: enum, read/write
Applies to:
root
March 2025 831 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_infer_enable
Related Information
Enabling Clock Gating and RTL Power Analysis in Genus Low Power Guide.
Affects these commands: syn_generic
report_clock_gates
Affected by this attribute: lp_insert_clock_gating
lp_clock_gating_is_flop_rc_gated
Syntax
lp_clock_gating_is_flop_rc_gated <string>
Applies to:
hinst
inst
Description
Default:
Data_type: string, read only
Indicates whether the flop is gated by a clock-gating instance inserted by Genus.
This attribute applies only to sequential instances.
lp_clock_gating_is_flop_user_gated
Syntax
lp_clock_gating_is_flop_user_gated <string>
Applies to:
hinst
inst
Description
Default:
Data_type: string, read only
Indicates whether the flop is gated by a user-instantiated clock-gating instance.
This attribute applies only to sequential instances.
March 2025 832 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_is_flop_user_gated
lp_clock_gating_is_leaf_clock_gate
Syntax
lp_clock_gating_is_leaf_clock_gate {false | true}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read only
Specifies whether this clock-gating instance is a leaf clock gate, that is, a clock-gating instance driving the flops.
This attribute applies only to clock-gating instances.
Related Information
Affected by this command: syn_generic
lp_clock_gating_max_flops
Syntax
lp_clock_gating_max_flops <integer>
Applies to:
design
module
Description
Default:
Data_type: integer, read/write
Determines the maximum number of registers that can be driven by each clock-gating element. If a register bank has a bit width larger than the specified size,
the low power (RC-LP) engine will duplicate the clock-gating cells and distribute the registers evenly over the clock-gating cells. You must specify an integer
larger than 1.
This attribute applies to any clock-gating logic type: user-defined clock-gating module, selected clock-gating integrated cell, or discrete clock-gating logic
created by the tool.
Example
If the register bank width is 32, and the maximum number is 20, each clock-gating cell will drive 16 registers.
March 2025 833 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_min_flops
Related Information
Affects this command: syn_generic
lp_clock_gating_min_flops
Syntax
lp_clock_gating_min_flops <integer>
Applies to:
design
module
Description
Default: 3
Data_type: integer, read/write
Enables clock-gating insertion for any register bank with a bit width larger than or equal to the specified size. You can specify a value from 1 to 1000.
This attribute applies to any clock-gating logic type: user-defined clock-gating module, selected clock-gating integrated cell, or discrete clock-gating logic
created by the tool.
Related Information
Affects this command: syn_generic
lp_clock_gating_module
Syntax
lp_clock_gating_module <path_name_for_module>
Applies to:
object Default Data_type
design no_value module|design, read/write
hinst no_value module|design, read only
inst no_value module|design, read only
module no_value module|design, read/write
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Genus Attribute Reference
Clock Gating--lp_clock_gating_module
Description
design Specifies the path to the module that defines the customized clock-gating logic.
hinst Returns the path name of the module used for clock-gating insertion. This attribute will return no value if the attribute was not set either on the
module corresponding to this instance (or its parent) or on the design.
inst Returns the path name of the module used for clock-gating insertion. This attribute can be queried on hierarchical instances and leaf sequential
instances. This attribute will return no value if the attribute was not set either on the module corresponding to this instance (or its parent) or on the
design.
module Specifies the path to the module that defines the customized clock-gating logic to be used for this module.
Related Information
Affects this command: syn_generic
lp_clock_gating_prefix
lp_clock_gating_prefix string
Description
Specifies the prefix to be added to all clock-gating modules, observability flip-flops, generated clock nets, and the ports created by clock-gating insertion.
Default:
Data_type: string, read/write
Example
If you set this attribute to lowp:
Description Name
clock-gating modules lowp_RC_CG_MOD_xx
clock-gating instances lowp_RC_CG_HIER_INST_xx
gated clock net lowp_rc_gclk_xx
Applies to:
root
Related Information
Affects these commands: elaborate
syn_generic
report_clock_gates
lp_clock_gating_stage
March 2025 835 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_stage
Syntax
lp_clock_gating_stage <string>
Applies to:
hinst
inst
Description
Default:
Data_type: string, read only
Returns the stage to which the clock-gating instance belongs.
This attribute will have no value for instances that are not clock-gating instances.
Example
Assume clock-gating instance CG1 is gating clock-gating instance CG2, which in turn gates a flop. The stage of CG1 is 1 and the stage of CG2 is 2.
Related Information
Affected by these commands: syn_generic
share_clock_gate
lp_clock_gating_style
Syntax
lp_clock_gating_style {latch | ff | none}
Applies to:
design
Description
Default: latch
Data_type: enum, read/write
Controls whether the integrated clock-gating cells must contain logic to prevent glitches on the enable signal and specifies whether to use a latch or a flip-flop
for the logic.
The low power (RC-LP) engine only uses integrated clock-gating cells that have a clock_gating_integrated_cell attribute of which the first substring matches
the value of this attribute.
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Genus Attribute Reference
Clock Gating--lp_clock_gating_test_signal
Related Information
Clock-Gating Cell Specification in the Genus Library Guide.
Affects these commands: report_clock_gates
syn_generic
lp_clock_gating_test_signal
Syntax
lp_clock_gating_test_signal <string>
Applies to:
design
hinst
inst
module
Description
Default:
Data_type: string, read/write
design Indicates which test signal to connect to the test pins of all the clock-gating instances in the design. If the clock-gating instance contains test logic
and you did not specify a test signal, Genus ties the test pin of all clock gating instances to the inactive value. For example, for active high (low)
test pin, the pin is tied to constant 0 (1). You can specify the values given in the next table.
hinst/inst Indicates which test signal to connect to the test pin of the (specified) clock-gating instance(s).
The RC-LP engine creates a separate module for the clock-gating logic in each clock-gating domain, consequently the clock-gating
instance names are similar to:
/designs/<design>/instances_hier/*/RC_CG_HIER_INST<x>
You can specify the values given in the next table.
module Indicates which test signal to connect to the test pin of the clock-gating instances in all instances of the specified module.
The RC-LP engine creates a separate module for the clock-gating logic in each clock-gating domain, consequently the clock-gating
instance names are similar to:
/designs/<design>/instances_hier/*/RC_CG_HIER_INST<x>
You can specify the values given in the next table.
use_shift_enable Indicates to use the shift-enable signal of the scan chain to which the gated flip-flops belong. If the gated flip-flops belong to different
scan chains with different shift enable signals, the shift enable signals are OR-ed and the output of the OR-tree is used as the clock-
gating test signal.
You can only use this value when you insert clock-gating in a mapped netlist after you have inserted the scan chains.
test_signal_object Indicates to use the specified test signal object.
March 2025 837 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_insert_clock_gating
Related Information
Clock-Gating Cell Specification in the Genus Library Guide.
Affects this command: syn_generic
lp_insert_clock_gating
lp_insert_clock_gating {false | true}
Description
Controls insertion of clock-gating logic during synthesis.
Default: false
Data_type: bool, read/write
Applies to:
root
Related Information
Enabling Clock Gating and RTL Power Analysis in Genus Low Power Guide.
Affects these commands: syn_generic
report_clock_gates
report_clock_from_different_views
Syntax
report_clock_from_different_views {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Reports the timing path for clk from different views. Setting the attribute results in reporting '-to clk', where multiple views are present but a view option is not
provided. It examines all views and reports the worst path.
Related Information
Affects this command: report_timing
March 2025 838 Product Version 23.1
Genus Attribute Reference
Clock Gating--lp_clock_gating_exclude_signal
lp_clock_gating_exclude_signal
Syntax
lp_clock_gating_exclude_signal {true | false}
Applies to:
hpin
hport
pin
port
Description
Default: false
Data_type: bool, read/write
Excludes this pin/port from clock-gating enable functions.
Related Information
Affects this command: syn_generic
March 2025 839 Product Version 23.1
Genus Attribute Reference
Conformal Constraint Designer (CCD)
19
Conformal Constraint Designer (CCD)
ccd_executable
wccd_threshold_percentage
ccd_executable
Syntax
ccd_executable <path>
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the Conformal ® Constraint Designer (CCD) executable that should be used for the
generate_constraints and validate_constraints commands.
wccd_threshold_percentage
March 2025 840 Product Version 23.1
Genus Attribute Reference
Conformal Constraint Designer (CCD)--ccd_executable
Syntax
wccd_threshold_percentage <float>
Applies to:
root
Description
Default: 0.8
Data_type: double, read/write
Specifies the threshold percentage in the dofiles for the false path generation flow and the directed
false path generation flow. This value instructs the Conformal ® Constraint Designer tool to
consider only those paths with logic length that is greater than the maximum logic length of all paths
in the design multiplied by the specified value. You can specify a real number between 0 and 1 for
the threshold percentage.
March 2025 841 Product Version 23.1
Genus Attribute Reference
Timing
20
Timing
The chapter describes the following attributes:
adjust_derate arrival box_has_aocv_derate
box_has_ocv_derate case_analysis_multi_driver_propagation causes_ideal_net
define_clock_with_new_cost_group delay delay_corner_pd_at_tc_no_timing_derate
delaycal_equivalent_waveform_model delaycal_library_interpolation_mode delaycal_socv_lvf_mode
delaycal_socv_use_lvf_tables design Attributes in Timing detailed_sdc_messages
disabled_arcs dont_break_combo_loops_thr_c_to_q dont_break_combo_loops_thr_c_to_q_macro
dont_break_combo_loops_thr_en_to_q dont_retime early_estimated_worst_irdrop_factor
early_fall_cell_check_sigma_derate_factor early_fall_clk_cell_sigma_derate_factor early_fall_clk_check_sigma_derate_factor
early_fall_data_cell_sigma_derate_factor early_irdrop_data early_rise_cell_check_sigma_derate_factor
early_rise_clk_cell_sigma_derate_factor early_rise_clk_check_sigma_derate_factor early_rise_data_cell_sigma_derate_factor
enable_break_timing_paths_by_mode enable_data_check exceptions
external_non_tristate_drivers free_global_vars_set_by_read_sdc hierarchical_name
init_prototype_design init_timing_enabled is_hierarchical
is_negative_level_sensitive is_positive_level_sensitive late_estimated_worst_irdrop_factor
late_fall_cell_check_sigma_derate_factor late_fall_clk_cell_sigma_derate_factor late_fall_clk_check_sigma_derate_factor
late_fall_data_cell_sigma_derate_factor late_irdrop_data late_rise_cell_check_sigma_derate_factor
late_rise_clk_cell_sigma_derate_factor late_rise_clk_check_sigma_derate_factor late_rise_data_cell_sigma_derate_factor
legacy_preserve_sdc_object_name mark_retention_pin_ideal min_pulse_width
min_timing_arcs ocv_mode phys_socv
preserve_sdc_annotated_comb_insts retime_original_registers scale_factor_group_path_weights
sdc_filter_match_more_slashes sdc_flat_view_default sdc_match_more_slashes
setup show_wns_in_log skip_default_lib_check
socv_derate spatial_path_group_effort_level synthesis_skip_pd_timing_derate
tim_ignore_data_check_for_non_endpoint_pins time_recovery_arcs timing_analysis_clock_propagation_mode
timing_analysis_clock_source_paths timing_analysis_type timing_case_disabled_arcs
timing_defer_mmmc_obj_updates timing_disable_library_data_to_data_checks timing_disable_non_sequential_checks
timing_enable_get_ports_for_current_instance timing_no_path_segmentation timing_path
timing_propagate_latch_data_uncertainty timing_report_default_formatting timing_report_enable_common_header
timing_report_endpoint_fields timing_report_exception_data timing_report_fields
timing_report_load_unit timing_report_path_type timing_report_unconstrained
timing_spatial_derate_chip_size total_derate trace_retime
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Genus Attribute Reference
Timing--adjust_derate
transition_type ui_units_capacitance_reporting ui_units_timing_reporting
use_multi_clks_latency_uncertainty_optimize use_multi_clks_latency_uncertainty_report user_mean_derate
user_sigma_derate write_mmmc_forking_enabled write_sdc_use_libset_name_set_dont_use
See also:
direction
pin
power_modes
priority
voltage
adjust_derate
Syntax
adjust_derate <double>
Applies to:
timing_point
Description
Default:
Data_type: double, read only
Returns the incremental_adjust derate of the timing point.
Example
The total derate for cell A will be 1 + 1.5 = 2.5, but timing_point adjust_derate value will be 1.5 in this case:
set_timing_derate -incremental_adjust [get_cells A] 1.5
arrival
Syntax
arrival <delay>
Applies to:
timing_path
timing_point
March 2025 843 Product Version 23.1
Genus Attribute Reference
Timing--box_has_aocv_derate
Description
Default:
Data_type: delay, read only
Returns the arrival delay of the timing path / timing point.
box_has_aocv_derate
Syntax
box_has_aocv_derate {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
Specifies the user-defined derate factor on the box.
box_has_ocv_derate
Syntax
box_has_ocv_derate {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
Specifies the user-defined derate factor on the box.
case_analysis_multi_driver_propagation
case_analysis_multi_driver_propagation {favor_neither | favor_0 | favor_1 | none}
Default: favor_neither
Read-write root attribute. Controls how case analysis values are propagated across nets that have multiple drivers. There are four possible settings:
none: If oneor more of the drivers of a multi-driven net are determined to be logic constants for the purposes of timing case analysis, then the constant
value is not propagated to the loads of the net.
March 2025 844 Product Version 23.1
Genus Attribute Reference
Timing--causes_ideal_net
The following three settings will cause Genus to propagate a timing case logic constant value to the loads of a multi-driven net. The following settings affect
how Genus behaves when one or more drivers has a value of 1 and one or more drivers has a value of 0 (conflicting case values).
favor_0: The conflict is resolved by propagating a case value of 0 to the loads.
favor_1: The conflict is resolved by propagating a case value of 1 to the loads.
favor_neither: The conflict is resolved by not propagating a case value to the loads.
Example
The following example shows how the various settings will affect the computation of a timing case value at the loads of the net In a case with a net with four
drivers:
none
driver case values load case value
--------------------------------------
x 1 x x x
1 1 x x x
0 x x x x
1 x 0 0 x
favor_0
driver case values load case value
--------------------------------------
x 1 x x 1
1 1 x x 1
0 x x x 0
1 x 0 0 0 <--
favor_1
driver case values load case value
--------------------------------------
x 1 x x 1
1 1 x x 1
0 x x x 0
1 x 0 0 1 <--
favor_neither
driver case values load case value
--------------------------------------
x 1 x x 1
1 1 x x 1
0 x x x 0
1 x 0 0 x <--
causes_ideal_net
Syntax
causes_ideal_net {true | false}
March 2025 845 Product Version 23.1
Genus Attribute Reference
Timing--define_clock_with_new_cost_group
Applies to:
hpin
hport
pin
port
Description
Default: false
Data_type: bool, read only
Indicates whether the specified pin/hpin/port/hport causes its net to become an ideal net. Genus implicitly sets an ideal net if the pin/hpin/port/hport is:
A pin of a sequential element that is a clock pin.
Any input pin of a sequential element that has no setup arc. That is, any sequential element that may be asynchronous.
Related Information
Related attributes: ideal_seq_async_pins
ttime_recovery_arcs
define_clock_with_new_cost_group
define_clock_with_new_cost_group {false | true}
Default: false
Read-write root attribute. Controls whether a new cost group can be created for each clock defined with the define_clock command. Set this attribute to
true to create cost groups.
Related Information
Affects these commands: create_clock
report_timing
syn_generic
syn_map
syn_opt
delay
Syntax
delay {integer_list}
Applies to:
external_delay
timing_point
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Genus Attribute Reference
Timing--delay_corner_pd_at_tc_no_timing_derate
Description
Default:
Object Data_type Description
external_delay delay*, Specifies the minimum and maximum rise and fall delay values of the external_delay constraint.
read/write
Genus does not use the minimum values, but storing the minimum values allows Genus to write out the SDC
constraints correctly.
timing_point delay, read Returns the delay of the timing point.
only
Related Information
Set by these commands: set_input_delay
set_output_delay
delay_corner_pd_at_tc_no_timing_derate
delay_corner_pd_at_tc_no_timing_derate {false | true}
Default: true
Read-write root attribute. Controls whether to use set_timing_derate -power_domain option while setting the derating factors.
Related Information
Related command: set_timing_derate
delaycal_equivalent_waveform_model
Syntax
delaycal_equivalent_waveform_model {none | no_propagate}
Applies to:
root
Description
Default: none
Data_type: string, read/write
Defines the equivalent waveform model to use during timing analysis.
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Genus Attribute Reference
Timing--delaycal_library_interpolation_mode
delaycal_library_interpolation_mode
Syntax
delaycal_library_interpolation_mode enum {auto | linear | non_linear | non_linear_advanced}
Applies to:
root
Description
Default: auto
Data_type: enum, read/write
Sets library interpolation mode for voltage scaling flow.
Related Information
Related commands: syn_opt
setDelayCalMode in the Innovus Text Command Reference
getDelayCalMode in the Innovus Text Command Reference
delaycal_socv_lvf_mode
Syntax
delaycal_socv_lvf_mode {early_late | moments}
Applies to:
root
Description
Default: early_late
Data_type: string, read/write
Defines the socv lvf mode to use during timing analysis.
March 2025 848 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
delaycal_socv_use_lvf_tables
Syntax
delaycal_socv_use_lvf_tables {delay | slew | constraint | all}
Applies to:
root
Description
Default: all
Data_type: string, read/write
Defines the type of lvf tables to use during timing analysis.
design Attributes in Timing
analysis_views arcs average_net_length
constraint_modes cost_groups delay_corners
dynamic_power_view dynamic_power_view_in_setup early_fall_cell_check_derate_factor
early_fall_clk_cell_derate_factor early_fall_clk_check_derate_factor early_fall_clk_net_delta_derate_factor
early_fall_clk_net_derate_factor early_fall_data_cell_derate_factor early_fall_data_net_delta_derate_factor
early_fall_data_net_derate_factor early_rise_cell_check_derate_factor early_rise_clk_cell_derate_factor
early_rise_clk_check_derate_factor early_rise_clk_net_delta_derate_factor early_rise_clk_net_derate_factor
early_rise_data_cell_derate_factor early_rise_data_net_delta_derate_factor early_rise_data_net_derate_factor
early_socv_inter_rc_variation_factor external_delays fep
force_wireload hold_views ideal_seq_async_pins
latch_borrow latch_max_borrow latch_max_borrow_interface
late_fall_cell_check_derate_factor late_fall_clk_cell_derate_factor late_fall_clk_check_derate_factor
late_fall_clk_net_delta_derate_factor late_fall_clk_net_derate_factor late_fall_data_cell_derate_factor
late_fall_data_net_delta_derate_factor late_fall_data_net_derate_factor late_rise_cell_check_derate_factor
late_rise_clk_cell_derate_factor late_rise_clk_check_derate_factor late_rise_clk_net_delta_derate_factor
late_rise_clk_net_derate_factor late_rise_data_cell_derate_factor late_rise_data_net_delta_derate_factor
late_rise_data_net_derate_factor late_socv_inter_rc_variation_factor leakage_power_view
leakage_power_view_in_setup lp_default_toggle_percentage multi_cycles
nl_has_aocv_derate path_adjusts path_delays
path_disables path_groups setup_views
slack slack_max timing_disable_internal_inout_net_arcs
March 2025 849 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
timing_paths tns total_net_length
tps tslk wireload
analysis_views
analysis_views list_of_analysis_views
Read-only design attribute. Returns a list of analysis views (objects) in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
arcs
arcs arc
Read-only design attribute. Returns the list of ’arc’ objects.
average_net_length
average_net_length float
Read-only design attribute. Computes the average net length of the design in microns. This is a computed attribute. Computed attributes are potentially very
time consuming to process and not listed by the vls command by default.
Related Information
Related commands: write_reports
report_qor
report_summary
constraint_modes
constraint_modes list_of_constraint_modes
Read-only design attribute. Returns a list of the constraint modes (objects) in the design. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
cost_groups
cost_groups list_of_cost_groups
Read-only design attribute. Returns a list of the cost groups (objects) in the design. This is a computed attribute. Computed attributes are potentially very
time consuming to process and not listed by the vls command by default.
delay_corners
delay_corners list_of_delay_corners
Read-only design attribute. Returns a list of the delay corners (objects) in the design. This is a computed attribute. Computed attributes are potentially very
March 2025 850 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
time consuming to process and not listed by the vls command by default.
dynamic_power_view
dynamic_power_view analysis_view
Read-only design attribute. Returns the analysis_view that is used for dynamic power analysis.
dynamic_power_view_in_setup
dynamic_power_view_in_setup analysis_view
Default: no value
Read-only design attribute. Returns the analysis_view for dynamic power analysis in setup.
early_fall_cell_check_derate_factor
early_fall_cell_check_derate_factor float
Read-write design attribute. Returns the cell check derating factor specified through the set_timing_derate command with the -early -fall -cell_check
options.
early_fall_clk_cell_derate_factor
early_fall_clk_cell_derate_factor float
Read-write design attribute. Returns the derating factor for early clock paths specified through the set_timing_derate command with the -early -fall -
clock options.
early_fall_clk_check_derate_factor
early_fall_clk_check_derate_factor float
Read-write design attribute. Returns the clock check derating factor specified through the set_timing_derate command with the -early -fall -clock
options.
early_fall_clk_net_delta_derate_factor
early_fall_clk_net_delta_derate_factor float
Default: 1.0
Read-write design attribute. Returns the early derating factor for the delta portion of the falling delays on the clock path nets. You can use -index option of
the get_db command to return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_fall_clk_net_derate_factor
March 2025 851 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
early_fall_clk_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the early derating factor for falling static delays on clock path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_fall_data_cell_derate_factor
early_fall_data_cell_derate_factor float
Read-write design attribute. Returns the derating factor for early data paths specified through the set_timing_derate command with the -early -fall -data
options.
early_fall_data_net_delta_derate_factor
early_fall_data_net_delta_derate_factor float
Default: 1.0
Read-write design attribute. Returns the early derating factor for the delta portion of the falling delays on the data path nets. You can use -index option of the
get_db command to return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_fall_data_net_derate_factor
early_fall_data_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the early derating factor for falling static delays on data path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_rise_cell_check_derate_factor
early_rise_cell_check_derate_factor float
Read-write design attribute. Returns the cell check derating factor specified through the set_timing_derate command with the -early -rise -cell_check
options.
March 2025 852 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
early_rise_clk_cell_derate_factor
early_rise_clk_cell_derate_factor float
Read-write design attribute. Returns the derating factor for early clock paths specified through the set_timing_derate command with the -early -rise -
clock options.
early_rise_clk_check_derate_factor
early_rise_clk_check_derate_factor float
Read-write design attribute. Returns the clock check derating factor specified through the set_timing_derate command with the -early -rise -clock
options.
early_rise_clk_net_delta_derate_factor
early_rise_clk_net_delta_derate_factor float
Default: 1.0
Read-write design attribute. Returns the early derating factor for the delta portion of the rising delays on the clock path nets. You can use -index option of the
get_db command to return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_rise_clk_net_derate_factor
early_rise_clk_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the early derating factor for rising static delays on clock path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_rise_data_cell_derate_factor
early_rise_data_cell_derate_factor float
Read-write design attribute. Returns the derating factor for early data paths specified through the set_timing_derate command with the -early -rise -data
options.
early_rise_data_net_delta_derate_factor
early_rise_data_net_delta_derate_factor float
March 2025 853 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
Default: 1.0
Read-write design attribute. Returns the early derating factor for the delta portion of the rising delays on the data path nets. You can use -index option of the
get_db command to return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_rise_data_net_derate_factor
early_rise_data_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the early derating factor for rising static delays on data path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
early_socv_inter_rc_variation_factor
early_socv_inter_rc_variation_factor double
Default: 0.0
Read-write design attribute. Returns the variation factor for early interconnect delays.
external_delays
Syntax
external_delays <list_of_external_delays>
Applies to:
design
hpin
pin
port
Description
Default:
Data_type: external_delay*, read only
Returns a list of the external delays (objects) in the design and associated with the hierarchical pin/pin/port.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
March 2025 854 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
Related Information
Set by these commands: set_input_delay
set_output_delay
fep
fep double
Default: 0.0
Read-only design attribute. Returns the total failing endpoints of design.
force_wireload
Syntax
force_wireload {auto_select | custom_wireload | inherit | none}
Applies to:
design
module
Description
Default: auto_select
Data_type: enum, read/write
Forces Genus to use the specified wire-load model.
auto_select Automatically selects wire-load models according to the wire-load selection table or default wire-load model in the technology library.
custom_wireload Forces Genus to use the specified custom wire-load model. Specify the hierarchical path to the wire-load model to be used.
inherit Causes the same behavior as auto_select.
none Prevents use of any wire-load models.
When you set this attribute on the design it does not affect any modules on which this attribute was set, unless the value on the module was set to
inherit.
Related Information
Affects this attribute: wireload
Affected by this attribute: wireload_selection
Related attribute: wireload_mode
hold_views
hold_views list_of_analysis_views
Read-only design attribute. Returns a list of hold_view objects in the design.
March 2025 855 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
ideal_seq_async_pins
ideal_seq_async_pins {true | false}
Default: true
Read-write design attribute. Affects those nets that have both asynchronous and synchronous loads. If this attribute is set to true, Genus will only treat the
asynchronous loads as ideal (0 capacitance) and not the entire net. Only the synchronous loads will be used to compute the total load capacitance of these
nets during timing and optimization. For example, if there are 20 asynchronous reset loads on a net and each has a load capacitance of 100 and there is also
two D-pin loads and each has a load capacitance of 150, the total load capacitance of the net is:
2 * 150 = 300
When a net has an inverter or buffer tree that in turn drives the synchronous or asynchronous loads, then any asynchronous pin of a register is considered to
be an asynchronous load. Any inverter or buffer that drives *only* other asynchronous loads is itself considered to be an asynchronous load for its driver net.
Thus, if a buffer or inverter tree drives asynchronous or synchronous loads, the asynchronous selection process is propagated backwards through the chain
of buffers or inverter.
Example
set_db design:rtor .ideal_seq_async_pins false
Setting attribute of design 'rtor': 'ideal_seq_async_pins' = false
1 false
latch_borrow
Syntax
latch_borrow {no_value | float}
Applies to:
design
inst
Description
Default: no_value
Data_type: delay, read/write
design Specifies the time (in ps) borrowed from the next clock cycle. If set to no_value, the latch borrow values are computed dynamically.
inst Specifies the time (in ps) borrowed from the next clock cycle. The resolution is 1.
A latch_borrow definition is only valid when inferencing a latch or a blackbox.
Example
The following example sets a latch_borrow value of 300 p.s:
set_db [vfind / -design rtor] .latch_borrow 300
Setting attribute of design 'rtor': 'latch_borrow' = 300.0
1 300.0
Related Information
Affected by this attribute: latch_max_borrow
March 2025 856 Product Version 23.1
Genus Attribute Reference
Timing--delaycal_socv_use_lvf_tables
latch_max_borrow
Syntax
latch_max_borrow {no_value | integer}
Applies to:
design
inst
pin
clock
Description
Default: no_value
Data_type: delay, read/write
Specifies the maximum amount of time that can be borrowed, in picoseconds, from the next clock cycle. The specified value must be an integer greater or
equal to 0 (decimal values are rounded to the nearest integer) or no_value. This attribute is available on latch cells, clocks, clock (enable) pin, data pin, or on
a design. If the attribute is set on multiple objects that overlap each other, for example a latch instance and its data pin, the minimum value will be taken. If the
latch_borrow attribute has already been set, then the latch_max_borrow attribute is ignored.
Related Information
Affected by these attributes: latch_borrow
latch_max_borrow_interface
Syntax
latch_max_borrow_interface {no_value | <bool>}
Applies to:
clock
design
inst
pin
Description
Default: no_value
Data_type: delay, read/write
Specifies the maximum amount of time that can be borrowed, in picoseconds, from the next clock cycle. The specified value must be an integer greater or
equal to 0 (decimal values are rounded to the nearest integer) or no_value. This attribute is available on latch cells, clocks, clock (enable) pin, data pin, or on
a design.
If the attribute is set on multiple objects that overlap each other, for example a latch instance and its data pin, the minimum value will be taken. If it is set
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on a latch cell, it replaces the value set on the design.
If the latch_borrow attribute has already been set, then the latch_max_borrow attribute is ignored. latch_max_borrow_interface is specified for IO
paths.
Related Information
Affected by this attribute: latch_borrow
late_fall_cell_check_derate_factor
late_fall_cell_check_derate_factor float
Read-write design attribute. Returns the cell check derating factor specified through the set_timing_derate command with the -late -fall -cell_check
options.
late_fall_clk_cell_derate_factor
late_fall_clk_cell_derate_factor float
Read-write design attribute. Returns the derating factor for late clock paths specified through the set_timing_derate command with the -late -fall -clock
options.
late_fall_clk_check_derate_factor
late_fall_clk_check_derate_factor float
Read-write design attribute. Returns the clock check derating factor specified through the set_timing_derate command with the -late -fall -clock
options.
late_fall_clk_net_delta_derate_factor
late_fall_clk_net_delta_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for the delta portion of the falling delays on the clock path nets. You can use -index option of the
get_db command to return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
late_fall_clk_net_derate_factor
late_fall_clk_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for falling static delays on clock path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
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Timing--delaycal_socv_use_lvf_tables
Related Information
Set by this command: set_timing_derate
late_fall_data_cell_derate_factor
late_fall_data_cell_derate_factor float
Read-write design attribute. Returns the derating factor for early data paths specified through the set_timing_derate command with the -late -fall -data
options.
late_fall_data_net_delta_derate_factor
late_fall_data_net_delta_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for the delta portion of the falling delays on the data path nets. You can use -index option of the
get_db command to return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
late_fall_data_net_derate_factor
late_fall_data_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for falling static delays on data path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
late_rise_cell_check_derate_factor
late_rise_cell_check_derate_factor float
Read-write design attribute. Returns the cell check derating factor specified through the set_timing_derate command with the -late -rise -cell_check
options.
late_rise_clk_cell_derate_factor
late_rise_clk_cell_derate_factor float
Read-write design attribute. Returns the derating factor for late clock paths specified through the set_timing_derate command with the -late -rise -clock
options.
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late_rise_clk_check_derate_factor
late_rise_clk_check_derate_factor float
Read-write design attribute. Returns the clock check derating factor specified through the set_timing_derate command with the -late -rise -clock
options.
late_rise_clk_net_delta_derate_factor
late_rise_clk_net_delta_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for the delta portion of the rising delays on the clock path nets. You can use -index option of the
get_db command to return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
late_rise_clk_net_derate_factor
late_rise_clk_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for rising static delays on clock path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
late_rise_data_cell_derate_factor
late_rise_data_cell_derate_factor float
Read-write design attribute. Returns the derating factor for early data paths specified through the set_timing_derate command with the -late -rise -data
options.
late_rise_data_net_delta_derate_factor
late_rise_data_net_delta_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for the delta portion of the rising delays on the data path nets. You can use -index option of the
get_db command to return the derate factor for a specific view.
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Timing--delaycal_socv_use_lvf_tables
Related Information
Set by this command: set_timing_derate
late_rise_data_net_derate_factor
late_rise_data_net_derate_factor float
Default: 1.0
Read-write design attribute. Returns the late derating factor for rising static delays on data path nets. You can use -index option of the get_db command to
return the derate factor for a specific view.
Related Information
Set by this command: set_timing_derate
late_socv_inter_rc_variation_factor
late_socv_inter_rc_variation_factor double
Default: 1.0
Read-write design attribute. Returns the variation factor for late interconnect delays.
leakage_power_view
leakage_power_view analysis_view
Read-only design attribute. Returns the analysis_view that is used for leakage power analysis.
leakage_power_view_in_setup
leakage_power_view_in_setup analysis_view
Default: no value
Read-only design attribute. Returns the analysis_view for leakage power analysis in setup.
lp_default_toggle_percentage
Syntax
lp_default_toggle_percentage <float>
Applies to:
clock
design
Description
Default: 0.2 (design) / inherited (clock)
Data_type: float, read/write
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Specifies the multiplication factor to be used with all clocks/this clock in the design to modify the default toggle rate of any activity propagation starting point
associated with clock information. The toggle rate of an activity propagation starting point is derived by multiplying this scaling factor with the toggle rate of
the associated clock information. If multiple clocks are related to the pin, the fastest clock is used. Specify a value between 0 and 1. You can use a value
greater than 1.0 to model cases with high glitching power, which can result in more than one value change per clock on average. A warning is printed if you
specify a value larger than 1.
For clock objects, this attribute inherits the value from the corresponding design attribute.
Related Information
Using Default Switching Activities in Genus Low Power Guide.
Affects this command: report_power
Affected by this attribute: lp_toggle_rate_unit
multi_cycles
multi_cycles list_of_multi_cycles
Read-only design attribute. Returns a list of multi_cycle objects in the design.
nl_has_aocv_derate
nl_has_aocv_derate {1 | 0 | true | false}
Default: false
Read-write design attribute. Specifies that the netlist has user-defined derating factor.
Related Information
Set by this command: set_timing_derate
path_adjusts
path_adjusts list_of_path_adjusts
Read-only design attribute. Returns a list of path_adjust objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
path_delays
path_delays list_of_path_delays
Read-only design attribute. Returns a list of path_delay objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
path_disables
path_disables list_of_path_disables
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Timing--delaycal_socv_use_lvf_tables
Read-only design attribute. Returns a list of path_disable objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
path_groups
path_groups list_of_path_groups
Read-only design attribute. Returns a list of path_group objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
setup_views
setup_views list_of_analysis_views
Read-only design attribute. Returns a list of setup views (objects) in the design.
slack
Syntax
slack {no_value | float}
Applies to:
object Default Data_type
design delay, read only
hinst delay, read only
inst delay, read only
cost_group delay, read only
timing_path delay, read only
timing_point delay, read only
pinstance 0.0 double, read/write
timing_bin_path string, read only
Description
design Returns the worst slack (over all paths) in the design in picoseconds. The resolution is 1.
hinst Returns the slack of the instance in picoseconds. The resolution is 1.
inst Returns the slack of the instance in picoseconds. The resolution is 1.
cost_group Returns the worst slack of the cost group in picoseconds. The resolution is 1.
timing_path Returns the slack of this timing path.
timing_point
pinstance
timing_bin_path
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This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related command: report_timing
slack_max
slack_max {no_value | float}
Read-only design attribute. Returns the maximum slack of the design in picoseconds. The resolution is 1. This is a computed attribute. Computed attributes
are potentially very time consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attributes: (hpin) slack_max
(pin) slack_max
(port) slack_max
timing_disable_internal_inout_net_arcs
Syntax
timing_disable_internal_inout_net_arcs {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Determines whether to disable the path from internal drivers of multi-driven nets when the net is connected to a bidirectional I/O port.
If this attribute is set to true, the following applies to multi-driven nets connected to an I/O port:
All timing paths starting from drivers other than the I/O port to loads of the net are disabled.
The only valid paths are from drivers other than the I/O port to the I/O and from the I/O to the loads.
The slew value at the input pin of the loads is propagated from the I/O ports.
In case of multiple I/O ports, the worst slew among the I/O ports gets propagated to the input pin of the loads.
timing_paths
timing_paths timing_path
Read-only design attribute. Returns the list of ’timing_path’ objects.
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tns
tns string
Read-only design attribute. Returns the sum (or total) of all worst negative slacks of all endpoints in the design in picoseconds. If the worst slack at an
endpoint is positive, it is not considered. If all endpoints in the design have a positive worst slack, a value of 0 will be reported. This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls command by default.
An endpoint can belong to several cost groups and can have a different worst slack value in each cost group. For the calculation of this value, the
worst slack of each endpoint is used.
Example
Assume a design has two endpoints, A and B, whose worst slack is -10 and +15 respectively. In this case, the tns value of the design returns 10, because
the slack value of +15 is treated as zero slack.
Related Information
Related command: report_timing
total_net_length
total_net_length float
Read-only design attribute. Computes the total net length of the design in microns. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related commands: write_reports
report_qor
report_summary
tps
tps double
Default: no value
Read-only design attribute. Returns the total positive slack of a design.
tslk
tslk double
Read-only design attribute. Returns the total slack of slacks less than 1000 per design.
wireload
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Timing--detailed_sdc_messages
Syntax
wireload <string>
Applies to:
design
module
Description
Default:
Data_type: string, read only
Returns the current wire-load model for the design/module.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Affected by these attributes: force_wireload
wireload_selection
detailed_sdc_messages
Syntax
detailed_sdc_messages {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the preciseness of the line numbers reported in the messages for failing SDC commands when reading in an SDC file.
Set this attribute to true to get an exact pointer to the line number of the failing SDC command during read_sdc. This is especially useful when the SDC
command is embedded within control structures (if, foreach, while etc) or within a TCL procedure.
By default, the warning and error messages simply point to the line number of the control structure (if,foreach,while) enclosing the SDC command or to the
line number of the procedure call.
Example
For the example below, the lines in the sample SDC file (test.sdc) below are numbered:
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Timing--detailed_sdc_messages
1.set temp 1
2. if {$temp} {
3.
4.
5.
6.
7.
8.
9.sdc_commands_re_set_false_path.html -from [get_cells ffff]
10.
11.
12.
13.}
The following messages are given with the default behavior:
Warning : Could not find requested search value. [SDC-208] [get_cells]
: The ’get_cells’ command on line ’2’ of the SDC file ’test.sdc’ cannot find any cells named ’ffff’.
: Use the ’cd’ and ’ls’ commands to browse the virtual directories to find the object because the specified name and/or
location does not exist.
Error : A required object parameter could not be found. [TUI-61] [parse_options]
: An object of type ’clock|port|instance|pin’ named ’’ could not be found.
: Check to make sure that the object exists and is of the correct type.
The ’what_is’ command can be used to determine the type of an object.
Usage: sdc_commands_re_set_false_path.html [-rise] [-fall] [-from <clock|port|instance|pin>+]
[-rise_from <clock|port|instance|pin>+]
[-fall_from <clock|port|instance|pin>+]
[-to <clock|port|instance|pin>+] [-rise_to <clock|port|instance|pin>+]
[-fall_to <clock|port|instance|pin>+] ...
...
Error : Could not interpret SDC command. [SDC-202] [read_sdc]
: The ’read_sdc’ command encountered an error while processing this command
on line ’2’ of the SDC file ’test.sdc’: if {$temp} {
sdc_commands_re_set_false_path.html -from [get_cells ffff]
}.
: The ’read_sdc’ command encountered a problem while trying to evaluate an
SDC command. This SDC command will be added to the Tcl variable
$::dc::sdc_failed_commands.
Statistics for commands executed by read_sdc:
"get_cells" - successful 0 , failed 1 (runtime 0.00)
"sdc_commands_re_set_false_path.html" - successful 0 , failed 1 (runtime 0.00)
Warning : Total failed commands during read_sdc are 2
Warning : One or more commands failed when these constraints were applied.[SDC-209]
: The ’read_sdc’ command encountered a problem while processing commands.
: You can examine the failed commands or save them to a file by querying
the Tcl variable $::dc::sdc_failed_commands.
Total runtime 0.0
The following messages are given when you set detailed_sdc_messages to true:
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Timing--disabled_arcs
-- Message on line ’9’ of the SDC file ’test.sdc’
-- The command present in the file is : ’get_cells ffff’
-- The command passed to the interpreter is : ’::dc::get_cells ffff’
-- Message type: Error
Warning : Could not find requested search value. [SDC-208] [get_cells]
: The ’get_cells’ command on line ’9’ of the SDC file ’test.sdc’ cannot
find any cells named ’ffff’.
-- End of messages for line ’9’
-- Message on line ’9’ of the SDC file ’test.sdc’
-- The command present in the file is : ’sdc_commands_re_set_false_path.html -from [get_cells ffff]’
-- The command passed to the interpreter is : ’::dc::sdc_commands_re_set_false_path.html -from {}’
-- Message type: Error
Error : A required object parameter could not be found. [TUI-61] [parse_options]
: An object of type ’clock|port|instance|pin’ named ’’ could not be found.
Usage: sdc_commands_re_set_false_path.html [-rise] [-fall] [-from <clock|port|instance|pin>+]
[-rise_from <clock|port|instance|pin>+]
[-fall_from <clock|port|instance|pin>+]
[-to <clock|port|instance|pin>+] [-rise_to <clock|port|instance|pin>+]
[-fall_to <clock|port|instance|pin>+] ...
...
-- End of messages for line ’9’
Error : Could not interpret SDC command. [SDC-202] [read_sdc]
: The ’read_sdc’ command encountered an error while processing this command
from line ’2’ to line ’13’ of the SDC file ’test.sdc’
: The command is:
if {$temp} {
sdc_commands_re_set_false_path.html -from [get_cells ffff]
}
##### M1 - End of error Messages from line ’2’ to line ’13’ of test.sdc
Statistics for commands executed by read_sdc:
"get_cells" - successful 0 , failed 1 (runtime 0.00)
"sdc_commands_re_set_false_path.html" - successful 0 , failed 1 (runtime 0.00)
Warning : Total failed commands during read_sdc are 2
Warning : One or more commands failed when these constraints were applied. [SDC-209]
: The ’read_sdc’ command encountered a problem while processing commands.
Total runtime 0.0
Related Information
Related command: read_sdc
disabled_arcs
disabled_arcs Tcl_list
Read-write inst attribute. Disables or breaks timing arcs (path delay) of library cells for synthesis and static timing analysis. This attribute affects only the
specified instance and not all references of the library cell in the top level of the design. A disable on the specific arc requests the static timing analysis
engine not to consider the path under consideration for timing analysis. You can specify a Tcl list of timing arcs.
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Timing--dont_break_combo_loops_thr_c_to_q
Only arcs of mapped instances can be disabled.
Related Information
Related command: report_timing
Related attributes: (inst) timing_case_disabled_arcs
dont_break_combo_loops_thr_c_to_q
Syntax
dont_break_combo_loops_thr_c_to_q {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Set to 'true' means not breaking combo loops through clock to q arcs.
dont_break_combo_loops_thr_c_to_q_macro
Syntax
dont_break_combo_loops_thr_c_to_q_macro {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Set to 'true' means not breaking combo loops through clock to 'q' arcs on macro seq model.
dont_break_combo_loops_thr_en_to_q
Syntax
dont_break_combo_loops_thr_en_to_q {false | true}
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Timing--dont_retime
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Set to 'true' means not breaking combo loops through enable to 'q' arcs of latches.
dont_retime
Syntax
dont_retime {false | true}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
Instructs Genus not to move any of the specified instances for retiming. This attribute is only available on registers.
Related Information
Affects this attribute: retime
Related attributes: retime_hard_region
retime_reg_naming_suffix
early_estimated_worst_irdrop_factor
Syntax
early_estimated_worst_irdrop_factor <float>
Applies to:
delay_corner
Description
Default: 1.0
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Timing--early_fall_cell_check_sigma_derate_factor
Data_type: double, read only
Returns the value specified with the '-early_estimated_worst_irdrop_factor' option of the 'create_delay_corner' command.
Example
genus@root:> get_db delay_corner:wc_dc .early_estimated_worst_irdrop_factor
1.02
Related Information
Set by this command: create_delay_corner
early_fall_cell_check_sigma_derate_factor
early_fall_cell_check_sigma_derate_factor float
Read-write hinst attribute. Returns the derating sigma factor to the falling edge of early datapaths on timing checks.
early_fall_clk_cell_sigma_derate_factor
early_fall_clk_cell_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the falling edge of early clock paths on cell delays.
early_fall_clk_check_sigma_derate_factor
early_fall_clk_check_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the falling edge of early clock paths on timing checks.
early_fall_data_cell_sigma_derate_factor
early_fall_data_cell_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the falling edge of early data paths on cell delays.
early_irdrop_data
Syntax
early_irdrop_data <file>
Applies to:
delay_corner
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Timing--early_rise_cell_check_sigma_derate_factor
Description
Default:
Data_type: string, read only
Returns the name of the IR drop data file to apply for the early delay calculation for this delay corner.
Related Information
Set by this command: create_delay_corner
early_rise_cell_check_sigma_derate_factor
early_rise_cell_check_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of early data paths on timing checks.
early_rise_clk_cell_sigma_derate_factor
early_rise_clk_cell_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of early clock paths on cell delays.
early_rise_clk_check_sigma_derate_factor
early_rise_clk_check_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of early clock paths on timing checks.
early_rise_data_cell_sigma_derate_factor
early_rise_data_cell_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of early data paths on cell delays.
enable_break_timing_paths_by_mode
enable_break_timing_paths_by_mode {true | false}
Default: true
Read-write root attribute. When in multi mode, indicates whether timing paths can be broken by mode to honor different timing constraints by mode, such as
clock gating checks.
Do not set this attribute to false unless the tool issued a warning message that instructs you to change the setting.
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Timing--enable_data_check
Related Information
Affects these commands: report_clocks
report_qor
read_sdc
report_timing
write_sdc
write_script
Related commands: multi_cycle
path_adjust
path_delay
path_disable
specify_paths
Related attributes: (pin) break_timing_paths
(port) break_timing_paths
disabled_arcs
(pin) timing_case_computed_value_by_mode
(instance) timing_case_disabled_arcs
(instance) timing_case_disabled_arcs_by_mode
(pin) timing_case_logic_value
(port) timing_case_logic_value
enable_data_check
enable_data_check {true | false}
Default: true
Read-write root attribute. When set to true, the data-to-data checks (specified through the set_data_check SDC command or in the library) are enabled. You
should set this attribute before reading in the design.
For non_seq_setup_falling/rising timing_type data checks, additionally, set the timing_disable_non_sequential_checks attribute to false.
Related Information
Affects these commands: report_timing
syn_generic
syn_map
syn_opt
Affects this attribute: min_timing_arcs
Related attributes: timing_disable_non_sequential_checks
type
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Timing--exceptions
exceptions
exceptions string
Read-only hinst attribute. Returns a list of all the timing exceptions that were applied to the specified instance.
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
Related attributes: (clock) exceptions
(cost_group) exceptions
(external_delay) exceptionsexceptions
(hpin) exceptions
(inst) exceptions
(pin) exceptions
(port) exceptions
(timin_path) exceptions
external_non_tristate_drivers
Syntax
external_non_tristate_drivers <double>
Applies to:
port
Description
Default: 0.0
Data_type: double, read/write
Specifies the number of parallel driving pins.
Related Information
Related attribute: external_driver
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Timing--free_global_vars_set_by_read_sdc
free_global_vars_set_by_read_sdc
Syntax
free_global_vars_set_by_read_sdc {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the unsetting of global variables set by the read_sdc command. Set this attribute to true before read_sdc to unset any of those global variables when
the read_sdc command finishes.
Having large TCL variables can cause potential issues during super-threading.
Example
Assume the SDC file has:
set X [get_cells 'hier]
set_false_path 'from $X
Setting this attribute to true before read_sdc, unsets the global variable X at the end of read_sdc.
hierarchical_name
Syntax
hierarchical_name <string>
Applies to:
timing_point
Description
Default:
Data_type: string, read only
Returns the hierarchical name of the timing point.
init_prototype_design
init_prototype_design {false | true}
Read-only root attribute. Indicates whether the design is a prototype.
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Timing--init_timing_enabled
init_timing_enabled
init_timing_enabled {false | true}
Read-only root attribute. Indicates whether the tool is in timing mode.
is_hierarchical
Syntax
is_hierarchical {true | false}
Applies to:
timing_point
Description
Default: false
Data_type: bool, read only
Indicates whether the timing point is hierarchical.
is_negative_level_sensitive
is_negative_level_sensitive {false | true}
Read-only hinst attribute. Indicates whether the hierarchical instance is negative level-sensitive.
Related Information
Related attribute: (inst) is_negative_level_sensitive
is_positive_level_sensitive
is_positive_level_sensitive {false | true}
Read-only hinst attribute. Indicates whether the hierarchical instance is positive level-sensitive.
Related Information
Related attribute: (inst) is_positive_level_sensitive
late_estimated_worst_irdrop_factor
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Timing--late_fall_cell_check_sigma_derate_factor
Syntax
late_estimated_worst_irdrop_factor <float>
Applies to:
delay_corner
Description
Default: 1.0
Data_type: double, read only
Returns the value specified with the '-late_estimated_worst_irdrop_factor' option of the 'create_delay_corner' command.
Example
genus@root:> get_db delay_corner:wc_dc .late_estimated_worst_irdrop_factor
1.02
Related Information
Set by this command: create_delay_corner
late_fall_cell_check_sigma_derate_factor
late_fall_cell_check_sigma_derate_factor double
Default: 0
Read-write hinst attribute. Specifies derating sigma factor to the falling edge of late data paths on timing checks.
late_fall_clk_cell_sigma_derate_factor
late_fall_clk_cell_sigma_derate_factor double
Default: 0
Read-write hinst attribute. Specifies derating sigma factor to the falling edge of late clock paths on cell delays.
late_fall_clk_check_sigma_derate_factor
late_fall_clk_check_sigma_derate_factor double
Default: 0
Read-write hinst attribute. Specifies derating sigma factor to the falling edge of late clock paths on timing checks.
late_fall_data_cell_sigma_derate_factor
late_fall_data_cell_sigma_derate_factor double
Default: 0
Read-write hinst attribute. Specifies derating sigma factor to the falling edge of late data paths on cell delays.
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Timing--late_irdrop_data
late_irdrop_data
Syntax
late_irdrop_data <file>
Applies to:
delay_corner
Description
Default:
Data_type: string, read only
Returns the name of the IR drop data file to apply for the late delay calculation for this delay corner.
Related Information
Set by this command: create_delay_corner
late_rise_cell_check_sigma_derate_factor
late_rise_cell_check_sigma_derate_factor double
Default: 0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of late data paths on timing checks.
late_rise_clk_cell_sigma_derate_factor
late_rise_clk_cell_sigma_derate_factor double
Default: 0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of late clock paths on cell delays.
late_rise_clk_check_sigma_derate_factor
late_rise_clk_check_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of late clock paths on timing checks.
late_rise_data_cell_sigma_derate_factor
late_rise_data_cell_sigma_derate_factor double
Default: 1.0
Read-write hinst attribute. Specifies derating sigma factor to the rising edge of late data paths on cell delays.
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Timing--legacy_preserve_sdc_object_name
legacy_preserve_sdc_object_name
Syntax
legacy_preserve_sdc_object_name {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
If set to true, preserves the legacy SDC objects name.
mark_retention_pin_ideal
Syntax
mark_retention_pin_ideal {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Marks retention pin driver as ideal or not.
min_pulse_width
Syntax
min_pulse_width { {no_value no_value} | Tcl_list}
Applies to:
clock
hpin
pin
port
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Timing--min_timing_arcs
Description
Default: no_value no_value
Data_type: delay*, read/write
Specifies the minimum pulse width constraint on the low and high signal levels of the clock or the value the clock should have when arriving at this pin/port.
You can specify one or two of these values:
Value Description
no_value If you specify a single value, then the same constraint applies to the low and high signal values of the clock or the value the clock
no_value should have when arriving at this pin/port.
Tcl_list If you specify a Tcl list containing two values, then the first value applies to the low signal of the clock, while the second value applies to
the high signal value of the clock.
min_timing_arcs
min_timing_arcs string
Applies to:
hpin
pin
Description
Default:
Data_type: string, read only
Returns the minimum delay timing arcs to this pin. This attribute is only computed if the pin requires to have the minimum delay computed to honor the data-
to-data timing constraints.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related attribute: (hpin) timing_arcs
ocv_mode
ocv_mode {false | true}
Default: false
Read-write root attribute. When set to true, enables the On-Chip Variation (OCV) mode for timing analysis.
Specifying ocv_mode true in Genus is equivalent to setting timing_analysis_type attribute to ocv in Innovus.
phys_socv
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Timing--preserve_sdc_annotated_comb_insts
phys_socv {false|true}
Default: false
Read-write root attribute. Controls Statistical On-Chip Variation (SOCV) support.
preserve_sdc_annotated_comb_insts
Syntax
preserve_sdc_annotated_comb_insts {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Preserves the combinational logic after elaboration to keep them away from move/delete operation during synthesis.
retime_original_registers
Syntax
retime_original_registers register_name
Applies to:
hinst
inst
Description
Default:
Data_type: string, read only
Returns the original name of the specified retimed register. Registers must first be marked with the trace_retime attribute before retiming optimization.
Related Information
Affected by this attribute: trace_retime
Related attributes: dont_retime
retime
retime_hard_region
retime_reg_naming_suffix
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Timing--scale_factor_group_path_weights
scale_factor_group_path_weights
Syntax
scale_factor_group_path_weights <integer>
Applies to:
root
Description
Default: 1
Data_type: int, read/write
Scales the weights specified in any group_path -weight SDC command(s). Set this attribute to a value which will convert all weights to whole numbers to
ensure that all weights are integers and the relative weights across all groups is maintained. Set the attribute before reading any constraints.
Example
Consider the following line in the SDC file:
group_path -weight 10 -name m -from in
The following command scales the weight of cost group m by 6.
set_db / .scale_factor_group_path_weights 6
As a result the weight of cost group m is now 60.
Related Information
Related command: group_path
sdc_filter_match_more_slashes
sdc_filter_match_more_slashes {false| true}
Default: false
Read-write root attribute. When enabled, Genus will try to match slashes (/) in the search pattern of the filter expression for the get_pins, get_nets, and
get_cells commands. Genus will consider the ’/’ as part of the instance name when searching for an instance name (instead of treating ’/’ as the hierarchy
separator). Set this attribute before you read in the SDC constraints.
This attribute is runtime intensive.
sdc_flat_view_default
sdc_flat_view_default {false | true}
Default: false
Read-write root attribute. When enabled, Genus will change to the flat netlist view to read in the SDC commands.
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Timing--sdc_match_more_slashes
Related Information
Using Cost Groups in Genus Timing Analysis Guide for Legacy UI.
Related command: read_sdc
sdc_match_more_slashes
sdc_match_more_slashes {false| true}
Default: false
Read-write root attribute. When enabled, Genus will try to match slashes (/) as part of the name in the search pattern for the get_pins, get_nets, and
get_cells commands. Genus will consider the ’/’ as part of the instance name when searching for an instance name (instead of treating ’/’ as the hierarchy
separator).. Set this attribute before you read in the SDC constraints.
This attribute is runtime intensive.
setup
Syntax
setup <delay>
Applies to:
timing_path
Description
Default:
Data_type: delay, read only
Returns the setup time of the timing path. Setup time is the amount of time the synchronous input must show up, and be stable before capturing the edge of
clock.
show_wns_in_log
show_wns_in_log {true | false}
Default: true
Read-write root attribute. Controls the display of additional columns for the worst negative slack (WNS) value and the corresponding cost-group to the
global mapping status, global incremental optimization status, and incremental optimization status in the log file during synthesis of a design with multiple
cost-groups.
Example
The following is an extract of the log file for a design with four cost groups.
Global mapping target info==========================Cost Group ’cg4’ target slack: -130 psTarget path end-point (Port: add/out[31])......Cost Group ’cg1’
target slack: -1340 psTarget path end-point (Port: add/out[14])
Global mapping status===================== Group Total Worst Worst Total Worst Neg
CostOperation Area Slacks Slack Group Worst Path-------------------------------------------------------------------------------global_map
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Timing--skip_default_lib_check
456 -3163 -1357 cg1 a[1] --> out[14]
Global incremental target info
==============================
Cost Group ’cg4’ target slack: -224 psTarget path end-point (Port: add/out[31])........Global incremental optimization
status====================================== Group Total Worst Worst Total Worst
Neg CostOperation Area Slacks Slack Group Worst Path------------------------------------------------------------------------------
-global_inc 458 -3136 -1350 cg1 a[1] --> out[14]
Incremental optimization status
===============================
Group Total DRC Total Worst Worst Total Worst Max Neg Cost Operation
Area Slacks Trans Slack Group Worst Path------------------------------------------------------------------------------- init_iopt 458 -
3136 0 -1350 cg1 a[1] --> out[14] Incremental optimization status=============================== Group
Total DRC Total Worst Worst Total Worst Max Neg Cost Operation Area Slacks Trans Slack Group Worst Path--
----------------------------------------------------------------------------- init_delay 466 -3034 0 -1338 cg1 a[1] --> out[12]
init_drc 466 -3034 0 -1338 cg1 a[1] --> out[12] init_area 466 -3034 0 -1338 cg1 a[1] --> out[12].....
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
skip_default_lib_check
skip_default_lib_check {1 | 0 | true | false}
Default: false
Read-write root attribute. Skip default library and search in active view's library for buffers/inverters during loop breaking.
socv_derate
Syntax
socv_derate <double>
Applies to:
timing_point
Description
Default:
Data_type: double, read only
Returns the socv derate of the timing point.
spatial_path_group_effort_level
Syntax
spatial_path_group_effort_level {low | high}
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Timing--synthesis_skip_pd_timing_derate
Applies to:
cost_group
Description
Default: low
Data_type: string, read/write
While a read-write attribute, it should be set through set_path_group_options so that it is fully managed. This is passed to Innovus through iSpatial flow and
controls path_group effort level in Innovus. It will not have any influence on the current Genus session.
Related Information
Related commands: group_path
set_path_group_options
synthesis_skip_pd_timing_derate
Syntax
synthesis_skip_pd_timing_derate {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Specifies whether to disable the power domain specified by the 'set_timing_derate -power_domain' command while setting the derating factors.
Related Information
Related command: set_timing_derate
tim_ignore_data_check_for_non_endpoint_pins
tim_ignore_data_check_for_non_endpoint_pins {false | true | sdc_set_data_check_only | lib_non_seq_setup_only}
Default: false
Read-write root attribute. Controls which data-to-data timing constraints are applied if the constrained pins (to_pin) are not endpoints.
You can specify the following values:
false Takes all data-to-data constraints into account, even when the constrained pin is not an endpoint.
lib_non_seq_setup_only Specifies to only ignore constraints on instances whose library cells have timing arcs of type non_seq_setup_rising or
non_seq_setup_falling.
sdc_set_data_check_only Specifies to only ignore constraints specified with the set_data_check SDC command.
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Timing--time_recovery_arcs
true Ignores all data-to-data constraints into account. This requirement avoids breaking timing paths at the to_pin.
time_recovery_arcs
time_recovery_arcs {false | true}
Default: false
Read-write root attribute. When set to true, all paths to the asynchronous pin of a flip-flop become constrained to the recovery arc of the flip-flop. This
attribute has no affect on those asynchronous inputs of flip-flops that are not modeled with recovery arcs. This attribute does not change the ideal setting (the
value of causes_ideal_net) of the asynchronous pin’s net.
Example
set_db time_recovery_arcs true
Related Information
Affects these commands: report_timing
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: causes_ideal_net
timing_analysis_clock_propagation_mode
timing_analysis_clock_propagation_mode {sdc_control | forced_ideal}
Default: sdc_control
Read-write root attribute. Specifies timing arc attributes that have an effect on the timing analysis results.
timing_analysis_clock_source_paths
Syntax
timing_analysis_clock_source_paths {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
When set to true, the tool creates external delays and breaks the timing path at the pin/port (if the pin/port is not already a startpoint/endpoint) where a clock is
defined. This enables the clock source paths to be timed.
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Timing--timing_analysis_type
timing_analysis_type
timing_analysis_type {best_case_worst_case | ocv | single}
Default: single or best_case_worst_case
Read-write root attribute. Specifies the timing analysis type to single, best case worst case, or on-chip variation.
If you do not set this attribute and you read in one library, the tool uses single by default. In this case the tool scales the delay values based on one operating
condition.
If you do not set this attribute and you read in two libraries, the tool uses best_case_worst_case by default. In this case, the tool checks the design for two
extreme operating conditions. The software uses the maximum delays for all paths during setup checks and minimum delays for all paths during hold checks.
If you set this attribute to ocv, the tool calculates the delay for one path based on the maximum operating condition while calculating the delay for another
path based on the minimum operating condition for setup or hold checks.
Currently, Genus only supports the best_case_worst_case value.
timing_case_disabled_arcs
timing_case_disabled_arcs {libarc_a libarc_b...}
Read-only hinst attribute. Identifies the timing arcs that are disabled due to case analysis. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
Related Information
Affects these commands: report_clocks
report_qor
read_sdc
report_timing
Related attribute: (inst) timing_case_disabled_arcs
(pin/port) timing_case_logic_value
timing_defer_mmmc_obj_updates
timing_defer_mmmc_obj_updates {true | false}
Default: true
Read-write root attribute. Defers to update the multi-mode multi-corner (MMMC) objects until init_design command is executed.
When the timing_defer_mmmc_obj_updates attribute is set to false , MMMC update commands, update_constraint_mode and update_analysis_view ,
actively load new data upon execution. When all the timing information is reloaded with each update command, executing a sequence of updates can result
in multiple reloads and a subsequent degradation of performance and turn-around-time.
Genus currently does not support the false value.
Example
genus@root:> set_db / .timing_defer_mmmc_obj_updates true
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Timing--timing_disable_library_data_to_data_checks
Setting attribute of root '/': 'timing_defer_mmmc_obj_updates' = true
1 true
genus@root:> get_db / .timing_defer_mmmc_obj_updates
true
timing_disable_library_data_to_data_checks
timing_disable_library_data_to_data_checks {1 | 0 | true | false}
Default: true
Read-write root attribute. When set to true, disables the data to data timing check arcs from libraries.
timing_disable_non_sequential_checks
timing_disable_non_sequential_checks {true|false}
Default: true
Read-write root attribute. Controls whether the non_seq_setup_rising and non_seq_setup_falling pin timing attributes specified in the library are taken into
account. Set this attribute to false to take these timing arcs into account.
Related Information
Affects these commands: report_timing
syn_generic
syn_map
syn_opt
Affects this attribute: min_timing_arcs
Affected by this attribute: enable_data_check
Related attribute: type
timing_enable_get_ports_for_current_instance
Syntax
timing_enable_get_ports_for_current_instance {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, cleans up the global variables set during read_sdc execution.
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Timing--timing_no_path_segmentation
timing_no_path_segmentation
Syntax
timing_no_path_segmentation list_of_timing_checks
Applies to:
root
Description
Default:
Data_type: enum*, read/write
Displays timing paths through broken points in addition to the paths leading up to the broken points for the specified timing checks. You can specify a
combination of the following checks: set_max_delay, clock_gating, and set_data_check. Set this attribute before you read in the SDC constraints.
Example
The following command prevents breaking of the timing path for the set_max_delay and set_data_check timing checks:
set_db timing_no_path_segmentation {set_max_delay set_data_check}
Related Information
Affects these commands: report_timing
syn_generic
syn_map
syn_opt
timing_path
Syntax
timing_path <timing_path>
Applies to:
timing_point
Description
Default:
Data_type: timing_path, read only
Returns the parent 'timing_path' object.
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Timing--timing_propagate_latch_data_uncertainty
timing_propagate_latch_data_uncertainty
Syntax
timing_propagate_latch_data_uncertainty {true | false}
Applies to:
root
Description
Default: false
Data_type: delay, read/write
When set to true, uses the clock phase associated with a flush latch's data pin as the from clock phase for downstream uncertainty timing calculations
This attribute is not directly used by Genus but instead, when set, is shared with Innovus.
Related Information
Related commands: syn_opt
set_global
timing_report_default_formatting
timing_report_default_formatting {stage_delay | split_delay}
Default: stage_delay
Read-write root attribute. Controls the report timing format. If set to split_delay, interconnect delays are also included.
Related Information
Affects this command: report_timing
timing_report_enable_common_header
timing_report_enable_common_header {false | true}
Default: false
Read-write root attribute. Reports the timing using the common UI format.
Related Information
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Timing--timing_report_endpoint_fields
timing_report_endpoint_fields
timing_report_endpoint_fields list_of_strings
Default: id slack endpoint group view
Read-write root attribute. Specifies the default set of fields to be used for the endpoint timing report.
Related Information
Affects this command: report_timing
timing_report_exception_data
timing_report_exception_data {false| true}
Default: false
Read-write root attribute. Controls whether to report the exception cross-linking information.
Related Information
Affects this command: report_timing
timing_report_fields
timing_report_fields list_of_strings
Default: timing_point flags arc edge cell fanout load transition delay arrival instance_location
Read-write root attribute. Specifies the default set of fields to be used for the timing report.
Valid field names are: timing_point flags id arc edge cell fanout load transition transition_mean transition_sigma delay delay_mean
delay_sigma arrival arrival_mean arrival_sigma user_derate user_mean_derate user_sigma_derate incr_derate slew_derate total_derate
aocv_derate socv_derate stage_count power_domain lib_set wire_length instance_location pin_location module frc voltage
A derate of 1.0 is not reported as 1.0, but as "-".
Related Information
Affects this command: report_timing
timing_report_load_unit
timing_report_load_unit {ff | fF | pf | pF}
Default: ff
Read-write root attribute. Specifies the load unit to be used in the timing report.
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Timing--timing_report_path_type
Related Information
Affects this command: report_timing
timing_report_path_type
timing_report_path_type {full | full_clock | endpoint | summary}
Default: full
Read-write root attribute. Controls the path type shown in the timing report.
You can specify the following values:
endpoint Generates an end point report for each path consisting of an endpoint, cause, slack, arrival time, required time, and phase.
full Generates a report that displays the full path with accompanying required time and slack calculation.
full_clock Reports the full clock path (Other End Path) in addition to the full data path (Timing Path) if the path reported ends at a timing check.
summary Generates a summary report for each path consisting of a start point, endpoint, cause, slack, arrival time, required time, and phase.
The -path_type option of the report_timing command overwrites the attribute setting.
Related Information
Affects this command: report_timing
timing_report_unconstrained
Syntax
timing_report_unconstrained {false | true}
Applies to:
root
Description
Default: false
Data_type: bool. read/write
Specifies whether to report the unconstrained paths in the timing report. When set to true, only unconstrained paths are reported.
The -unconstrained option of the report_timing command overwrites the attribute setting.
Related Information
Affects this command: report_timing
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Timing--timing_spatial_derate_chip_size
timing_spatial_derate_chip_size
timing_spatial_derate_chip_size float
Default: 1e+30
Read-write root attribute. Specifies the static chip size (in microns) to be used for SOCV analysis. If this attribute is set to any other value then the default,
this value will be used for the chip size.
total_derate
Syntax
adjust_derate <double>
Applies to:
timing_point
Description
Default:
Data_type: double, read only
Returns the total derate of the timing point.
trace_retime
Syntax
trace_retime {false | true}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
When set to true, the specified register is "marked" so that it can be retrieved and identified after retiming optimization. All registers that were marked with this
attribute can be retrieved with the retime_original_registers attribute.
This attribute is meant to be used for debugging purposes only due to potential performance implications.
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Timing--transition_type
Related Information
Affects these attributes: retime_original_registers
Related attributes: dont_retime
retime
retime_hard_region
retime_reg_naming_suffix
transition_type
Syntax
transition_type <string>
Applies to:
timing_point
Description
Default:
Data_type: string, read only
Returns the transition type of the timing point.
ui_units_capacitance_reporting
Syntax
ui_units_capacitance_reporting { }
Applies to:
root
Description
Default: ff
Data_type: enum, read/write
Capacitance reporting unit for CUI. Valid values are 1pf, 1ff, 10ff, and 100ff.
ui_units_timing_reporting
Syntax
ui_units_timing_reporting { }
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Timing--use_multi_clks_latency_uncertainty_optimize
Applies to:
root
Description
Default: ps
Data_type: enum, read/write
Time reporting unit for CUI. Valid values are 1ns, 1ps, 10ps, and 100ps.
use_multi_clks_latency_uncertainty_optimize
use_multi_clks_latency_uncertainty_optimize {false | true}
Default: false
Read-write root attribute. Enables optimization to take into account network and source latencies on the pins and ports.
Related Information
Affects these commands: report_timing
set_clock_latency -clock
syn_generic
syn_map
syn_opt
Affects these attributes: (pin) setup_uncertainty_by_clock
(port) setup_uncertainty_by_clock
(pin) source_late_latency_by_clock
(port) source_late_latency_by_clock
use_multi_clks_latency_uncertainty_report
use_multi_clks_latency_uncertainty_report {false | true}
Default: false
Read-write root attribute. Enables the timing analysis engine to take into account network and source latencies on the pins and ports.
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Timing--user_mean_derate
Related Information
Affects these commands: report_timing
set_clock_latency -clock
syn_generic
syn_map
syn_opt
Affects these attributes: (pin) setup_uncertainty_by_clock
(port) setup_uncertainty_by_clock
(pin) source_late_latency_by_clock
(port) source_late_latency_by_clock
user_mean_derate
Syntax
user_mean_derate <double>
Applies to:
timing_point
Description
Default:
Data_type: double, read only
Returns the user derate of the timing point.
user_sigma_derate
Syntax
user_mean_derate <double>
Applies to:
timing_point
Description
Default:
Data_type: double, read only
Returns the user derate of the timing point.
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Timing--write_mmmc_forking_enabled
write_mmmc_forking_enabled
Syntax
write_mmmc_forking_enabled {true | false}
Applies to:
root
Description
Default:
Data_type: bool, read/write
Returns if mmmc_forking is allowed or not. If 'true', forking is enabled, which saves runtime. If 'false', forking is disabled, which saves memory.
Example
genus@root:> get_db write_mmmc_forking_enabledResult -> true/false
write_sdc_use_libset_name_set_dont_use
write_sdc_use_libset_name_set_dont_use {false | true}
Default: false
Read-write root attribute. Specifies whether to add the library set name in the set_dont_use commands written out by the write_sdc command.
Related Information
Affects this command: write_sdc
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Datapath
21
Datapath
The chapter describes the following attributes in the 'dp' category:
apply_booth_encoding control_logic_optimization dp_analytical_opt
dp_area_mode dp_csa dp_csa_factorize
dp_rewriting dp_sharing dp_speculation
dp_ungroup_during_syn_map dpopt_instance_constant_input_based_speculation dpopt_power_opto
dpopt_power_opto_scaling dpopt_toggle_skew_threshold_for_booth_encoding hdl_pipeline_comp
is_booth_encoded one_pass_formal_verification
apply_booth_encoding
apply_booth_encoding {nonbooth | auto_bitwidth | auto_togglerate | manual | inherited}
Description
Default: inherited (for hinst/inst), auto_bitwidth (for root)
Data_type: enum, read/write
Applies booth encoding by using user-specified method (for all instances or a specified instance).
Applies to:
hinst
inst
root
control_logic_optimization
control_logic_optimization {advanced | basic | inherited | none}
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Datapath--dp_analytical_opt
Description
Default: inherited (for design/module), basic (for root)
Data_type: enum, read/write
Controls the optimization of control logic (described in the RTL through conditional constructs like case statements, if-
then-else statements, conditional selects, and so on) during generic synthesis.
You can specify any of the following values:
basic Applies basic optimization.
advanced Applies advanced level optimization.
inherited Inherits the value from the control_logic_optimization root attribute.
Note: Applies only to design and module.
none Turns off optimization.
All control optimization transformations are verifiable. The advanced transformations might result in better QoR
but can also increase the runtime. For best results, set this attribute after you have elaborated the design, but
before generic synthesis.
Applies to:
design
module
root
Related Information
Affects this command: syn_generic
dp_analytical_opt
dp_analytical_opt {standard | extreme | off}
Description
Default: standard
Data_type: enum, read/write
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Datapath--dp_area_mode
Specifies the effort level for analytical optimization of datapath logic. You can specify any of the following values:
standard Enables analytical optimizations that reduce area without degrading timing.
extreme Enables the most aggressive area-mode analytical optimizations, possibly degrading timing.
off Disables analytical optimization.
For best results, set the attribute prior to the elaborate command.
Analytical optimization is not affected by the values of these attributes:
syn_generic_effort
dp_area_mode
Applies to:
root
Related Information
Affected commands: elaborate
syn_generic
dp_area_mode
dp_area_mode {true | false}
Description
Default: false
Data_type: bool, read/write
Setting the attribute to true enables datapath optimizations that focus on improving area results.
Applies to:
root
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Datapath--dp_csa
Related Information
Affects these commands: elaborate
syn_generic
dp_csa
dp_csa {basic | inherited | none}
Description
Default: inherited (for design/module), basic (for root)
Data_type: enum, read/write
Controls the carry-save adder (CSA) transformations in datapath synthesis. By default, CSA transformations are
performed when synthesis is performed with the -effort option set to high.
You can specify any of the following values:
basic Applies basic transformation.
inherited Inherits the value from the
dp_csa root attribute.
Note: Applies only to
design and module.
none Turns off transformation.
Applies to:
design
module
root
Related Information
Affects this command: syn_generic
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Datapath--dp_csa_factorize
dp_csa_factorize
dp_csa_factorize {basic | inherited | none}
Description
Default: inherited (for design/module), basic (for root)
Data_type: enum, read/write
Controls datapath csa_factorize in syn_generic.
You can specify any of the following values:
basic Enables factorization optimization.
inherited Inherits the value from the dp_csa_factorize root attribute.
Note: Applies only to design and module.
none Turns off optimization.
Applies to:
design
module
root
dp_rewriting
dp_rewriting {advanced | basic | inherited | none}
Description
Default: inherited (for design/module), basic (for root)
Data_type: enum, read/write
Controls how the datapath rewriting optimization is applied during synthesis and generic optimization with 'high' effort.
You can specify any one of the following values:
advanced Applies advanced optimization
basic Applies basic optimization.
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Datapath--dp_sharing
inherited Inherits the value from the root attribute.
Note: Applies only to design and module.
none Turns off optimization.
All basic transformations are verifiable. The advanced transformations might result in better QoR but not all of
them are verifiable.
Applies to:
design
module
root
Related Information
Affects this command: syn_generic
dp_sharing
dp_sharing {inherited | none | advanced}
Description
Default: inherited (for design/hinst/module) and advanced (for root)
Data_type: enum, read/write
Controls resource sharing in datapath on the design during syn_generic with high effort. If the value is set to inherited,
the effort level of the optimization on the design will be identical to ("inherited from") the effort specified at the root.
inherited Inherits the value from the dp_sharing root attribute.
Note: Only applies to design, hinst, and module.
advanced Applies advanced level optimization.
none Turns off optimization.
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Datapath--dp_speculation
Example
The following command turns off RTL sharing transformations:
set_db dp_sharing none
Applies to:
design
hinst
module
root
Related Information
Affects this command: syn_generic
dp_speculation
dp_speculation {basic | inherited | none}
Description
Default: inherited (for design/module), basic (for root)
Data_type: enum, read/write
Controls RTL speculation (unsharing) transformations in datapath synthesis.
You can specify any of the following values:
basic When set to basic and the dp_analytical_opt attribute is set to off, speculation transformations are
performed when synthesis is performed with the syn_generic_effort attribute set to high. In this case,
speculation can only be applied to operators driven by a single MUX.
When set to basic and the dp_analytical_opt attribute is set to standard or extreme, speculation are
applied to operators driven by a chain of MUXES. In this case, speculation is independent of the
syn_generic_effort setting.
inherited Inherits the value from the dp_speculation root attribute.
Note: Only applies to design and module.
none Turns off RTL speculation (unsharing) transformations.
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Datapath--dp_ungroup_during_syn_map
Applies to:
design
module
root
Related Information
Affects this command: syn_generic
Affected by these attributes: dp_analytical_opt
syn_generic_effort
dp_ungroup_during_syn_map
dp_ungroup_during_syn_map {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether the inferred datapath hierarchies and instantiated ChipWare hierarchies should be ungrouped during
mapping (syn_map). When set to false, ungrouping occurs during optimization (syn_opt).
Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
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Datapath--dpopt_instance_constant_input_based_speculation
dpopt_instance_constant_input_based_speculation
Syntax
dpopt_instance_constant_input_based_speculation {false | true}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
Controls constant input based datapath speculation of datapath module in syn_generic.
dpopt_power_opto
dpopt_power_opto {false | true}
Description
Default: false
Data_type: bool (root), enum (design and module), read/write
Controls the datapath power optimization flow. Some runtime hit is expected.
Applies to:
design
module
root
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Datapath--dpopt_power_opto_scaling
Related Information
Datapath Power Optimization in the Datapath Synthesis Guide.
Affects this command: syn_generic
Related attribute: dpopt_power_opto_scaling
dpopt_power_opto_scaling
Syntax
dpopt_power_opto_scaling <double>
Applies to:
root
Description
Default: 1.0
Data_type: double, read/write
Adjusts the tradeoff between area and power within the datapath power optimization flow. For example:
Smaller (< 1.0) values give less weight to predicted power and area change has a bigger impact on datapath
decisions.
Bigger (> 1.0) values accept larger area degradations if the power is expected to improve.
The recommended range is '0.1' to '10.0'.
Related Information
Datapath Power Optimization in the Datapath Synthesis Guide.
dpopt_toggle_skew_threshold_for_booth_encoding
Syntax
dpopt_toggle_skew_threshold_for_booth_encoding <integer>
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Datapath--hdl_pipeline_comp
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Sets the integer value for the skew threshold when in the auto_togglerate mode for apply_booth_encoding.
hdl_pipeline_comp
Syntax
hdl_pipeline_comp {false | true}
Applies to:
design
module
Description
Default: false
Data_type: bool, read only
Specifies whether the module represented by the particular module object is a pipelined ChipWare component that
needs to be retimed.
is_booth_encoded
Syntax
is_booth_encoded {true | false}
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Datapath--one_pass_formal_verification
Applies to:
hpin
hport
pg_pin
pin
port
Description
Default: false
Data_type: bool, read/write
Specifies the user-defined booth encoded setting to input port.
one_pass_formal_verification
Syntax
one_pass_formal_verification {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enables a synthesis flow that allows Conformal LEC to perform a single, RTL-to-final netlist comparison. The flow
prevents datapath modules from being ungrouped by syn_map and syn_opt.
Using this attribute may affect the QoR.
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Datapath--one_pass_formal_verification
Related Information
Affects these commands: syn_map
syn_opt
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Optimization
22
Optimization
alias_names allow_seq_in_out_phase_opto area
assigned_library_set backup_power_pins base_cell
boundary_opto default design
design Attributes in Opt direction dont_touch_sources
dont_use_qbar_pin hdl_instantiated hinst
hpin_busses hport_busses hports
inherited_preserve inverted_phase iopt_allow_inst_dup
is_black_box is_buffer is_combinational
is_cw_component is_dont_touch is_flop
is_interface_timing is_inverter is_latch
is_macro is_master_slave_flop is_master_slave_lssd_flop
is_memory is_pad is_phase_inverted
is_physical is_sequential is_tristate
lib_cells map_to_multibit_bank_label map_to_multibit_register
map_to_mux map_to_register merge_combinational_hier_instance
module module attributes for Opt multibit_rejection_reason
negative_edge_clock optimize_constant_0_seq optimize_constant_1_seq
optimize_merge_seq parent pg_hports
pg_nets_ls pg_pins pin_busses
primitive_function relaxed_seq_map_constraints retime_ssw_sync_enable
root Attributes in Optimization state_retention_rule std_cell_main_rail_pin
unique_versions unresolved usable_flop
usable_latch user_defined
See also:
is_backside
location
type
voltage
alias_names
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Optimization--allow_seq_in_out_phase_opto
Syntax
alias_names <string>
Applies to:
hnet
net
Description
Default:
Data_type: string, read only
Returns the 'alias_names' of nets and hierarchical nets.
Example
@genus:root:> get_db net:top/n_8 .alias_names
Result -> alias_name_n_8 a_n_8
allow_seq_in_out_phase_opto
allow_seq_in_out_phase_opto {true|false}
Default: true
Read-write inst attribute. Controls whether phase inversion is allowed on sequential gates during global mapping. By default, phase inversion is allowed.
Related Information
Affects this command: syn_map
area
area float
Read-only hinst attribute. Returns the cell area of the hierarchical instance. An estimate is used for unmapped logic. This is a computed attribute. Computed
attributes are potentially very time consuming to process and not listed by the vls command by default.
Related Information
Related attribute: (inst) area
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Optimization--assigned_library_set
assigned_library_set
Syntax
assigned_library_set <inst>
Applies to:
inst
Description
Default:
Data_type: inst | null instance, read only
Returns the library_set associated with this instance.
Example
The following command returns the library_set associated with this instance:
get_db inst:top/b1 .assigned_library_set
library_set:LS_1
backup_power_pins
backup_power_pins backup_power_pins
Read-only inst attribute. Returns the back up power pins of the instance.
Related Information
Related attributes: (lib_cell) is_black_box
base_cell
base_cell base_cell
Read-only inst attribute. Returns the base_cell for the mapped instance.
boundary_opto
Syntax
boundary_opto {true | false | strict_no}
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Optimization--default
Applies to:
module
Description
Default: true
Data_type: enum, read/write
Controls boundary optimization on the module and hierarchical pin inversion.
You can specify one of the following values:
false Limits boundary optimization to hard-region like boundary optimization type. Boundary optimization going into a module and affecting the
module is allowed, but not any optimization going outside the module, impacting logic outside the module.
Constant propagation, or equal-opposite signal merging is allowed at input pins only, but not at output pins of the module. Removal of logic not
driving any primary output is possible at output pins, but not at input pins.
Hierarchical pin inversion is disabled at input and output pins, because it always affects logic inside and outside the module.
strict_no Completely disables boundary optimization during synthesis on the module.
true Allows full boundary optimization during synthesis on the module.
By default, Genus performs boundary optimization during synthesis for all modules in the design.
To exclude individual pins from boundary optimization, use the 'preserve' attribute.
Setting this attribute to 'false' prevents ungrouping of the module.
Related Information
Affects these commands: syn_generic
syn_map
Affected by this attribute: prune_unused_logic
Affects these attributes: boundary_optimize_constant_hpins
boundary_optimize_equal_opposite_hpins
boundary_optimize_invert_hpins
default
Syntax
default {false | true}
Applies to:
library_domain
power_mode
Description
Default: false
Data_type: bool, read/write (library_domain), read only (power_mode)
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Optimization--design
library_domain Indicates whether the library domain is the default library domain. By default, the first library domain for which you specify the libraries,
becomes the default library domain. Set this attribute to true for the desired domain. The tool automatically changes the value of the
previous default library domain to false.
power_mode Indicates whether the power mode was identified as the default power mode in the CPF file.
Related Information
Affected by this command: read_power_intent
Related attributes: is_default
design
Syntax
design <design>
Applies to:
all objects
Description
Default:
Data_type: design, read only
Returns the design to which the 'object' belongs.
Example
get_db analysis_view:dtmf_recvr_core/view_wcl_slow .design
design:dtmf_recvr_core
design Attributes in Opt
analysis blackboxes clusters
constant_0_loads constant_0_nets constant_1_loads
constant_1_nets constants def_pins
dont_touch dont_touch_effective dont_touch_file
dont_touch_reason dont_use_base_cell_set dont_use_cells
dont_use_cells_effective fills hdl_v2001
hinsts hnets hpins
ignore_library_drc ignore_library_max_fanout insts
insts_area local_hinsts local_hnets
local_hpins local_insts local_pins
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Optimization--design
max_cap_cost max_capacitance max_fanout
max_fanout_cost max_trans_cost max_transition
min_cap_cost min_fanout_cost min_trans_cost
modules net_area nets
num_insts num_local_hpins num_nets
num_pg_nets pg_hnets pg_nets
pg_ports physical_cell_area pins
pinstances pnets port_busses
ports preserve protected
retime retime_period_percentage route_types
seq_reason_deleted slots specialnets
styles total_area track_patterns
use_base_cell_set use_cells use_only_on_power_critical_nets
Some others are:
route_rules
analysis
Syntax
analysis <list_of_timing_bins>
Applies to:
design
Description
Default:
Data_type: timing_bin*, read only
Returns a list of timing_bin objects in the design.
blackboxes
Syntax
blackboxes <blackbox>
Applies to:
design
Description
Default:
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Optimization--design
Data_type: blackbox*, read only
Returns the list of 'blackbox' object types.
clusters
Syntax
clusters <cluster>
Applies to:
design
Description
Default:
Data_type: cluster*, read only
Returns the list of 'cluster' object types.
constant_0_loads
Syntax
constant_0_loads <list_of_pins_and_ports>
Applies to:
design
module
Description
Default:
Data_type: hpin* | pin* | constant* | pg_pin* | hport* | port*, read only
Returns a list of pins, ports, and busses in the design/module driven by constant 0.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
constant_0_nets
Syntax
constant_0_nets <list_of_nets>
Applies to:
design
module
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Optimization--design
Description
Default:
Data_type: net* | hnet*, read only
Returns a list of nets driven by constant 0.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
constant_1_loads
Syntax
constant_1_loads <list_of_pins_and_ports>
Applies to:
design
module
Description
Default:
Data_type: hpin* | pin* | constant* | pg_pin* | hport* | port*, read only
Returns a list of pins, ports, and busses in the design/module driven by constant 1.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
constant_1_nets
Syntax
constant_1_nets <list_of_nets>
Applies to:
design
module
Description
Default:
Data_type: net* | hnet*, read only
Returns a list of nets driven by constant 1.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
constants
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Optimization--design
Syntax
constants <list_of_constants>
Applies to:
design
hinst
Description
Default:
Data_type: constant*, read only
Returns a list of constant objects in the design/hierarchical instance.
def_pins
Syntax
def_pins <list_of_def_pins>
Applies to:
design
Description
Default:
Data_type: def_pin*, read only
Returns a list of the def_pin objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
dont_touch
Syntax
dont_touch {true | false}
Applies to:
Object Default Data_type
base_cell false bool, read/write
lib_cell false bool, read/write
Description
Controls whether instances of this cell should be preserved during optimization.
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Optimization--design
Syntax
dont_touch {false | true | add_ok | add_invert_ok | const_prop_delete_ok | const_prop_size_delete_ok | delete_ok | invert_ok |
map_size_ok | size_delete_ok | size_ok | size_same_footprint_ok | size_same_height_ok | none}
Applies to:
Object Default Data_type Description
design false enum, Controls the optimization of the design. This setting will apply to all instances within the design unless overridden at a
read/write lower level hinst or on the inst object itself. The dont_touch_effective attribute on each child inst and hinst will return the
resolved value.
hinst none enum, Controls optimization of a mapped hierarchical instance. The setting of this attribute will set the dont_touch attribute on
read/write the parent module of this hinst and all hinsts of the same module. This setting will apply to all insts within the hinst unless
overridden at a lower level hinst or on the inst object itself. The dont_touch_effective attribute on each child inst and
hinst will return the resolved value.
hnet false enum, Controls the preservation of the hnet during optimization. Setting this will preserve all connections on the hnet at the level
read/write of hierarchy where the hnet exists (it will stop at the hpins and hports connected to this hnet).
hpin none enum, Controls the preservation of the hpin during synthesis. A preserved hpin means the logical function of the hpin must be
read/write preserved to maintain a simulation or test-point hpin in the netlist. However, the name does not need to be preserved.
inst none enum, Controls optimization of a mapped instance.
read/write
module false bool, Controls the optimization of the module. Setting this attribute will set the dont_touch attribute on all hinsts of the same
read/write module. This setting will apply to all instances within the hinst unless overridden at a lower level hinst or on the inst
object itself. The dont_touch_effective attribute on each child inst and hinst will return the resolved value.
net false enum, Controls the preservation of the net segment during optimization. Setting this attribute will preserve all connections on
read/write this net. When set, this overrides any setting on hnets of this net. The use attribute for the net can also cause the net to be
preserved.
pin none enum, Controls the preservation of the pin during optimization.
read/write
Description
You can set the following values:
value description
add_ok Allows adding or duplicating an object.
Available in these objects: hpin/pin
add_invert_ok Allows changing the object's polarity and adding or duplicating it.
Available in these objects: hpin/pin
const_prop_delete_ok Allows deletion if the object has no fanout, and is propagating a constant through the object.
Available in these objects: design/module/hinst/inst
const_prop_size_delete_ok Allows deletion if the object has no fanout, resizing, or is propagating a constant through the object.
Available in these objects: design/module/hinst/inst
delete_ok Allows deletion of the object during optimization if it has no fanout (driving logic).
Available in these objects: design/module/hinst/inst/hnet/net/hpin/pin
invert_ok Allows to change the polarity of the object.
Available in these objects: hpin/pin
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Optimization--design
map_size_ok Allows resizing, and unmapping and remapping of mapped sequential instances during optimization.
Available in these objects: design/module/hinst/inst
size_delete_ok Allows resizing or deleting an object during optimization if it has no fanout.
Available in these objects: design/module/hinst/inst
size_ok Allows resizing an object during optimization.
Available in these objects: design/module/hinst/inst
size_same_footprint_ok Available in these objects: design/module/hinst/inst
size_same_height_ok Allows resizing with cells of the same height.
Available in these objects: design/module/hinst/inst
false Allows logic changes to any object in the design during optimization: mapping, resizing, deleting, constant propagation
through the objects.
Available in these objects: design/module/hinst/inst/hnet/net/hpin/pin
true Prevents logic changes to any object in the design during optimization.
Available in these objects: design/module/hinst/inst/hnet/net/hpin/pin
none Indicates that the object has no optimization constraints and inherits from module or hinst.
Available in these objects: design/module/hinst/inst/hpin/pin
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affects this attribute: map_to_multibit_bank_label
Related attribute: dont_touch_effective
dont_touch_effective
Syntax
dont_touch_effective {const_prop_delete_ok | const_prop_size_delete_ok | delete_ok | map_size_ok | size_delete_ok | size_ok |
size_same_height_ok | none | false | true}
Applies to:
design
hinst
inst
net
Description
Default: false
Data_type: enum, read only
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Optimization--design
design Defines the effective (most pessimistic) preservation status of a design during optimization. This attribute has all the values mentioned in the
syntax.
hinst Defines the effective (most pessimistic) preservation status of a hierarchical instance during optimization based on the sources found in the
'dont_touch_sources' attribute. This attribute has all the values mentioned in the syntax.
inst Defines the effective (most pessimistic) preservation status of an instance during optimization based on the sources found in the
'dont_touch_sources' attribute. This attribute has all the values mentioned in the syntax.
net Defines the effective (most pessimistic) preservation status of a net during optimization. This attribute has only the following values:
delete_ok | false | true
This attribute can have the following values:
const_prop_delete_ok Indicates that the instance can be deleted and that constants can be propagated through it.
const_prop_size_delete_ok Indicates that the instance can be resized or deleted and that constants can be propagated through it.
delete_ok Indicates that the instance can be deleted if it has no fanout, but cannot be resized.
map_size_ok Indicates that the instance can be mapped or sized (but not deleted). Applies only to sequential instances so cannot be
applied on the module or hinst object.
size_delete_ok Indicates that the instance can be resized or deleted if it has no fanout.
size_ok Indicates that the instance can only be resized.
size_same_footprint_ok
size_same_height_ok Indicates that the instance can only be resized to a cell of the same height.
none Indicates that the instance is unconstrained.
true Indicates that the instance can not be touched or optimized.
false Indicates that the instance can be mapped, sized, deleted, and that constants can be propagated through it.
Related Information
Related attribute: dont_touch_sources
dont_touch_file
Syntax
dont_touch_file <filename>
Applies to:
design
hinst
hnet
hpin
inst
module
pin
Description
Default:
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Genus Attribute Reference
Optimization--design
Data_type: string, read/write
Specifies the file name from where the dont_touch attribute is set.
dont_touch_reason
Syntax
dont_touch_reason {inherited | set_dont_touch | set_dont_touch_network | upf | user_attribute}
Applies to:
design
hinst
hnet
hpin
inst
module
pin
Description
Default:
Data_type: string, read/write
Specifies the reason for setting dont_touch on an object. The attribute can have the following values:
inherited Indicates that the dont_touch property is inherited from the parent module.
set_dont_touch Indicates that dont_touch is set during setting of sdc constraint set_dont_touch.
set_dont_touch_network Indicates that dont_touch is set during setting of sdc constraint set_dont_touch_network.
upf Indicates that dont_touch is set during the power intent flow.
user_attribute Indicates that dont_touch is set by the user.
dont_use_base_cell_set
Syntax
dont_use_base_cell_set <base_cell_set>
Applies to:
design
hinst
inst
Description
Default:
Data_type: base_cell_set, read/write
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Optimization--design
design Specifies not to use lib_cells from the specified set during synthesis and optimization. The tool generates an error if there are no other lib_cells
available to synthesize the design other than in the set.
hinst Specifies not to use lib_cells from the specified set during synthesis and optimization. The tool generates an error if there are no other lib_cells
available to synthesize the design other than in the set.
By default, the instance attribute inherits the value of the parent instance attribute. If the values of this attribute differ for the hierarchical instances of
a module, these hierarchical instances get automatically uniquified.
inst Specifies not to use lib_cells from the specified set during synthesis and optimization. The tool generates an error if there are no other lib_cells
available to synthesize the design other than in the set.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
dont_use_cells
Syntax
dont_use_cells {list_of_cells}
Applies to:
design
hinst
module
Description
Default:
Data_type: base_cell, read/write
design List of cell names to disallow for this design during optimization. This can be overridden at a lower hinst level.
Overrides cells in the use_cells list for the design. If a cell is added to this list that is already in the use_cells list, it will be removed from the
use_cells list so that both the lists (use_cells and dont_use_cells) are non-overlapping.
hinst Specifies not to use cells from the set during synthesis and optimization of this hierarchical instance.
Input for this attribute is a list of cell names to disallow for this hierarchical instance during optimization.
Setting on an hierarchical instance is applied to all hierarchical instances that share the same module with the hierarchical instance given as
argument and all the hierarchical instance siblings inherit the same value. All lib_cells of each base_cell will be allowed.
If a cell is added to this list that is already in the use_cells list, it will be removed from the use_cells list so that both the lists (use_cells and
dont_use_cells) are non-overlapping.
module List of cell names to disallow for this module during optimization. Setting this applies to all hinsts sharing the module.
Setting this applies to all hierarchical instances sharing this module.
If a cell is added to this list that is already in the use_cells list, it will be removed from the use_cells list so that both the lists (use_cells and
dont_use_cells) are non-overlapping.
Setting on hierarchical instance of this module will update the module setting of this attribute.
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Optimization--design
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affects this attribute: use_cells
dont_use_cells_effective
Syntax
dont_use_cells_effective {list_of_cells}
Applies to:
design
hinst
module
Description
Default:
Data_type: base_cell, read only
design The resolved list of all cell names to disallow for the design based on the library dont_use and the dont_use_cells and use_cells attributes of the
design.
hinst The resolved list of all cell names to disallow for this hierarchical instance, based on the library dont_use and the dont_use_cells and use_cells
attributes of this hinst or the closest parent hierarchical instance with a non-empty list.
module The resolved list of all cell names to disallow for all the hierarchical instances sharing this module based on the library dont_use and the
dont_use_cells and use_cells attributes of the module.
Related Information
Related commands: syn_generic
syn_map
syn_opt
Related attributes: dont_use
dont_use_cells
use_cells
fills
Syntax
fills {list_of_fills}
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Optimization--design
Applies to:
design
Description
Default:
Data_type: fill*, read only
Returns a list of fill objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by this command: read_def
Related attributes: fill Attributes
hdl_v2001
Syntax
hdl_v2001 <string>
Applies to:
design
hinst
hnet
hpin
hport
inst
module
net
pg_pin
pin
port
Description
Default:
Data_type: string, read/write only
design Sets the specified Verilog 2001 attributes on this design.
hinst Sets the specified Verilog 2001 attributes on this hierarchical instance.
hnet
hpin Sets the specified Verilog 2001 attributes on this hierarchical pin.
hport Sets the specified Verilog 2001 attributes on this hierarchical port.
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Optimization--design
inst Sets the specified Verilog 2001 attributes on this instance.
module Sets the specified Verilog 2001 attributes on this module.
net
pg_pin Sets the specified Verilog 2001 attributes on this instance pgpin. The instance can be a primitive, gate, blackbox, logic abstract, or hierarchical
instance.
pin Sets the specified Verilog 2001 attributes on this instance pin. The instance can be a primitive, gate, blackbox, logic abstract, or hierarchical
instance.
port Sets the specified Verilog 2001 attributes on this port.
Examples
The following command removes the Verilog 2001 attributes from the design:
get_db hinst:test/u0 .hdl_v2001
{top_inst_name="u0"}
The following command retrieves the Verilog 2001 attributes set on instance test/u6:
get_db inst:test/u6 .hdl_v2001
{prcode}
Related Information
Set by this command: read_netlist
hinsts
Syntax
hinsts {list_of_hinst}
Applies to:
design
hinst
group
module
Description
Default:
Data_type: hinst*(design, hinst, group), inst* | hinst* (module), read only
Returns all hierarchical instances in the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by this command: read_def
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Optimization--design
hnets
Syntax
hnets {list_of_hnets}
Applies to:
design
hinst
hnet
net
Description
Default:
Data_type: hnet*(design, hinst), net* | hnet* (hnet, net), read only
Returns a list of all hierarchical nets in the design/hierarchical instance and the segments of the net.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
hpins
Syntax
hpins {list_of_hpins}
Applies to:
design
hinst
Description
Default:
Data_type: hpin*, read only
Returns all hierarchical pins of this design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
ignore_library_drc
Syntax
ignore_library_drc {false | true}
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Optimization--design
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Controls the use of design rule constraints from the technology library. When set to true, forces Genus to ignore any design rule constraints specified in the
technology library. You can use this attribute in conjunction with the max_capacitance, max_fanout, and max_transition attributes to set looser design rule
constraints than the ones appearing in the technology library. Use the ignore_library_drc attribute with care. The ignore_library_drc attribute applies to the
top-level module and all modules.
Related Information
Affects these commands: report_design_rules
syn_opt
Affects these attributes: drc_first
ignore_library_max_fanout
max_fanout
max_transition
min_pulse_width
timing_disable_internal_inout_net_arcs
ignore_library_max_fanout
Syntax
ignore_library_max_fanout {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Determines whether to use the maximum fanout design rule limits from the technology library.
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Optimization--design
Related Information
Affects these commands: report_design_rules
syn_opt
Affected by this attribute: ignore_library_drc
Affects this attribute: max_fanout
Related attributes: drc_first
max_fanout
max_transition
min_pulse_width
timing_disable_internal_inout_net_arcs
insts
Syntax
insts {list_of_insts}
Applies to:
design
hinst
Description
Default:
Data_type: inst*, read only
Returns all leaf instances in the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
insts_area
Syntax
insts_area <float>
Applies to:
design
module
Description
Default:
Data_type: area, read only
Returns the cell area of the design/module.
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Optimization--design
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
local_hinsts
Syntax
local_hinsts {list_of_hinsts}
Applies to:
design
hinsts
Description
Default:
Data_type: hinst*, read only
Returns a list of hierarchical instances at the top-level (local level) of the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
local_hnets
Syntax
local_hnets {list_of_hnets}
Applies to:
design
hinsts
Description
Default:
Data_type: hnets*, read only
Returns a list of all hierarchical nets at the top-level (local level) of the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
local_hpins
Syntax
local_hpins {list_of_hpins}
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Optimization--design
Applies to:
design
hinsts
Description
Default:
Data_type: hpin*, read only
Returns a list of all hierarchical pins at the top-level (local level) of the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
local_insts
Syntax
local_insts {list_of_insts}
Applies to:
design
hinsts
Description
Default:
Data_type: inst*, read only
Returns a list of all leaf instances at the top-level (local level) of the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
local_pins
Syntax
local_pins {list_of_pins}
Applies to:
design
hinsts
Description
Default:
Data_type: pin*, read only
Returns a list of the pins of all leaf instances at the top-level (local level) of the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
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Optimization--design
max_cap_cost
Syntax
max_cap_cost <string>
Applies to:
design
Description
Default:
Data_type: capacitance, read only
Returns the sum of the capacitance violations on all pins and ports in the design. A violation is flagged when the actual capacitance on a pin or port is larger
than the max_capacitance constraint (attribute).
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related command: report_design_rules
Affected by these attributes: timing_disable_internal_inout_net_arcs
max_capacitance
Related attributes: max_fanout_cost
max_trans_cost
max_capacitance
Syntax
max_cap_cost <no_value | float>
Applies to:
design
hpin
lib_pin
pg_lib_pin
port
pin
Description
Default: INFINITY (lib_pin and pg_lib_pin), no_value (design, hpin, port, and pin)
Data_type: capacitance, read/write
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Optimization--design
design Specifies the maximum capacitance design rule limit in femtofarads for all nets in a design. The resolution is 1/10. When optimizing a design,
Genus attempts to satisfy all design rule constraints. These constraints can come from attributes on a module or port, or from the technology
library.
If set to no_value, no design-level constraint is applied, although design rules may still be inferred from port attributes or from the technology
library.
hpin
lib_pin Specifies the maximum capacitance in femtofarads that an output pin can drive.
This attribute has no value for input pins.
pg_lib_pin Specifies the maximum capacitance in femtofarads that an output pin can drive.
This attribute has no value for input pins.
port Specifies the maximum capacitance design rule constraint in femtofarads for all nets connected to the port. The resolution is 1/1000. When
optimizing a design, Genus attempts to satisfy all design rule constraints. These constraints can come from attributes on a block or port, or
from the technology library.
If set to no_value, no port constraint is applied, although design rules may still be inferred from block attributes or from any driving pin that has
been applied to the port.
pin
Related Information
Affects these commands: report_design_rules
report_timing
syn_opt
Related attributes: drc_first
drc_max_cap_first
ignore_library_drc
max_fanout
max_transition
max_fanout
Syntax
max_fanout <no_value | float>
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Optimization--design
Applies to:
object Default Data_type
design no_value double, read/write
hpin INFINITY double, read only
lib_pin INFINITY double, read/write
pg_lib_pin INFINITY double, read/write
port no_value double, read/write
pin INFINITY double, read only
Description
design Specifies the maximum fanout design rule limit for all nets in a design. The resolution is 1/1000. When optimizing a design, Genus attempts to
satisfy all design rule constraints. These constraints can come from attributes on a module or port, or from the technology library.
If set to no_value, no design-level constraint is applied, although design rules may still be inferred from port attributes or from the technology
library.
hpin
lib_pin Specifies the maximum fanout that an output pin of the library cell can drive.
This attribute has no value for input pins.
pg_lib_pin Specifies the maximum fanout that an output pin of the library cell can drive.
This attribute has no value for input pins.
port Specifies the maximum fanout rule limit for the net connected to the port. The resolution is 1/1000. When optimizing a design, Genus attempts
to satisfy all design rule constraints. These constraints can come from attributes on a block or port, or from the technology library.
If set to no_value, no port constraint is applied, although design rules may still be inferred from module attributes or from any driving pin that
has been applied to the port.
pin
Related Information
Affects these commands: report_design_rules
report_timing
syn_opt
Related attributes: drc_first
drc_max_fanout_first
ignore_library_drc
ignore_library_max_fanout
max_capacitance
max_transition
max_fanout_cost
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Optimization--design
Syntax
max_fanout_cost <float>
Applies to:
design
Description
Default:
Data_type: double, read only
Returns the sum of the fanout violations on all ports in the design. A violation is flagged when the actual fanout on a port is larger than the max_fanout constraint
(attribute).
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related command: report_design_rules
Affected by these attributes: max_fanout
Related attributes: max_cap_cost
max_trans_cost
max_trans_cost
Syntax
max_trans_cost <delay>
Applies to:
design
Description
Default:
Data_type: delay, read only
Returns the sum of the transition time violations on all ports in the design. A violation is flagged when the actual transition time on a port is larger than the
max_transition constraint (attribute).
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related command: report_design_rules
Affected by these attributes: max_transition
Related attributes: max_cap_cost
max_fanout_cost
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Optimization--design
max_transition
Syntax
max_transition <no_value | integer>
Applies to:
object Default Data_type
design no_value delay, read/write
hpin no_value delay, read/write
lib_pin INFINITY delay, read/write
module no_value delay, read/write
pg_lib_pin INFINITY delay, read/write
port no_value delay, read/write
pin no_value delay, read/write
Description
design Specifies a maximum transition design rule limit for all nets in a design. The resolution is 1. When optimizing a design, Genus attempts to
satisfy all design rule constraints. These constraints can come from attributes on a module or port, or from the technology library.
If set to no_value, no design-level constraint is applied, although design rules may still be inferred from port attributes or from the technology
library.
hpin
lib_pin Specifies the maximum acceptable transition time (in picoseconds) on the pin. This attribute applies to input and output pins.
pg_lib_pin Specifies the maximum acceptable transition time (in picoseconds) on the library pin. This attribute applies to input and output pins.
port Specifies the maximum transition design rule limit (in picoseconds) for the net connected to the port. The resolution is 1. When optimizing a
design, Genus attempts to satisfy all design rule constraints. These constraints can come from attributes on a module or port, or from the
technology library.
If set to no_value, no port constraint is applied, although design rules may still be inferred from module attributes or from any driving pin that
has been applied to the port.
The specified value for the max_transition attribute must be at least 55 ps.
pin
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Optimization--design
Related Information
Affects these commands: report_design_rules
report_timing
syn_opt
Related attributes: drc_first
drc_max_trans_first
ignore_library_drc
max_capacitance
max_fanout
min_cap_cost
Syntax
min_cap_cost <string>
Applies to:
design
Description
Default:
Data_type: capacitance, read only
Returns the sum of the capacitance violations on all pins and ports in the design. A violation is flagged when the actual capacitance on a pin or port is smaller
than the min_capacitance constraint (attribute).
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Affected by this attribute: min_capacitance
Related attributes: min_fanout_cost
min_trans_cost
min_fanout_cost
Syntax
min_fanout_cost {no_value | float}
Applies to:
design
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Optimization--design
Description
Default:
Data_type: double, read only
Returns the sum of the fanout violations on all ports in the design. A violation is flagged when the actual fanout on a port is smaller than the min_fanout
constraint (attribute).
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Affected by this attribute: min_fanout
Related attributes: min_cap_cost
min_trans_cost
min_trans_cost
Syntax
min_trans_cost {no_value | float}
Applies to:
design
Description
Default:
Data_type: delay, read only
Returns the sum of the transition time violations on all ports in the design. A violation is flagged when the actual transition time on a port is smaller than the
min_transition constraint (attribute).
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Affected by this attribute: min_transition
Related attributes: min_cap_cost
min_fanout_cost
modules
Syntax
modules <list_of_modules>
Applies to:
design
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Optimization--design
Description
Default:
Data_type: module*, read only
Returns the list of modules in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
net_area
Syntax
net_area <string>
Applies to:
design
hinsts
hpin
module
pin
pg_pin
port
Description
Default:
Data_type: area, read only
Returns the net area of the design/hierarchical instance/module/pin. The area is specified in terms of the units specified in the library.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related command: report_area
nets
Syntax
nets {list_of_nets}
Applies to:
design
hinsts
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Optimization--design
Description
Default:
Data_type: net*, read only
Returns the list of all nets in the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
num_insts
Syntax
num_insts <integer>
Applies to:
design
module
Description
Default:
Data_type: integer, read only
Returns the number of all leaf instances in the design/module.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
num_local_hpins
Syntax
num_local_hpins <integer>
Applies to:
design
hinst
Description
Default:
Data_type: integer, read only
Returns the number of all hierarchical pins directly in the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
num_nets
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Optimization--design
Syntax
num_nets <integer>
Applies to:
design
Description
Default:
Data_type: integer, read only
Returns the number of all pg_nets in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
num_pg_nets
Syntax
num_pg_nets <integer>
Applies to:
design
Description
Default:
Data_type: integer, read only
Returns the number of all nets in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
pg_hnets
Syntax
pg_hnets {list_of_pg_hnets}
Applies to:
design
hinst
Description
Default:
Data_type: pg_hnet*, read only
Returns the list of pg_hnet objects in the design/hierarchical instance.
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Optimization--design
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
pg_nets
Syntax
pg_nets {list_of_pg_nets}
Applies to:
design
hinst
Description
Default:
Data_type: net* (design), pg_net* (hnist), read only
Returns the list of pg_net objects in the design/hierarchical instance.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
pg_ports
Syntax
pg_ports <string>
design
Description
Default:
Data_type: pg_port*, read only
Returns the list of pg_port objects in the design.
Related Information
Related attribute: pg_hports
physical_cell_area
Syntax
physical_cell_area {no_value | float}
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Optimization--design
Applies to:
design
module
Description
Default:
Data_type: double, read only
Computes the cell area of the design/module using the LEF area values. The area is specified in terms of the units specified in the library.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related command: report_area
pins
Syntax 1
pins <pin_list>
Applies to:
Object Data_type Description
gcell string, read only Lists the names of the instance pins that can be accessed within the gcell.
hdl_architecture string, read only Keeps an ordered list of all pins of the Verilog module or VHDL entity represented by the hdl_architecture object.
hdl_component string, read only Returns an ordered list of all pins of the specified ChipWare component.
Do not confuse this attribute with the pins branch of vdir objects attached to this hdl_architecture / hdl_component object. Under that branch, each pin
is represented by its own hdl_pin object.
Related Information
Set by this command: read_def
Syntax 2
pins {<hpin>*|<pin>*|<constant>*|<pg_pin>*|<hport>*|<port>*}
Applies to:
isolation_rule
level_shifter_rule
Description
Default:
Data_type: hpin* | pin* | constant* | pg_pin* | hport* | port*, read only
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Optimization--design
object Description
isolation_rule Returns the list of pins to which this isolation rule applies.
level_shifter_rule Returns the list of pins to which the rule defined with the create_level_shifter_rule CPF command is applicable.
Related Information
Affected by this command: read_power_intent
Syntax 3
pins <list_of_pins>
Applies to:
Object Data_type Description
design pin*, read only Returns the list of leaf pins in the design.
hinst pin*, read only Returns the list of leaf pins of the hierarchical instance.
inst pin*, read only Returns the list of leaf pins of the hierarchical instance.
pg_hnet hpin* | pin* | constant* | pg_pin* | hport* | port*, read only Returns the pins that belong to this this pg_hnet.
pg_net hpin* | pin* | constant* | pg_pin* | hport* | port*, read only Returns the pins that are connected to this this pg_net.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
pinstances
Syntax
pinstances <pinstance>
Applies to:
design
Description
Default:
Data_type: pinstance*, read only
Returns the list of ’pinstance’ object types.
pnets
Syntax
pnets {list_of_pnets}
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Optimization--design
Applies to:
design
Description
Default:
Data_type: pnet*, read only
Returns the list of pnets in the design.
port_busses
Syntax
port_busses {list_of_port_busses}
Applies to:
design
Description
Default:
Data_type: port_bus*, read only
Returns the list of port_bus objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
ports
Syntax: design
ports {list_of_ports}
Syntax: def_pin
ports { <placementStatus> <location_x> <location_y> <orientation>
{{<layer> <minspacing> <designrulewidth> {<llx lly urx ury>}} ...} {{<layer> <minspacing>
<designrulewidth> {<pt pt pt> [<pt>]}} ...} {{<vianame location_x location_y>}...} }...
Applies to:
def_pin
design
Description
Default:
Data_type: string (def_pin), port* (design), read only
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Optimization--design
def_pin Returns one or more lists if the DEF file contains PORT statement(s) for the physical pin . Each list contains:
placement status
location of the physical pin
orientation
a list with layer information (corresponding to the LAYER statements for the PORT)
a list with polygon information (corresponding to the POLYGON statements for the PORT)
a list with via information (corresponding to the VIA statements for the PORT)
If the DEF did not contain a LAYER, POLYGON or VIA statement for the PORT, the corresponding list will be empty.
design Returns the list of ports in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by
default.
Related Information
Set by this command: read_def
preserve
Syntax
preserve {false | true | const_prop_delete_ok | const_prop_size_delete_ok | delete_ok | map_size_ok | size_ok | size_delete_ok}
Applies to:
base_cell
lib_cell
design
module
hinst
inst
hnet
net
hpin
pin
pg_pin
Description
Default: false
Data_type: bool (lib_cell), enum (others), read/write
base_cell Preserves base_cell instances from optimization (specified by library or user-defined).
lib_cell Preserves instances of this cell from optimization. By default, Genus performs optimizations that can result in logic changes to any object in the
design. You can prevent any logic changes on instances of this cell while still allowing mapping optimizations in the surrounding logic.
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Optimization--design
design Controls the optimization of the design.
module Controls the optimization of the module.
hinst Controls optimization of a mapped hierarchical instance.
inst Controls optimization of a mapped instance.
hnet Controls the deletion of the net segment during synthesis. The preservation will not propagate across hierarchies unless you specify as such.
net Controls the deletion of the net segment during synthesis. The preservation will not propagate across hierarchies unless you specify as such.
hpin Controls the deletion of the pin during synthesis.
pin Controls the deletion of the pin during synthesis.
pg_pin Controls the deletion of the power or ground pin during synthesis.
You can set the following options:
const_prop_delete_ok Allows deleting a mapped module and its instances, and constant propagation through the mapped module and its instances,
but not resizing, renaming or remapping.
Available in: design, module, hinst, inst
const_prop_size_delete_ok Allows deleting and resizing a mapped module and its instances, or constant propagation through a mapped module and its
instances, but not renaming or remapping.
Available in: design, module, hinst, inst
map_size_ok Allows resizing, unmapping, and remapping of a mapped sequential instance during optimization, but not renaming or
deleting it.
Available in: design, module, hinst, inst
size_delete_ok Allows resizing or deleting a mapped module or child instance during optimization, but not renaming or remapping it.
Available in: design, module, hinst, inst
size_ok Allows resizing a mapped module or child instance during optimization, but not deleting, renaming, or remapping it.
Available in: design, module, hinst, inst
delete_ok Allows deleting a mapped module or child instance during optimization, but not resizing, renaming, or remapping it.
Available in: design, module, hinst, inst, hnet, net, hpin, pin, pg_pin
false Allows logic changes to any object in the design during optimization.
Available in: lib_cell, design, module, hinst, inst, hnet, net, hpin, pin, pg_pin
true Prevents logic changes to any object in the design during optimization.
Available in: lib_cell, design, module, hinst, inst, hnet, net, hpin, pin, pg_pin
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affects this attribute: map_to_multibit_bank_label
Affected by this attribute: user_defined
protected
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Optimization--design
Syntax
protected {false | true}
Applies to:
command
command_option
design
module
hdl_architecture
Description
object Default Data_type
command false bool, read only
command_option false bool, read only
design false bool, read only
module false bool, read only
hdl_architecture false bool, read only
command Indicates whether the command is hidden.
command_option Indicates whether the command option is hidden.
design This attribute is set to true if the design object represents a module or entity whose HDL source code is encrypted or only partially
encrypted.
module This attribute is set to true if the module object represents a module or entity whose HDL source code is encrypted or only partially
encrypted.
hdl_architecture This attribute is set to true if the architecture was read in encrypted format and the output netlist will be in encrypted format.
Related Information
Affects these commands: write_hdl
report_dp
retime
Syntax
retime {false | true}
Applies to:
design
module
Description
Default: false
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Optimization--design
Data_type: bool, read/write
Marks the specified design or module to be retimed during synthesis. This attribute must be set after the elaborate command but before the syn_generic
command.
Specifying retime attribute for a module prevents its partitioning during Partition-based Synthesis (PBS).
Related Information
Affects these commands: syn_generic
Affected by these attributes: dont_retime
retime_hard_region
retime_reg_naming_suffix
retime_period_percentage
Syntax
retime_period_percentage <float>
Applies to:
design
module
Description
Default: 1.0
Data_type: double, read/write
Adjusts the clock period in retiming. You can use this for a tradeoff between delay, area, and sequential count. For example, to be more conservative during
retiming you can set the attribute to 0.9. This would mean on a 1 ns clock, 0.9 ns would be taken as a constraint for retiming.
Related Information
Affects these commands: syn_generic
route_types
Syntax
route_types {list_of_route_types}
Applies to:
design
Description
Default:
Data_type: route_type*, read only
Returns the list of all route_type objects in the design.
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Optimization--design
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Related command: read_def
seq_reason_deleted
Syntax
seq_reason_deleted {{<instance> <reason>}...}
Applies to:
design
Description
Default:
Data_type: string+*, read/write
Returns a Tcl list of Tcl lists. Each Tcl list contains the name of a sequential instance that was deleted during optimization and the reason why the instance was
deleted.
If the delete_unloaded_seqs root attribute is set to false, the reason might be appended with an asterisk ( * ) to indicate that the sequential instance is optimized
for the reason reported but not deleted. In this case, the flop output pin will be dangling, not driving any loads. The loads driven by the flop before optimization,
will be replaced/driven by a constant, or by the output pins of the merged flops pin.
Related Information
Related command: report_sequential -deleted_seqs
Affected by this attribute: delete_unloaded_seqs
slots
Syntax
slots {list_of_slots}
Applies to:
design
Description
Default:
Data_type: slot*, read only
Returns the list of all slot objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
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Optimization--design
specialnets
Syntax
specialnets {list_of_specialnets}
Applies to:
design
Description
Default:
Data_type: specialnet*, read only
Returns the list of all specialnets in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
styles
Syntax
styles {list_of_styles}
Applies to:
design
Description
Default:
Data_type: style*, read only
Returns the list of all style objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
total_area
Syntax
total_area <area>
Applies to:
design
hinst
module
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Optimization--design
Description
Default:
Data_type: area, read only
Computes the total area of the design (including the net area). An estimate is used for unmapped logic.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
track_patterns
Syntax
track_patterns track_pattern
Applies to:
design
Description
Default:
Data_type: track_pattern*, read only
Returns the list of ’track_pattern’ objects.
use_base_cell_set
Syntax
use_base_cell_set {base_cell_set}
Applies to:
design
hinst
inst
Description
Default:
Data_type: base_cell_set, read/write
design Specifies to use lib_cells from the set during synthesis and optimization of the design.
hinst Specifies to use lib_cells from the set during synthesis and optimization of this hierarchical instance. By default, the instance attribute inherits the
value of the parent instance attribute.
inst Specifies to use lib_cells from the set during synthesis and optimization of this instance. By default, the instance attribute inherits the value of the
parent instance attribute.
use_cells
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Optimization--design
Syntax
use_cells {list_of_cells}
Applies to:
design
hinst
module
Description
Default:
Data_type: base_cell, read/write
design List of cell names to allow for this design during optimization. This is intended to override and remove the cells present in dont_use_cells list only.
Setting this attribute does not imply that cells will be used only from this list. Tool can pick other usable cells also.
This can be overridden at a lower hinst level.
Overrides cells in the dont_use_cells list for the design. If a cell is added to this list that is already in the dont_use_cells list, it will be removed
from the use_cells list so that both the lists are non-overlapping.
hinst Specifies to use cells during synthesis and optimization of this hierarchical instance. This is intended to override and remove the cells present in
dont_use_cells list only. Setting this attribute does not imply, that cells will be used only from this list. Tool can pick other usable cells also.
Input for this attribute is a list of cell names to allow for this hierarchical instance during optimization.
Setting on an hierarchical instance is applied to all hierarchical instances that share the same module with the hierarchical instance given as
argument and all the hierarchical instance siblings inherit the same value. All lib_cells of each base_cell will be allowed.
If a cell is added to this list that is already in the dont_use_cells list, it will be removed from the dont_use_cells list so that both the lists are non-
overlapping.
module List of cell names to allow for this module during optimization. This is intended to override and remove the cells present in dont_use_cells list only.
Setting this attribute does not imply, that cells will be used only from this list. Tool can pick other usable cells also.
Setting this applies to all hierarchical instances sharing the module.
If a cell is added to this list that is already in the dont_use_cells list, it will be removed from the dont_use_cells list so that both the lists (use_cells
and dont_use_cells) are non-overlapping.
Setting on hierarchical instance of this module will update the value of this module attribute.
Related Information
Related commands: syn_generic
syn_map
syn_opt
Related attribute: dont_use_cells
use_only_on_power_critical_nets
Syntax
use_only_on_power_critical_nets <base_cell_set>
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Optimization--direction
Applies to:
design
Description
Default:
Data_type: base_cell_set, read/write
Specifies the base cell set from which library cells will be used on power critical nets.
direction
Syntax 1
direction {internal | in | out | inout}
object Default Data_type Description
base_pin -- enum, read only Returns the direction of the base_pin.
hpin -- enum, read only Returns the direction of the pin.
hpin_bus -- enum, read only Returns the direction of the hpin bus.
hport -- enum, read only Returns the direction of the hport.
hport_bus -- enum, read only Returns the direction of the hport bus.
lib_pin -- enum, read only Returns the direction of the pin.
pg_lib_pin -- enum, read only Returns the direction of the library pin.
pg_pin -- enum, read only Returns the direction of the pg_pin.
If the direction attribute of a pg_pin is missing in the Liberty library, Genus sets the direction to
inout by default.
pg_hport -- enum, read only Returns the direction of the pg_hport.
pg_port -- enum, read only Returns the direction of the pg_hport.
pin -- enum, read only Returns the direction of the pin.
port -- enum, read only Returns the direction of the port.
port_bus -- enum, read only Returns the direction of the port.
timing_point -- timing_point, read Returns the direction of the timing point.
only
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Optimization--direction
Syntax 2
direction {up | down | bidir}
Applies to:
level_shifter_group
Description
Default:
Data_type: enum, read only
Specifies the direction in which this group of level shifters can shift the voltage:
Value Description
up Indicates that the level shifters connect from a lower voltage domain to a higher voltage domain.
down Indicates that the level shifters connect from a higher voltage domain to a lower voltage domain.
bidir Indicates that the direction of the level shifters can be up or down.
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Optimization--direction
Syntax 3
direction {up | down | both}
Applies to:
level_shifter_rule
Description
Default:
Data_type: enum, read only
Specifies the direction of the level shifters for a global level shifter rule.
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Optimization--direction
Syntax 4
direction <string>
object Default Data_type Description
def_pin -- def_pin, read only Returns the direction of the physical pin. Following are the possible values:
INPUT - Pin that accepts signals coming into the cell.
OUTPUT - Pin that drives signals out of the cell.
INOUT - Pin that can accept signals going either in or out of the cell.
FEEDTHRU - Pin that goes completely across the cell.
gcell_grid -- gcell_grid, read only Returns the direction of the lines that defined the grid.
track_pattern -- track_pattern, read only Returns the direction of the lines that defined the track.
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Optimization--direction
Syntax 5
direction {horizontal | vertical}
Applies to:
layer
Description
Default:
Data_type: string, read only
Returns the preferred routing direction for this layer.
The tool ignores the diag45 and diag135 values.
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Optimization--dont_touch_sources
Syntax 6
direction {input | output | inout}
Applies to:
hdl_pin
Description
Default:
Data_type: enum, read only
Returns the direction of the specified pin.
Related Information
Affected by this command: read_power_intent
Set by this command: read_def
Set by this attribute: lef_library
dont_touch_sources
dont_touch_sources {{source value}...}
Read-only hinst attribute. Returns the list of {source value>} pairs contributing to the value of the dont_touch_effective attribute for this object:
{{user value} {lib value} {parent value} {scan value}}
user—This hinst dont_touch value
lib—The base_cell dont_touch value
parent—The dont_touch value from an hinst above (the closest hinst above that is not false)
scan—Is this inst part of a scan-chain (value is either size_ok or false).
Related Information
Affects this attribute: dont_touch_effective
Related attribute: (inst) dont_touch_sources
dont_use_qbar_pin
dont_use_qbar_pin {false | true}
Default: false
Read-write inst attribute. Controls the use of the Qbar output pin of this sequential instance during optimization if other possibilities exist. By default, these pins
can be used.
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Optimization--hdl_instantiated
Related Information
Affects these commands: syn_map
syn_opt
Related attribute: dont_use_qbar_seq_pins
hdl_instantiated
hdl_instantiated {true | false}
Read-only hinst attribute. Indicates whether the instance is present in the input RTL description (true) or generated by Genus during synthesis (false).
Related Information
Set by these commands: elaborate
read_netlist
hinst
hinst hinst
Read-only hinst attribute. Returns the hierarchical instance that the hierarchical instance belongs to.
Related Information
Related attributes: (constant)) hinst
(hnet) hinst
(hpin) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
(pg_pin) hinst
hpin_busses
hpin_busses list_of_hpin_busses
Read-only hinst attribute. Returns a list of hpin_bus objects for this hierarchical instance.
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Optimization--hport_busses
hport_busses
hport_busses list_of_hport_busses
Read-only hinst attribute. Returns a list of hport_bus objects for this hierarchical instance.
Related Information
Related attribute: insts
hports
hports list_of_hpins
Read-only hinst attribute. Returns all hierarchical ports of this hierarchical instance.
inherited_preserve
inherited_preserve {const_prop_delete_ok | const_prop_size_delete_ok | delete_ok | false | true | map_ok | map_size_ok | size_ok | size_delete_ok}
Read-only hinst attribute. Returns the effective preserve value that is seen by the tool. The preserve value could have been set explicitly set on this instance,
or this instance inherited the value from its parent module or hierarchical instance, or the instance could have been preserved internally for various reasons.
The attribute can have the following values:
const_prop_delete_ok Allows deleting a mapped instance and constant propagation through the mapped instance, but not resizing, renaming or
remapping it.
const_prop_size_delete_ok Allows deleting and resizing a mapped instance, or constant propagation through a mapped instance, but not renaming or
remapping it.
delete_ok Allows deleting a mapped instance during optimization, but not resizing, renaming, or remapping it.
false Allows logic changes to a mapped instance in the design during optimization.
map_ok Allows mapping, and remapping of unmapped sequential instances during optimization, but not deleting, renaming or
resizing them.
map_size_ok Allows mapping, resizing, and remapping of unmapped sequential instances during optimization, but not renaming or
deleting them.
size_delete_ok Allows resizing or deleting a mapped instance during optimization, but not renaming or remapping it.
size_ok Allows resizing a mapped instance during optimization, but not deleting, renaming, or remapping it.
true Prevents logic changes to a mapped instance in the design during optimization.
When the preserve attribute is set on an instance and its parent module, the most restrictive value is inherited.
Example
Assuming that preserve was set to delete_ok on an instance and set to size_ok on the parent module, the value of inherited_preserve would be true.
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Optimization--inverted_phase
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affected by this attribute: preserve
Related attribute: (inst) inherited_preserve
inverted_phase
inverted_phase {true | false}
Read-only inst attribute. Indicates whether a transformation (as described for the lbr_seq_in_out_phase_opto attribute) did occur for this instance.
Transformations can only occur when you enabled the lbr_seq_in_out_phase_opto root attribute.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the vls command by default.
This attribute applies only to mapped instances.
Example
genus@design:test> get_db inst:test/mul_130_25/g2539 .inverted_phase
false
The returned value indicates that there was no phase inversion for this instance.
Related Information
Affected by this attribute: lbr_seq_in_out_phase_opto
Related attribute: (hinst) inverted_phase
iopt_allow_inst_dup
Syntax
iopt_allow_inst_dup {true | false}
Applies to:
hinst
inst
Description
Default: true
Data_type: bool, read/write
Controls whether the instance can be duplicated.
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Optimization--is_black_box
Related Information
Related attribute: hdl_proc_name
is_black_box
is_black_box {true | false}
Read-only inst attribute. Indicates if the instance is a black box. This implies that the timing is understood, but not the function of the instance.
This cell either has no .lib definition or has a .lib definition but no timing_arcs. In either case, timing analysis cannot propagate through this cell.
Related Information
Related attributes: (base_cell) is_black_box
(lib_cell) is_black_box
is_buffer
Syntax
is_buffer {true | false}
Applies to:
base_cell
hinst
inst
lib_cell
Description
Default: false
Data_type: bool, read only
Indicates if the object (base_cell/hinst/inst/lib_cell) is a buffer.
is_combinational
is_combinational {false | true}
Read-only inst attribute. Indicates if the instance is a combinational or tristate instance.
is_cw_component
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Optimization--is_dont_touch
Syntax
is_cw_component {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read only
Indicates whether the instance is a CW component.
is_dont_touch
Syntax
is_dont_touch {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read only
Indicates whether to preserve instance from optimization.
is_flop
Syntax
is_flop {true | false}
Applies to:
base_cell
inst
hinst
lib_cell
Description
Default: false
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Optimization--is_interface_timing
Data_type: bool, read only
Indicates if the object (base_cell/hinst/inst/lib_cell) is a flip-flop (or edge-triggered sequential element).
is_interface_timing
is_interface_timing {false | true}
Read-only inst attribute. Indicates whether the instance has the interface_timing Liberty cell attribute.
Related Information
Related attributes: (base_cell) is_interface_timing
(lib_cell) is_interface_timing
is_inverter
Syntax
is_inverter {true | false}
Applies to:
base_cell
inst
hinst
lib_cell
Description
Default: false
Data_type: bool, read only
Indicates if the object (base_cell/hinst/inst/lib_cell) is an inverter.
is_latch
Syntax
is_latch {true | false}
Applies to:
base_cell
hinst
inst
lib_cell
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Optimization--is_macro
Description
Default: false
Data_type: bool, read only
Indicates if the object (base_cell/hinst/inst/lib_cell) is a latch.
is_macro
is_macro {false | true}
Read-only hinst attribute. Specifies whether this instance is a macro cell.
Related Information
Related attributes: (base_cell) is_macro
(lib_cell) is_macro
(inst) is_macro
is_master_slave_flop
is_master_slave_flop {false | true}
Read-only inst attribute. Indicates if the instance is a master-slave flip-flop.
Related Information
Related attributes: (base_cell) is_master_slave_flop
(lib_cell) is_master_slave_flop
is_master_slave_lssd_flop
is_master_slave_lssd_flop {false | true}
Read-only inst attribute. Indicates if the instance is a master-slave LSSD flip-flop.
Related Information
Related attributes: (base_cell) is_master_slave_lssd_flop
(lib_cell) is_master_slave_lssd_flop
is_memory
is_memory {false | true}
Read-only inst attribute. Specifies that this instance is a memory. You should only set this if the cell has address, data, and enable pins.
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Optimization--is_pad
Related Information
Related attributes: (base_cell) is_memory
(lib_cell) is_memory
is_pad
is_pad {false | true}
Read-only inst attribute. Indicates if the base_cell is a pad cell.
The attribute value will be set to true if the cell has a corresponding cell in the LEF library defined as CLASS PAD.
Related Information
Related attributes: (base_cell) is_pad
(lib_cell) is_pad
is_phase_inverted
Syntax
is_phase_inverted {true | false}
Applies to:
hinst
inst
Description
Default:
Data_type: bool, read only
Specifies whether the instance has a phase inversion associated with it.
is_physical
is_physical {false | true}
Read-only hinst attribute. Indicates if the hierarchical instance is a physical instance.
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Optimization--is_sequential
Related Information
Related attributes: (hpin) is_physical
(inst) is_physical
(pg_pin) is_physical
(pin) is_physical
is_sequential
is_sequential {false | true}
Read-only inst attribute. Indicates if the base_cell is a sequential logic circuit.
Related Information
Related attributes: (base_cell) is_sequential
(lib_cell) is_sequential
is_tristate
is_tristate {true | false}
Read-only inst, base_cell, lib_cell, lib_pin, and pg_lib_pin attribute. Indicates if the object has at least one tristate output.
lib_cells
lib_cells base_cell
Read-only inst attribute. Returns the base_cell for the mapped instance.
map_to_multibit_bank_label
map_to_multibit_bank_label string
Default: cdns_default_bank
Read-write inst attribute. Defines a bank label for a sequential instance. Instances with the same label can be considered for multibit mapping to the same
bank of multibit instance.
If this attribute is set on a flop but no value is given to the map_to_multibit_register attribute, the flop is considered for regular multibit cell inferencing.
If several instances have the same bank label and the same map_to_multibit_register attribute value, those instances will be considered to be mapped to the
same bank of the multibit cells specified by the map_to_multibit_register attribute.
Related Information
Affects this command: syn_opt
Related attribute: map_to_multibit_register
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Optimization--map_to_multibit_register
map_to_multibit_register
map_to_multibit_register lib_cell_list
Read-write inst attribute. Enables predefined multibit cell inferencing (MBCI) for the sequential instance and limits the multibit mapping of this instance to the
specified multibit library cells. Since this attribute enables predefined multibit cell inferencing, it implies a forced type of mapping and is therefore not QoR-
driven.
All the specified library cells must
Have same bit width.
A bit width mismatch implies no multibit cell inferencing for this bank-label.
Be functionally swappable.
A mismatch will not allow you to set the value for this attribute.
All instances with the same bank label (set through the map_to_multibit_bank_label attribute) and the same map_to_multibit_register attribute value, are
considered to be mapped to the same bank of multibit cells.
Related Information
Affects this command: syn_opt
Affected by this attribute: map_to_multibit_bank_label
Related attribute: bank_based_multibit_inferencing
map_to_mux
map_to_mux {false | true}
Default: false
Read-write hinst attribute. When set to true, maps the hierarchical instance to a binary mux cell. If the map_to_mux pragma is found in the RTL, and there is a
way to infer a mux cell from the RTL annotated by this pragma, then elaboration creates a binary mux instance. Examining the map_to_mux pragma of specific
instances let you find out whether they are honored by Genus.
Using this attribute may affect the QoR.
Related Information
Affects these commands: syn_map
syn_opt
Related attributes: input_map_to_mux_pragma
map_to_register
map_to_register lib_cell_list
Read-write inst attribute. Lists the lib_cells that can be used for mapping the specified sequential cell.
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Optimization--merge_combinational_hier_instance
Related Information
Affects these commands: syn_map
syn_opt
merge_combinational_hier_instance
Syntax
merge_combinational_hier_instance {inherited | false | true}
Applies to:
hinst
inst
Description
Default: inherited
Data_type: enum, read/write
Controls the merging of this combinational hierarchical instance. You can specify the following values:
false Prevents merging of this combinational hierarchical instance.
inherited If the instance is a combinational hierarchical instance, it inherits the value of the merge_combinational_hier_instances root attribute.
true Allows merging of this combinational hierarchical instance.
This attribute applies only to combinational hierarchical instances.
Related Information
Affects these commands: syn_generic
syn_map
Affected by this attribute: merge_combinational_hier_instances
module
Syntax
module <string>
Applies to:
hinst
Description
Default:
Data_type: module | design, read only
Returns the name of the module that is instantiated.
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Optimization--module attributes for Opt
module attributes for Opt
dont_touch_hports hard_region logical_hier
retime_hard_region ungroup_ok
dont_touch_hports
Syntax
dont_touch_hports {true | false | delete_ok | add_ok | invert_ok | add_invert_ok}
Applies to:
hinst
module
Description
Default: false
Data_type: enum, read/write
This attribute defines the user preservation status for the hports of this module/hierarchical instance during optimization.
You can set the following values:
false Allows the hports to be optimized.
true Prevents hports to be optimized.
delete_ok Allows hports to be deleted if they do not have a fanout.
add_ok Allows adding or duplicating hports.
invert_ok Allows changing the polarity of hports.
add_invert_ok Allows changing the polarity of hports and adding or duplicating hports.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
hard_region
Syntax
hard_region {true | false}
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Optimization--module attributes for Opt
Applies to:
hinst
inst
module
Description
Default: false
Data_type: bool, read/write
Specifies that the hierarchical instances/instances/module will be treated as a hard region in the floorplan during logic synthesis and preserves pins and
subports.
Some place and route tools operate better if your design has no buffers between regions at the top level. To accommodate this, specify hard regions
before mapping.
Related Information
Creating Hard Regions in Genus User Guide.
logical_hier
Syntax
logical_hier {true | false}
Applies to:
module
Description
Default: true
Data_type: bool, read/write
Indicates if the module is a logical hierarchy object, that is, it corresponds to a user-defined entity (in VHDL) or user-defined module (in Verilog).
Related Information
Related command: report_area
retime_hard_region
Syntax
retime_hard_region {true | false}
Applies to:
module
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Optimization--multibit_rejection_reason
Description
Default: false
Data_type: bool, read/write
When set to true, prevents registers from being moved across the module boundaries during retiming optimization. When set to false, register movements are
not restricted by module boundaries.
Related Information
Affects these attributes: dont_retime
retime
Related attribute: retime_reg_naming_suffix
ungroup_ok
Syntax
ungroup_ok {true | false}
Applies to:
hinst
module
Description
Default: true
Data_type: bool, read/write
Controls ungrouping of the hierarchical instances of this module/hierarchical instance during automatic ungrouping. Set the attribute to false to prevent the
ungrouping of the module and its instances/hierarchical instances.
Related Information
Affects these commands: syn_generic
syn_map
Affected by this attribute: auto_ungroup
multibit_rejection_reason
multibit_rejection_reason {string}
Read-only inst attribute. Reports the reason why the instance could not be merged into a multibit cell. By default, the attribute value will be empty if no reason
is set or if multibit mapping was not run.
negative_edge_clock
negative_edge_clock {false |true}
Read-only inst attribute. When true, indicates that the flop instance was inferred from an RTL statement triggered by a negedge (Verilog) or falling_edge
(VHDL) condition.
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Optimization--optimize_constant_0_seq
Example
Assume your RTL description has the following:
assign nclk = ~clk;
always @(posedge nclk)
begin
ou1 <= in;
end
always @(negedge clk)
begin
ou2 <= in;end
After elaborate, the attribute values are:
genus@root:> get_db [get_db insts */ou1_reg] .negative_edge_clock
false
genus@root:> get_db [get_db insts */ou2_reg] .negative_edge_clock
true
optimize_constant_0_seq
Syntax
optimize_constant_0_seq {inherited | true | false}
Applies to:
inst
Description
Default: inherited
Data_type: enum, read/write
Controls constant 0 propagation through this sequential instance. You can specify the following values:
false Prevents constant 0 propagation through this sequential instance.
inherited If the sequential instance is a flop, it inherits the value of the optimize_constant_0_flops root attribute. If the sequential instance is a latch, it
inherits the value of the optimize_constant_latches root attribute.
true Allows constant 0 propagation through the sequential instance, and thus allows removal of the instance.
This attribute applies only to sequential instances.
Related Information
Affects these commands: syn_generic
syn_map
Affected by this attribute: optimize_constant_0_flops
optimize_constant_latches
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Optimization--optimize_constant_1_seq
optimize_constant_1_seq
Syntax
optimize_constant_1_seq {inherited | true | false}
Applies to:
inst
Description
Default: inherited
Data_type: enum, read/write
Controls constant 1 propagation through this sequential instance. You can specify the following values:
false Prevents constant 1 propagation through this sequential instance.
inherited If the sequential instance is a flop, it inherits the value of the optimize_constant_1_flops root attribute. If the sequential instance is a latch, it
inherits the value of the optimize_constant_latches root attribute.
true Allows constant 1 propagation through the sequential instance, and thus allows removal of the instance.
This attribute applies only to sequential instances.
Related Information
Affects these commands: syn_generic
syn_map
Affected by this attribute: optimize_constant_0_flops
optimize_constant_latches
optimize_merge_seq
Syntax
optimize_merge_seq {inherited | true | false}
Applies to:
inst
Description
Default: inherited
Data_type: enum, read/write
Controls merging of this instance with equivalent sequential instances. You can specify the following values:
false Prevents merging of this sequential instance with other equivalent sequential instances.
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Optimization--parent
inherited If the sequential instance is a flop, it inherits the value of the optimize_merge_flops root attribute. If the sequential instance is a latch, it inherits
the value of the optimize_merge_latches root attribute.
true Allows merging of this sequential instance with other equivalent sequential instances.
This attribute applies only to sequential instances.
Related Information
Affects these commands: syn_generic
syn_map
Affected by these attributes: optimize_merge_flops
optimize_merge_latches
parent
Syntax
parent <string>
Applies to:
Object Data_type
attribute obj_type, read only
hinst root | design, read only
inst
Description
Object Description
attribute Returns the parent object_type of the attribute.
hinst Returns the name of the hierarchical instance or design to which the hierarchical instance belongs.
inst Returns the name of the hierarchical instance or design to which the instance belongs.
Example
The following example shows that the innovus_executable attribute is a root attribute.
get_db [get_db attributes */innovus_executable] .parent
root
pg_hports
pg_hports list_of_pg_hports
Read-only hinst attribute. Returns the list of pg_hports in the hierarchical instance.
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Optimization--pg_nets_ls
pg_nets_ls
pg_nets_ls list_of_pg_nets
Read-only inst attribute. Returns the list of pg_nets in the local scope of the instance.
pg_pins
pg_pins list_of_pg_pins
Read-only hinst attribute. Returns the list of pg_pins in the hierarchical instance.
Related Information
Related attribute: (inst) pg_pins
pin_busses
pin_busses list_of_pin_bus
Read-only inst attribute. Returns the list of pin_busses in the instance.
primitive_function
primitive_function string
Read-only inst attribute. Returns the primitive function if the instance is a primitive. Possible values are and, nand, or, nor, buf, not, d_flop, latch, mux, bmux,
xor,xnor, bufif0, bufif1, notif0, notif1, and dc.
Related Information
Related command: create_primitive
relaxed_seq_map_constraints
relaxed_seq_map_constraints string
Read-only inst attribute. Reports the the sequential requirements that were relaxed during global mapping.
Related Information
Related command: syn_map
retime_ssw_sync_enable
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Optimization--root Attributes in Optimization
Syntax
retime_ssw_sync_enable {false | true}
Applies to:
design
module
Description
Default: false
Data_type: bool, read/write
Directs retiming to use SAT-sweep to find equivalence classes for synchronous enable signals.
Related Information
Affects this command: syn_generic
Related attributes: dont_retime
retime_move_mux_loop_with_reg
root Attributes in Optimization
auto_partition auto_super_thread auto_ungroup
auto_ungroup_max_threshold avoid_tied_inputs bit_blasted_port_style
boundary_optimize_constant_hpins boundary_optimize_equal_opposite_hpins boundary_optimize_feedthrough_hpins
boundary_optimize_invert_hpins boundary_optimize_invert_hpins_rename_nets boundary_optimize_invert_hpins_renaming_extension
bus_naming_style comb_seq_merge_message_threshold cts_buffer_cells
cts_clock_gating_cells cts_inverter_cells cts_logic_cells
current_design delete_flops_on_preserved_net delete_hier_insts_on_preserved_net
delete_unloaded_insts delete_unloaded_seqs derive_bussed_pins
design_power_effort designs disable_ungroup_for_hierarchy
display_information_of_edit_netlist dont_use_qbar_seq_pins double_cell_search_pattern
drc_first drc_max_cap_first drc_max_fanout_first
drc_max_trans_first driver_for_unloaded_hier_pins enable_aon_type_in_remove_assign
enable_strict_percent_control exact_match_seq_async_ctrls fix_min_drcs
group_generate_portname_from_netname group_instance_suffix handle_ungroup_names
ignore_preserve_in_tiecell_insertion inst_prefix iopt_allow_tiecell_with_inversion
iopt_enable_floating_output_check iopt_force_constant_removal iopt_remap_avoided_cells
iopt_sequential_duplication iopt_sequential_resynthesis iopt_sequential_resynthesis_min_effort
iopt_temp_directory iopt_ultra_optimization map_clock_tree
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Optimization--root Attributes in Optimization
map_drc_first map_latch_allow_async_decomp map_prefer_non_inverted_clock_line
map_respect_rtl_clk_phase map_to_multiple_output_gates max_cpus_per_server
merge_combinational_hier_instances merge_non_scan_to_scan_flops minimize_uniquify
mtdcl_traverse_by_level multibit_allow_sr_head_flop_merge multibit_allow_unused_bits
multibit_area_power_scoring multibit_aware_seq_mapping multibit_aware_seq_mapping_higher_priority
multibit_debug multibit_invert_clock_phase multibit_mapping_effort_level
multibit_predefined_allow_unused_bits multibit_unused_input_value opt_allow_floating_outputs
opt_high_effort_cells opt_spatial_effort opt_tns
optimize_constant_0_flops optimize_constant_1_flops optimize_constant_across_preserved
optimize_constant_feedback_seqs optimize_constant_latches optimize_merge_flops
optimize_merge_latches optimize_seq_x_to optimize_yield
partition_based_synthesis pbs_db_directory pbs_gen_summary
pbs_iopt_summary pbs_load_lib_in_group_of pbs_map_summary
percent_control_tolerance_for_map predict_floorplan_enable_during_generic preserve_combinational_loop_ports_nets
print_ports_nets_preserved_for_cb propagate_constant_from_timing_model proto_feasible_target
proto_feasible_target_adjust_slack_pct proto_feasible_target_threshold proto_feasible_target_threshold_clock_pct
remove_assigns retime_async_reset retime_effort_level
retime_move_mux_loop_with_reg retime_optimize_reset retime_reg_naming_suffix
retime_verification_flow retiming_clocks skip_ungroup_on_applied_constraint
skip_ungroup_with_exception st_launch_wait_time stop_at_iopt_state
super_thread_batch_command super_thread_debug_directory super_thread_debug_jobs
super_thread_equivalent_licenses super_thread_kill_command super_thread_rsh_command
super_thread_servers super_thread_shell_command super_thread_status_command
syn_generic_effort syn_global_effort syn_map_effort
syn_opt_effort tns_critical_range treat_net_as_analog
ui_respects_preserve ungroup_separator uniquify_naming_style
uniquify_rename_all update_sv_wrapper_post_elab use_max_cap_lut
use_tiehilo_for_const write_db_auto_save_user_globals write_db_use_relative_filepath
auto_partition
auto_partition {true | false}
Description
Default: true
Data_type: bool, read/write
Activates automatic internal partitioning of large designs for efficient synthesis. This attribute must be set before synthesis.
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Applies to:
root
Related Information
Grouping and Ungrouping Objects in Genus User Guide.
Affects these commands: syn_generic
syn_map
auto_super_thread
auto_super_thread {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether super-threading is automatically launched when the tool is running on a multi-processor machine, you have a Genus_Synthesis license, and
no super-thread servers were explicitly specified through the super_thread_servers attribute.
When the auto_super_thread attribute is set to true, the initial license will give you access to eight remote server processes.
This attribute defaults to false when:
Running on a single-processor
Invoking Genus in an LSF environment
Applies to:
root
Related Information
Affected by these attributes: max_cpus_per_server
super_thread_servers
auto_ungroup
auto_ungroup {none | both}
Description
Default: both
Data_type: enum, read/write
Activates automatic ungrouping to improve area and timing optimization during synthesis. This attribute must be specified before synthesis.
none Ungrouping will not be performed.
both Ungrouping will be performed with an emphasis on optimizing both timing and area.
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Optimization--root Attributes in Optimization
Aggressive ungrouping of user hierarchies happens during:
RTL optimization—syn_generic with high effort
Technology mapping—syn_map with high effort
Some ungrouping can occur with low or medium effort as well.
Applies to:
root
Related Information
Grouping and Ungrouping Objects in Genus User Guide.
Affects these commands: syn_generic
syn_map
Affects this attribute: ungroup_ok
auto_ungroup_max_threshold
auto_ungroup_max_threshold <integer>
Description
Default: 0
Data_type: integer, read/write
Specifies that any module with more instances than the specified max threshold value must not be ungrouped by the auto-ungroup feature. But allows
ungrouping for the instances within the specified max threshold value.
Applies to:
root
avoid_tied_inputs
avoid_tied_inputs {true | false}
Description
Default: false
Data_type: bool, read/write
When enabled, the mapper will try to avoid mapping to cells with tied or connected inputs, when possible. This restriction impacts QoR.
Applies to:
root
Related Information
Affects this command: syn_map
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Optimization--root Attributes in Optimization
bit_blasted_port_style
Syntax
bit_blasted_port_style <string>
Applies to:
root
Description
Default: %s_%d
Data_type: string, read/write
Specifies the naming style to be used if mapped ports are bit blasted. The attribute value needs to contain elements %s and %d, in that order.
The following rules apply:
An port name always starts with the base name (represented by %s)
The suffix is appended to the base name to form the port name, according to the format specified in the attribute value.
%d represents the bit information
Example
set_db bit_blasted_port_style %s\[%d\]
%s[%d]
Related Information
Preparing the Netlist for Place-and-Route or Third-Party Tools in Genus User Guide.
Affects these commands: bitblast_all_ports
write_hdl
boundary_optimize_constant_hpins
boundary_optimize_constant_hpins {true | false | inherited}
Applies to:
root
module
hpin
Description
Default: true (root), inherited (module and hpin)
Data_type: bool (root), enum (module and hpin), read/write
Controls constant propagation through the hierarchical boundary pins.
You can specify the following values:
true Allows constant propagation.
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false Prevents constant propagation.
inherited Inherits the value of the boundary_optimize_constant_hpins root attribute.
If the boundary_opto attribute on a module is set and disables boundary optimization on the pins, the setting of this attribute is ignored for that module.
If the boundary_optimize_constant_hpins attribute on an instance pin or module is set to false or true (does not have the inherited value), the setting of
this root attribute is ignored for that pin or module.
Related Information
Setting Boundary Optimization in Genus User Guide.
Affects these commands: syn_generic
syn_map
Affected by this attribute: boundary_opto
Related attributes: boundary_optimize_equal_opposite_hpins
boundary_optimize_feedthrough_hpins
boundary_optimize_invert_hpins
boundary_optimize_equal_opposite_hpins
boundary_optimize_equal_opposite_hpins {true | false | inherited}
Applies to:
root
module
hpin
Description
Default: true (root), inherited (module and hpin)
Data_type: bool (root), enum (module and hpin), read/write
Controls collapsing of equal and opposite hierarchical boundary pins. Two hierarchical boundary pins are considered equal (opposite), if the tool determines
that they always have the same (opposite or inverse) logic value.
You can specify the following values:
true Allows collapsing of the hierarchical boundary pins.
false Prevents collapsing of the hierarchical boundary pins.
inherited Inherits the value of the boundary_optimize_equal_opposite_hpins root attribute.
If the boundary_opto attribute on a module is set and disables boundary optimization on the pins, the setting of this attribute is ignored for that module. If
the boundary_optimize_equal_opposite_hpins attribute on an instance pin or module is set to false or true (does not have the inherited value), the
setting of this root attribute is ignored for that pin or module.
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Related Information
Setting Boundary Optimization in Genus User Guide.
Affects these commands: syn_generic
syn_map
Affected by this attribute: boundary_opto
Related attributes: boundary_optimize_constant_hpins
boundary_optimize_feedthrough_hpins
boundary_optimize_invert_hpins
boundary_optimize_feedthrough_hpins
boundary_optimize_feedthrough_hpins {true | false | inherited}
Applies to:
root
module
hpin
Description
Default: true (root), inherited (module and hpin)
Data_type: bool (root), enum (module and hpin), read/write
Controls optimization of feedthrough pins. Hierarchical boundary pins are feedthrough pins, if output pins have always the same (or inverted) logic value as an
input pin. Such feedthrough pins can be routed around the module and no connections or logic is needed inside the module for these pins. To disable this type
of boundary optimization, set the attribute to false.
You can specify the following values:
true Allows optimization of feedthrough pins.
false Prevents optimization of feedthrough pins.
inherited Inherits the value of the boundary_optimize_feedthrough_hpins module attribute.
If the boundary_opto attribute on a module is set and disables boundary optimization on the pins, the setting of this attribute is ignored for that module. If
the boundary_optimize_feedthrough_hpins attribute on an instance pin or module is set to false or true (does not have the inherited value), the setting of
this root attribute is ignored for that pin or module.
Related Information
Setting Boundary Optimization in Genus User Guide.
Affects these commands: syn_generic
syn_map
Affected by this attribute: boundary_opto
Related attributes: boundary_optimize_constant_hpins
boundary_optimize_equal_opposite_hpins
boundary_optimize_invert_hpins
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boundary_optimize_invert_hpins
boundary_optimize_invert_hpins {true | false | inherited}
Applies to:
root
module
hpin
Description
Default: false(root), inherited (module and hpin)
Data_type: bool (root), enum (module and hpin), read/write
Controls hierarchical boundary pin inversion. By default, hierarchical boundary pin inversion is disabled. If set to true, the boundary pin inversion is controlled
by the boundary_opto module attributes.
You can specify the following values:
true Allows boundary pin inversion.
false Prevents boundary pin inversion.
inherited Inherits the value of the boundary_optimize_invert_hpins module attribute.
If the boundary_opto attribute on a module is set and disables boundary optimization on the pins, the setting of this attribute is ignored for that
module. If the boundary_optimize_invert_hpins attribute on an instance pin or module is set to false or true (does not have the inherited value),
the setting of this root attribute is ignored for that pin or module.
If this attribute is set to true, the write_do_lec command adds the following LEC command to the dofile:
SET Naming Rule _BAR -Inverted_pin_extension
This LEC command specifies the string that is appended to pin names and net names by the tool when hierarchical boundary pins are inverted
during synthesis. To modify this string use the boundary_optimize_invert_hpins_renaming_extension root attribute. In the command above, the
_BAR value corresponds to the default value of this attribute.
Related Information
Setting Boundary Optimization in Genus User Guide.
Interfacing with Conformal Logical Equivalence Checker in Genus Interface to Conformal.
Affects these commands: syn_generic
syn_map
Affected by this attribute: boundary_opto
Related attributes: boundary_optimize_constant_hpins
boundary_optimize_equal_opposite_hpins
boundary_optimize_feedthrough_hpins
boundary_optimize_invert_hpins_rename_nets
boundary_optimize_invert_hpins_renaming_extension
boundary_optimize_invert_hpins_rename_nets
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Optimization--root Attributes in Optimization
boundary_optimize_invert_hpins_rename_nets {true | false}
Description
Default: true
Data_type: bool, read/write
Controls renaming of nets driven by the inverted hierarchical boundary pins. By default, the nets will be renamed.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
Affected by this attribute: boundary_optimize_invert_hpins
Related attribute: boundary_optimize_invert_hpins_renaming_extension
boundary_optimize_invert_hpins_renaming_extension
boundary_optimize_invert_hpins_renaming_extension <string>
Description
Default: _BAR
Data_type: string, read/write
Specifies the string to be appended to pin names and net names when hierarchical boundary pins are inverted during synthesis.
If you specify an empty string, you implicitly disable renaming for pins and nets. However this is not recommended, because the formal verification
tools need the naming extension to identify inverted boundary pins.
If the boundary_optimize_invert_hpins root attribute is set to true, the write_do_lec command adds the following LEC command to the dofile:
SET Naming Rule _BAR -Inverted_pin_extension
This LEC command specifies the string that is appended to pin names and net names by the tool when hierarchical boundary pins are inverted
during synthesis. To modify this string use the boundary_optimize_invert_hpins_renaming_extension root attribute. In the command above, the
_BAR value corresponds to the default value of this attribute.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
Affected by this attribute: boundary_optimize_invert_hpins
Related attribute: boundary_optimize_invert_hpins_rename_nets
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Optimization--root Attributes in Optimization
bus_naming_style
Syntax
bus_naming_style <string>
Applies to:
root
Description
Default: %s[%d]
Data_type: string, read/write
Specifies the naming convention for bussed ports and nets in the design. The new naming convention will only be available within Genus. When the netlist is
written out, the naming convention will revert to the default %s[%d] format.
Related Information
Affects these commands: syn_generic
syn_map
comb_seq_merge_message_threshold
comb_seq_merge_message_threshold <integer>
Description
Default: 10
Data_type: integer, read/write
Enables the printing of detailed messages when hierarchical instances with more cells than the specified threshold value are merged.
Example
set_db comb_seq_merge_message_threshold 2
2
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
Affect by this attribute: merge_combinational_hier_instances
cts_buffer_cells
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Optimization--root Attributes in Optimization
Syntax
cts_buffer_cells {list_of_buffer_cells}
Applies to:
root
Description
Default:
Data_type: string, read/write
Set of buffer cells allowed for clock tree implementation.
Related Information
Affects these commands: syn_generic
syn_map
Related attribute: map_clock_tree
cts_clock_gating_cells
Syntax
cts_clock_gating_cells {list_of_clock_gating_cells}
Applies to:
root
Description
Default:
Data_type: string, read/write
Set of clock_gating cells allowed for clock tree implementation.
Related Information
Affects these commands: syn_generic
syn_map
Related attribute: map_clock_tree
cts_inverter_cells
Syntax
cts_inverter_cells {list_of_inverter_cells}
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Optimization--root Attributes in Optimization
Applies to:
root
Description
Default:
Data_type: string, read/write
Set of inverter cells allowed for clock tree implementation.
Related Information
Affects these commands: syn_generic
syn_map
Related attribute: map_clock_tree
cts_logic_cells
Syntax
cts_logic_cells {list_of_logic_cells}
Applies to:
root
Description
Default:
Data_type: string, read/write
Set of buffer cells allowed for clock tree implementation.
Related Information
Affects these commands: syn_generic
syn_map
Related attribute: map_clock_tree
current_design
Syntax
current_design <object>
Applies to:
root
Description
Default:
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Optimization--root Attributes in Optimization
Data_type: object, read only
Returns the current top design object.
delete_flops_on_preserved_net
delete_flops_on_preserved_net {true | false}
Description
Default: true
Data_type: bool, read/write
Controls the deletion of load flip-flops on a preserved net. By default, the flops can be deleted.
Set this attribute to false to keep load flip-flops even if they do not drive any primary output, can be replaced with a constant, or can be deleted in some other
optimization.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
delete_hier_insts_on_preserved_net
delete_hier_insts_on_preserved_net {true | false}
Description
Default: true
Data_type: bool, read/write
Controls the deletion of empty hierarchical instances driven by a preserved net.
Set this attribute to false to keep the empty modules on a preserved net, even if they do not drive any primary output.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
delete_unloaded_insts
delete_unloaded_insts {true | false | inherited}
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Optimization--root Attributes in Optimization
Applies to:
module
root
Description
Default: true (root), inherited (module)
Data_type: bool (root), enum (module), read/write
Controls the deletion of unloaded hierarchical instances. You can specify one of the following values:
true Removes logic if none of the outputs are connected.
false Preserves any pre-existing hierarchical instances.
If you just want to maintain mapped and unmapped sequential instances, set the delete_unloaded_seqs attribute to false. Unmapped
(boolean) non-hierarchical instances cannot be rescued if they are unloaded.
inherited Inherits the value from the delete_unloaded_insts root attribute.
Related Information
Affects these commands: syn_generic
syn_map
Related attribute: delete_unloaded_seqs
delete_unloaded_seqs
delete_unloaded_seqs {true | false | inherited}
Applies to:
design
module
root
Description
Default: true (root), inherited (design and module)
Data_type: bool (root), enum (design and module), read/write
Controls the deletion of unloaded sequential instances.
You can specify one of the following values:
true Removes flip-flops and logic if they are not connected (transitively fanning out to output ports).
false Prevents the deletion of unloaded sequential instances.
inherited Inherits the value from the delete_unloaded_seqs root attribute.
This attribute only affects the syn_generic and syn_map commands, while the hdl_preserve_unused_registers attribute only affects the elaborate
command.
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Optimization--root Attributes in Optimization
Related Information
Affects these commands: syn_generic
syn_map
Related attributes: delete_unloaded_insts
hdl_preserve_unused_registers
derive_bussed_pins
Syntax
derive_bussed_pins {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Merges all indexed pins into a bus.
Example
If derive_bussed_pins is set to true, the following pins will be merged into a three-bit bus named A:
A[0]
A[1]
A[2]
design_power_effort
Syntax
design_power_effort {none | low | high)
Applies to:
root
Description
Default: none
Data_type: enum, read/write
Enables and controls power optimization, together with the opt_leakage_to_dynamic_ratio attribute. When performing power optimization, the tool will make a
trade off between power, delay, area, and runtime.
You can specify any of the following values:
none Disables power optimization.
low Performs a low-effort power optimization with minimum trade-off on delay, area, and runtime.
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Optimization--root Attributes in Optimization
high Performs the best power optimization with a higher trade-off on delay, area, and runtime. In this case, the runtime can be significantly higher.
It is recommended to use activity data from simulation.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related attribute: opt_leakage_to_dynamic_ratio
designs
Syntax
designs {list_of_designs}
Applies to:
root
Description
Default:
Data_type: design*, read only
Returns the list of design objects. This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls
command by default.
disable_ungroup_for_hierarchy
Syntax
disable_ungroup_for_hierarchy {false | true}
Applies to:
root
Description
Default: false
Data_type: boolean, read/write
Disables ungrouping for the hierarchy, if any instance has an exception applied on it.
display_information_of_edit_netlist
Syntax
display_information_of_edit_netlist {false | true}
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Optimization--root Attributes in Optimization
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Displays information about pins that are disconnected or connected through the 'edit_netlist' command. Shows instance name that are removed. Includes
information about Changelink. Set this attribute to 'true' to view messages. By default, the message limited is 20, which can be increased by using the
'message_count' attribute.
dont_use_qbar_seq_pins
dont_use_qbar_seq_pins {true | false}
Description
Default: false
Data_type: bool, read/write
Controls the use of the Qbar output pins of sequential libcells during optimization if other possibilities exist. By default, these pins can be used.
Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
Related attribute: dont_use_qbar_pin
double_cell_search_pattern
double_cell_search_pattern <string>
Description
Default:
Data_type: string, read/write
In case LEF is not provided, a search pattern is needed to identify which cells are double cells.
Applies to:
root
drc_first
drc_first {true | false}
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Optimization--root Attributes in Optimization
Description
Default: false
Data_type: bool, read/write
Specifies whether to give all design rule constraints higher priority than the timing constraints.
The design rule constraints are optimized in the following order:
1. max_transition
2. max_capacitance
3. max_fanout
Applies to:
root
Related Information
Affects these commands: report_design_rules
report_timing
syn_opt
Related attributes: drc_max_cap_first
drc_max_fanout_first
drc_max_trans_first
ignore_library_drc
map_drc_first
max_capacitance
max_fanout
max_transition
min_pulse_width
timing_disable_internal_inout_net_arcs
drc_max_cap_first
drc_max_cap_first {true | false}
Description
Default: false
Data_type: bool, read/write
Specifies whether to give the maximum capacitance cost higher priority than the timing constraints.
To optimize the maximum capacitance cost before the timing constraints, set the drc_first attribute to false and this attribute to true. In this case, the two other
design rule constraints are optimized after the timing constraints have been taken into account.
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If you set the drc_max_cap_first, drc_max_fanout_first, and drc_max_trans_first attributes to true, all design rule constraints are optimized before the
timing constraints and they are optimized in the following order:
1. max_transition
2. max_capacitance
3. max_fanout
Applies to:
root
Related Information
Affects these commands: report_design_rules
report_timing
syn_opt
Affected by this attribute: drc_first
Related attributes: drc_max_fanout_first
drc_max_trans_first
ignore_library_drc
max_capacitance
timing_disable_internal_inout_net_arcs
drc_max_fanout_first
drc_max_fanout_first {true | false}
Description
Default: false
Data_type: bool, read/write
Specifies whether to give the maximum fanout cost higher priority than the timing constraints.
To optimize the maximum fanout cost before the timing constraints, set the drc_first attribute to false and this attribute to true. In this case, the two other
design rule constraints are optimized after the timing constraints have been taken into account.
If you set the drc_max_cap_first, drc_max_fanout_first, and drc_max_trans_first attributes to true, all design rule constraints are optimized before the
timing constraints and in the following order:
1. max_transition
2. max_capacitance
3. max_fanout
Applies to:
root
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Related Information
Affects these commands: report_design_rules
report_timing
syn_opt
Affected by this attribute: drc_first
Related attributes: drc_max_cap_first
drc_max_trans_first
ignore_library_drc
max_fanout
drc_max_trans_first
drc_max_trans_first {true | false}
Description
Default: false
Data_type: bool, read/write
Specifies whether to consider the maximum transition cost before the timing constraints.
To optimize the maximum transition cost before the timing constraints, set the drc_first attribute to false and this attribute to true. In this case, the two other
design rule constraints are optimized after the timing constraints have been taken into account.
If you set the drc_max_cap_first, drc_max_fanout_first, and drc_max_trans_first attributes to true, the design rule constraints are optimized in the
following order:
1. max_transition
2. max_capacitance
3. max_fanout
Applies to:
root
Related Information
Affects these commands: report_design_rules
report_timing
syn_opt
Affected by this attribute: drc_first
Related attributes: drc_max_cap_first
drc_max_fanout_first
ignore_library_drc
max_transition
timing_disable_internal_inout_net_arcs
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Optimization--root Attributes in Optimization
driver_for_unloaded_hier_pins
Syntax
driver_for_unloaded_hier_pins {Z | 0}
Applies to:
root
Description
Default: Z
Data_type: enum, read/write
Controls how unloaded module ports are handled during incremental optimization. You can specify to connect these ports to constant 0, or you can leave them
unconnected (default) to minimize the number of assigns in the netlist.
This attribute does not apply to clock-gating hierarchies.
Related Information
Affects this command: syn_opt
enable_aon_type_in_remove_assign
enable_aon_type_in_remove_assign {true | false}
Description
Default: false
Data_type: bool, read/write
If set to true, it enables checking of aon type compatibility during remove assigns.
Applies to:
root
enable_strict_percent_control
enable_strict_percent_control {true | false}
Description
Default: false
Data_type: bool, read/write
Threshold value to be used as hard limit.
Applies to:
root
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Optimization--root Attributes in Optimization
exact_match_seq_async_ctrls
exact_match_seq_async_ctrls {true | false}
Description
Default: false
Data_type: bool, read/write
If set to true, the tool tries to avoid tying off the asynchronous control inputs of a flop to constants during technology mapping.
You must set this attribute to true before you load your library.
Applies to:
root
Related Information
Set and Reset Synthesis Pragmas in Genus HDL Modeling Guide.
Affects this command: syn_map
Related attribute exact_match_seq_sync_ctrls
fix_min_drcs
fix_min_drcs {true | false}
Description
Default: false
Data_type: bool, read/write
When set to true, fixes the minimum design rule costs based on calculations in the library. Specifically, the tool fixes the minimum capacitance, minimum
transition, and minimum fanout design rule violations by resizing the driver and its loads.
Applies to:
root
Related Information
Affects this command: syn_opt
group_generate_portname_from_netname
Syntax
group_generate_portname_from_netname {true | false}
Applies to:
root
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Optimization--root Attributes in Optimization
Description
Default: false
Data_type: bool, read/write
Determines whether the port names of a grouped module should be generated based on the names of the nets connected to these ports.
By default, the port name might be generated arbitrarily. Usually the port name of a new group is generated based on the names of the instance and pin to
which the port is connected.
Related information
Affects this command: group
group_instance_suffix
Syntax
group_instance_suffix <string>
Applies to:
root
Description
Default: i
Data_type: string, read/write
Controls the suffix added to the instance name of a new group hierarchy.
Example
The following command prevents a suffix to be added:
set_db / .group_instance_suffix ""
Related information
Affects this command: group
handle_ungroup_names
Syntax
handle_ungroup_names {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
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Enables handling names on different objects created during ungroup.
ignore_preserve_in_tiecell_insertion
Syntax
ignore_preserve_in_tiecell_insertion {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Ignores all preserve settings when inserting tie-cells during synthesis. During synthesis, the insertion of tie cells is controlled by the use_tiehilo_for_const root
attribute.
This attribute has no effect when the insertion of tie cells is requested using the insert_tiehilo_cells command.
Related Information
Affected by this attribute: use_tiehilo_for_const
Related attribute: iopt_allow_tiecell_with_inversion
inst_prefix
Syntax
inst_prefix <string>
Applies to:
root
Description
Default: g
Data_type: string, read/write
Specifies the prefix to be used together with an integer to generate new instance names. For example, g4044.
Each gate is named by constructing a string from the instance prefix and an integer that allows Genus to construct unique instance names. This attribute lets
you change the naming scheme for gates.
Related Information
Affects these commands: elaborate
syn_generic
syn_map
syn_opt
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Optimization--root Attributes in Optimization
iopt_allow_tiecell_with_inversion
Syntax
iopt_allow_tiecell_with_inversion {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the use of a tie cell with an inverter if either the tie high or tie low cell is not found. By default, a tie cell with inverter will not be used.
Related Information
Affects this command: syn_opt
Affected by this attribute: use_tiehilo_for_const
Related attribute: ignore_preserve_in_tiecell_insertion
iopt_enable_floating_output_check
Syntax
iopt_enable_floating_output_check {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the use of multiple output gates with floating outputs during incremental optimization. By default, multiple output gates with floating outputs can be
used.
Setting the attribute to true has the following effects:
During sizing, a gate can only be replaced with a higher or lower driver with the same number of outputs.
During gate composition, a gate will not be replaced with a multiple-output gate with floating outputs, that is, it can be replaced with a single output gate.
Related Information
Affects this command: syn_opt
iopt_force_constant_removal
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Optimization--root Attributes in Optimization
Syntax
iopt_force_constant_removal {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Forces the optimization of gates with inputs tied to constants independent of the QoR.
Related Information
Affects this command: syn_opt
iopt_remap_avoided_cells
Syntax
iopt_remap_avoided_cells {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether to replace (remap) unpreserved avoided cells in the mapped netlist. For those cells that cannot be remapped, the tool will issue messages.
Related Information
Affects this command: syn_opt
iopt_sequential_duplication
Syntax
iopt_sequential_duplication {true | false}
Applies to:
root
Description
Default: false
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Optimization--root Attributes in Optimization
Data_type: bool, read/write
Controls duplication of sequential (flops) elements during incremental optimization. It duplicates the flops on the critical timing path to improve the timing of this
path.
Duplicate registers will have the following naming style:
<original register name>_SYNTHESIS_SEQ_DUP_<index>
Related Information
Affects this command: syn_opt
iopt_sequential_resynthesis
Syntax
iopt_sequential_resynthesis {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls sequential resynthesis during incremental optimization.
Related Information
Affects this command: syn_opt
Affected by this attribute: iopt_sequential_resynthesis_min_effort
iopt_sequential_resynthesis_min_effort
Syntax
iopt_sequential_resynthesis_min_effort {high | medium | low}
Applies to:
root
Description
Default: high
Data_type: enum, read/write
Specifies the minimum effort required for incremental optimization to perform sequential resynthesis.
Related Information
Affects this command: syn_opt
Affects this attribute: iopt_sequential_resynthesis
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Optimization--root Attributes in Optimization
iopt_temp_directory
Syntax
iopt_temp_directory <string>
Applies to:
root
Description
Default: .
Data_type: string, read/write
Specifies the directory where parallel incremental optimization can write temporary files. By default, the files are written to the current directory from where
Genus was invoked. The directory must be writable.
Related Information
Affects this command: syn_opt
iopt_ultra_optimization
Syntax
iopt_ultra_optimization {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls how rigorously incremental optimization should work to achieve the best QoR (timing and area).
Due to the iterative nature of the algorithms, this attribute will have an impact on the run-time.
Related Information
Affects this command: syn_opt
map_clock_tree
map_clock_tree {true | false}
Description
Default: false
Data_type: bool, read/write
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Genus Attribute Reference
Optimization--root Attributes in Optimization
Enables mapping of clock logic to a specified set of library cells. You should specify allowed clock tree cells by using the following attributes:
cts_buffer_cells, cts_inverter_cells, cts_clock_gating_cells, and cts_logic_cells. Specification of clock tree cells and enabling mapping of clock logic
should be done before calling syn_generic. At the end of syn_map all clock tree logic will then be mapped to the specified set of cells.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
Related attributes: cts_buffer_cells
cts_clock_gating_cells
cts_inverter_cells
cts_logic_cells
map_drc_first
map_drc_first {true | false}
Description
Default: false
Data_type: bool, read/write
Specifies whether to use the design rule constraints as a preferred costing factor for selecting cells from the library during mapping. These constraints are
considered with the other costs, such as area, timing and power, but by default they are not given the highest weight.
Applies to:
root
Related Information
Affects this command: syn_map
Related attribute: drc_first
map_latch_allow_async_decomp
map_latch_allow_async_decomp {true | false}
Description
Default: false
Data_type: bool, read/write
If set to true, the tool will implement asynchronous control logic outside the latch using combinational gates if the library does not have latch libcells with the
required asynchronous functionality. For example, a reset latch could be implemented using a simple latch libcell with combinational logic driving the d and ena
inputs.
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Optimization--root Attributes in Optimization
Applies to:
root
Related Information
Affects this command: syn_map
map_prefer_non_inverted_clock_line
map_prefer_non_inverted_clock_line {true | false}
Description
Default: true
Data_type: bool, read/write
Controls the insertion of inverters on the clock line. By default, the tool tries to avoid inserting inverters on the clock line. If you set this attribute to false, the tool
chooses the best solution for QoR, which might include inserting inverters.
Applies to:
root
Related Information
Affects this command: syn_map
map_respect_rtl_clk_phase
map_respect_rtl_clk_phase {true | false}
Description
Default: false
Data_type: bool, read/write
If set to true, the tool will use sequential elements with the same sensitivity, as specified in the RTL:
In case of high-level RTL using @posedge or @negedge
This applies to flip-flops only. The desired clock edge of the target flip-flop is derived from the @xxxedge.
In case of netlist RTL
If the tool finds already instantiated library cells when reading an RTL description it remembers the clock edge for flip-flops or the enable active level for
latches and tries to keep that in subsequent remappings.
If the library has no libcells with the required sensitivity, the tool will use any available libcells.
By default, the tool will use flip-flop libcells with a certain clock phase that avoid adding an inverter for the clock.
Example
Consider the following module in RTL:
module mix_edge ( clk, d0, q0, q1, q0_inv, q1_inv, d1, d2,d3);
input clk, d0, d1, d2, d3;
output q0, q1, q0_inv, q1_inv;
reg q0, q1, q0_inv, q1_inv;
wire clkn;
assign clkn = ~clk;
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always @(negedge clk)
q0 = d0;
always @(posedge clk)
q1 = d1;
always @(negedge clkn)
q0_inv = d2;
always @(posedge clkn)
q1_inv = d3;
endmodule
If you use the default setting of false for map_respect_rtl_clk_phase, the tool will use the following mappings:
q0_reg will be mapped to FFRNQ1, a negative-edge triggered flip-flop
q1_reg will be mapped to FFPQ1,a positive-edge triggered flip-flop
q0_inv_reg will be mapped to FFPQ1,a positive-edge triggered flip-flop
q1_inv_reg will be mapped to FFRNQ1,a negative-edge triggered flip-flop
If you set map_respect_rtl_clk_phase to true, the tool uses the following mappings:
q0_reg will be mapped to FFRNQ1, a negative-edge triggered flip-flop
q1_reg will be mapped to FFPQ1,a positive-edge triggered flip-flop
q0_inv_reg will be mapped to FFRNQ1,a negative-edge triggered flip-flop + inverter
q1_inv_reg will be mapped to FFPQ1,a positive-edge triggered flip-flop + inverter
Applies to:
root
Related Information
Affects this command: syn_map
Related attribute: map_prefer_non_inverted_clock_line
map_to_multiple_output_gates
Syntax
map_to_multiple_output_gates {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
When the value is true (default), Genus can map to more complex multi-output cells beyond half and full adders during incremental optimization.
Related Information
Affects this command: syn_opt
max_cpus_per_server
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Optimization--root Attributes in Optimization
max_cpus_per_server <integer>
Description
Default: 8
Data_type: integer, read/write
Controls the maximum number of active CPUs that the tool is allowed to use per server for super-threading and multi-threading.
Examples
The following command enables 3 CPUs on the local host:
set_db / .max_cpus_per_server 3
The following commands enable 5 CPUs on various servers:
set_db / .super_thread_servers {localhost linux33}
set_db / .max_cpus_per_server 5
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: auto_super_thread
super_thread_servers
merge_combinational_hier_instances
merge_combinational_hier_instances {true | false}
Description
Default: true
Data_type: bool, read/write
Allow merging of combinational hierarchical instances.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
merge_non_scan_to_scan_flops
merge_non_scan_to_scan_flops {true | false}
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Description
Default: false
Data_type: bool, read/write
If set to true, it enables merging of non scan flops to scan flops during multibit merging.
Applies to:
root
minimize_uniquify
minimize_uniquify {true | false | inherited}
Applies to:
module
root
Description
Default: false (root), inherited (module)
Data_type: bool (root), enum (module), read/write
Controls uniquification of all modules in the design. By default, the tool uniquifies multiple instantiations with different context (timing, constants, and so on) to
deliver the best QoR.
Set this attribute to true to limit the scenarios of uniquification of multiply-instantiated modules and potentially improve runtime with a trade-off against QoR .
This will not necessarily prevent uniquification from algorithmic considerations of the design topology.
Related Information
Affects this command: syn_map
mtdcl_traverse_by_level
mtdcl_traverse_by_level {true | false}
Description
Default: false
Data_type: bool, read/write
Traverses instances in the clock path, 1 level at a time.
Applies to:
root
multibit_allow_sr_head_flop_merge
multibit_allow_sr_head_flop_merge {true | false}
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Optimization--root Attributes in Optimization
Description
Default: false
Data_type: bool, read/write
If set to true, it enables merging of head flops of shift register during multibit merging.
Applies to:
root
multibit_allow_unused_bits
multibit_allow_unused_bits {true | false}
Description
Default: true
Data_type: bool, read/write
Controls whether a mapped multibit instance can have one or more unused bits. By default, the tool will try to merge the single-bit registers to multibit
instances without unused bits. If during merging, the tool cannot find a suitable multibit lib_cell with a width that matches the left-over bits of a bus, it will
choose the closest matching width which leaves the minimum unused bits. If the attribute is set to false, any merging which results in unused
(undriven/unloaded) bits will be prevented and thus reduce the multibit merging coverage.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attributes: bit_width
use_multibit_cells
multibit_area_power_scoring
multibit_area_power_scoring {none | area_only | area_power}
Description
Default: none
Data_type: enum, read/write
Controls whether area and power are to be scored in merging.
Applies to:
root
multibit_aware_seq_mapping
multibit_aware_seq_mapping {auto | true | false}
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Description
Default: auto
Data_type: enum, read/write
The mapper prefers sequential cells which have corresponding multibit variants. If the library does not have suitable cells with multibit equivalents, all
sequential cells are used. The tool does not perform this optimization for the instances where multibit merging is disabled with 'dont_merge_multibit'.
This attribute can have the following values:
auto Enables the multibit-aware mapping only if use_multibit_cells is true.
true Enables the multibit-aware mapping independent from use_multibit_cells.
false Disables the multibit-aware mapping.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_map
Related attributes: use_multibit_cells
dont_merge_multibit
merge_multibit
multibit_aware_seq_mapping_higher_priority
multibit_aware_seq_mapping_higher_priority
multibit_aware_seq_mapping_higher_priority {true | false}
Description
Default: false
Data_type: bool, read/write
Prioritize multibit_aware_seq_mapping over other constraints such as avoid_tied_inputs, map_prefer_non_inverted_clock_line,
exact_match_seq_async_ctrls, or exact_match_seq_sync_ctrls. When enabled, multibit_aware_seq_mapping still has lower priority than map_to_register,
and map_to_ser_register constraints. Additionally, scan and state retention requirements will also be honored.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_map
Related attributes: multibit_aware_seq_mapping
multibit_debug
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Optimization--root Attributes in Optimization
multibit_debug {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether to write debug information related to multibit mapping to the logfile.
Example
Consider the following netlist after mapping and before incremental synthesis:
module test(resetn, clk, in, out);
input resetn, clk;
input [1:0] in;
output [1:0] out;
DFCF cnt_0_reg[0] (.CDN (resetn), .CP (clk), .D(in[0]), .Q (out[0] ));
DFCF cnt_0_reg[1] (.CDN (resetn), .CP (clk), .D(in[1]), .Q (out[1] ));
endmodule
module top(resetn, clk, in, out);
input resetn, clk;
input [1:0] in;
output [1:0] out;
test t(resetn, clk, in, out);
endmodule
When multibit_debug is set to true, the following debug information is dumped in logfile during multibit mapping:
If multibit instance is created:
Trying to make multibit bank CDN_MBIT_cnt_0_reg[0]_MB_cnt_0_reg[1] out of
cnt_0_reg[0] (DFCF)
cnt_0_reg[1] (DFCF)
CDN_MBIT_cnt_0_reg[0]_MB_cnt_0_reg[1] multibit bank of type DUALDFSF accepted in sandbox.
If multibit instance is not created:
Trying to make multibit bank CDN_MBIT_cnt_0_reg[0]_MB_cnt_0_reg[1] out of
cnt_0_reg[0] (DFCF)
cnt_0_reg[1] (DFCF)
CDN_MBIT_cnt_0_reg[0]_MB_cnt_0_reg[1] multibit bank rejected (worse QoR).
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attributes: bit_width
use_multibit_cells
multibit_invert_clock_phase
multibit_invert_clock_phase {false | true}
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Description
Default: false
Data_type: bool, read/write
If set to 'true', enables merging of cells with inverted clock phase.
Applies to:
root
multibit_mapping_effort_level
multibit_mapping_effort_level {auto | high | low}
Description
Default: high
Data_type: enum, read/write
Controls the effort level for physical-aware multibit mapping. That is, controls the tradeoff between multibit coverage and QoR.
This attribute can have the following values:
auto Balances multibit coverage and QoR to get the most optimal results.
high Increases multibit coverage but might impact QoR.
low Gives the best QoR.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt -spatial
Related attributes: use_multibit_cells
multibit_predefined_allow_unused_bits
multibit_predefined_allow_unused_bits {true | false}
Description
Default: false
Data_type: bool, read/write
Controls whether instances of predefined mulitibit cells can have unused bits. By default, the tool does not allow unused bits in predefined multibit instances.
Applies to:
root
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Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attributes: bit_width
use_multibit_cells
multibit_unused_input_value
multibit_unused_input_value {0 | 1 | none}
Description
Default: 0
Data_type: string, read/write
Specifies the value to which all unconnected input pins in the multibit cells must be connected. By default, the unused input pins of multibit cells are connected
to constant 0. If you set the attribute to none, the input pins will be left floating.
Applies to:
root
Related Information
Mapping to Multibit Cells in Genus Synthesis Flows Guide.
Affects this command: syn_opt
Related attribute: use_multibit_cells
opt_allow_floating_outputs
opt_allow_floating_outputs {false | true}
Description
Default: false
Data_type: bool, read/write
If set to 'true', mapping and incremental optimization are allowed to use multi-output gates and leave some outputs dangling.
Applies to:
root
Related Information
Affects this command: syn_map
opt_high_effort_cells
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Optimization--root Attributes in Optimization
Syntax
opt_high_effort_cells { }
Applies to:
root
Description
Default:
Data_type: lib_cell*, read/write
Accepts a list of cells to be used for high effort optimization. Dont-use and Dont-touch constraints for these cells are ignored for high effort optimization.
This attribute is not directly used by Genus but instead, when set, is shared with Innovus.
Related Information
Related commands: syn_opt
setOptMode
getOptMode
opt_spatial_effort
Syntax
opt_spatial_effort {standard | extreme}
Applies to:
root
Description
Default: standard
Data_type: enum, read/write
Specifies the level of optimization effort for executing syn_opt -spatial.
Related Information
Related command: syn_opt
opt_tns
opt_tns {true | false}
Description
Default: true
Data_type: bool, read/write
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Controls whether timing slack is optimized only on the most critical path or also on other paths with negative slack.
By default, the syn_map command focuses on the critical path to produce a smaller design. When the critical path has negative slack, other near critical paths
can also be relaxed to recover area.
When the opt_tns attribute is set to true, it forces the tool to consider all the endpoints for the optimization. The appropriate weight is given to the slack of each
endpoint during the optimization. More drastic area recovery is not performed on violating paths to prevent worsening the total negative slack (TNS).
Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
optimize_constant_0_flops
optimize_constant_0_flops {true | false}
Description
Default: true
Data_type: bool, read/write
Allows constant 0 propagation through flip-flops.
Applies to:
root
Related Information
Affects these commands: elaborate
syn_generic
syn_map
Affects this attribute: optimize_constant_0_seq
optimize_constant_1_flops
optimize_constant_1_flops {true | false}
Description
Default: true
Data_type: bool, read/write
Allows constant 1 propagation through flip-flops.
Applies to:
root
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Related Information
Affects these commands: elaborate
syn_generic
syn_map
Affects this attribute: optimize_constant_1_seq
optimize_constant_across_preserved
optimize_constant_across_preserved {true | false}
Description
Default: true
Data_type: bool, read/write
Allows constant to propagate across preserved instances.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
optimize_constant_feedback_seqs
optimize_constant_feedback_seqs {true | false}
Description
Default: true
Data_type: bool, read/write
Controls constant propagation through a FF with feedback. By default, these flip-flops can be optimized, that is, replaced with a logic constant.
Example
Consider the following RTL:
module test(clk, a, z, z2);
input clk, a;
output z, z2;
wire clk, d;
reg z, z2, q;
assign d2 = 1'b1;
assign d = q & a;
always @(posedge clk) begin
z2 <= d2;
q <= d;
z <= q;
end
endmodule // test
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Assume the following script:
set_db library tutorial.lib
set_db information_level 9
read_hdl test.v
elab
#set_db optimize_constant_feedback_seqs false
syn_gen
syn_map
write
When you use the default value of the optimize_constant_feedback_seqs attribute, the following netlist is written after mapping:
module test(clk, a, z, z2);
input clk, a;
output z, z2;
wire clk, a;
wire z, z2;
assign z2 = 1'b1;
assign z = 1'b0;
endmodule
Register q is an uninitialized flip-flop with feedback. Because the input d is the output of an AND logic, the stable state will be constant 0. When both the
optimize_constant_feedback_seqs root attribute and the optimize_constant_feedback_seq instance attribute for q_reg are set to true, q_reg is replaced
with constant 0.
When you set the optimize_constant_feedback_seqs attribute to false, the following netlist is written after mapping:
module test(clk, a, z, z2);
input clk, a;
output z, z2;
wire clk, a;
wire z, z2;
wire n_0, n_1, q;
assign z2 = 1'b1;
fflopd q_reg(.CK (clk), .D (n_1), .Q (q));
inv1 g27(.A (n_0), .Y (n_1));
nand2 g28__7837(.A (q), .B (a), .Y (n_0));
fflopd z_reg(.CK (clk), .D (q), .Q (z));
endmodule
In this case, the q_reg (with feedback loop) is not replaced by a constant.
Applies to:
root
Related Information
Affects these commands: elaborate
syn_generic
syn_map
optimize_constant_latches
optimize_constant_latches {true | false}
Description
Default: true
Data_type: bool, read/write
When set to true, a latch whose output never changes is replaced by the corresponding constant value.
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Applies to:
root
Related Information
Affects these commands: elaborate
syn_generic
syn_map
Affects this attribute: optimize_constant_0_seq
optimize_constant_1_seq
optimize_merge_flops
optimize_merge_flops {true | false}
Description
Default: true
Data_type: bool, read/write
Controls merging of equivalent flops. Set this attribute to false to prevent merging.
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
Affects this attribute: optimize_merge_seq
Related attribute: optimize_merge_latches
optimize_merge_latches
optimize_merge_latches {true | false}
Description
Default: true
Data_type: bool, read/write
Controls merging of equivalent latches. Set this attribute to false to prevent merging.
Applies to:
root
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Related Information
Affects these commands: syn_generic
syn_map
Affects this attribute: optimize_merge_seq
Related attribute: optimize_merge_flops
optimize_seq_x_to
optimize_seq_x_to {0 | 1 | x}
Description
Default: 0
Data_type: enum, read/write
Allows the propagation of the specified constant value (0, 1, or dont_care(x)) through flops/latches when they are in dont care (x) state.
Applies to:
root
optimize_yield
optimize_yield {false | true}
Description
Default: false
Data_type: bool, read/write
Sets the tool into yield optimization mode. You must set this attribute to true to use the design for manufacturing (DFM) flow.
Applies to:
root
Related Information
Design For Manufacturing Flow in the Genus Synthesis Flows Guide.
Affects these commands: report_gates -yield
report_yield
Affects this attribute: yield
partition_based_synthesis
Syntax
partition_based_synthesis {false | true}
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Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls the partition-based synthesis flow.
Setting this attribute to false can significantly impact the runtime.
pbs_db_directory
pbs_db_directory string
Description
Default: .
Data_type: string, read/write
Specifies the directory where partition-based synthesis can write temporary files.
root
pbs_gen_summary
Syntax
pbs_gen_summary <string>
root
Description
Default:
Data_type: string, read only
Prints the partition metrics summary for the pbs generic stage.
pbs_iopt_summary
Syntax
pbs_iopt_summary <string>
root
Description
Default:
Data_type: string, read only
Prints the partition metrics summary for the pbs iopt stage.
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pbs_load_lib_in_group_of
Syntax
pbs_load_lib_in_group_of <integer>
Applies to:
root
Description
Default: 0
Data_type: integer, read/write
Specifies the number of background servers on which the libraries can be loaded in parallel.
This attribute is useful for machines with multiple CPUs but small memory using localhost to run super-thread jobs. Since some memory is freed up after
reading in libraries, it can prevent Genus from using too much memory at one time.
Example
Assume you have 8 background servers. If you set the value of the pbs_load_lib_in_group_of attribute to 4, library loading will happen in parallel for the first
four servers, and when the call to these four servers is complete, library loading will happen on the next four servers.
pbs_map_summary
Syntax
pbs_map_summary <string>
root
Description
Default:
Data_type: string, read only
Prints the partition metrics summary for the pbs mapping stage.
percent_control_tolerance_for_map
percent_control_tolerance_for_map <double>
Description
Default: 10.0
Data_type: double, read/write
Specifies the tolerance to add for tall and short limits for mapping (does not apply to doubles).
Applies To:
root
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predict_floorplan_enable_during_generic
Syntax
predict_floorplan_enable_during_generic {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enables the predict_floorplan flow in generic stage.
Related Information
Affects this command: predict_floorplan
preserve_combinational_loop_ports_nets
preserve_combinational_loop_ports_nets {true | false}
Description
Default: true
Data_type: bool, read/write
Preserves nets and hierarchical pins involved in combinational loops after elaboration to keep reference points for further verification.
Applies to:
root
Related Information
Related attribute: print_ports_nets_preserved_for_cb
print_ports_nets_preserved_for_cb
print_ports_nets_preserved_for_cb {true | false}
Description
Default: false
Data_type: bool, read/write
Prints nets and hierarchical pins involved in combinational loops that were preserved for verification.
Applies to:
root
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propagate_constant_from_timing_model
propagate_constant_from_timing_model {true | false | inherited}
Applies to:
hinst
inst
root
Description
Default: true (root), inherited (hinst and inst)
Data_type: bool (root), enum (hinst and inst), read/write
Controls constant propagation from timing model instances. If your design contains instances of timing models whose output function is defined as constant 0 or
1, you must indicate whether the tool can propagate the constant. If you set the attribute to false, constants will not be propagated. The available values are:
true Allows constant propagation from this timing model instance.
false Prevents constant propagation from this timing model instance.
inherited Inherits the value of the propagate_constant_from_timing_model root attribute.
Related Information
Affects these commands: syn_generic
syn_map
proto_feasible_target
proto_feasible_target {true | false}
Description
Default: false
Data_type: bool, read/write
Enables support for incomplete SDC constraints. When enabled, the mapper ignores huge negative slack endpoints in the target computation and optimization.
Applies to:
root
Related Information
Affects this command: syn_map
proto_feasible_target_adjust_slack_pct
proto_feasible_target_adjust_slack_pct <integer>
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Description
Default: 100
Data_type: integer, read/write
Specifies the percentage of slack value to be used as positive adjust value in path_adjust exceptions.
This attribute has only effect if the proto_feasible_target attribute was enabled.
Applies to:
root
Related Information
Affects this command: syn_map
Affected by this attribute: proto_feasible_target
proto_feasible_target_threshold
proto_feasible_target_threshold <float>
Description
Default:
Data_type: delay, read/write
Specifies the minimum threshold delay for which path_adjust should be applied.
This attribute has only effect if the proto_feasible_target attribute is enabled.
Applies to:
root
Related Information
Affects this command: syn_map
Affected by this attribute: proto_feasible_target
proto_feasible_target_threshold_clock_pct
proto_feasible_target_threshold_clock_pct <integer>
Description
Default: 75
Data_type: integer, read/write
Specifies the slack to clock period percentage for which path_adjust should be applied.
This attribute has only effect if the proto_feasible_target attribute is enabled.
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Applies to:
root
Related Information
Affects this command: syn_map
Affected by this attribute: proto_feasible_target
Related attribute: proto_feasible_target_threshold
remove_assigns
Syntax
remove_assigns {true | false}
Applies to:
design
root
Description
Default: false
Data_type: bool, read/write
Determines whether assign statements should be replaced with buffers or inverters in the netlist.
When this attribute is set to true, the generated netlist will not contain any assign statements. Depending on the availability of cells in the library, and the
settings of the set_remove_assign_options command, the assign statements might be replaced with buffers or inverters.
Examples
For the following examples, assume the following constant assignments in the RTL code:
assign out1 = 1’b0;
assign out2 = 1’b0;
If the remove_assigns attribute us set to false, the netlist will remain unchanged.
If the remove_assigns attribute us set to true, the netlist will look like:
BUFX1 rm_assigns_buf_q3(.A (1’b0), .Y (out1));
BUFX1 rm_assigns_buf_q3(.A (1’b0), .Y (out2));
Related Information
Affects this command: syn_opt
Affected by this command: remove_assigns_without_opt
Affects this attribute: use_tiehilo_for_const
retime_async_reset
retime_async_reset {true | false}
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Description
Default: true
Data_type: bool, read/write
Specifies whether registers with asynchronous set or reset signals should be retimed. Registers with both asynchronous set and reset signals will not be
retimed regardless of this attribute’s value.
Applies to:
root
Related Information
Affects these commands: syn_generic
Related attributes: dont_retime
retime
retime_optimize_reset
retime_effort_level
retime_effort_level {low | medium | high}
Description
Default: medium
Data_type: enum, read/write
Controls the optimizations used during retiming.
Using the default medium effort ensures that the design can be verified with the Conformal ® Logical Equivalence Checker using the default flow. Using high
effort causes the tool to use optimization techniques that could trade off better QoR against ease of formal verification.
Applies to:
root
Related Information
Affects these commands: syn_generic
write_do_lec
Related attributes: dont_retime
retime
retime_move_mux_loop_with_reg
retime_move_mux_loop_with_reg {true | false}
Description
Default: true
Data_type: bool, read/write
Directs retiming to maintain the mux-feedback loop for a flop with the flop itself during the retiming moves. This implies that retiming cannot separate the mux
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loop and move logic through the feedback loop.
Applies to:
design
module
root
Related Information
Affects this command: syn_generic
Related attributes: dont_retime
retime
retime_ssw_sync_enable
retime_optimize_reset
retime_optimize_reset {true | false}
Description
Default: false
Data_type: bool, read/write
Specifies whether the asynchronous reset signals of registers should be optimized during retiming optimization. If set to true, any asynchronous reset signal
that can be eliminated while preserving the functionality of the logic will be removed. That is, the reset will be dropped if the computation results in a dont_care
value.
Applies to:
root
Related Information
Affects this command: syn_generic
Related attributes: dont_retime
retime
retime_async_reset
retime_reg_naming_suffix
retime_reg_naming_suffix string
Description
Default: _reg
Data_type: string, read/write
Marks those registers that were moved due to retiming optimization with the specified suffix.
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Example
The following example instructs the tool to add the '_retimed_reg' suffix to all registers that are moved during retiming optimization:
set_db retime_reg_naming_suffix _retimed_reg
Setting attribute of root '/': 'retime_reg_naming_suffix' = _retimed_reg
1 _retimed_reg
The affected registers could look like the following example:
(n_124)); D_F_LPH0002_H 16_retime_reg(.E (ck), .D (n_118), .L2N (n_159)); INVERT_J g48(.A (n_167), .Z (n_119)); D_F_LPH0001_E
17_retime_reg(.E (ck), .D (n_118), .L2 (n_158)); D_F_LPH0002_E 18_retime_reg(.E (ck), .D (n_112), .L2N (n_165)); INVERT_H g52(.A (n_116), .Z
(n_117)); INVERT_H g55(.A (n_104), .Z (n_115));
Applies to:
root
Related Information
Affects this command: syn_generic
Related attributes dont_retime
retime
retime_async_reset
retime_original_registers
trace_retime
retime_verification_flow
retime_verification_flow {true | false}
Description
Default: true
Data_type: bool, read/write
Enables retiming verification with the Conformal ® Logical Equivalence Checker. Set this attribute to true before you use the syn_generic command.
Applies to:
root
Related Information
Affects this command: syn_generic
Related attributes dont_retime
retime
retime_async_reset
retime_original_registers
trace_retime
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retiming_clocks
Syntax
retiming_clocks <clocks>
Applies to:
design
root
Description
Default:
Data_type: object*, read/write
Performs retiming on the registers clocked by the specified clocks.
Related Information
Affects this command: syn_generic
Affected by these attributes: dont_retime
retime
Related attributes: retime_async_reset
retime_original_registers
trace_retime
skip_ungroup_on_applied_constraint
Syntax
skip_ungroup_on_applied_constraint {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Disables the ungroup on hierarchies when there is a constraint applied to it.
The tagging of hierarchies with constraint applied is enabled only when the 'start_preserve_for_auto_ungroup_constraints' command is specified while
loading the constraint files.
skip_ungroup_with_exception
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Syntax
skip_ungroup_with_exception {false | true}
Applies to:
root
Description
Default: false
Data_type: boolean, read/write
Controls allowing a hierarchical instance with an exception or timing constraint to ungroup.
st_launch_wait_time
st_launch_wait_time <integer>
Description
Default: 10
Data_type: int, read/write
Specifies the maximum wait time (in minutes) before launching super-thread processes.
If all required resources (specified by the max_cpus_per_server and super_thread_servers attributes) can be obtained before the specified wait time is finished,
the tool will start the synthesis job. If not, the tool will start with the resources that are available at the end of the wait time.
The longer the waiting time, the better the chance you have to obtain all required resources. You are encouraged to change this value according to your
resource conditions.
Applies to:
root
stop_at_iopt_state
Syntax
stop_at_iopt_state <integer>
Applies to:
root
Description
Default:
Data_type: int, read/write
Specifies the state (integer) at which incremental optimization stopped. If you use the cntrl-c key sequence in the middle of incremental optimization, Genus
will stop, bring you back to the Genus command line, and issue a warning message with an IOPT state. Next time you enter a Genus session (with the same
commands, constraints, script, etc. that preceded the cntrl-c halt) you can use specify the IOPT state at which you stopped with the stop_at_iopt_state
attribute. Genus will continue with the netlist it had generated at the specified state.
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Related Information
Affects these commands: syn_map
syn_opt
super_thread_batch_command
Syntax
super_thread_batch_command {queue_command}
Applies to:
root
Description
Default: bsub
Data_type: string, read/write
Specifies LSF or SGE commands to submit jobs to the queueing system for super-threading. Use this attribute in conjunction with the
super_thread_kill_command attribute, which specifies LSF or SGE commands to remove jobs from the queueing system.
Recommended settings are:
for LSF
bsub -q -o /dev/null -J
and
for SGE
qsub -q -b y -j y -o /dev/null
Examples
The following example uses the SGE qsub command to submit the "RC_server" job to the "lnx-penny" queue and specifies that no output file should be
created. The super_thread_kill_command attribute passes the qdel command to SGE to appropriately remove the job after it has finished:
set_db super_thread_batch_command \
{qsub -N RC_server -q lnx-penny -b y -j y -o /dev/null}
set_db super_thread_kill_command {qdel} /
The following example uses the LSF bsub command to submit the "RC_server" job to the "lnx-penny" queue and specifies that no output file should be
created. The super_thread_kill_command attribute passes the bkill command to LSF to appropriately remove the job after it has finished:
set_db super_thread_batch_command \
{bsub -q lnx-penny -o /dev/null -J RC_server}
set_db super_thread_kill_command {bkill}
Do not use the bsub options -I, -Ip, or -Is. The super-threading behavior can become unpredictable with these LSF options.
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Related Information
Related attributes: super_thread_debug_directory
super_thread_equivalent_licenses
super_thread_kill_command
super_thread_rsh_command
super_thread_servers
super_thread_status_command
super_thread_debug_directory
Syntax
super_thread_debug_directory <directory>
Applies to:
root
Description
Default:
Data_type: string, read/write
Facilitates debugging of super-threading related issues and specifies the directory where super-thread data is to be saved for debugging purposes.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: super_thread_batch_command
super_thread_equivalent_licenses
super_thread_kill_command
super_thread_rsh_command
super_thread_servers
super_thread_status_command
super_thread_debug_jobs
Syntax
super_thread_debug_jobs {false | true}
Applies to:
root
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Description
Default: false
Data_type: boolean, read/write
Dumps the debug information for jobs.
super_thread_equivalent_licenses
Syntax
super_thread_equivalent_licenses <string>
Applies to:
root
Description
Default: GENUS_CPU_Opt Genus_Synthesis Virtuoso_Digital_Implem Virtuoso_Digital_Implem_XL
Data_type: string, read/write
Specifies the order in which licenses can be checked out for super-thread servers.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Related attributes: super_thread_batch_command
super_thread_debug_directory
super_thread_kill_command
super_thread_rsh_command
super_thread_servers
super_thread_status_command
super_thread_kill_command
Syntax
super_thread_kill_command {queue_command}
Applies to:
root
Description
Default: bkill -s 9
Data_type: string, read/write
Specifies LSF or SGE commands to remove jobs from the queueing system for super-threading. Use this attribute in conjunction with the
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Optimization--root Attributes in Optimization
super_thread_batch_command attribute, which specifies LSF or SGE commands to submit jobs to the queueing system.
Examples
The following example uses the SGE qsub command to submit the "RC_server" job to the "lnx-penny" queue and specifies that no output file should be
created. The super_thread_kill_command attribute passes the qdel command to SGE to appropriately remove the job after it has finished:
set_db super_thread_batch_command \
{qsub -N RC_server -q lnx-penny -b y -j y -o /dev/null}
set_db super_thread_kill_command {qdel} /
The following example uses the LSF bsub command to submit the "RC_server" job to the "lnx-penny" queue and specifies that no output file should be
created. The super_thread_kill_command attribute passes the bkill command to LSF to appropriately remove the job after it has finished:
set_db super_thread_batch_command \
{bsub -q lnx-penny -o /dev/null -J RC_server}
set_db super_thread_kill_command {bkill}
Related Information
Related attributes: super_thread_batch_command
super_thread_debug_directory
super_thread_equivalent_licenses
super_thread_rsh_command
super_thread_servers
super_thread_status_command
super_thread_rsh_command
Syntax
super_thread_rsh_command <command>
Applies to:
root
Description
Default: rsh
Data_type: string, read/write
Specifies the UNIX command to start a shell on another host.
For security reasons, some hosts do not allow you to use the rsh command (default) to connect to them, but they may allow you to use ssh or another command.
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Optimization--root Attributes in Optimization
Related Information
Related attributes: super_thread_batch_command
super_thread_debug_directory
super_thread_equivalent_licenses
super_thread_kill_command
super_thread_servers
super_thread_status_command
super_thread_servers
Syntax
super_thread_servers {machine_names [batch]}
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies a list of machine names that should be used for super-threading. Genus supports super-thread servers of different platform types. Super-threading is
the process of distributing work across multiple CPUs.
If you want to specify either the LSF or SGE queue managers, use the batch argument instead of any machine name.
Examples
The following example illustrates Genus launching three processes on the current machine for super-threading:
set_db super_thread_servers {<localhost> <localhost> <localhost>}
The runtime reduction using the super-threading feature is proportional to the number of CPUs provided for synthesis.
The following example illustrates Genus launching two server processes on the machine called linux33, one process on sun42, and one process on a
queue manager:
set_db super_thread_servers {linux33 linux33 sun42 batch}
Related Information
Related attributes: max_cpus_per_server
super_thread_batch_command
super_thread_debug_directory
super_thread_equivalent_licenses
super_thread_kill_command
super_thread_rsh_command
super_thread_status_command
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Optimization--root Attributes in Optimization
super_thread_shell_command
Syntax
super_thread_shell_command <string>
Applies to:
root
Description
Default: /bin/csh -f
Data_type: string, read/write
Specifies in which shell the background servers must be launched during a super-threading session.
By default, the background servers will be launched in the c shell in a fast mode.
super_thread_status_command
Syntax
super_thread_status_command {queue_command}
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the LSF or SGE command to check the status of the batch jobs in the queueing system for super-threading.
Example
The following example uses the SGE qstat command to check the status of the jobs:
set_db super_thread_status_command {qstat -f -j}
The following example uses the LSF bjobs command to check the status of the jobs in the queue:
set_db super_thread_status_command {bjobs -l}
Related Information
Related attributes: super_thread_batch_command
super_thread_debug_directory
super_thread_equivalent_licenses
super_thread_kill_command
super_thread_rsh_command
super_thread_servers
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Optimization--root Attributes in Optimization
syn_generic_effort
Syntax
syn_generic_effort {none | low | medium | high}
Applies to:
root
Description
Default: medium
Data_type: enum, read/write
Specifies the optimization effort to use for the syn_generic command. The available optimization levels are:
none Individual settings of this attribute are overridden by the value of syn_global_effort attribute.
low The design is mapped to gates, but Genus does very little RTL optimization, incremental clean up, DRC fixing, or redundancy identification and
removal. The low setting is generally not recommended.
medium Genus performs better timing-driven structuring, incremental synthesis, and redundancy identification and removal on the design.
high Genus does the timing-driven structuring on larger sections of logic and spends more time and makes more attempts on incremental clean up. This
effort level involves very aggressive redundancy identification and removal.
Related Information
Affects this command: syn_generic
syn_global_effort
Syntax
syn_global_effort {none | low | medium | high}
Applies to:
root
Description
Default: none
Data_type: enum, read/write
Specifies the global effort to use for all synthesis commands. By default (attribute is set to none), the values of the syn_generic_effort, syn_map_effort and
syn_opt_effort attributes are used, otherwise the value of this attribute overrides the individual settings of the syn_generic_effort, syn_map_effort and
syn_opt_effort attributes.
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Related Information
Affects these commands: syn_generic
syn_map
syn_opt
syn_map_effort
Syntax
syn_map_effort {none | low | medium | high}
Applies to:
root
Description
Default: high
Data_type: enum, read/write
Specifies the optimization effort to use for the syn_map command. The available optimization levels are:
none Individual settings of this attribute are overridden by the value of syn_global_effort attribute.
low The design is mapped to gates, but Genus does very little structuring, redundancy identification and removal, and datapath architecture
exploration. The timing estimations in the mapper are less accurate, lower effort is put on ungrouping and module unification due to different timing
environment, and the mapper will try a smaller set of library cells.
medium Genus performs better timing-driven structuring, redundancy identification and removal on the design. The timing estimations in the mapper are
more accurate, higher effort is put on ungrouping and module unification due to different timing environment, and the mapper will try a bigger set of
library cells.
high Genus does the timing-driven structuring on larger sections of logic. Higher effort is put on ungrouping and module unification due to different
timing environment, and the mapper will try a bigger set of library cells. More effort is put on datapath architecture exploration and post map
optimizations.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt_effort
Syntax
syn_opt_effort {none | low | medium | high | extreme}
Applies to:
root
Description
Default: high
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Data_type: enum, read/write
Specifies the optimization effort to use for the syn_opt command.
Setting the effort to extreme invokes rigorous incremental optimization to achieve the best QoR (timing and area). Due to the iterative nature of the algorithms,
this value will have an impact on the run-time.
Related Information
Affects this command: syn_opt
tns_critical_range
tns_critical_range <delay>
Description
Default: 0.0
Data_type: delay, read/write
When set to a positive value (in ps), logic structuring treats paths with a slack within the specified range from the worst negative slack (WNS) as critical paths to
help optimizing the total negative slack (TNS).
You cannot set the attribute to a negative value.
Applies to:
cost_group
root
Related Information
Affects this command: syn_map
treat_net_as_analog
Syntax
treat_net_as_analog {false | driver_is_analog | atleast_one_connected_pin_is_analog}
Applies to:
root
Description
Default: all_connected_pins_are_analog
Data_type: enum, read/write
Determines if a net is marked as analog if its driver is analog or at least one connected pin is analog.
ui_respects_preserve
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Optimization--root Attributes in Optimization
ui_respects_preserve {true | false}
Description
Default: true
Data_type: bool, read/write
Specifies whether netlist editing commands should fail if they attempt to modify preserved logic. Set this attribute to false to allow netlist editing commands to
modify preserved instances.
Applies to:
root
Related Information
Affects these commands: add_tieoffs
delete_obj
ungroup_separator
Syntax
ungroup_separator <string>
Applies to:
root
Description
Default: _
Data_type: string, read/write
Specifies the string used to separate the hierarchical names of instances that are ungrouped (flattened) after elaboration.
Example
The following example uses the slash ("/") to separate ungrouped instances:
set_db / .ungroup_separator /
legacy_genus:/> set_attribute ungroup_separator /
uniquify_naming_style
Syntax
uniquify_naming_style <string>
Applies to:
root
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Optimization--root Attributes in Optimization
Description
Default: %s_%d
Data_type: string, read/write
Specifies the naming style of uniquified modules. This attribute must be set before issuing the elaborate command, otherwise the attribute value will not be
honored.
This attribute is supported in the RTL flow and the structural flow.
Related Information
Related command: uniquify
read_netlist
uniquify_rename_all
Syntax
uniquify_rename_all {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Renames all the modules during uniquification.
By default, only the clones will follow the uniquify_naming_style. Once this attribute is set, all the modules including clones will follow this naming style during
uniquification, with the first module starting with _0 by default.
Related Information
Related commands: uniquify
update_sv_wrapper_post_elab
Syntax
update_sv_wrapper_post_elab {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Updates the sv_wrapper attribute with new port names, when the port name is changed post elaboration stage.
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Related information
Affects this command: write_sv_wrapper
use_max_cap_lut
use_max_cap_lut {true | false}
Description
Default: true
Data_type: bool, read/write
Controls the use of frequency-based max_cap lookup table values from the library for design rule verification. By default, the use of frequency-based max_cap
lookup table values is enabled.
Applies to:
root
Related Information
Affects this command: report_design_rules
Related attribute: timing_library_lookup_drv_per_frequency
use_tiehilo_for_const
use_tiehilo_for_const {none | duplicate | unique}
Description
Default: none
Data_type: string, read/write
Determines whether a constant assignment should be replaced with a tie cell in the netlist.
The attribute can have the following values:
none Prevents the replacement of constants in the netlist with tie cells.
duplicate Allows each constant assignment to be replaced with a tie cell.
unique Allows only one unique tie cell in the netlist. Treatment of the remaining constant assignments depends on settings of the remove_assigns
attribute and the command.
When tie-cell insertion is done as part of incremental optimization, hierarchical constant connected pins which are not used inside the module are by
default skipped during insertion of tie high and tie low cells. If you use the insert_tiehilo_cells command to insert tie high and tie low cells, these
hierarchical pins are not skipped by default and you can use the -skip_unused_hier_pins option to skip them.
Examples
For the following examples, assume the following constant assignments in the RTL code:
assign out1 = 1’b0;
assign out2 = 1’b0;
In addition, assume the remove_assigns attribute is set to false.
If the use_tiehilo_for_const attribute us set to none, the netlist will remain unchanged.
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If the use_tiehilo_for_const attribute us set to duplicate, the netlist will look like:
TIELO tie_0_cell(.Y (out1));
TIELO tie_0_cell(.Y (out2));
If the use_tiehilo_for_const attribute us set to unique, the netlist will look like:
TIELO tie_0_cell(.Y (out1));
assign out2 = out1;
Applies to:
root
Related Information
Affects these commands: syn_map
syn_opt
Affected by this command: add_assign_buffer_options
Affected by these attribute: ignore_preserve_in_tiecell_insertion
remove_assigns
write_db_auto_save_user_globals
Syntax
write_db_auto_save_user_globals {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether to save the user-specified Tcl variables in the database when you issue the write_db command.
write_db_use_relative_filepath
Syntax
write_db_use_relative_filepath {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Use file path relative to lib_search_path attribute, while writing out the attributes library, lef_library, qrc_tech_file and cap_table_file to database.
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Optimization--state_retention_rule
state_retention_rule
Syntax
state_retention_rule <state_retention_rule>
Applies to:
hinst
inst
Description
Default:
Data_type: state_retention_rule, read only
Returns the state retention rule that applies to this instance.
Related Information
Affected by this command: read_power_intent
std_cell_main_rail_pin
std_cell_main_rail_pin {pg_pin | pin}
Read-only inst attribute. Returns the pin which is the main rail primary power pin.
Related Information
Related attribute: (lib_cell) std_cell_main_rail_pin
unique_versions
unique_versions string
Read-only hinst attribute. Returns a list of the unique uses of an instance from a collection of instances. An object can have multiple object versions in the
design. Use this attribute to get all the objects it represents.
unique_versions string
Read-only constant attribute. Returns a list of the unique uses of a constant from a collection of constants. An object can have multiple object versions in the
design. Use this attribute to get all the objects it represents.
unique_versions string
Read-only hnet attribute. Returns a list of the unique uses of a net from a collection of nets. An object can have multiple object versions in the design. Use this
attribute to get all the objects it represents.
unique_versions string
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Optimization--unresolved
Read-only hpin attribute. Returns a list of the unique uses of a pin from a collection of pins. An object can have multiple object versions in the design. Use this
attribute to get all the objects it represents. This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
unique_versions string
Read-only hport attribute. Returns a list of the unique uses of a hport from a collection of hports. An object can have multiple object versions in the design. Use
this attribute to get all the objects it represents.
unique_versions string
Read-only pg_pin attribute. Returns a list of the unique uses of a pin from a collection of pins. An object can have multiple object versions in the design. Use
this attribute to get all the objects it represents.
unique_versions string
Read-only pin attribute. Returns a list of the unique uses of a pin from a collection of pins. An object can have multiple object versions in the design. Use this
attribute to get all the objects it represents.
unique_versions string
Read-only port attribute. Returns a list of the unique uses of a port from a collection of ports. An object can have multiple object versions in the design. Use this
attribute to get all the objects it represents.
Related Information
Related command: report_timing
unresolved
Syntax
unresolved {false | true}
Applies to:
hinst
Description
Default: false
Data_type: bool, read/write
Controls whether the instance should be treated as an unresolved macro in the design and whether to preserve the logical gates driving this instance.
Set this attribute to true on a hard macro to treat it as a blackbox without timing characteristics. This prevents the logic that drives the hard macro pins from
being deleted during synthesis because transitive signal flow cannot be detected across the hard block in the absence of a timing library model in the
technology library. (This is part of boundary optimization in Genus).
When you set the unresolved attribute to true on a hierarchical instance, the instance becomes a blackbox. The attribute setting is irreversible for the
session.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
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Optimization--usable_flop
usable_flop
Syntax
usable_flop {true | false}
Applies to:
hinst
inst
lib_cell
Description
Default: false
Data_type: bool, read only
Indicates whether the instance / lib_cell is a non timing model flop.
usable_latch
Syntax
usable_latch {true | false}
Applies to:
hinst
inst
lib_cell
Description
Default: false
Data_type: bool, read only
Indicates whether the instance / libcell is a non timing model latch.
user_defined
Syntax
user_defined <string>
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Optimization--usable_flop
Applies to:
Object Data Type Object Data Type
design string, read/write lib_pin string, read/write
hinst string, read/write module string, read/write
hnet string, read/write pg_lib_pin string, read/write
hpin string, read/write pg_pin string, read/write
hport string, read/write pin string, read/write
inst string, read/write port string, read/write
lib_cell string, read/write
Description
Default:
Enables Tcl scripting easier. The string can contain any provided value for the attribute.
Syntax
user_defined {true | false}
Applies to:
Object Data Type Description
attribute bool, read only
command bool, read only Indicates whether the command is user-
defined.
dft_configuratio bool, read only Returns the user-defined configuration mode.
n_mode
jtag_port bool, read/write
memory_lib_pin_a bool, read only Indicates whether the port alias is user-
lias defined.
route_rule bool, read only Indicates whether a non-default route rule was
user-defined.
Description
Default: false
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Optimization--usable_flop
Related Information
Set by this command: define_dft_cfg_mode
Affects these commands: check_dft_rules
compress_scan_chains
connect_scan_chains
connect_serial_scan_chains
define_scan_abstract_segment
report_scan_chains
write_dft_abstract_model
write_dft_atpg
write_dft_atpg_other_vendor_files
write_scandef
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Genus Attribute Reference
Power
23
Power
add_pin_name_to_lp_instance commit_delete_invalid_iso_ls continuous_fast_report_timing
cpf_macro_inherit_parent_power_domain cpi_allow_avoided_cells cpi_allow_dont_touch_cells
cpi_allow_inverted_ls cpi_enable_third_domain_buffering cpi_insert_on_switch_network
cpi_invert_preserved_net cpi_inverter_name_prefix cpi_iso_ls_skip_const_prop_loads
cpi_output_net_name_prefix init_power_intent_files is_isolation
is_level_shifter is_retention isolate_zero_pin_retention
isonor_2017 part_power_intent_file pi_disable_aon_buffering
pi_parser_error_on_missing_objects pi_parser_honor_avoided_cells pi_read_enable_exhaustive_search
pi_relax_map_iso_cell_checks pi_relax_map_ls_cell_checks pias_aon_enable_mode_analysis
power_domain power_domains power_dynamic
power_internal power_leakage power_switching
power_total preserve_power_domain_boundary secondary_domain
See also:
location
add_pin_name_to_lp_instance
add_pin_name_to_lp_instance {false | true}
Description
When enabled, adds the interface pin nampi_find_enable_non_lrm_searche to the name of the isolation instance or level shifter that
the commit_power_intent command inserts for the1801 flow.
The software uses the following convention for the instance names:
UPF_ISO_ IsolationStrategyName _ PinHierName
UPF_LS_ LevelShifterSrategyName _ PinHierName
Assuming PinHierName would be A/B/out, then the pin name would be shown as: A_B_out.
Default: false
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Genus Attribute Reference
Power--commit_delete_invalid_iso_ls
Data_type: bool, read/write
Applies to:
root
commit_delete_invalid_iso_ls
Syntax
commit_delete_invalid_iso_ls {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether to delete invalid isolation or level-shifter cells when executing commit_power_intent.
Related Information
Affects this command: commit_power_intent
continuous_fast_report_timing
Syntax
continuous_fast_report_timing {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
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Genus Attribute Reference
Power--cpf_macro_inherit_parent_power_domain
Enables the fast reporting of timing path if reported continuously without changing any setting in flow.
cpf_macro_inherit_parent_power_domain
Syntax
cpf_macro_inherit_parent_power_domain {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Controls whether the macro instances in CPF will inherit their power domain from the parent instance.
By default, the power domain of a macro instance is inferred from the default power domain specified in the macro definition. If this
attribute is set to true, the tool will assume that the power domain of these instances is always the same as that of the parent
hierarchy in which they are instantiated.
You must set this attribute before you specify the commit_power_intent command.
Related Information
Affects this command: commit_power_intent
cpi_allow_avoided_cells
cpi_allow_avoided_cells {false | true}
Description
Specify whether to allow use of avoided cells for commit_power_intent.
Default: false
Data_type: bool, read/write
Applies to:
root
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Genus Attribute Reference
Power--cpi_allow_dont_touch_cells
cpi_allow_dont_touch_cells
cpi_allow_dont_touch_cells {true | false}
Description
Allow use of dont touch cells for commit_power_intent.
Default: false
Data_type: bool, read/write
Applies to:
root
cpi_allow_inverted_ls
cpi_allow_inverted_ls {false | true}
Description
Specify whether to allow use of level shifters with inverter functionality.
Default: true
Data_type: bool, read/write
Applies to:
root
cpi_enable_third_domain_buffering
cpi_enable_third_domain_buffering {true | false}
Description
Enables buffering in third domain on data and output paths of isolation and level shifter cells.
Doing buffering in third domain can cause unexpected violations with verification tools like Conformal. It may be necessary to
enable special switches like TRAVERSE_BUF_AND_INV_FOR_STRATEGY_MATCHING for clean verification. In addition, buffers in third
domain can confuse downstream tools.
The default value is false, to prevent such third domain buffering.
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Genus Attribute Reference
Power--cpi_insert_on_switch_network
This attribute should be set before the commit_power_intent command.
Default: false
Data_type: bool, read/write
Applies to:
root
Related Information
Affected Command: commit_power_intent
cpi_insert_on_switch_network
cpi_insert_on_switch_network {false | true}
Applies to:
root
Description
Enable or disable insertion of isolation and level shifter cells on switch network. By default commit_power_intent skips insertion of
isolation and level shifter cells on switch network. To enable insertion on switch network, set this attribute to true.
For any port having switch loads and non switch loads, default behavior is to try insertion on non switch loads. You need to make
sure that switch cells have supply connectivity defined either in power intent or in def file before enabling the attribute.
Default: false
Data_type: bool, read/write
cpi_invert_preserved_net
cpi_invert_preserved_net {false | true}
Description
By default, commit_power_intent does not do any inversion on preserved net for insertion of isolation cells and always tries to use
isolation cells which can be inserted without inversion. If such cells are missing, then insertion will be skipped. Enable this attribute
to try disable above behavior.
Default: false
Data_type: bool, read/write
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Power--cpi_inverter_name_prefix
Applies to:
root
cpi_inverter_name_prefix
Syntax
cpi_inverter_name_prefix <string>
Applies to:
design
Description
Default: cpi_inv
Data_type: string, read/write
Specifies the prefix to be used for inverters added by the commit_power_intent command.
Related Information
Affects this command: commit_power_intent
cpi_iso_ls_skip_const_prop_loads
cpi_iso_ls_skip_const_prop_loads {none | all | top_ports | macro_inputs | timing_model_inputs | blackbox_inputs |
zero_pin_retention_inputs}
Description
Defines the type of loads of isolation on constants for which const prop is skipped (does not to be done). The table lists the basic
types. The actual value is effective OR of the given values. The attribute must be set before applying power intent.
all Indicates skip
const prop for all
loads.
top_ports Indicates skip
const prop for
top_ports as
loads.
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Power--cpi_output_net_name_prefix
macro_inputs Indicates skip
const prop for
macro inputs as
loads.
none Indicates dont
skip constant
propagation for
any pin.
timing_model_inputs Indicates skip
const prop for
timing model
inputs as loads.
blackbox_inputs Indicates skip
const prop for
blackbox inputs
as loads.
zero_pin_retention_inputs Indicates skip
const prop for
zero pin retention
inputs as loads.
Default: ""
Data_type: string, read/write
Applies to:
root
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
cpi_output_net_name_prefix
Syntax
cpi_output_net_name_prefix <string>
Applies to:
design
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Power--init_power_intent_files
Description
Default:
Data_type: string, read/write
Specifies the prefix to be used for net names on the output pins of instances inserted by the commit_power_intent command.
Related Information
Affects this command: commit_power_intent
init_power_intent_files
Syntax
init_power_intent_files <filelist>
Applies to:
root
Description
Default:
Data_type: string, read only
Returns the list of files read by the last read_power_intent command.
Related Information
Set by this command: read_power_intent
is_isolation
Syntax
is_isolation {false | true}
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Power--is_level_shifter
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read only
Indicates if the instance is an isolation cell. Isolation cells are used in n designs with switchable power domains.
is_level_shifter
Syntax
is_level_shifter {false | true}
Applies to:
base_cell
hinst
inst
lib_cell
Description
Default: false
Data_type: bool, read/write (base_cell and lib_cell), read only (hinst and inst)
Object Description
base_cell, lib_cell Specifies whether the lib_cell is a level-shifter cell. Level shifters are used in MSV designs.
hinst, inst Indicates if the instance is a level shifter cell.
Related Information
Related attribute: is_latch
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Power--is_retention
is_retention
Syntax
is_retention {false | true}
Applies to:
base_cell
hinst
inst
lib_cell
Description
Default: false
Data_type: bool, read/write (base_cell and lib_cell), read only (hinst and inst)
Object Description
base_cell, lib_cell ...
hinst, inst Indicates if the instance is a retention cell.
isolate_zero_pin_retention
Syntax
isolate_zero_pin_retention {true | false}
design
Description
Default: true
Data_type: bool, read/write
Controls whether to insert an isolation cell on a zero-pin state retention cell,
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Power--isonor_2017
Related Information
Affects this command: commit_power_intent
isonor_2017
isonor_2017 {false | true}
Description
Enables insertion of ISONOR cells (isolation cells of the NOR type).
Default: false
Data_type: bool, read/write
Applies to:
root
Related Information
Affects this command: commit_power_intent
part_power_intent_file
Syntax
part_power_intent_file <file>
Applies to:
hinst
Description
Default:
Data_type: string, read/write
Specifies the name of the hierarchical instance final CPF, which is written out after synthesis and placement of the instance. This file
will be read as macro CPF file when the top level of the design is synthesized. It is your responsibility to make sure that the instance
attribute value matches the final CPF macro file.
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Power--pi_disable_aon_buffering
Related Information
Affects this command: write_power_intent
pi_disable_aon_buffering
pi_disable_aon_buffering {true | false}
Description
Controls whether to Disable always-on buffering for some hierarchies where always-on cell may not be available.
Default: false
Data_type: bool, read/write
Applies to:
root
pi_parser_error_on_missing_objects
pi_parser_error_on_missing_objects {true | false}
Description
Controls whether to continue applying power intent even when missing objects are flagged.
By default, the command stops when missing objects are flagged. Setting this attribute to false, allows to continue applying power
intent. This attribute setting is not recommended because it can lead to incorrect interpretation of power intent across tools. It is
recommended to fix the power intent file instead.
Default: true
Data_type: string, read/write
Applies to:
root
Related Information
Set by this command: apply_power_intent
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Power--pi_parser_honor_avoided_cells
pi_parser_honor_avoided_cells
pi_parser_honor_avoided_cells {true | false}
Description
Controls whether to honor avoid attribute on library cell(s).
Default: false
Data_type: bool, read/write
Applies to:
root
Related Information
Set by this command: apply_power_intent
pi_read_enable_exhaustive_search
pi_read_enable_exhaustive_search {true | false}
Description
Set this attribute to false to disable all extra searches done while parsing the power intent file.
Default: true
Data_type: bool, read/write
Applies to:
root
Related Information
Related command: apply_power_intent
pi_relax_map_iso_cell_checks
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Power--pi_relax_map_ls_cell_checks
Syntax
pi_relax_map_iso_cell_checks {true | false}
design
Description
Default: false
Data_type: bool, read/write
Controls whether to relax sanity checks on isolation cells listed with the map_isolation_cell command specified in the power intent
file using the format described in the IEEE 1801-2009 standard.
If this attribute is enabled, the tool will skip checks on the isolation type during isolation cell insertion.
However, the tool will still check if the library domain of the cell matches with the library domain of the insertion location.
If the isolation cells specified with the map_isolation_cell command are not referenced in the isolation rule, the attribute setting has
no effect.
Related Information
Appendix B: UPF (IEEE-1801) Support in Genus Low Power Guide.
Affects this command: commit_power_intent
pi_relax_map_ls_cell_checks
Syntax
pi_relax_map_ls_cell_checks {true | false}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Controls whether to relax sanity checks on level shifter cells listed with the map_level_shifter_cell command specified in the
power intent file using the format described in the IEEE 1801-2009 standard.
If this attribute is enabled, the tool will skip checks during level shifter insertion on
the input and output range of the cell
the direction of the level shifter cell
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Power--pias_aon_enable_mode_analysis
However, the tool will still check if the library domain of the cell matches with the library domain of the insertion location.
If the level shifters specified with the map_level_shifter_cell command are not referenced in the level shifter rule, the attribute
setting has no effect.
Related Information
Appendix B: UPF (IEEE-1801) Support in Genus Low Power Guide.
Affects this command: commit_power_intent
pias_aon_enable_mode_analysis
pias_aon_enable_mode_analysis {false | true}
Description
Enable mode analysis for always on buffering.
Default: true
Data_type: bool, read/write
Applies to:
root
power_domain
Syntax
power_domain <domain>
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Power--pias_aon_enable_mode_analysis
Applies to:
Object Data_type
string, read only
actual_scan_chain
actual_scan_segment
scan_segment
power_domain, read/write
hinst
hpin
inst
pin
port
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Power--power_domains
Description
Object Description
actual_scan_chain Returns the list of power domains to which this scan chain belongs.
actual_scan_segment Returns the power domain of this scan segment.
This attribute applies only to segments inserted by the add_core_wrapper_cell command that
also have the following actual_scan_segment attribute settings:
core_wrapper = true
type = preserved
scan_segment Returns the power domain of this scan segment.
This attribute applies only to segments inserted by the add_core_wrapper_cell command that
also have the following scan_segment attribute settings:
core_wrapper = true
type = preserved
hinst Identifies the primary power domain to which this instance belongs. You can only set this attribute on a
hierarchical instance or a timing model instance.
hpin Identifies the power domain to which this hpin belongs. You can only change the power domain of the
hpin of a timing-model instance or of an unresolved reference instance.
inst Identifies the primary power domain to which this instance belongs.
pin Identifies the power domain to which this pin belongs. You can only change the power domain of the pin
of a timing-model instance or of an unresolved reference instance.
port Specifies the power domain to which this port belongs: power domain of the driver of an input port or
power domain of the receiver of an output port.
Related Information
Set by this commands: connect_scan_chains
add_core_wrapper_cell
Related commands: report_scan_chains
Related attributes: core_wrapper
type
power_domains
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Power--power_dynamic
Syntax
power_domains <list_of_power_domains>
Applies to:
design
power_scope
Description
Default:
Data_type: power_domain*, read only
Returns the list of power_domain objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
power_dynamic
Syntax
power_dynamic <double>
Applies to:
design
hinst
inst
Description
Default: 0.000000
Data_type: double, read only
design Returns the sum of dynamic power values for all the instances inside this design. A value of no_value is treated as 0.
hinst/inst For hierarchical instances, returns the sum of the switching and internal power values for all the instances inside this
hierarchical instance. For leaf instances, returns the switching and internal power of this instance computed by
report_power. A value of no_value is treated as 0.
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Power--power_internal
Related Information
Related command: report_power
Related attribute: power_domains
power_internal
Syntax
power_internal <double>
Applies to:
design
hinst
inst
Description
Default: 0.000000
Data_type: double, read only
For hierarchical instances, returns the sum of the internal power values for all the instances inside this design. For leaf instances,
returns the internal power of this instance computed by report_power. A value of no_value is treated as 0.
Related Information
Related commands: report_power
write_power_intent
power_leakage
Syntax
power_leakage <double>
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Power--power_switching
Applies to:
design
hinst
inst
Description
Default: 0.000000
Data_type: double, read only
Returns the sum of the leakage power values for all the instances inside this design. A value of no_value is treated as 0.
Related Information
Related attribute: power_domains
power_switching
Syntax
power_switching <double>
Applies to:
design
hinst
hnet
inst
Description
Default: 0.000000
Data_type: double, read only
design Returns the sum of the switching power values for the instances inside this design. A value of no_value is treated
as 0.
hinst/inst For hierarchical instances, returns the sum of the switching power values for all the instances inside this
hierarchical instance. For leaf instances, returns the switching power of the nets driven by this instance computed
by report_power. A value of no_value is treated as 0.
hnet Returns the switching power of the net computed by report_power.
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Power--power_total
Related Information
Related command: report_power
Related attribute: power_domains
power_total
Syntax
power_total <double>
Applies to:
design
hinst
inst
Description
Default: 0.000000
Data_type: double, read only
design Returns the sum of the total power values for all the instances inside this design. A value of no_value is treated as
0.
hinst/inst For hierarchical instances, returns the sum of the switching, internal, and leakage power values for all the
instances inside this hierarchical instance. For leaf instances, returns the switching, internal, and leakage power of
this instance computed by report_power. A value of no_value is treated as 0.
Related Information
Related command: report_power
Related attribute: power_domains
preserve_power_domain_boundary
Syntax
preserve_power_domain_boundary {false | true | const_prop_delete_ok | delete_ok}
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Power--secondary_domain
Applies to:
design
Description
Default: false
Data_type: enum, read/write
Preserves all power domain boundary pins with the specified preserve value.
You must set this attribute before you execute the apply_power_intent command, or in case you use the MMMC flow, before
you execute the init_design command.
Related Information
Related commands: apply_power_intent
init_design
secondary_domain
Syntax
secondary_domain <power_domain>
Applies to:
hinst
inst
isolation_rule
state_retention_rule
Description
Default:
Object Data_type Description
hinst power_domain, Returns the secondary domain of the hierarchical instance of a special low power
inst
read only cell (level shifter cell, isolation cell, state retention cell, always-on cell, or power
switch cell).
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Power--secondary_domain
isolation_rule power_domain, Returns the secondary domain of the instances of the isolation rule. The secondary
read/write domain is the domain whose primary power and ground nets must be connected to
the secondary power and ground pins of an isolation cell.
state_retention_rule power_domain, Specifies the name of the power domain that provides continuous power when the
read/write state retention registers of this rule are in retention mode.
Related Information
Affected by this command: read_power_intent
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Safety
24
Safety
The chapter describes the following attributes:
exclusive_group_gap exclusive_group_type exclusive_groups
safety_dcls_isolate_clock safety_dcls_isolate_groups safety_dcls_isolate_halo_type
safety_dcls_isolate_inputs safety_dcls_isolate_is_group_input_cell safety_dcls_isolate_is_group_output_cell
safety_dcls_isolate_is_halo safety_dcls_isolate_outputs safety_dcls_isolate_pin
safety_dcls_isolate_reset safety_dcls_isolate_scan_enable safety_dcls_isolate_signal_type
safety_dcls_isolate_type safety_dcls_isolate_use_halo safety_dcls_route_types
safety_failure_mode safety_flow_enable safety_mechanism
safety_mechanism_type safety_midas_enable safety_parity_bit
safety_parity_bit_cells safety_parity_endpoint safety_parity_error_signal_endpoint
safety_parity_group_size_max safety_parity_group_size_min safety_ser_cells
safety_ser_type safety_tmr_clones safety_tmr_custom_voter_cell
safety_tmr_error_signal_endpoint safety_tmr_isolate_clock safety_tmr_isolate_reset
safety_tmr_isolate_scan_enable safety_tmr_parent safety_tmr_spacing
safety_tmr_spacing_x safety_tmr_spacing_y safety_tmr_voters
safety_tmr_well_tap_cells safety_tmr_well_tap_left_padding safety_tmr_well_tap_right_padding
exclusive_group_gap
Syntax
exclusive_group_gap <coord>
Applies to:
group
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Safety--exclusive_group_type
Description
Default: 0.00
Data_type: coord, read/write
Specifies the gap that needs to be maintained between exclusive_groups (per safety island groups). The value is measured in
microns. It can be set by the 'create_exclusive_groups -gap' command. It is only valid when the group’s constraint_type is a region or
fence.
exclusive_group_type
Syntax
exclusive_group_type {none | master | checker | mutually_exclusive}
Applies to:
group
Description
Default: none
Data_type: string, read/write
Specifies the type of exclusive group.
exclusive_groups
Syntax
exclusive_groups <string>
Applies to:
group
Description
Default:
Data_type: string, read/write
Specifies a list of groups that are exclusive of a group. It can be used to implement safety islands in automotive application designs.
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Safety--safety_dcls_isolate_clock
safety_dcls_isolate_clock
Syntax
safety_dcls_isolate_clock {none | split_net | split_network}
Applies to:
group
Description
Default: none
Data_type: string, read only
Specifies the type of isolation required for the clock signals driving this dcls (dual core lock step) group. The supported values are:
none
split_net The net directly driving the group should be driven by an isolation cell that drives only that group.
split_network The network driving the group should split at the last combinational cell (excluding buffering) on that network, to
form a new branch driving only that group and no other logic.
safety_dcls_isolate_groups
Syntax
safety_dcls_isolate_groups <group*>
Applies to:
inst
Description
Default:
Data_type: object*, read only
Specifies the dcls (dual core lock step) groups isolated by this inst.
safety_dcls_isolate_halo_type
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Safety--safety_dcls_isolate_inputs
Syntax
safety_dcls_isolate_halo_type <hard | soft>
Applies to:
root
Description
Default: soft
Data_type: string, read only
Specifies the type of isolation halo required for dcls (dual core lock step) groups. The supported values are:
hard the isolation cells on a group's input/output nets should always be placed inside the group's isolation halo boundary.
soft same as hard, but can move the isolation cells inside the group boundary if required to improve timing.
safety_dcls_isolate_inputs
Syntax
safety_dcls_isolate_inputs <none | split_net>
Applies to:
group
Description
Default: none
Data_type: string, read only
Specifies the type of isolation required for all the input signals driving this dcls (dual core lock step) group. The supported values are:
none
split_net The net directly driving the group should be driven by an isolation cell that drives only that group.
safety_dcls_isolate_is_group_input_cell
Syntax
safety_dcls_isolate_is_group_input_cell {true | false}
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Safety--safety_dcls_isolate_is_group_output_cell
Applies to:
inst
Description
Default: false
Data_type: bool, read only
If true, then this inst is an isolation cell on an input net for a dcls (dual core lock step) group.
safety_dcls_isolate_is_group_output_cell
Syntax
safety_dcls_isolate_is_group_output_cell {true | false}
Applies to:
inst
Description
Default: false
Data_type: bool, read only
If true, then this inst is an isolation cell on an output net for a dcls (dual core lock step) group.
safety_dcls_isolate_is_halo
Syntax
safety_dcls_isolate_is_halo {true | false}
Applies to:
group
Description
Default: false
Data_type: bool, read only
When true, this group is an isolation halo for a dcls (dual core lock step) group. The isolation cells on the input/output nets for the dcls-
group will be placed inside this halo around the dcls-group boundary. The halo-group will be the parent-group of the dcls-group.
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Safety--safety_dcls_isolate_outputs
safety_dcls_isolate_outputs
Syntax
safety_dcls_isolate_outputs <none | split_net>
Applies to:
group
Description
Default: none
Data_type: string, read only
Specifies the type of isolation required for all the output signals driven by this dcls (dual core lock step) group. The supported values
are:
none
split_net The net directly driven by the group should drive an isolation cell that is the only net load logically outside of that
group.
safety_dcls_isolate_pin
Syntax
safety_dcls_isolate_pin {none | split_net | split_network}
Applies to:
hpin
Description
Default: none
Data_type: string, read only
Specifies the type of isolation required for the signal driving this pin inside a dcls (dual core lock step) group. The supported values
are:
none
split_net The net directly driving the pin should be driven by an isolation cell that drives only that pin.
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Safety--safety_dcls_isolate_reset
split_network The network driving the pin should split at the last combinational cell (excluding buffering) on that network, to
form a new branch driving only that pin and no other logic.
safety_dcls_isolate_reset
Syntax
safety_dcls_isolate_reset {none | split_net | split_network}
Applies to:
group
Description
Default: none
Data_type: string, read only
The type of isolation required for the reset signals driving this dcls (dual core lock step) group. The supported values are:
none
split_net The net directly driving the group should be driven by an isolation cell that drives only that group.
split_network The network driving the group should split at the last combinational cell (excluding buffering) on that network, to
form a new branch driving only that group and no other logic. The signal can then leave the group to drive other
logic but cannot drive it's exclusive_groups.
safety_dcls_isolate_scan_enable
Syntax
safety_dcls_isolate_scan_enable {none | split_net | split_network}
Applies to:
group
Description
Default: none
Data_type: string, read only
The type of isolation required for the scan_enable signals driving this dcls (dual core lock step) group. The supported values are:
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Safety--safety_dcls_isolate_signal_type
none
split_net The net directly driving the group should be driven by an isolation cell that drives only that group.
split_network The network driving the group should split at the last combinational cell (excluding buffering) on that network, to
form a new branch driving only that group and no other logic. The signal can then leave the group to drive other
logic but cannot drive it's exclusive_groups.
safety_dcls_isolate_signal_type
Syntax
safety_dcls_isolate_signal_type <none | clock | reset | scan_enable | pin | input | output>
Applies to:
inst
Description
Default: none
Data_type: string, read only
Specifies the type of signal isolated by this inst for a dcls (dual core lock step) group. The supported values are:
none
clock clock signal driving a dcls group.
reset reset signal driving a dcls group.
scan_enable scan_enable signal driving a dcls group.
pin signal driving a user specified pin inside a dcls group.
input input signal driving a dcls group. Used for those signals outside of clock/reset/scan_enable/pin.
output output signal driven by a dcls group.
safety_dcls_isolate_type
Syntax
safety_dcls_isolate_type <hard | soft>
Applies to:
root
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Safety--safety_dcls_isolate_use_halo
Description
Default: soft
Data_type: string, read only
Specifies the type of isolation required for dcls (dual core lock step) groups. The supported values are:
hard isolation networks (insts and nets) must avoid the boundary of the exclusive_groups of the groups they isolate.
soft isolation networks (insts and nets) are not required to avoid the boundary of the exclusive_groups of the groups they
isolate.
safety_dcls_isolate_use_halo
Syntax
safety_dcls_isolate_use_halo {true | false}
Applies to:
group
Description
Default: false
Data_type: bool, read only
When true, the isolation cells on the input/output nets for this dcls (dual core lock step) group will be placed inside a halo around the
dcls-group boundary. The halo-group will be the parent-group of the dcls-group.
safety_dcls_route_types
Syntax
safety_dcls_route_types <none | internal | interface| common| top>
Applies to:
root
Description
Default: ""
Data_type: string, read only
Specifies the type of nets on which to enforce routing rules for dcls (dual core lock step) groups.. The supported values are:
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Safety--safety_failure_mode
"" none.
internal this net's pins are all logically inside a single dcls group. This net cannot route outside of the group boundary.
interface this net has pins logically inside a dcls group, and pins logically outside of that group AND logically outside of it's
exclusive_groups. This net cannot route over the boundary of it's exclusive_groups.
common this net has pins logically inside two or more dcls exclusive_groups. This net can route inside the boundary of those
groups to complete the connections, but a violation should be reported.
top this net's pins are all logically outside of dcls groups. This net can route over the boundary of any dcls group, but
cannot route over the boundary of two or more exclusive_groups.
safety_failure_mode
Syntax
safety_failure_mode <string>
Applies to:
inst
group
pin
Description
Default:
Data_type: string, read only
Specifies the name of the failure-mode to which the object belongs, as defined in the USF (Unified Safety Format) file.
safety_flow_enable
Syntax
safety_flow_enable {true | false}
Applies to:
root
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Safety--safety_mechanism
Description
Default: false
Data_type: bool, read only
Master switch that enables the implementation and analysis of the safety-mechanisms defined in the USF (Unified Safety Format) file.
This USF attribute used for physical implementation is only supported in the next release onwards. Since there is a need for
FMEDA USF commands in this release, these attributes have been included along with them.
safety_mechanism
Syntax
safety_mechanism <string>
Applies to:
inst
group
pin
Description
Default:
Data_type: string, read only
Specifies the name of the safety-mechanism applied to the object, as defined in the USF (Unified Safety Format) file.
safety_mechanism_type
Syntax
safety_mechanism_type <string>
Applies to:
inst
group
pin
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Safety--safety_midas_enable
Description
Default:
Data_type: string, read only
Specifies the type of safety-mechanism applied to the object as defined in the USF (Unified Safety Format) file.
safety_midas_enable
Syntax
safety_midas_enable {none | fmeda | physical}
Applies to:
root
Description
Default: none
Data_type: string, read/write
Enables USF (Unified Safety Format) technology from Midas. The supported values are:
fmeda Enables the USF command set for Failure mode Effect and Diagnostic Analysis. This is supported in Genus only.
physical Enables the USF command set for physical implementation of safety-mechanisms. This is supported in both Genus
and Innovus.
safety_parity_bit
Syntax
safety_parity_bit <pin>
Applies to:
pin
Description
Default:
Data_type: object, read only
After parity circuitry has been inserted, this attribute is set to the Q output pin of the associated parity flip-flop.
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Safety--safety_parity_bit_cells
safety_parity_bit_cells
Syntax
safety_parity_bit_cells <base_cell_list>
Applies to:
root
Description
Default: null string
Data_type: object*, read only
Specifies a list of base_cells that may be used for the parity-bit flops.
safety_parity_endpoint
Syntax
safety_parity_endpoint <string>
Applies to:
hpin
pin
port
Description
Default:
Data_type: string, read only
This object is the endpoint for the combined error signal from multiple parity-groups. The error signal should only originate from flops
that are:
1. defined within the specified failure_modes
2. clocked by the specified clock signal root, and
3. reset by the specified reset signal root.
Supported formats are:
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Safety--safety_parity_error_signal_endpoint
pre-parity insertion:
{ {failure_modes {<list of mission failure_modes>}} {clock <clock-signal-root>} {reset <reset-signal-root>}
{reset_type <non_reset | reset | all>} {unmask_non_reset_flops <none | unmask-signal-root>} {pipeline_flops n} }
post-parity insertion:
{ {failure_modes {<list of mission failure_modes>} {<passive failure_mode>}} {clock <clock-signal-root>}
{reset <reset-signal-root>} {reset_type <non_reset | reset | all>} {unmask_non_reset_flops <none | unmask-
signal-root>} {pipeline_flops n} }
safety_parity_error_signal_endpoint
Syntax
safety_parity_error_signal_endpoint <string>
Applies to:
hpin
pin
port
Description
Default:
Data_type: string, read only
This object is the endpoint for a safety-mechanism's error-signal. This attribute must contain the following keywords:
Keywords Explanation
failure_modes The error-signal should only come from flops within these failure_modes.
clock The error-signal should only come from flops driven by this clock source.
reset The error-signal should only come from reset-flops driven by this reset source.
reset_type The error-signal should only come from flops with this type of reset.
unmask_non_reset_flops When low, this signal (port/hpin/pin) will suppress the error-signal from non_reset flops (false
errors at system startup). When high, this signal will allow the error-signal from non_reset flops to
propagate.
pipeline_flops The number of pipeline-flops to add after the error-signal OR tree, and before the endpoint.
Supported formats are:
pre-parity insertion:
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Safety--safety_parity_group_size_max
{ {failure_modes {<list of mission failure_modes>}} {clock <clock-signal-root>} {reset <none | reset-signal-root>}
{reset_type <non_reset | reset | all>} {unmask_non_reset_flops <none | unmask-signal-root>} {pipeline_flops n} }
post-parity insertion:
{ {failure_modes {<list of mission failure_modes>} {<passive failure_mode>}} {clock <clock-signal-root>}
{reset_type <non_reset | reset | all>} {unmask_non_reset_flops <none | unmask-signal-root>} {pipeline_flops n} }
safety_parity_group_size_max
Syntax
safety_parity_group_size_max <string>
Applies to:
root
Description
Default: null string
Data_type: string, read only
Specifies the maximum number of flops allowed in a single parity-group. Does not include the parity-bit flop of a group. The supported
formats are:
single value per design <natural number>
value per failure_mode { {<failure_mode> <natural number>} {<failure_mode> <natural number>}... }
safety_parity_group_size_min
Syntax
safety_parity_group_size_min <string>
Applies to:
root
Description
Default: null string
Data_type: string, read only
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Genus Attribute Reference
Safety--safety_ser_cells
Specifies the minimum number of flops allowed in a single parity-group. Does not include the parity-bit flop of a group. The supported
formats are:
single value per design <natural number>
value per failure_mode { {<failure_mode> <natural number>} {<failure_mode> <natural number>}... }
safety_ser_cells
Syntax
safety_ser_cells <list of base_cells>
Applies to:
power_domain (for designs with power_domains)
root (for designs without power_domains)
Description
Default:
Data_type: object*, read only
This attribute specifies a list of flip-flops that may be used in the Soft Error Resilient (SER) flow. Specify the base_cell names of the
FFs.
Where power domains are used and there are some SER cell names that are unique to a power domain, specify this attribute as
follows:
{ base_cell base_cell ... }
safety_ser_type
Syntax
safety_ser_type {hard | soft}
Applies to:
root
Description
Default: hard
Data_type: string, read only
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Safety--safety_tmr_clones
Specifies the The type of ser (soft error resilience) safety mechanism.
The supported values are:
hard Always use ser cells for those instances with an ser safety mechanism.
soft Use ser cells for those instances with an ser safety mechanism, except for those instances where using a non-ser cell can
improve timing.
safety_tmr_clones
Syntax
safety_tmr_clones <object*>
Applies to:
inst
Description
Default:
Data_type: object*, read only
Specifies the TMR (triple modular redundancy) clone flops of a parent flop. This attribute is stored only on TMR parent flops.
safety_tmr_custom_voter_cell
Syntax
safety_tmr_custom_voter_cell <string>
Applies to:
root
Description
Default: null string
Data_type: string, read/write
Specifies the custom base-cell or module to perform the voter function for the TMR (triple modular redundancy) flops. If not defined,
Genus will create its own voter logic.
The base-cell should have either of the following:
a. 3 inputs and 1 output, or
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Safety--safety_tmr_error_signal_endpoint
b. 3 inputs and 2 complementary outputs.
If a voter-module is specified, it should be loaded into the design database, and should have:
a. 3 inputs named: A, B, and C,
b. and one of the following:
a. 1 output named: Q (assumed positive), or
b. 1 output named: QN (assumed negative), or
c. 2 outputs named: Q, QN
For single power-domain designs: specify only one base-cell or voter-module.
a. set_db safety_tmr_custom_voter_cell {base_cell}, or
b. set_db safety_tmr_custom_voter_cell {voter_module}
For multi power-domain designs: specify one base-cell or voter-module per domain.
a. set_db safety_tmr_custom_voter_cell {{<power_domain_1> <base_cell_1>} {<power_domain_2> <base_cell_2>}}, or
b. set_db safety_tmr_custom_voter_cell {{<power_domain_1> <voter_module_1>} {<power_domain_2>
<voter_module_2>}}, or
c. set_db safety_tmr_custom_voter_cell {{<power_domain_1> <base_cell_1>} {<power_domain_2> <voter_module_2>}}
safety_tmr_error_signal_endpoint
Syntax
safety_tmr_error_signal_endpoint <string>
Applies to:
hpin
pin
port
Description
Default:
Data_type: string, read only
This object is the endpoint for a safety-mechanism's error-signal. This attribute must contain the following keywords:
Keywords Explanation
failure_modes The error-signal should only come from flops within these failure_modes.
clock The error-signal should only come from flops driven by this clock source.
reset The error-signal should only come from reset-flops driven by this reset source.
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Safety--safety_tmr_isolate_clock
reset_type The error-signal should only come from flops with this type of reset.
unmask_non_reset_flops When low, this signal (port/hpin/pin) will suppress the error-signal from non_reset flops (false
errors at system startup). When high, this signal will allow the error-signal from non_reset flops to
propagate.
pipeline_flops The number of pipeline-flops to add after the error-signal OR tree, and before the endpoint.
Supported formats are:
pre-TMR insertion:
{ {failure_modes {<list of mission failure_modes>}} {clock <clock-signal-root>} {reset <none | reset-signal-root>}
{reset_type <non_reset | reset | all>} {unmask_non_reset_flops <none | unmask-signal-root>} {pipeline_flops n} }
post-TMR insertion:
{ {failure_modes {<list of mission failure_modes>} {<passive failure_mode>}} {clock <clock-signal-root>} {reset
<none | reset-signal-root>} {reset_type <non_reset | reset | all>} {unmask_non_reset_flops <none | unmask-signal-
root>} {pipeline_flops n} }
safety_tmr_isolate_clock
Syntax
safety_tmr_isolate_clock <none | split_net | split_network>
Applies to:
root
Description
Default: none
Data_type: string, read only
Specifies the type of clock isolation required for TMR (triple modular redundancy) flops. The supported values:
none
split_net The net driving a tmr flop cannot directly drive either of the other two flops from the same tmr group.
split_network The network driving the tmr flops should split at the last combinational cell (excluding buffering) on that network.
Each branch can drive multiple tmr and non-tmr flops, but can only drive one of the three flops in a tmr group.
safety_tmr_isolate_reset
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Safety--safety_tmr_isolate_scan_enable
Syntax
safety_tmr_isolate_reset <none | split_net | split_network>
Applies to:
root
Description
Default: none
Data_type: string, read only
Specifies the type of isolation required for the reset signals driving tmr (triple modular redundancy) flops. The supported values are:
none
split_net The net directly driving a tmr flop cannot directly drive either of the other two flops from the same tmr group.
split_network The network driving the tmr flops should split at the last combinational cell (excluding buffering) on that network.
Each branch can drive multiple tmr and non-tmr flops, but can only drive one of the three flops in a tmr group.
safety_tmr_isolate_scan_enable
Syntax
safety_tmr_isolate_scan_enable <none | split_net | split_network>
Applies to:
root
Description
Default: none
Data_type: string, read only
Specifies the type of isolation required for the scan_enable signals driving tmr (triple modular redundancy) flops. The supported
values are:
none
split_net The net directly driving a tmr flop cannot directly drive either of the other two flops from the same tmr group.
split_network The network driving the tmr flops should split at the last combinational cell (excluding buffering) on that network.
Each branch can drive multiple tmr and non-tmr flops, but can only drive one of the three flops in a tmr group.
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Safety--safety_tmr_parent
safety_tmr_parent
Syntax
safety_tmr_parent <object>
Applies to:
inst
Description
Default:
Data_type: object, read only
Specifies the TMR (triple modular redundancy) parent flop of an instance. The TMR safety mechanism is initially applied to the parent
flop, adding clone flops and voting logic.
safety_tmr_spacing
Syntax
safety_tmr_spacing <coord>
Applies to:
root
Description
Default: 0.000
Data_type: coord, read only
Specifies the radial spacing in any direction that should be maintained between the 3 flops in a the TMR (triple modular redundancy)
group. The value is measured in microns.
Attributes 'safety_tmr_spacing_x', 'safety_tmr_spacing_y', and 'safety_tmr_spacing' are mutually exclusive.
safety_tmr_spacing_x
Syntax
safety_tmr_spacing_x <coord>
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Safety--safety_tmr_spacing_y
Applies to:
root
Description
Default: 0.000
Data_type: coord, read only
Specifies the horizontal spacing that should be maintained between the 3 flops in a TMR (triple modular redundancy) group. The
value is measured in microns.
You need to specify either 'safety_tmr_spacing_x' or 'safety_tmr_spacing_y', because the attributes 'safety_tmr_spacing_x',
'safety_tmr_spacing_y', and 'safety_tmr_spacing' are mutually exclusive.
safety_tmr_spacing_y
Syntax
safety_tmr_spacing_y <coord>
Applies to:
root
Description
Default: 0.000
Data_type: coord, read only
Specifies the horizontal spacing that should be maintained between the 3 flops in a TMR (triple modular redundancy) group. The
value is measured in microns.
You need to specify either 'safety_tmr_spacing_x' or 'safety_tmr_spacing_y', because the attributes 'safety_tmr_spacing_x',
'safety_tmr_spacing_y', and 'safety_tmr_spacing' are mutually exclusive.
safety_tmr_voters
Syntax
safety_tmr_voters <object*>
Applies to:
inst
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Safety--safety_tmr_well_tap_cells
Description
Default:
Data_type: object*, read only
Specifies the TMR (triple modular redundancy) voting logic of this parent flop. This attribute is stored only on TMR parent-flops.
safety_tmr_well_tap_cells
Syntax
safety_tmr_well_tap_cells <base_cell*>
Applies to:
power_domain (for designs with power_domains)
root (for designs without power_domains)
Description
Default:
Data_type: object*, read only
The well-tap cells to be placed next to the left and right edges of tmr (triple modular redundancy) flops.
safety_tmr_well_tap_left_padding
Syntax
safety_tmr_well_tap_left_padding <inst>
Applies to:
inst
Description
Default: 0
Data_type: int, read only
Specifies the padding used to reserve space for well-tap cells to be placed next to the left edges of tmr (triple modular redundancy)
flops. In units of site width. For example: <inst>.left_padding
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Safety--safety_tmr_well_tap_right_padding
safety_tmr_well_tap_right_padding
Syntax
safety_tmr_well_tap_right_padding <inst>
Applies to:
inst
Description
Default: 0
Data_type: int, read only
Specifies the padding used to reserve space for well-tap cells to be placed next to the right edges of tmr (triple modular redundancy)
flops. In units of site width. For example: <inst>.right_padding
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Analysis Attributes
25
Analysis Attributes
The chapter describes the attributes of the following object types:
clock Attributes for constant Attributes for cost_group Attributes for
Analysis Analysis Analysis
exception Attributes for external_delay Attributes for hdl_architecture
Analysis Analysis Attributes for Analysis
hdl_bind Attributes for hdl_block Attributes for hdl_component Attributes
Analysis Analysis for Analysis
hdl_configuration hdl_implementation hdl_inst Attributes for
Attributes for Analysis Attributes for Analysis Analysis
hdl_label Attributes for hdl_lib Attributes for hdl_operator Attributes for
Analysis Analysis Analysis
hdl_package Attributes for hdl_parameter Attributes for hdl_pin Attributes for
Analysis Analysis Analysis
hdl_procedure Attributes hdl_subprogram Attributes hnet Attributes for
for Analysis for Analysis Analysis
hpin Attributes for Analysis hpin_bus Attributes in hport Attributes for
Analysis Analysis
hport_bus Attributes for message_group Attribute for net Attributes for Analysis
Analysis Analysis
pcell Attributes for pg_hnet Attributes for pg_hport Attributes for
Analysis Analysis Analysis
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Analysis Attributes--clock Attributes for Analysis
pg_net Attributes for pg_pin Attributes for pg_hnet
Analysis Analysis
pin Attributes for Analysis pin_bus Attributes for port Attributes for
Analysis Analysis
port_bus Attributes for timing_bin Attributes for timing_bin_path Attribute
Analysis Analysis for Analysis
timing_path Attributes for
Analysis
clock Attributes for Analysis
actual_period
clock_domain
clock_groups
clock_relation_to_others
clock_sense_all_stop
clock_sense_clock_source_data_stop_propagation
clock_sense_clock_stop_propagation
clock_sense_data_stop_propagation
clock_sense_logical_stop_propagation
clock_sense_negative
clock_sense_positive
clock_sense_stop_propagation
delay_max_fall
delay_max_rise
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Analysis Attributes--clock Attributes for Analysis
delay_min_fall
delay_min_rise
divide_by
divide_by_4prop
divide_fall
divide_period
divide_rise
divide_waveform
duty_cycle
edge_shift
edges
exceptions
fall
generated_clocks
is_generated
is_inverted
is_library_created
is_propagated
is_virtual
master_clock
master_source
min_pulse_width_high
min_pulse_width_low
multiply_by
period
rise
sources
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Analysis Attributes--clock Attributes for Analysis
view_name
waveform
waveform_4prop
actual_period
actual_period
Read-only clock attribute. Returns the real clock period of the clock. You can also derive the real
clock period (specified in picoseconds)by divding the value of the period attribute by the value of
the divide_period attribute.
Related Information
Set by this command: create_clock
Related attributes: (clock) divide_period
(clock) period
clock_domain
clock_domain domain
Read-only clock attribute. Returns the (timing) domain of the clock.
clock_groups
clock_groups groups
Read-only clock attribute. Returns the clock groups that the clock belongs to.
Related Information
Related command: set_clock_groups
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Analysis Attributes--clock Attributes for Analysis
clock_relation_to_others
clock_relation_to_others {relation_type {clock1 clock2} relation_type {clock3 clock4}...}
Read-only clock attribute. Returns the clock relation type and the clocks related to this based on a
set_clock_groups constraint.
Related Information
Related command: set_clock_groups
clock_sense_all_stop
clock_sense_all_stop {constant | hpin | hport | pg_pin | pin | port}+
Read-only clock attribute. Returns the pins that stop propagate data, data out and clock.
Related Information
Set by this command: set_clock_sense -type all
clock_sense_clock_source_data_stop_propagation
clock_sense_clock_source_data_stop_propagation {constant | hpin | hport | pg_pin | pin | port}+
Read-only clock attribute. Returns the pins that stop data out from propagation.
Related Information
Set by this command: set_clock_sense -type clock_source_data
clock_sense_clock_stop_propagation
clock_sense_clock_stop_propagation {constant | hpin | hport | pg_pin | pin | port}+
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Genus Attribute Reference
Analysis Attributes--clock Attributes for Analysis
Read-only clock attribute. Returns the pins that stop clocks from propagation.
Related Information
Set by this command: set_clock_sense -type clock
clock_sense_data_stop_propagation
clock_sense_data_stop_propagation {constant | hpin | hport | pg_pin | pin | port}+
Read-only clock attribute. Returns the pins that stop data launched by clocks for propagation.
Related Information
Set by this command: set_clock_sense -type data
clock_sense_logical_stop_propagation
clock_sense_logical_stop_propagation {constant | hpin | hport | pg_pin | pin | port} ...
Read-only clock attribute. Returns the pins where the propagation of the clock is stopped.
clock_sense_negative
clock_sense_negative {constant | hpin | hport | pg_pin | pin | port} ...
Read-only clock attribute. Returns the pins that propagate the negative sense of this clock.
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Analysis Attributes--clock Attributes for Analysis
Related Information
Set by this command: set_clock_sense -negative
Related attributes: (hpin) clock_sense_negative
(pin) clock_sense_negative
(clock) clock_sense_positive
(clock) clock_sense_stop_propagation
clock_sense_positive
clock_sense_positive {constant | hpin | hport | pg_pin | pin | port} ...
Read-only clock attribute. Returns the pins that propagate the positive sense of this clock.
Related Information
Set by this command: set_clock_sense -negative
Related attributes: (hpin) clock_sense_positive
(pin) clock_sense_positive
(clock) clock_sense_negative
(clock) clock_sense_stop_propagation
clock_sense_stop_propagation
clock_sense_stop_propagation {constant | hpin | hport | pg_pin | pin | port} ...
Read-only clock attribute. Returns the pins that stop propagation of the clock.
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Genus Attribute Reference
Analysis Attributes--clock Attributes for Analysis
Related Information
Set by this command: set_clock_sense -stop_propagation
Related attributes: (hpin) clock_sense_stop_propagation
(pin) clock_sense_stop_propagation
(clock) clock_sense_negative
(clock) clock_sense_positive
delay_max_fall
delay_max_fall delay
Read-only clock attribute. Returns the assumed input maximal falling slew at the clock pins using
this clock.
Related Information
Related attributes: (hpin) delay_max_fall
(pin) delay_max_fall
(port) delay_max_fall
delay_max_rise
delay_max_rise delay
Read-only clock attribute. Returns the assumed input maximal rising slew at the clock pins using
this clock.
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Genus Attribute Reference
Analysis Attributes--clock Attributes for Analysis
Related Information
Related attributes: (hpin) delay_max_rise
(pin) delay_max_rise
(port) delay_max_rise
delay_min_fall
delay_min_fall delay
Read-only clock attribute. Returns the assumed input minimal falling slew at the clock pins using
this clock.
Related Information
Related attributes: (hpin) delay_min_fall
(pin) delay_min_fall
(port) delay_min_fall
delay_min_rise
delay_min_rise delay
Read-only clock attribute. Returns the assumed input minimal rising slew at the clock pins using
this clock.
Related Information
Related attributes: (hpin) delay_min_rise
(pin) delay_min_rise
(port) delay_min_rise
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Analysis Attributes--clock Attributes for Analysis
divide_by
divide_by integer
Read-only clock attribute. Returns the value specified using the -divide_by option of the
create_generated_clock command.
Related Information
Set by this command: create_generated_clock
divide_by_4prop
divide_by_4prop integer
Default: 0
Read-only clock attribute. Returns divide_by generated clock.
divide_fall
divide_fall integer
Read-only clock attribute. Returns the value specified using the -divide_fall option of the
create_clock command.
Related Information
Set by this command: create_clock
Related attributes: (test_clock) divide_fall
(test_signal) divide_fall
fall
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Analysis Attributes--clock Attributes for Analysis
divide_period
divide_period integer
Read-only clock attribute. Returns the value specified using the -divide_period option of the
create_clock command.
Related Information
Set by this command: create_clock
Related attributes: (test_clock) divide_period
(test_signal) divide_period
period
divide_rise
divide_rise integer
Read-only clock attribute. Returns the value specified using the -divide_rise option of the
create_clock command.
Related Information
Set by this command: create_clock
Related attributes: (test_clock) divide_rise
(test_signal) divide_rise
rise
divide_waveform
divide_waveform integer_list
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Analysis Attributes--clock Attributes for Analysis
Read-only clock attribute. Returns a list of integers that is used together with the values of the
waveform attribute. The values of the waveform attribute are used as nominators, while the
corresponding values of the divide_waveform attribute are used as denominators to determine edge
changes during the clock period.
Example
In the example below a new clock is generated using the edges of a source clock. Since the
generated clock refers to six edges, the difference between 2 edges in the generated clock is 1/5
the of the period of the generated clock. So edge 2 has nominator 1 and denominator 5. Since the
last edge of any generated clock corresponds to the end of the period, it does not need to be
included in the list because its nominator and denominator are always equal.
genus@root:> create_clock -period 30 -name clk ports_in/clkgenus@root:> create_generated_clock -name
genclck -source ports_in/clk \-edges {1 2 4 5 6} flop/CK
Related Information
Set by this command: create_generated_clock
Related attribute: waveform
duty_cycle
duty_cycle float
Read-only clock attribute. Returns the duty cycle of of the generated clock.
Related Information
Set by this command: create_generated_clock
edge_shift
edge_shift string
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Analysis Attributes--clock Attributes for Analysis
Read-only clock attribute. Returns how much each of the edges of the generated clock is shifted.
edges
edges string
Read-only clock attribute. Returns the list of edges of the generated clock.
exceptions
exceptions string
Read-only clock attribute. Returns a list of all the timing exceptions that were applied to the
specified clock.
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Analysis Attributes--clock Attributes for Analysis
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
Related attributes: (cost_group) exceptions
(external_delay) exceptions
(hinst) exceptions
(hpin) exceptions
(inst) exceptions
(pin) exceptions
(port) exceptions
(timin_path) exceptions
fall
fall integer
Read-only clock attribute. Returns the value specified using the -fall option of the create_clock
command.
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Analysis Attributes--clock Attributes for Analysis
Related Information
Set by this command: create_clock
Related attributes: divide_fall
(test_clock) divide_fall
(test_signal) divide_fall
generated_clocks
generated_clocks list_of_clocks
Read-only clock attribute. Returns the list of clocks generated from this clock.
Related Information
Set by this command: create_generated_clock
is_generated
is_generated {false | true}
Read-only clock attribute. Indicates whether this clock is a generated clock.
is_inverted
is_inverted {false | true}
Read-only clock attribute. Indicates whether this generated clock is inverted.
Related Information
Set by this command: create_generated_clock
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Analysis Attributes--clock Attributes for Analysis
is_library_created
is_library_created {false | true}
Read-only clock attribute. Indicates whether this clock is generated by the libcell.
is_propagated
is_propagated {false | true}
Read-only clock attribute. Indicates whether this clock is propagated.
is_virtual
is_virtual {false | true}
Default: false
Read-only clock attribute. Checks for virtual clock.
master_clock
master_clock clock
Read-only clock attribute. Returns the value specified using the -master_clock option of the
create_generated_clock command.
Related Information
Set by this command: create_generated_clock
master_source
master_source {hpin|pin|constant|pg_pin|hport|port}
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Analysis Attributes--clock Attributes for Analysis
Read-only clock attribute. Returns the value specified using the -source option of the
create_generated_clock command.
Related Information
Set by this command: create_generated_clock
min_pulse_width_high
min_pulse_width_high float
Read-only clock attribute. Returns the minimum pulse width constraint on the high signal level of
the clock.
Related Information
Related attribute: min_pulse_width
min_pulse_width_low
min_pulse_width_low float
Read-only clock attribute. Returns the minimum pulse width constraint on the low signal level of
the clock.
Related Information
Related attribute: min_pulse_width
multiply_by
multiply_by integer
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Read-only clock attribute. Returns the factor by which the frequency of the generated clock is
multiplied,
period
period integer
Read-only clock attribute. Returns the value specified using the -period option of the
create_clock command.
To derive the real clock period (specified in picoseconds), you can divide the value of the period
attribute by the value of the divide_period attribute.
Related Information
Set by this command: create_clock
Related attributes: divide_period
(test_clock) divide_period
(test_signal) divide_period
rise
rise integer
Read-only clock attribute. Returns the value specified using the -rise option of the create_clock
command.
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Analysis Attributes--clock Attributes for Analysis
Related Information
Set by this command: create_clock
Related attributes: divide_rise
(test_clock) divide_rise
(test_signal) divide_rise
sources
sources pin_list
Read-only clock attribute. Returns a list of pins, or ports, or constants that are sources of the clock
signal.
view_name
view_name string
Read-only clock attribute. Returns the name of the analysis_view to which the clock applies in
case of multi-mode analysis.
waveform
waveform integer_list
Read-only clock attribute. Returns a list of integers that together with the values of the
divide_waveform attribute determine the waveform of the clock. The values of the waveform
attribute are used as nominators, while the corresponding values of the divide-waveform attribute
are used as denominators to determine edge changes in the clock period.
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Analysis Attributes--constant Attributes for Analysis
Related Information
Set by this command: create_generated_clock
Related attribute: divide_waveform
waveform_4prop
waveform_4prop string
Default: no value
Read-only clock attribute. Returns waveform of the clock.
constant Attributes for Analysis
capacitance_max_fall
capacitance_max_rise
capacitance_min_fall
capacitance_min_rise
external_net_wire_capacitance
hinst
wire_capacitance
wire_length
wire_resistance
capacitance_max_fall
capacitance_max_fall max_cap
Read-only constant attribute. Returns the maximum capacitance of the net driving this constant for
a fall transition. This is a computed attribute. Computed attributes are potentially very time
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Analysis Attributes--constant Attributes for Analysis
consuming to process and not listed by the vls command by default.
Related Information
Related attributes: (hpin) capacitance_max_fall
(hport) capacitance_max_fall
(pin) capacitance_max_fall
(port) capacitance_max_fall
capacitance_max_rise
capacitance_max_rise max_cap
Read-only constant attribute. Returns the maximum capacitance of the net driving this constant for
a rise transition. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related attributes: (hpin) capacitance_max_rise
(hport) capacitance_max_rise
(pin) capacitance_max_rise
(port) capacitance_max_rise
capacitance_min_fall
capacitance_min_fall min_cap
Read-only constant attribute. Returns the minimum capacitance of the net driving this constant for
a fall transition. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
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Related Information
Related attributes: (hpin) capacitance_min_fall
(hport) capacitance_min_fall
(pin) capacitance_min_fall
(port) capacitance_min_fall
capacitance_min_rise
capacitance_min_rise min_cap
Read-only constant attribute. Returns the minimum capacitance of the net driving this constant for
a rise transition. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related attributes: (hpin) capacitance_min_rise
(hport) capacitance_min_rise
(pin) capacitance_min_rise
(port) capacitance_min_rise
external_net_wire_capacitance
external_net_wire_capacitance {no_value | float}
Read-only constant attribute. Returns the external wire capacitance (in femtofarad) seen at this
constant. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
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Related Information
Related attributes: (hpin) external_net_wire_capacitance
(hport) external_net_wire_capacitance
(pin) external_net_wire_capacitance
(port) external_net_wire_capacitance
hinst
hinst hinst
Read-only constant attribute. Returns the hierarchical instance that the constant belongs to.
Related Information
Related attributes: (hinst) hinst
(hnet) hinst
(hpin) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
(pg_pin) hinst
wire_capacitance
wire_capacitance float
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Analysis Attributes--constant Attributes for Analysis
Read-only constant attribute. Returns the wire-capacitance of a constant’s net. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Example
The following command returns the wire capacitance of the constant’s net:
get_db constant:inst1/0 .wire_capacitance 0.0
Related Information
Related attributes: (hpin) wire_capacitance
(hport) wire_capacitance
(pin) wire_capacitance
(port) wire_capacitance
wire_length
wire_length {no_value | float}
Read-only constant attribute. Returns the wire length of the net connected to the given constant.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
The value for constant objects is zero.
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Analysis Attributes--cost_group Attributes for Analysis
Related Information
Related attributes: (hpin) wire_length
(hport) wire_length
(pin) wire_length
(port) wire_length
wire_resistance
wire_resistance {no_value | float}
Read-only constant attribute. Returns the net resistance of a constant’s net in kilohms. Resolution
is 1/1000. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
Related Information
Related attributes: (hpin) wire_resistance
(hport) wire_resistance
(pin) wire_resistance
(port) wire_resistance
cost_group Attributes for Analysis
exceptions
fep
tslk
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Analysis Attributes--cost_group Attributes for Analysis
exceptions
exceptions string
Read-only cost_group attribute. Returns a list of all the timing exceptions that were applied to the
specified cost group.
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
Related attributes: (clock) exceptions
(external_delay) exceptions
(hinst) exceptions
(hpin) exceptions
(inst) exceptions
(pin) exceptions
(port) exceptions
(timin_path) exceptions
fep
fep double
Default: 0.0
Read-only cost_group attribute. Returns the total failing endpoints of cost group.
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Analysis Attributes--exception Attributes for Analysis
tslk
tslk double
Read-only cost_group attribute. Returns the total slack of slacks less than 1000 per design.
exception Attributes for Analysis
adjust_value
delay_value
domain
exception_type
from_points
lenient
paths
precluded_path_adjusts
priority
shift_capture
shift_launch
shift_launch_default
through_points
to_points
adjust_value
adjust_value {no_value | float}
Read-only exception attribute. Returns the delay constraint value of a path_adjust exception. The
no_value value applies to all exceptions other than the path_adjust exception.
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Analysis Attributes--exception Attributes for Analysis
Related Information
Set by this command: path_adjust
delay_value
delay_value {no_value | float}
Read-only exception attribute. Returns the delay constraint for a path_delay exception. The
no_value value applies to all exceptions other than the path_delay exception.
Related Information
Set by this command: set_max_delay
domain
domain clock_domain
Read-only exception attribute. Returns the clock domain that this exception applies to.
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
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Analysis Attributes--exception Attributes for Analysis
exception_type
exception_type {multi_cycle | path_delay | path_disable | path_adjust | path_group}
Read-only exception attribute. Returns the exception type multi_cycle, path_delay, path_disable,
path_adjust, or path_group, depending on the command used to create the exception.
Related Information
Constraints in the Genus Command Reference.
SDC Commands in the Genus Command Reference.
Set by one of these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
from_points
from_points {clock* | port* | inst* | hinst* | pin* | hpin* | port_bus* | hpin_bus*}
Read-only exception attribute. Returns the objects specified with the -from option of a timing
exception command.
As the design is optimized, some of these points may have their names changed (for example, if a
new hierarchy is introduced or if a hierarchy is flattened). This attribute is dynamically updated
during such changes.
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Analysis Attributes--exception Attributes for Analysis
Related Information
Set by one of these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
set_path_specification
lenient
lenient {true | false}
Read-only exception attribute. Indicates if the exception was created with the -lenient option.
Related Information
Set by one of these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
set_path_specification
paths
paths string
Read-only exception attribute. Returns the Tcl command that specifies the paths to which the
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Analysis Attributes--exception Attributes for Analysis
exception is being applied.
Related Information
precluded_path_adjusts
precluded_path_adjusts string
Read-only exception attribute. Returns a list of path_adjust objects that can be ignored if this
path_adjust exception is satisfied. By default, path_adjust exceptions accumulate and their effects
are added together. You do not need to set this attribute—it is normally only set by the
create_derived_design command.
This attribute is only valid on path_adjust exceptions.
Related Information
Set by this command: create_derived_design
priority
See: priority
shift_capture
shift_capture {no_value | integer}
Read-only exception attribute. Returns the capture clock shift value of a multi_cycle exception.
The no_value value applies to all exceptions other than the multi_cycle exception.
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Analysis Attributes--exception Attributes for Analysis
Related Information
Set by this command: set_multicycle_path
shift_launch
shift_launch {no_value | integer}
Read-only exception attribute. Returns the launch clock shift value of a multi_cycle exception.
The no_value value applies to all exceptions other than the multi_cycle exception.
Related Information
Set by this command: set_multicycle_path
shift_launch_default
shift_launch_default {1 | 0 | true | false}
Default: no value
Read-write exception attribute. Controls whether the source clock cycle shifts default flag.
through_points
through_points {port* | inst* | hinst* | hpin* | pin* | hnet* | port_bus* | hpin_bus*}
Read-only exception attribute. Returns the objects using the -through option of a timing exception
command. As the design is optimized, some of these points may have their names changed (for
example, if a new hierarchy is introduced or if a hierarchy is flattened). This attribute is dynamically
updated during such changes.
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Analysis Attributes--exception Attributes for Analysis
Related Information
Set by one of these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
set_path_specification
to_points
to_points {clock* | port* | inst* | hinst* | pin* | hpin* | port_bus* | hpin_bus*}
Read-only exception attribute. Returns the objects specified with the -to option of a timing
exception command. As the design is optimized, some of these points may have their names
changed (for example, if a new hierarchy is introduced or if a hierarchy is flattened). This attribute is
dynamically updated during such changes.
Related Information
Set by one of these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
set_path_specification
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Analysis Attributes--external_delay Attributes for Analysis
external_delay Attributes for Analysis
clock
clock_rise
exceptions
external_delay_pins
input_delay
level_sensitive
sigma_delay
clock
clock string
Read-only external_delay attribute. Returns the clock object for the external_delay constraint.
Related Information
Set by this command: create_clock
Affects these commands: set_input_delay
set_output_delay
clock_rise
clock_rise {true | false}
Read-only external_delay attribute. Returns true if the external_delay is relative to a rising clock
edge and false if it is relative to a falling edge.
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Related Information
Set by these commands: set_input_delay
set_output_delay
exceptions
exceptions string
Read-only external_delay attribute. Returns a list of all the timing constraints that were applied to
the specified external delay.
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
Related attributes: (clock) exceptions
(cost_group) exceptions
(hinst) exceptions
(hpin) exceptions
(inst) exceptions
(pin) exceptions
(port) exceptions
(timin_path) exceptions
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Analysis Attributes--external_delay Attributes for Analysis
external_delay_pins
external_delay_pins string
Read-only external_delay attribute. Returns the Tcl list of pins and ports for the external_delay
constraint.
Related Information
Set by these commands: set_input_delay
set_output_delay
Related attributes: external_delays
input_delay
input_delay {true | false}
Read-only external_delay attribute. Returns true if the external_delay is an input delay and
false if it is an output delay.
Related Information
Set by these commands: set_input_delay
set_output_delay
level_sensitive
level_sensitive {true | false}
Read-only external_delay attribute. Returns true if the external register is level-sensitive and
false if the external register is edge-triggered.
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Analysis Attributes--hdl_architecture Attributes for Analysis
Related Information
Set by these commands: set_input_delay
set_output_delay
sigma_delay
sigma_delay double
Read-write external_delay attribute. Specifies the external sigma delay value in the following
format:
{max_rise max_fall}
Related Information
Set by these commands: set_input_delay
set_output_delay
hdl_architecture Attributes for Analysis
blocks
hdl_lib
hdl_pins
labels
parameters
processes
start_source_line
structural
subprograms
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Analysis Attributes--hdl_architecture Attributes for Analysis
verilog_macros
blocks
blocks list_of_hdl_blocks
Read-only hdl_architecture attribute. Returns a list of hdl_block objects for this architecture. This
is a computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Informatio
Related attribute: (hdl_block) blocks
hdl_lib
hdl_lib object
Read-only hdl_architecture attribute. Returns the hdl_lib to which the architecture belongs.
Related Information
Related attributes: (hdl_block) hdl_lib
(hdl_component) hdl_lib
(hdl_configuration) hdl_lib
(hdl_operator) hdl_lib
(hdl_package) hdl_lib
hdl_pins
hdl_pins list_of_hdl_pins
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Analysis Attributes--hdl_architecture Attributes for Analysis
Read-only hdl_architecture attribute. Returns a list of hdl_pin objects for this architecture. This is
a computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Information
Related attributes: (hdl_component) hdl_pins
(hdl_operator) hdl_pins
labels
labels list_of_hdl_label
Read-only hdl_architecture attribute. Returns the list of hdl_label objects for this architecture.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related attribute: (hdl_block) labels
parameters
parameters string
Read-only hdl_architecture attribute. In Verilog, this attribute keeps an ordered list of all
parameters of the module represented by the hdl_architecture object. In VHDL, this attribute
keeps an ordered list of generics of the entity represented by the hdl_architecture object.
Do not confuse this attribute with the parameters branch of vdir objects attached to the
hdl_object. Under that branch, each parameter is represented by its own hdl_parameter
object.
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Related Information
Related attribute: (hdl_component) parameters
processes
processes list_of_hdl_procedures
Read-only hdl_architecture attribute. Returns the list of hdl_procedure objects for this
architecture. This is a computed attribute. Computed attributes are potentially very time consuming
to process and not listed by the vls command by default.
Related Information
Related attribute: (hdl_block) processes
start_source_line
start_source_line integer
Read-only hdl_architecture attribute. Returns the start line number in an HDL input file for a
module.
This attribute is supported only in the RTL flow.
structural
structural {true | false}
Read-only hdl_architecture attribute. Returns whether the architecture specified in an HDL file is
structural.
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Analysis Attributes--hdl_bind Attributes for Analysis
subprograms
subprograms list_of_hdl_subprograms
Read-only hdl_architecture attribute. Returns the list of hdl_subprogram objects for this
architecture. This is a computed attribute. Computed attributes are potentially very time consuming
to process and not listed by the vls command by default.
Related Information
Related attribute: (hdl_block) subprograms
(hdl_package) subprograms
verilog_macros
verilog_macros list
Read-only hdl_architecture attribute. Returns information about all the `define macros and their
values used in this user-defined module using the following Tcl list format:
{file_name line_number {macro_name macro_value}}
This attribute must be used after the read_hdl command, but before the elaborate command.
Related Information
Related command: read_hdl
hdl_bind Attributes for Analysis
hdl_component
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Analysis Attributes--hdl_block Attributes for Analysis
hdl_component hdl_component
Read-only hdl_bind attribute. Returns the hdl_component for this hdl_bind object.
Related Information
Related attributes: (hdl_implementation) hdl_component
(hdl_parameter) hdl_component
(hdl_pin) hdl_component
operator
operator operator_name
Read-only hdl_bind attribute. Returns the name of the synthetic operator to which the specified
binding applies.
hdl_block Attributes for Analysis
blocks
hdl_architecture
hdl_block
hdl_lib
labels
processes
subprograms
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Analysis Attributes--hdl_block Attributes for Analysis
blocks
blocks list_of_hdl_blocks
Read-only hdl_block attribute. Returns a list of hdl_block objects for this block. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Related Information
Related attribute: (hdl_architecture) blocks
hdl_architecture
hdl_architecture object
Read-only hdl_block attribute. Returns the hdl_architecture for this block.
Related Information
Related attributes: (hdl_inst) hdl_architecture
(hdl_label) hdl_architecture
(hdl_parameter) hdl_architecture
(hdl_pin) hdl_architecture
(hdl_procedure) hdl_architecture
(hdl_subprogram) hdl_architecture
hdl_block
hdl_block object
Read-only hdl_block attribute. Returns the hdl_block for this block.
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Analysis Attributes--hdl_block Attributes for Analysis
Related Information
Related attributes: (hdl_inst) hdl_block
(hdl_label) hdl_block
(hdl_procedure) hdl_block
(hdl_subprogram) hdl_block
hdl_lib
hdl_lib object
Read-only hdl_block attribute.Returns the hdl_lib to which the block belongs.
Related Information
Related attributes: (hdl_architecture) hdl_lib
(hdl_component) hdl_lib
(hdl_configuration) hdl_lib
(hdl_operator) hdl_lib
(hdl_package) hdl_lib
labels
labels list_of_hdl_label
Read-only hdl_block attribute. Returns the list of hdl_label objects for this block. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
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Analysis Attributes--hdl_component Attributes for Analysis
Related Information
Related attribute: (hdl_architecture) labels
processes
processes list_of_hdl_procedures
Read-only hdl_block attribute. Returns the list of hdl_procedure objects for this block. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Information
Related attribute: (hdl_architecture) processes
subprograms
subprograms list_of_hdl_subprograms
Read-only hdl_block attribute. Returns the list of hdl_subprogram objects for this block. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Information
Related attribute: (hdl_architecture) subprograms
(hdl_package) subprograms
hdl_component Attributes for Analysis
bindings
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Analysis Attributes--hdl_component Attributes for Analysis
hdl_lib
hdl_pins
implementations
parameters
bindings
bindings list_of_hdl_bind
Read-only hdl_component attribute. Returns a list of hdl_bind objects for this hdl_component. This
is a computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
hdl_lib
hdl_lib object
Read-only hdl_component attribute. Returns the hdl_lib to which the hdl_component belongs.
Related Information
Related attributes: (hdl_architecture) hdl_lib
(hdl_block) hdl_lib
(hdl_configuration) hdl_lib
(hdl_operator) hdl_lib
(hdl_package) hdl_lib
hdl_pins
hdl_pins list_of_hdl_pins
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Analysis Attributes--hdl_component Attributes for Analysis
Read-only hdl_component attribute. Returns a list of hdl_pin objects for this component. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Information
Related attributes: (hdl_architecture) hdl_pins
(hdl_operator) hdl_pins
implementations
implementations list_of_hdl_implementations
Read-only hdl_component attribute. Returns a list of hdl_implementation objects for this component.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
parameters
parameters string
Read-only hdl_component attribute. Returns an ordered list of all parameters of the specified
ChipWare component.
Do not confuse this attribute with the parameters branch of vdir objects attached to the
hdl_component object. Under that branch, each parameter is represented by its own
hdl_parameter object.
Related Information
Related attribute: (hdl_architecture) parameters
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Analysis Attributes--hdl_configuration Attributes for Analysis
hdl_configuration Attributes for Analysis
entity
entity string
Read-only hdl_configuration attribute. Specifies the name of the entity to which this configuration
applies.
hdl_lib
hdl_lib object
Read-only hdl_configuration attribute. Returns the hdl_lib to which the configuration belongs.
Related Information
Related attributes: (hdl_architecture) hdl_lib
(hdl_block) hdl_lib
(hdl_component) hdl_lib
(hdl_operator) hdl_lib
(hdl_package) hdl_lib
hdl_implementation Attributes for Analysis
hdl_component
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Analysis Attributes--hdl_inst Attributes for Analysis
hdl_component hdl_component
Read-only hdl_implementation attribute. Returns the hdl_component for this hdl_implementation.
Related Information
Related attributes: (hdl_bind) hdl_component
(hdl_parameter) hdl_component
(hdl_pin) hdl_component
hdl_inst Attributes for Analysis
component
component string
Read-only hdl_inst attribute. Returns the module corresponding to this instance.
This attribute is supported only in the RTL flow.
hdl_architecture
hdl_architecture object
Read-only hdl_inst attribute. Returns the hdl_architecture for this hdl_inst.
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Analysis Attributes--hdl_label Attributes for Analysis
Related Information
Related attributes: (hdl_block) hdl_architecture
(hdl_label) hdl_architecture
(hdl_parameter) hdl_architecture
(hdl_pin) hdl_architecture
(hdl_procedure) hdl_architecture
(hdl_subprogram) hdl_architecture
hdl_block
hdl_block object
Read-only hdl_inst attribute. Returns the hdl_block for this hdl_inst.
Related Information
Related attributes: (hdl_block) hdl_block
(hdl_label) hdl_block
(hdl_procedure) hdl_block
(hdl_subprogram) hdl_block
hdl_label Attributes for Analysis
hdl_architecture
hdl_architecture object
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Analysis Attributes--hdl_lib Attributes for Analysis
Read-only hdl_label attribute. Returns the hd_architecture for this label.
Related Information
Related attributes: (hdl_block) hdl_architecture
(hdl_inst) hdl_architecture
(hdl_parameter) hdl_architecture
(hdl_pin) hdl_architecture
(hdl_procedure) hdl_architecture
(hdl_subprogram) hdl_architecture
hdl_block
hdl_block object
Read-only hdl_label attribute. Returns the hdl_block for this label.
Related Information
Related attributes: (hdl_block) hdl_block
(hdl_inst) hdl_block
(hdl_procedure) hdl_block
(hdl_subprogram) hdl_block
hdl_lib Attributes for Analysis
architectures
components
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Analysis Attributes--hdl_lib Attributes for Analysis
configurations
operators
packages
architectures
architectures list_of_hdl_architectures
Read-only hdl_lib attribute. Returns the list of hdl_arhictectures for this hdl_lib. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
components
components list_of_hdl_components
Read-only hdl_lib attribute. Returns the list of components for this hdl_lib. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
configurations
configurations list_of_hdl_configurations
Read-only hdl_lib attribute. Returns the list of configurations for this hdl_lib. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
operators
operators list_of_hdl_operators
Read-only hdl_lib attribute. Returns the list of hdl_operators for this hdl_lib. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
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Analysis Attributes--hdl_operator Attributes for Analysis
packages
packages list_of_hdl_packages
Read-only hdl_lib attribute. Returns the list of hdl_packages for this hdl_lib. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
hdl_operator Attributes for Analysis
hdl_lib
hdl_lib object
Read-only hdl_operator attribute. Returns the hdl_lib to which this operator belongs.
Related Information
Related attributes: (hdl_architecture) hdl_lib
(hdl_block) hdl_lib
(hdl_component) hdl_lib
(hdl_configuration) hdl_lib
(hdl_package) hdl_lib
hdl_pins
hdl_pins list_of_hdl_pins
Read-only hdl_operator attribute. Returns the list of of hdl_pin objects for this operator. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
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Genus Attribute Reference
Analysis Attributes--hdl_package Attributes for Analysis
Related Information
Related attributes: (hdl_architecture) hdl_pins
Related attributes: (hdl_component) hdl_pins
hdl_package Attributes for Analysis
default_location
hdl_lib
subprograms
default_location
default_location pathname
Read-only hdl_package attribute. Returns the physical location of the source file that contains the
registered VHDL package. Registered VHDL packages are only created through the hdl_create
package command.
Related Information
Affected by this command: create_component_parameter
Related Attribute: location
hdl_lib
hdl_lib object
Read-only hdl_package attribute. Returns the hdl_lib to which this package belongs.
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Analysis Attributes--hdl_parameter Attributes for Analysis
Related Information
Related attributes: (hdl_architecture) hdl_lib
(hdl_block) hdl_lib
(hdl_component) hdl_lib
(hdl_configuration) hdl_lib
(hdl_operator) hdl_lib
subprograms
subprograms list_of_hdl_subprograms
Read-only hdl_package attribute. Returns the list of hdl_subprogram objects for this package. This
is a computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Information
Related attribute: (hdl_architecture) subprograms
(hdl_block) subprograms
hdl_parameter Attributes for Analysis
hdl_architecture
hdl_architecture object
Read-only hdl_parameter attribute. Returns the hd_architecture for this hdl_parameter.
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Analysis Attributes--hdl_parameter Attributes for Analysis
Related Information
Related attributes: (hdl_block) hdl_architecture
(hdl_inst) hdl_architecture
(hdl_label) hdl_architecture
(hdl_pin) hdl_architecture
(hdl_procedure) hdl_architecture
(hdl_subprogram) hdl_architecture
hdl_component
hdl_component hdl_component
Read-only hdl_parameter attribute. Returns the hdl_component for this hdl_parameter.
Related Information
Related attributes: (hdl_bind) hdl_component
(hdl_implementation) hdl_component
(hdl_pin) hdl_component
hdl_parameter
hdl_parameter {true | false}
Read-only hdl_parameter attribute. Returns whether the specified parameter is visible within the
ChipWare component. If the specified parameter was created with the hdl_create parameter
command without its -hdl_invisible option, the default value of this attribute will be false. If the
specified parameter was created with the -hdl_invisible option, this attribute value becomes true.
This attribute is valid on all parameters (hdl_parameter objects), not just those created by the
hdl_create parameter command.
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Analysis Attributes--hdl_pin Attributes for Analysis
Related Information
Related command: create_component_parameter
hdl_pin Attributes for Analysis
hdl_architecture
hdl_component
hdl_operator
hdl_architecture
hdl_architecture object
Read-only hdl_pin attribute. Returns the hd_architecture for this hdl_pin.
hdl_component
hdl_component hdl_component
Read-only hdl_pin attribute. Returns the hdl_component for this hdl_pin.
hdl_operator
hdl_operator object
Read-only hdl_pin attribute. Returns the hdl_operator for this hdl_pin.
hdl_procedure Attributes for Analysis
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Analysis Attributes--hdl_pin Attributes for Analysis
hdl_architecture
hdl_architecture object
Read-only hdl_procedure attribute. Returns the hd_architecture for this procedure.
Related Information
Related attributes: (hdl_block) hdl_architecture
(hdl_inst) hdl_architecture
(hdl_label) hdl_architecture
(hdl_parameter) hdl_architecture
(hdl_pin) hdl_architecture
(hdl_subprogram) hdl_architecture
hdl_block
hdl_block object
Read-only hdl_procedure attribute. Returns the hdl_block for this procedure.
Related Information
Related attributes: (hdl_block) hdl_block
(hdl_inst) hdl_block
(hdl_label) hdl_block
(hdl_subprogram) hdl_block
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Analysis Attributes--hdl_subprogram Attributes for Analysis
hdl_subprogram Attributes for Analysis
hdl_architecture
hdl_architecture object
Read-only hdl_subprogram attribute. Returns the hd_architecture for this subprogram.
Related Information
Related attributes: (hdl_block) hdl_architecture
(hdl_inst) hdl_architecture
(hdl_label) hdl_architecture
(hdl_parameter) hdl_architecture
(hdl_pin) hdl_architecture
(hdl_procedure) hdl_architecture
hdl_block
hdl_block object
Read-only hdl_subprogram attribute. Returns the hdl_block for this subprogram.
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Genus Attribute Reference
Analysis Attributes--hnet Attributes for Analysis
Related Information
Related attributes: (hdl_block) hdl_block
(hdl_inst) hdl_block
(hdl_label) hdl_block
(hdl_procedure) hdl_block
hdl_package
hdl_package
Read-only hdl_subprogram attribute. Returns the hdl_package for this subprogram.
hnet Attributes for Analysis
dont_touch_file
dont_touch_reason
drivers
hinst
is_constant
is_driven_by_supply0
is_driven_by_supply1
is_ideal
is_part_of_bus
loads
net
num_drivers
num_loads
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Analysis Attributes--hnet Attributes for Analysis
type
dont_touch_file
dont_touch_file string
Read-write hnet attribute. Specify to set the sourced file as dont_touch.
dont_touch_reason
dont_touch_reason list_of_delay_corners
Read-write hnet attribute. Specify the reason for setting the sourced file as dont_touch.
drivers
drivers string
Read-only hnet attribute. Returns the hierarchical path to the pin driving this net.
Related Information
Related attributes: (hpin) drivers
(hport) drivers
(net) driver_pins
(pg_pin) drivers
hinst
hinst hinst
Read-only hnet attribute. Returns the hierarchical instance that the hierarchical net belongs to.
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Analysis Attributes--hnet Attributes for Analysis
Related Information
Related attributes: (constant)) hinst
(hinst) hinst
(hpin) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
(pg_pin) hinst
is_constant
is_constant {false | true}
Read-only hnet attribute. Indicates whether the specified net is driven by a constant.
Related Information
Related attribute (net) is_constant
is_driven_by_supply0
is_driven_by_supply0 {true | false}
Read-only hnet attribute. Indicates whether the specified net is driven by a supply0 net (ground
net).
This attribute is only supported in the structural flow.
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Analysis Attributes--hnet Attributes for Analysis
is_driven_by_supply1
driven_by_supply1 {true | false}
Read-only hnet attribute. Indicates whether the specified net is driven by a supply1 net (power
net).
This attribute is only supported in the structural flow.
is_ideal
is_ideal {true | false}
Read-only hnet attribute. Indicates whether the specified net is ideal.
Valid causes for a net being ideal are:
An ideal_driver attribute is set on a driver of the net
An ideal_network attribute is set on a driver in the fan in of the net
A clock pin for a sequential instance is on the net
A logic constant drives the net
The net is connected to a pin whose propagated_ideal_network attribute is set to true.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Affected by these attributes: (pin) ideal_driver
(port) ideal_driver
is_part_of_bus
is_part_of_bus {false | true}
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Analysis Attributes--hnet Attributes for Analysis
Read-only hnet attribute. Indicates whether the specified net is a single net or part of a bus.
Related Information
Affects this command: update_names
loads
loads list_of_pins
Read-only hnet attribute. Returns the hierarchical path to the pins loading this net.
Related Information
Related attributes: (hpin) loads
(hport) loads
(net) load_pins
(pg_pin) loads
net
net hnet
Read-only hnet attribute. Returns the flat net of this net.
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Analysis Attributes--hnet Attributes for Analysis
Related Information
Related attributes: (hpin) net
(hport) net
(pin) net
(pg_pin) net
(port) net
num_drivers
num_drivers integer
Read-only hnet attribute. Lists the number of drivers on the net.
Related Information
Related attribute: (net) num_drivers
num_loads
num_loads integer
Read-only hnet attribute. Lists the number of loads on the net.
Related Information
Related attribute: (net) num_loads
type
type {wire | wand | wor | supply0 | supply1}
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Analysis Attributes--hpin Attributes for Analysis
Default: wire
Read-write hnet attribute. Returns the type of the net.
hpin Attributes for Analysis
arrival_max_fall
arrival_max_rise
arrival_min_fall
arrival_min_rise
arrival_window
boundary_optimize_hpin_invertible
capacitance_max_fall
capacitance_max_rise
capacitance_min_fall
capacitance_min_rise
capturer
clock_sense_all_stop
clock_sense_clock_source_data_stop_propagation
clock_sense_clock_stop_propagation
clock_sense_data_stop_propagation
clock_sense_logical_stop_propagation
clock_sense_negative
clock_sense_positive
clock_sense_stop_propagation
clock_sources_inverted
clock_sources_non_inverted
clocks
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Analysis Attributes--hpin Attributes for Analysis
connect_delay
delay_max_fall
delay_max_rise
delay_min_fall
delay_min_rise
dont_touch_file
dont_touch_reason
drivers
endpoint
exceptions
external_net_wire_capacitance
generates_clocks
hinst
hnet
hport
is_clock_gating_pin
is_clock_used_as_clock
is_clock_used_as_data
is_physical
launcher
lib_pins
loads
net
pg_hnet
pg_net
propagated_clocks
propagated_ideal_network
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Analysis Attributes--hpin Attributes for Analysis
rf_slack
slack_max
slack_max_edge
slack_max_fall
slack_max_rise
slew
slew_by_mode
startpoint
timing_arcs
timing_case_computed_value
timing_info
timing_info_favor_startpoint
wire_capacitance
wire_length
wire_resistance
wireload_model
arrival_max_fall
arrival_max_fall delay
Read-only hpin attribute. Returns the fall delay applied for setup analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
arrival_max_rise
arrival_max_rise delay
Read-only hpin attribute. Returns the rise delay applied for setup analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
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Analysis Attributes--hpin Attributes for Analysis
vls command by default.
arrival_min_fall
arrival_min_fall delay
Read-only hpin attribute. Returns the fall delay applied for hold analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Genus does not support hold analysis.
arrival_min_rise
arrival_min_rise delay
Read-only hpin attribute. Returns the rise delay applied for hold analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Genus does not support hold analysis.
arrival_window
arrival_window string
Read-only hpin attribute.Returns a tcl list of min/max/max rise/fall arrival times through that pin with
respect to each and every clock.
boundary_optimize_hpin_invertible
boundary_optimize_hpin_invertible {true | false}
Read-only hpin attribute. Indicates whether the pin can be inverted during boundary optimization.
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Analysis Attributes--hpin Attributes for Analysis
Preserved pins, pins of preserved nets, and pins of preserved instances are not invertible. In
addition, there are internal restrictions (such as multibit ports/busses, pins with timing exceptions or
pins were a clock is defined on) that do not allow inversion of a pin.
This attribute is set to false for pins that are not hierarchical boundary pins.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affected by these attributes: (hpin) boundary_optimize_invert_hpins
(module) boundary_optimize_invert_hpins
(root) boundary_optimize_invert_hpins
Related attributes: (hport) boundary_optimize_hpin_invertible
capacitance_max_fall
capacitance_max_fall max_cap
Read-only hpin attribute. Returns the maximum capacitance of the net driving this pin for a fall
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related attributes: (constant) capacitance_max_fall
(hport) capacitance_max_fall
(pin) capacitance_max_fall
(port) capacitance_max_fall
capacitance_max_rise
capacitance_max_rise max_cap
Read-only hpin attribute. Returns the maximum capacitance of the net driving this pin for a rise
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related attributes: (constant) capacitance_max_rise
(hport) capacitance_max_rise
(pin) capacitance_max_rise
(port) capacitance_max_rise
capacitance_min_fall
capacitance_min_fall min_cap
Read-only hpin attribute. Returns the minimum capacitance of the net driving this pin for a fall
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related attributes: (constant) capacitance_min_fall
(hport) capacitance_min_fall
(pin) capacitance_min_fall
(port) capacitance_min_fall
capacitance_min_rise
capacitance_min_rise min_cap
Read-only hpin attribute. Returns the minimum capacitance of the net driving this pin for a rise
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related attributes: (constant) capacitance_min_rise
(hport) capacitance_min_rise
(pin) capacitance_min_rise
(port) capacitance_min_rise
capturer
capturer {true | false}
Read-only hpin attribute. Indicates if the pin’s required time was derived through static analysis
from a setup check (false) or user-defined output delay constraint (true). This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related command: report_timing
Related attributes: (pin) capturer
(port) capturer
clock_sense_all_stop
clock_sense_all_stop clock+
Read-only hpin attribute. Returns the pins that stop propagate data, data out and clock.
Related Information
Set by this command: set_clock_sense -type all
clock_sense_clock_source_data_stop_propagation
clock_sense_clock_source_data_stop_propagation clock+
Read-only hpin attribute. Returns the pins that stop data out from propagation.
Related Information
Set by this command: set_clock_sense -type clock_source_data
clock_sense_clock_stop_propagation
clock_sense_clock_source_data_stop_propagation clock+
Read-only hpin attribute. Returns the pins that stop data out from propagation.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Set by this command: set_clock_sense -type clock
clock_sense_data_stop_propagation
clock_sense_data_stop_propagation clock+
Read-only hpin attribute. Returns the pins that stop data launched by clocks for propagation.
Related Information
Set by this command: set_clock_sense -type data
clock_sense_logical_stop_propagation
clock_sense_logical_stop_propagation {hpin | pin | constant | pg_pin | hport | port} ...
Read-only hpin attribute. Returns the clocks whose propagation is stopped at this pin.
clock_sense_negative
clock_sense_negative clock...
Read-only hpin attribute. Returns the clocks that are propagated with a negative clock sense at this
pin.
March 2025 1172 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--hpin Attributes for Analysis
Related Information
Set by this command: set_clock_sense -negative
Related attributes: (clock) clock_sense_negative
(pin) clock_sense_negative
(hpin) clock_sense_positive
(hpin) clock_sense_stop_propagation
clock_sense_positive
clock_sense_positive clock...
Read-only hpin attribute. Returns the clocks that are propagated with a positive clock sense at this
pin.
Related Information
Set by this command: set_clock_sense -positive
Related attributes: (hpin) clock_sense_positive
(pin) clock_sense_positive
(hpin) clock_sense_negative
(hpin) clock_sense_stop_propagation
clock_sense_stop_propagation
clock_sense_stop_propagation clock...
Read-only hpin attribute. Returns the clocks that stop propagatiing at this pin.
March 2025 1173 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--hpin Attributes for Analysis
Related Information
Set by this command: set_clock_sense -stop_propagation
Related attributes: (clock) clock_sense_stop_propagation
(pin) clock_sense_stop_propagation
(hpin) clock_sense_negative
(hpin) clock_sense_positive
clock_sources_inverted
clock_sources_inverted string
Read-only hpin attribute. Returns a Tcl list of clock objects that were applied in the inverted sense
to the specified pin.
Related Information
Related attributes (pin) clock_sources_inverted
(port) clock_sources_inverted
inverted_sources
clock_sources_non_inverted
clock_sources_non_inverted string
Read-only hpin attribute. Returns a Tcl list of clock objects that were applied in the non-inverted
sense to the specified pin or port.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related attributes (pin) clock_sources_non_inverted
(port) clock_sources_non_inverted
non_inverted_sources
clocks
clocks list_of_clocks
Read-only hpin attribute. Returns a list of clocks arriving at this pin. This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
Related Information
Related attributes: (pin) clocks
(port) clocks
connect_delay
connect_delay { {no_value no_value} | {float float}}
Read-only hpin attribute. Returns the rise and fall connect delay to this pin in picoseconds.
Resolution is 1. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attributes: (pin) connect_delay
(port) connect_delay
March 2025 1175 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--hpin Attributes for Analysis
delay_max_fall
delay_max_fall delay
Read-only hpin attribute. Returns the maximum delay (in picoseconds) set with the set_max_delay
command for a falling edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
Related Information
Related attributes: (clock) delay_max_fall
(pin) delay_max_fall
(port) delay_max_fall
delay_max_rise
delay_max_rise delay
Read-only hpin attribute. Returns the maximum delay (in picoseconds) set with the set_max_delay
command for a rising edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
Related Information
Related attributes: (clock) delay_max_rise
(pin) delay_max_rise
(port) delay_max_rise
delay_min_fall
delay_min_fall delay
Read-only hpin attribute. Returns the minimum delay (in picoseconds) set with the set_min_delay
March 2025 1176 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--hpin Attributes for Analysis
command for a falling edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
This delay is not supported by Genus.
Related Information
Related attributes: (clock) delay_min_fall
(pin) delay_min_fall
(port) delay_min_fall
delay_min_rise
delay_min_rise delay
Read-only hpin attribute. Returns the minimum delay (in picoseconds) set with the set_min_delay
command for a rising edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
This delay is not supported by Genus.
Related Information
Related attributes: (clock) delay_min_rise
(pin) delay_min_rise
(port) delay_min_rise
dont_touch_file
dont_touch_file string
Read-write hpin attribute. Specify to set the sourced file as dont_touch.
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Analysis Attributes--hpin Attributes for Analysis
dont_touch_reason
dont_touch_reason list_of_delay_corners
Read-write hpin attribute. Specify the reason for setting the sourced file as dont_touch.
drivers
drivers {constant | pin | port | hport}
Read-only hpin attribute. Returns the drivers for the pin.
Related Information
Related attributes: (hnet) drivers
(hport) drivers
(net) driver_pins
(pg_pin) drivers
endpoint
endpoint {true | false}
Read-only hpin attribute. Indicates if the pin is the endpoint of a timing path. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related command: report_timing
Related attributes: (pin) endpoint
(port) endpoint
(timing_path) endpoint
exceptions
exceptions string
Read-only hpin attribute. Returns a list of all the timing exceptions that were applied to the
specified pin.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
Related attributes: (clock) exceptions
(cost_group) exceptions
(external_delay) exceptions
(hinst) exceptions
(inst) exceptions
(pin) exceptions
(port) exceptions
(timin_path) exceptions
external_net_wire_capacitance
external_net_wire_capacitance {no_value | float}
Read-only hpin attribute. Returns the external wire capacitance (in femtofarad) seen at this hpin.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related attributes: (constant) external_net_wire_capacitance
(hport) external_net_wire_capacitance
(pin) external_net_wire_capacitance
(port) external_net_wire_capacitance
generates_clocks
generates_clocks clock_list
Read-only hpin attribute. Returns the clock objects that were generated from this hierarchical pin
using the create_generated_clock command.
Related Information
Related attributes (pin) generates_clocks
(port) generates_clocks
hinst
hinst hinst
Read-only hpin attribute. Returns the hierarchical instance that the hpin belongs to.
March 2025 1181 Product Version 23.1
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related attributes: (constant)) hinst
(hinst) hinst
(hnet) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
(pg_pin) hinst
hnet
hnet hnet
Read-only hpin attribute. Returns the hierarchical net connected to this hpin.
Related Information
Related attributes: (hport) hnet
(pin) hnet
(port) hnet
(pg_pin) hnet
hport
hport hport
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Analysis Attributes--hpin Attributes for Analysis
Read-only hpin attribute. Returns the hierarchical port associated with this hpin.
is_clock_gating_pin
is_clock_gating_pin {false | true}
Read-only hpin attribute. Indicates whether this pin is the input pin of a clock-gating cell.
Related Information
Related attribute: (pin) is_clock_gating_pin
is_clock_used_as_clock
is_clock_used_as_clock {false | true}
Read-only hpin attribute. Indicates whether this pin is a through-pin in the clock network and at
least one of the clocks arriving at the port is used as a clock in the downstream network of the port.
Related Information
Set by this command: set_max_transition
Related attributes: (pin) is_clock_used_as_clock
(port) is_clock_used_as_clock
is_clock_used_as_data
is_clock_used_as_data {false | true}
Read-only hpin attribute. Indicates whether this pin is a through-pin in the clock network and at
least one of the clocks arriving at the port is used as data in the downstream network of the port.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Set by this command: set_max_transition
Related attributes: (pin) is_clock_used_as_data
(port) is_clock_used_as_data
is_physical
is_physical {false | true}
Read-only hpin attribute. Indicates if the hierarchical pin is a physical pin.
Related Information
Related attributes: (hinst) is_physical
(inst) is_physical
(pg_pin) is_physical
(pin) is_physical
launcher
launcher {true | false}
Read-only hpin attribute. Indicates if the arrival time at this pin was derived through static analysis
from a clock signal arriving at an edge-triggered or level-sensitive point, or from a user-defined input
delay. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related command: report_timing
Related attributes: (pin) launcher
(port) launcher
lib_pins
lib_pins {lib_pin | pg_lib_pin}
Read-only hpin attribute. Returns the library base_pin associated with a pin of a mapped instance.
Related Information
Related attributes: (pin) lib_pins
(port) lib_pins
loads
loads list_of_pins
Read-only hpin attribute. Returns the hierarchical path to the pins or ports loading this pin.
Related Information
Related attributes: (hnet) loads
(hport) loads
(net) load_pins
(pg_pin) loads
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Analysis Attributes--hpin Attributes for Analysis
net
net string
Read-only hpin attribute. Returns the net connected to the hpin.
Related Information
Related attributes: (hnet) net
(hport) net
(pin) net
(pg_pin) net
(port) net
pg_hnet
pg_hnet string
Read-only hpin attribute. Returns the pg_hnet connected to the hpin.
Related Information
Related attributes: (hport) pg_hnet
(pin) pg_hnet
(pg_pin) pg_hnet
(port) pg_hnet
pg_net
pg_net string
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Analysis Attributes--hpin Attributes for Analysis
Read-only hpin attribute. Returns the pg_net connected to the hpin.
Related Information
Related attributes: (hport) pg_net
(pin) pg_net
(pg_pin) pg_net
(port) pg_net
propagated_clocks
propagated_clocks pin_name
Read-only hpin attribute. Returns a Tcl list of clock information that has propagated to the specified
pin. Each element of the list contains information about a single clock that was propagated.
The clock information contained in the Tcl list can be easily converted into an associative array
using the Tcl command array get. This provides a convenient method to query for information
about propagated clocks in a design. The keys of the associative array are:
clock — The clock object that has been propagated.
phase — A string value indicating whether the clock has been inverted ("+" or "-").
clock_source_late_latency — A Tcl list containing any source latency values that have been
picked up from the clock_source_late_latency attribute on pins or ports in the clock network.
This does not include latency values from the clock object itself.
clock_network_late_latency — A Tcl list containing any network latency values that have
been picked up from the clock_network_late_latency attribute on pins or ports in the clock
network. This does not include latency values from the clock object itself.
clock_setup_uncertainty — A Tcl list containing any uncertainty values that have been
picked up from the clock_setup_uncertainty attribute on pins or ports in the clock network.
This does not include uncertainty values from the clock object itself.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_design -innovus
write_sdc
Related commands: read_sdc
Related attributes: (pin) propagated_clocks
(port) propagated_clocks
disabled_arcs
external_delays
propagated_ideal_network
propagated_ideal_network {true | false }
Read-only hpin attribute. Indicates whether the specified pin is ideal. Specifically, the attribute
checks whether the specified pin is in the fanout of another pin with the ideal_network attribute set
to true.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Propagation Rules
The propagation of the ideal_network attribute follows these rules:
A pin is treated as ideal if it is either a:
Pin specified in the object list of the ideal_network attribute.
Driver pin and its cell is ideal.
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Analysis Attributes--hpin Attributes for Analysis
Load pin attached to an ideal net.
A net is treated as ideal if all its driving cells are ideal.
A combinational cell is treated as ideal if all its input pins are ideal.
A hierarchical pin can propagate the ideal_network attribute.
Propagation stops at the pins where these conditions are not met. These pins are referred to as
network boundary pins, and they are ideal pins.
Related Information
Affected by these attributes: (pin) ideal_network
(port) ideal_network
Related attribute: (pin) propagated_ideal_network
rf_slack
rf_slack rise fall
Read-only hpin attribute. Returns the slack for the rising and falling edges in picoseconds. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Information
Related attributes: (pin) rf_slack
slack_max
slack_max {no_value | float}
Read-only hpin attribute. Returns the maximum slack of the hpin in picoseconds. The resolution is
1. This is a computed attribute. Computed attributes are potentially very time consuming to process
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Analysis Attributes--hpin Attributes for Analysis
and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attributes: (pin) slack_max
(port) slack_max
slack_max_edge
slack_max_edge string
Read-only hpin attribute. Returns the edge (rise or fall) of the worst slack-causing path at this hpin
in late mode.in picoseconds. The resolution is 1. This is a computed attribute. Computed attributes
are potentially very time consuming to process and not listed by the vls command by default.
Related Information
Related attribute: (pin) slack_max_edge
(port) slack_max_edge
slack_max_fall
slack_max_fall {no_value | float}
Read-only hpin attribute. Returns the maximum falling slack of the hpin in picoseconds. The
resolution is 1. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related command: report_timing
Related attributes: (pin) slack_max_fall
(port) slack_max_fall
slack_max_rise
slack_max_rise {no_value | float}
Read-only hpin attribute. Returns the maximum rising slack of the hpin in picoseconds. The
resolution is 1. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attributes: (port) slack_max_rise
slew
slew {rise fall}
Read-only hpin attribute. Returns the computed rise and fall slew values, respectively, in
picoseconds. The values are returned as a Tcl list.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attributes: (pin) slew
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Analysis Attributes--hpin Attributes for Analysis
slew_by_mode
slew_by_mode {{mode_name_1 rise fall} [{mode_name_2 rise fall}]...}
Read-only hpin attribute. Returns a Tcl list of lists. Each list contains the mode name followed by
the computed rise and fall slew values for the pin for that mode, in picoseconds.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attributes: (pin) slew_by_mode
(port) slew_by_mode
startpoint
startpoint {true | false}
Read-only hpin attribute. Indicates if the pin is the startpoint of a timing path. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Related Information
Related command: report_timing
Related attributes: (pin) startpoint
(port) startpoint
timing_arcs
timing_arcs string
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Analysis Attributes--hpin Attributes for Analysis
Read-only hpin attribute. Returns the timing arcs to this pin. This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
Related Information
Related command: report_timing
Related attributes: (pin) timing_arcs
timing_case_computed_value
timing_case_computed_value {0 | 1 | no_value}
Read-only hpin attribute. Indicates if the value of this pin was computed to have a constant logic
value. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_design -innovus
write_sdc
Related commands: read_sdc
Related attributes: (pin) timing_case_computed_value
(port) timing_case_computed_value
(hpin) timing_case_computed_value
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Analysis Attributes--hpin Attributes for Analysis
timing_info
timing_info string
Read-only hpin attribute. Returns a Tcl list containing other Tcl lists about timing path information.
If the pin is both a timing startpoint and an endpoint, then this attribute returns information from the
endpoint.The outer Tcl list corresponds to a set of timing paths that share a common set of
launching clock edge, capturing clock edge, and timing exceptions that are being applied. The
inner Tcl lists correspond to name/value pairs that provide information about that particular set of
timing paths. The ted name/value pairs are:
name: launch
value: A Tcl list containing a clock object and a R or F character that indicates whether the
launching clock edge is the rising or falling edge of the clock waveform. If the launch was not
relative to a particular clock, for example at a register with no clock waveform, then unclocked
is the value.
name: capture
value: A Tcl list containing a clock object and a R or F character that indicates whether the
capturing clock edge is the rising or falling edge of the clock waveform. If the capture was not
relative to a particular clock, for example at a register with no clock waveform, then unclocked
is the value.
name: cost_group
value: The cost_group object that this particular set of timing paths is being applied to.
Unconstrained paths are always applied to the default cost group.
name: exceptions
value: A Tcl list of exception objects that are being applied to the timing paths. The list is
empty if no timing exceptions are being applied.
name: mode
value: The mode object that the set of paths belong to. This value is provided only in the
presence of multi-mode constraints.
name: constraint
value: The timing constraint value for this set of paths is in picoseconds. If the paths are
unconstrained, then the value is listed as no_value.
name: slack
value: A Tcl list containing the worst timing slack for this set of paths for rising and falling
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Analysis Attributes--hpin Attributes for Analysis
transitions at the pin. The values are in picoseconds. If a particular transition is unconstrained,
then the value is listed as no_value.
name: input_delay
value: A Tcl list containing the input delays in picoseconds for the rising and falling worst-
slack paths. The values are in picoseconds. If a particular input delay is not valid, then the
value is listed as no_value.
name: output_delay
value: A Tcl list containing the output delays in picoseconds for the rising and falling worst-
slack paths. The values are in picoseconds. If a particular output path is not valid, then the
value is listed as no_value.
For certain pins in the design, the timer has two sets of path information. These are pins that are
both timing startpoints and also timing endpoints. The and attributes can be used to locate such
pins, but these are typically clock inputs of sequential cells, D pins of latches, or pins at which
timing paths have been broken using the attribute. At these special pins the timing_info attribute
will return information about the paths ending at that particular pin. To query about the paths that
start at the particular pin instead, use the attribute. At pins and ports in the design that are not both
timing startpoints and endpoints, the timing_info and the timing_info_favor_startpoint attributes
return the same information.
Related Information
Related command: report_timing
Related attributes: (pin) timing_info
(port) timing_info
(hpin) timing_info_favor_startpoint
timing_info_favor_startpoint
timing_info_favor_startpoint Tcl_list
Read-only hpin attribute. Returns a Tcl list of information about timing paths. If the pin is both a
timing startpoint and an endpoint, then this attribute returns information from the startpoint.
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Analysis Attributes--hpin Attributes for Analysis
Related Information
Related command: report_timing
Related attributes: (pin) timing_info_favor_startpoint
(port) timing_info_favor_startpoint
(hpin) timing_info
wire_capacitance
wire_capacitance {no_value | float}
Read-only hpin attribute. Returns the net capacitance for the pin in femtofarads. Resolution is 1/10.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related attributes: (constant) wire_capacitance
(hport) wire_capacitance
(pin) wire_capacitance
(port) wire_capacitance
wire_length
wire_length {no_value | float}
Read-only hpin attribute. Returns the wire length of the net connected to the pin. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
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Related Information
Related attributes: (constant) wire_length
(hport) wire_length
(pin) wire_length
(port) wire_length
wire_resistance
wire_resistance {no_value | float}
Read-only hpin attribute. Returns the net resistance for the pin in kilohms. Resolution is 1/1000.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related attributes: (constant) wire_resistance
(hport) wire_resistance
(pin) wire_resistance
(port) wire_resistance
wireload_model
wireload_model string
Read-only hpin attribute. Retrieves the wire-load model of the parent module. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
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Analysis Attributes--hpin_bus Attributes in Analysis
Related Information
Related attribute: (pin) wireload_model
hpin_bus Attributes in Analysis
bits
hinst
hport_bus
bits
bits string
Read-only hpin_bus attribute. Returns a list of individual bits that constitute the hport bus. This list
includes the full pathnames of each individual hport object.
Related Information
Related attributes: (hport_bus) bits
(port_bus) bits
hinst
hinst
Read-only hpin_bus attribute. Returns the hierarchical instance that the hpin_bus belongs.
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Analysis Attributes--hport Attributes for Analysis
Related Information
Related attributes: (constant)) hinst
(hinst) hinst
(hnet) hinst
(hpin) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
(pg_pin) hinst
hport_bus
hport_bus hport_bus
Read-only hpin_bus attribute. Returns an hport bus of the hpin_bus.
hport Attributes for Analysis
boundary_optimize_hpin_invertible
bus
capacitance_max_fall
capacitance_max_rise
capacitance_min_fall
capacitance_min_rise
drivers
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Analysis Attributes--hport Attributes for Analysis
external_net_wire_capacitance
hinst
hnet
hpin
loads
net
pg_hnet
pg_net
wire_capacitance
wire_length
wire_resistance
boundary_optimize_hpin_invertible
boundary_optimize_hpin_invertible {true | false}
Read-only hport attribute. Indicates whether the hport can be inverted during boundary
optimization.
Preserved pins, pins of preserved nets, and pins of preserved modules are not invertible. In
addition, there are internal restrictions (such as multibit ports/busses, pins with timing exceptions or
pins were a clock is defined on) that do not allow inversion of a pin.
Related Information
Affects these commands: syn_generic
syn_map
syn_opt
Affected by these attributes: boundary_optimize_invert_hpins
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Analysis Attributes--hport Attributes for Analysis
bus
bus string
Read-only hport attribute. Returns the full path name of the bus object to which the hport belongs.
Related Information
Related attributes: (port) bus
capacitance_max_fall
capacitance_max_fall max_cap
Read-only hport attribute. Returns the maximum capacitance of the net driving this hport for a fall
transition on the hport. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_max_rise
capacitance_max_rise max_cap
Read-only hport attribute. Returns the maximum capacitance of the net driving this hport for a rise
transition on the hport. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_min_fall
capacitance_min_fall min_cap
Read-only hport attribute. Returns the minimum capacitance of the net driving this hport for a fall
transition on the hport. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
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Analysis Attributes--hport Attributes for Analysis
capacitance_min_rise
capacitance_min_rise min_cap
Read-only hport attribute. Returns the minimum capacitance of the net driving this hport for a rise
transition on the hport. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
drivers
drivers {constant | pin | port | hport}
Read-write hport attribute.Returns the drivers for the hport.
Related Information
Related attributes: (hnet) drivers
(hpin) drivers
(net) driver_pins
(pg_pin) drivers
external_net_wire_capacitance
external_net_wire_capacitance {no_value | float}
Read-only hport attribute. Returns the external wire capacitance (in femtofarad) seen at this hport.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
hinst
hinst hinst
Read-only hport attribute. Returns the hierarchical instance that the hport belongs to.
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Analysis Attributes--hport Attributes for Analysis
hnet
hnet hnet
Read-only hport attribute. Returns the hierarchical net connected to this hport.
hpin
hpin hpin
Read-only hport attribute. Returns the hpin of the hport.
loads
loads list_of_pins
Read-only hport attribute. Returns the hierarchical path to the pins or ports loading this hport.
Related Information
Related attributes: (hnet) loads
(hpin) loads
(net) load_pins
(pg_pin) loads
net
net string
Read-only hport attribute. Returns the name of the net connected to the hport.
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Analysis Attributes--hport Attributes for Analysis
pg_hnet
pg_hnet string
Read-only hport attribute. Returns the pg_hnet connected to the hport.
pg_net
pg_net string
Read-only hport attribute. Returns the pg_net connected to the hport.
wire_capacitance
wire_capacitance {no_value | float}
Read-only hport attribute. Returns the net capacitance for the hport in femtofarads. Resolution is
1/10. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
wire_length
wire_length {no_value | float}
Read-only hport attribute. Returns the wire length of the net connected to the hport. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
wire_resistance
wire_resistance {no_value | float}
Read-only hport attribute. Returns the net resistance for the hport in kilohms. Resolution is 1/1000.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
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Analysis Attributes--hport_bus Attributes for Analysis
hport_bus Attributes for Analysis
bits
hinst
hpin_bus
order
bits
bits string
Read-only hport_bus attribute. Returns a list of individual bits that constitute the hport bus. This list
includes the full pathnames of each individual hport object.
hinst
hinst
Read-only hport_bus attribute. Returns the hierarchical instance that the hport_bus belongs.
hpin_bus
hpin_bus
Read-only hport_bus attribute. Returns an hpin bus of the hport_bus.
order
order integer
Read-only hport_bus attribute. Returns the order of the bus in the design port declaration list, the
value of the leftmost bit being the first. The order value of the first bus is 0.
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Analysis Attributes--message_group Attribute for Analysis
Related Information
Related attribute: (port_bus) order
message_group Attribute for Analysis
is_user
is_user {true | false}
Read-only message_group attribute. Indicates if a message is user-defined or is a member of an
internal group (created by Genus). Messages created by the user have the value true while internal
group messages have the value false.
net Attributes for Analysis
constant
driver_pins
driver_ports
hinst
is_constant
is_ideal
load_pins
load_ports
num_drivers
num_loads
wire_capacitance_max
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Analysis Attributes--message_group Attribute for Analysis
constant
constant {no_constant | 0 | 1}
Default: no_constant
Read-only net attribute. Returns the type of constant that drives the net.
0 Specifies that the net is driven by a constant 0.
1 Specifies that the net is driven by a constant 1.
no_constant Specifies that the net is not driven by a constant.
driver_pins
driver_pins {pg_pin| pin}...
Read-only net attribute. Returns the hierarchical path to the leaf pins driving this net.
driver_ports
driver_ports port_list
Read-only net attribute. Returns the hierarchical path to the ports driving this net.
hinst
hinst hinst
Read-only net attribute. Returns the hierarchical instance that the net belongs to.
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Analysis Attributes--message_group Attribute for Analysis
Related Information
Related attributes: (constant)) hinst
(hinst) hinst
(hnet) hinst
(hpin) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(pg_pin) hinst
is_constant
is_constant {false | true)
Read-only net attribute. Indicates whether the net is driven by a constant.
is_ideal
is_ideal {true | false}
Read-only net attribute. Indicates whether the specified net is ideal.
Valid causes for a net being ideal are:
An ideal_driver attribute is set on a driver of the net
An ideal_network attribute is set on a driver in the fan in of the net
A clock pin for a sequential instance is on the net
A logic constant drives the net
The net is connected to a pin whose propagated_ideal_network attribute is set to true.
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Analysis Attributes--message_group Attribute for Analysis
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Affected by these attributes: (pin) ideal_driver
(port) ideal_driver
load_pins
load_pins {pg_pin | pin}...
Read-only net attribute. Returns the hierarchical path to the pins loading this net.
load_ports
load_ports port_list
Read-only net attribute. Returns the hierarchical path to the ports loading this net.
num_drivers
num_drivers integer
Read-only net attribute. Lists the number of drivers on the net.
Related Information
Related attributes: (hnet) num_drivers
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Analysis Attributes--pcell Attributes for Analysis
num_loads
num_loads integer
Read-only net attribute. Lists the number of loads on the net.
Related Information
Related attributes: (hnet) num_loads
wire_capacitance_max
wire_capacitance_max float
Read-only net attribute. Returns the wire-capacitance of a net. This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
The following command returns the wire capacitance of the net:
get_db net:test/w1 .wire_capacitance_max 0.0
Related Information
Related attributes: (pin) wire_capacitance
pcell Attributes for Analysis
base_cell
base_cell base_cell
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Analysis Attributes--pg_hnet Attributes for Analysis
Read-only pcell attribute. Returns the base_cell name of the pcell.
pg_hnet Attributes for Analysis
hinst
pg_hport
pg_hports_of_hinsts
pg_net
pins
hinst
hinst hinst
Read-only pg_hnet attribute. Returns the hierarchical instance that the pg_hnet belongs to.
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Analysis Attributes--pg_hnet Attributes for Analysis
Related Information
Related attributes: (constant) hinst
(hinst) hinst
(hnet) hinst
(hpin) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
(pg_net) hinst
(pg_pin) hinst
pg_hport
pg_hport {pg_port | pg_hport}
Read-only pg_hnet attribute. Returns pg_hport of pg_hnet.
pg_hports_of_hinsts
pg_hports_of_hinsts {pg_port | pg_hport}
Read-only pg_hnet attribute. Returns pg_hports of hierarchical instances connected to pg_hnet.
pg_net
pg_net list_of_pg_net
March 2025 1212 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hport Attributes for Analysis
Read-only pg_hnet attribute. Returns pg_net of pg_hnet.
pins
pins list_of_pins
Read-only pg_hnet attribute. Returns the pins that belong to this pg_hnet.
Related Information
Related attribute: (pg_net) pins
pg_hport Attributes for Analysis
hinst
parent_pg_hnet
pg_hnet
hinst
hinst hinst
Default: no_value
Read-only pg_hport attribute. Returns parent hinst object.
parent_pg_hnet
parent_pg_hnet
Read-only pg_hport attribute. Returns the parent pg_hnet of the pg_hport.
March 2025 1213 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_net Attributes for Analysis
pg_hnet
pg_hnet pg_hnet
Read-only pg_hport attribute. Returns pg_hnet of pg_hport.
pg_net Attributes for Analysis
hinst
inst
pins
sub_pg_nets
upper_pg_net
hinst
hinst hinst
Read-only pg_net attribute. Returns the hierarchical instance that the pg_net belongs to.
March 2025 1214 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_net Attributes for Analysis
Related Information
Related attributes: (constant) hinst
(hinst) hinst
(hnet) hinst
(hpin) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
(pg_hnet) hinst
(pg_pin) hinst
inst
inst inst
Read-only pg_net attribute. Returns the instance that this pg_net belongs to.
Related Information
Related attribute: (pg_pin) inst
(pin) inst
pins
pins list_of_pins
March 2025 1215 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_pin Attributes for Analysis
Read-only pg_net attribute. Returns the pins that are connected to this this pg_net.
Related Information
Related attribute: (pg_hnet) pins
sub_pg_nets
sub_pg_nets list_of_pg_nets
Read-only pg_net attribute. Returns the list of all segments of this pg_net in the lower scopes.
upper_pg_net
upper_pg_net pg_net
Read-only pg_net attribute. Returns the segment of the pg_net in the upper scope.
pg_pin Attributes for Analysis
base_pin
drivers
hinst
hnet
inst
is_async
is_data
is_physical
is_std_cell_main_rail
loads
March 2025 1216 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_pin Attributes for Analysis
net
pg_hnet
pg_net
pg_type
physical
base_pin
base_pin base_pin
Read-only pg_pin attribute. Returns the base_pin associated with the pin of the mapped instance.
Related Information
Related attributes: (pin) base_pin
drivers
drivers {constant | pin | port | hport}
Read-only pg_pin attribute. Returns the drivers for the pg_pin.
Related Information
Related attributes: (hnet) drivers
(hpin) drivers
(hport) drivers
(net) driver_pins
March 2025 1217 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_pin Attributes for Analysis
hinst
hinst hinst
Read-only pg_pin attribute. Returns the hierarchical instance that the pg_pin belongs to.
Related Information
Related attributes: (constant) hinst
(hinst) hinst
(hnet) hinst
(hpin) hinst
(hpin_bus) hinst
(hport) hinst
(hport_bus) hinst
(inst) hinst
(net) hinst
hnet
hnet hnet
Read-only pg_pin attribute. Returns the hierarchical net connected to this pg_pin.
March 2025 1218 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_pin Attributes for Analysis
Related Information
Related attributes: (hpin) hnet
(hport) hnet
(pin) hnet
(port) hnet
inst
inst inst
Read-only pg_pin attribute. Returns the instance that this pg_pin belongs to.
Related Information
Related attribute: (pin) inst
is_async
is_async {false| true}
Read-only pg_pin attribute. Indicates whether this pin is an asynchronous pin.
Related Information
Related attribute: (pin) is_async
is_data
is_data {false| true}
Read-only pg_pin attribute. Indicates whether this pin is a data pin.
March 2025 1219 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_pin Attributes for Analysis
Related Information
Related attribute: (pin) is_data
is_physical
is_physical {false | true}
Read-only pg_pin attribute. Indicates whether this pgpin is a pure physical pin or not. Pure physical
pins are only defined in the LEF library.
Related Information
Related attributes: (hinst) is_physical
(hpin) is_physical
(inst) is_physical
(pin) is_physical
is_std_cell_main_rail
is_std_cell_main_rail {false | true}
Read-only pg_pin attribute. Indicates whether this power pin is a primary power pin on the main
rail.
loads
loads list_of_pins
Read-only pg_pin attribute. Returns the hierarchical path to the pins or ports loading this pg_pin.
March 2025 1220 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_pin Attributes for Analysis
Related Information
Related attributes: (hnet) loads
(hpin) loads
(hport) loads
(net) load_pins
net
net net
Read-only pg_pin attribute. Returns the net connected to the pg_pin.
Related Information
Related attributes: (hnet) net
(hpin) net
(hport) net
(pin) net
(port) net
pg_hnet
pg_hnet pg_hnet
Read-only pg_pin attribute. Returns the pg_hnet connected to the pg_pin.
March 2025 1221 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_pin Attributes for Analysis
Related Information
Related attributes: (hpin) pg_hnet
(hport) pg_hnet
(pin) pg_hnet
(port) pg_net
pg_net
pg_net pg_net
Read-only pg_pin attribute. Returns the pg_net connected to the pg_pin.
Related Information
Related attributes: (hpin) pg_net
(hport) pg_net
(pin) pg_net
(port) pg_net
pg_type
pg_type pg_type
Read-only pg_pin attribute. Returns the pg_type (power or ground) of the pg_pin.
physical
physical {false | true}
Read-only pg_pin attribute. Indicates whether this pgpin is a pure physical pin or not. Pure physical
March 2025 1222 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
pins are only defined in the LEF library.
Related Information
Related attribute: (pin) physical
pg_hnet
pg_hnet pg_hnet
Read-only pg_port attribute. Returns pg_hnet of pg_hport.
pin Attributes for Analysis
arrival_max_fall
arrival_max_rise
arrival_min_fall
arrival_min_rise
arrival_window
base_pin
bus
capacitance_max_fall
capacitance_max_rise
capacitance_min_fall
capacitance_min_rise
capturer
clock_sense_all_stop
March 2025 1223 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
clock_sense_clock_source_data_stop_propagation
clock_sense_clock_stop_propagation
clock_sense_data_stop_propagation
clock_sense_logical_stop_propagation
clock_sense_negative
clock_sense_positive
clock_sense_stop_propagation
clock_sources_inverted
clock_sources_non_inverted
clocks
connect_delay
delay_max_fall
delay_max_rise
delay_min_fall
delay_min_rise
dont_touch_file
dont_touch_reason
endpoint
exceptions
external_net_wire_capacitance
generates_clocks
hnet
inst
is_async
is_clock
is_clock_gating_pin
is_clock_used_as_clock
March 2025 1224 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
is_clock_used_as_data
is_data
is_physical
launcher
lib_pins
net
pg_hnet
pg_net
physical
propagated_clocks
propagated_ideal_network
rf_slack
slack_max
slack_max_edge
slack_max_fall
slack_max_rise
slew
slew_by_mode
startpoint
timing_arcs
timing_case_computed_value
timing_info
timing_info_favor_startpoint
wire_capacitance
wire_length
wire_resistance
wireload_model
March 2025 1225 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
arrival_max_fall
arrival_max_fall delay
Read-only pin attribute. Returns the fall delay applied for setup analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
arrival_max_rise
arrival_max_rise delay
Read-only pin attribute. Returns the rise delay applied for setup analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
arrival_min_fall
arrival_min_fall delay
Read-only pin attribute. Returns the fall delay applied for hold analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Genus does not support hold analysis.
arrival_min_rise
arrival_min_rise delay
Read-only pin attribute. Returns the rise delay applied for hold analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Genus does not support hold analysis.
March 2025 1226 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
arrival_window
arrival_window string
Read-only pin attribute. Returns a tcl list of min/max/max rise/fall arrival times through that pin with
respect to each and every clock.
base_pin
base_pin base_pin
Read-only pin attribute. Returns the base_pin associated with the pin of the mapped instance.
Related Information
Related attribute: (pg_pin) base_pin
bus
bus string
Read-only pin attribute. Returns the full path name of the bus object to which the port belongs.
capacitance_max_fall
capacitance_max_fall max_cap
Read-only pin attribute. Returns the maximum capacitance of the net driving this pin for a fall
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_max_rise
capacitance_max_rise max_cap
March 2025 1227 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Read-only pin attribute. Returns the maximum capacitance of the net driving this pin for a rise
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_min_fall
capacitance_min_fall min_cap
Read-only pin attribute. Returns the minimum capacitance of the net driving this pin for a fall
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_min_rise
capacitance_min_rise min_cap
Read-only pin attribute. Returns the minimum capacitance of the net driving this pin for a rise
transition on the pin. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capturer
capturer {true | false}
Read-only pin attribute. Indicates if the pin’s required time was derived through static analysis from
a setup check (false) or user-defined output delay constraint (true). This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
Related Information
Related command: report_timing
March 2025 1228 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
clock_sense_all_stop
clock_sense_all_stop clock+
Read-only pin attribute. Returns the pins that stop propagate data, data out and clock.
Related Information
Set by this command: set_clock_sense -type all
clock_sense_clock_source_data_stop_propagation
clock_sense_clock_source_data_stop_propagation clock+
Read-only pin attribute. Returns the pins that stop data out from propagation.
Related Information
Set by this command: set_clock_sense -type clock_source_data
clock_sense_clock_stop_propagation
clock_sense_clock_source_data_stop_propagation clock+
Read-only pin attribute. Returns the pins that stop data out from propagation.
Related Information
Set by this command: set_clock_sense -type clock
March 2025 1229 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
clock_sense_data_stop_propagation
clock_sense_data_stop_propagation clock+
Read-only pin attribute. Returns the clocks that stop data launched by clocks for propagation.
Related Information
Set by this command: set_clock_sense -type data
clock_sense_logical_stop_propagation
clock_sense_logical_stop_propagation {hpin|pin|constant|pg_pin|hport|port}...
Read-only pin attribute. Returns the clocks whose propagation is stopped at this pin.
clock_sense_negative
clock_sense_negative clock...
Read-only pin attribute. Returns the clocks that are propagated with a negative clock sense at this
pin.
Related Information
Set by this command: set_clock_sense -negative
Related attributes: (pin) clock_sense_positive
(pin) clock_sense_stop_propagation
clock_sense_positive
clock_sense_positive clock...
March 2025 1230 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Read-only pin attribute. Returns the clocks that are propagated with a positive clock sense at this
pin.
Related Information
Set by this command: set_clock_sense -positive
Related attributes: (pin) clock_sense_negative
(pin) clock_sense_stop_propagation
clock_sense_stop_propagation
clock_sense_stop_propagation clock...
Read-only pin attribute. Returns the clocks that stop propagatiing at this pin.
Related Information
Set by this command: set_clock_sense -stop_propagation
Related attributes: (pin) clock_sense_negative
(pin) clock_sense_positive
clock_sources_inverted
clock_sources_inverted string
Read-only pin attribute. Returns a Tcl list of clock objects that were applied in the inverted sense to
the specified pin.
March 2025 1231 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Related Information
Related attributes: (pin) clock_sources_non_inverted
inverted_sources
clock_sources_non_inverted
clock_sources_non_inverted string
Read-only pin attribute. Returns a Tcl list of clock objects that were applied in the non-inverted
sense to the specified pin or port.
Related Information
Related attributes: (pin) clock_sources_inverted
non_inverted_sources
clocks
clocks list_of_clocks
Read-only pin attribute. Returns a list of clocks arriving at this pin. This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
Example
Consider the following capture clock path:
#---------------------------------------------------------------------------------------------------
--------------------------
# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay
Arrival Instance
# (fF) (ps) (ps) (ps) Location
March 2025 1232 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
#---------------------------------------------------------------------------------------------------
--------------------------
in1 (i) - R (arrival) 3 0.0 200000 0 0 (-,-)
buf2/Y (i,m) A->Y R BUF_X3M_A12TS_C35 2 0.0 0 8418 8418 (-,-)
and1/Y (i,m) B->Y R AND2_X1M_A12TS_C35 8 0.0 0 10 8428 (-,-)
scenario3_user_disble_check_at_D_pin/CK <<< - R SDFFRPQ_X1M_A12TS_C35 8 -
0 0 8428 (-,-)
#---------------------------------------------------------------------------------------------------
--------------------------
connect_delay
connect_delay { {no_value no_value} | {float float}}
Read-only pin attribute. Returns the rise and fall connect delay to this pin in picoseconds.
Resolution is 1. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
delay_max_fall
delay_max_fall delay
Read-only pin attribute. Returns the maximum delay (in picoseconds) set with the set_max_delay
command for a falling edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
delay_max_rise
delay_max_rise delay
March 2025 1233 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Read-only pin attribute. Returns the maximum delay (in picoseconds) set with the set_max_delay
command for a rising edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
Related Information
delay_min_fall
delay_min_fall delay
Read-only pin attribute. Returns the minimum delay (in picoseconds) set with the set_min_delay
command for a falling edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
This delay is not supported by Genus.
delay_min_rise
delay_min_rise delay
Read-only pin attribute. Returns the minimum delay (in picoseconds) set with the set_min_delay
command for a rising edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
This delay is not supported by Genus.
dont_touch_file
dont_touch_file string
Read-write pin attribute. Specify to set the sourced file as dont_touch.
March 2025 1234 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
dont_touch_reason
dont_touch_reason list_of_delay_corners
Read-write pin attribute. Specify the reason for setting the sourced file as dont_touch.
endpoint
endpoint {true | false}
Read-only pin attribute. Indicates if the pin is the endpoint of a timing path. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Related Information
Related command: report_timing
exceptions
exceptions string
Read-only pin attribute. Returns a list of all the timing exceptions that were applied to the specified
pin.
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
March 2025 1235 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
external_net_wire_capacitance
external_net_wire_capacitance {no_value | float}
Read-only pin attribute. Returns the external wire capacitance (in femtofarad) seen at this pin. This
is a computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
generates_clocks
generates_clocks clock_list
Read-only pin attribute. Returns the clock objects that were generated from this pin using the
create_generated_clock command.
hnet
hnet hnet
Read-only pin attribute.Returns the hierarchical net connected to this pin.
inst
inst inst
Read-only pin attribute. Returns the instance that this pin belongs to.
is_async
is_async {false| true}
Read-only pin attribute. Indicates whether this pin is an asynchronous pin.
March 2025 1236 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Related Information
Related attribute: (pg_pin) is_async
is_clock
is_clock {false | true}
Read-only pin attribute. Indicates whether this pin is a clock pin.
is_clock_gating_pin
is_clock_gating_pin {false | true}
Read-only pin attribute. Indicates whether this pin is the input pin of a clock-gating cell.
Related Information
Related attribute: (hpin) is_clock_gating_pin
is_clock_used_as_clock
is_clock_used_as_clock {false | true}
Read-only pin attribute. Indicates whether this pin is a through-pin in the clock network and at least
one of the clocks arriving at the port is used as a clock in the downstream network of the port.
Related Information
Set by this command: set_max_transition
March 2025 1237 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
is_clock_used_as_data
is_clock_used_as_data {false | true}
Read-only pin attribute. Indicates whether this pin is a through-pin in the clock network and at least
one of the clocks arriving at the port is used as data in the downstream network of the port.
Related Information
Set by this command: set_max_transition
is_data
is_data {false| true}
Read-only pin attribute. Indicates whether this pin is a data pin.
Related Information
Related attribute: (pg_pin) is_async
is_physical
is_physical {false | true}
Read-only pin attribute. Indicates whether this is a pure physical pin or not. Pure physical pins are
only defined in the LEF library.
launcher
launcher {true | false}
Read-only pin attribute. Indicates if the arrival time at this pin was derived through static analysis
from a clock signal arriving at an edge-triggered or level-sensitive point, or from a user-defined input
delay. This is a computed attribute. Computed attributes are potentially very time consuming to
March 2025 1238 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
process and not listed by the vls command by default.
Related Information
Related command: report_timing
lib_pins
lib_pins {lib_pin | pg_lib_pin}
Read-only pin attribute. Returns the library base_pin associated with a pin of a mapped instance.
net
net string
Read-only pin attribute. Returns the net connected to the pin.
pg_hnet
pg_hnet string
Read-only pin attribute. Returns the pg_hnet connected to the pin.
pg_net
pg_net string
Read-only pin attribute. Returns the pg_net connected to the pin.
physical
physical {false | true}
March 2025 1239 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Read-only pin attribute. Indicates whether this is a pure physical pin or not. Pure physical pins are
only defined in the LEF library.
Related Information
Related attribute: (pg_pin) physical
propagated_clocks
propagated_clocks pin_name
Read-only pin attribute. Returns a Tcl list of clock information that has propagated to the specified
pin. Each element of the list contains information about a single clock that was propagated.
The clock information contained in the Tcl list can be easily converted into an associative array
using the Tcl command array get. This provides a convenient method to query for information
about propagated clocks in a design. The keys of the associative array are:
clock — The clock object that has been propagated.
phase — A string value indicating whether the clock has been inverted ("+" or "-").
clock_source_late_latency — A Tcl list containing any source latency values that have been
picked up from the clock_source_late_latency attribute on pins or ports in the clock network.
This does not include latency values from the clock object itself.
clock_network_late_latency — A Tcl list containing any network latency values that have
been picked up from the clock_network_late_latency attribute on pins or ports in the clock
network. This does not include latency values from the clock object itself.
clock_setup_uncertainty — A Tcl list containing any uncertainty values that have been
picked up from the clock_setup_uncertainty attribute on pins or ports in the clock network.
This does not include uncertainty values from the clock object itself.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
March 2025 1240 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_design -innovus
write_sdc
Related commands: read_sdc
Related attributes: disabled_arcs
external_delays
propagated_ideal_network
propagated_ideal_network {true | false }
Read-only pin attribute. Indicates whether the specified pin is ideal. Specifically, the attribute
checks whether the specified pin is in the fanout of another pin with the ideal_network attribute set
to true.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Propagation Rules
The propagation of the ideal_network attribute follows these rules:
A pin is treated as ideal if it is either a:
Pin specified in the object list of the ideal_network attribute.
Driver pin and its cell is ideal.
Load pin attached to an ideal net.
A net is treated as ideal if all its driving cells are ideal.
March 2025 1241 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
A combinational cell is treated as ideal if all its input pins are ideal.
A hierarchical pin can propagate the ideal_network attribute.
Propagation stops at the pins where these conditions are not met. These pins are referred to as
network boundary pins, and they are ideal pins.
Related Information
Affected by these attributes: (pin) ideal_network
(port) ideal_network
rf_slack
rf_slack rise fall
Read-only pin attribute. Returns the slack for the rising and falling edges in picoseconds. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
Related Information
Related attributes: (hpin) rf_slack
slack_max
slack_max {no_value | float}
Read-only pin attribute. Returns the maximum slack of the pin in picoseconds. The resolution is 1.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
March 2025 1242 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
Related Information
Related command: report_timing
slack_max_edge
slack_max_edge string
Read-only pin attribute. Returns the edge (rise or fall) of the worst slack-causing path at this pin in
late mode.in picoseconds. The resolution is 1. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
slack_max_fall
slack_max_fall {no_value | float}
Read-only pin attribute. Returns the maximum slack for the falling transition at the pin in
picoseconds. The resolution is 1. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
slack_max_rise
slack_max_rise {no_value | float}
Read-only pin attribute. Returns the maximum rising slack of the pin in picoseconds. The
resolution is 1. This is a computed attribute. Computed attributes are potentially very time
March 2025 1243 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
slew
slew {rise fall}
Read-only pin attribute. Returns the computed rise and fall slew values, respectively, in
picoseconds. The values are returned as a Tcl list.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related command: report_timing
slew_by_mode
slew_by_mode {{mode_name_1 rise fall} [{mode_name_2 rise fall}]...}
Read-only pin attribute. Returns a Tcl list of lists. Each list contains the mode name followed by the
computed rise and fall slew values for the pin for that mode, in picoseconds.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related command: report_timing
March 2025 1244 Product Version 23.1
Genus Attribute Reference
Analysis Attributes--pg_hnet
startpoint
startpoint {true | false}
Read-only pin attribute. Indicates if the pin is the startpoint of a timing path. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Related Information
Related command: report_timing
timing_arcs
timing_arcs string
Read-only pin attribute. Returns the timing arcs to this pin. This is a computed attribute. Computed
attributes are potentially very time consuming to process and not listed by the vls command by
default.
Related Information
Related command: report_timing
timing_case_computed_value
timing_case_computed_value {0 | 1 | no_value}
Read-only pin attribute. Indicates if the value of this pin was computed to have a constant logic
value. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
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Analysis Attributes--pg_hnet
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_design -innovus
write_sdc
Related commands: read_sdc
timing_info
timing_info string
Read-only pin attribute. Returns a Tcl list containing other Tcl lists about timing path information. If
the pin is both a timing startpoint and an endpoint, then this attribute returns information from the
endpoint.The outer Tcl list corresponds to a set of timing paths that share a common set of
launching clock edge, capturing clock edge, and timing exceptions that are being applied. The
inner Tcl lists correspond to name/value pairs that provide information about that particular set of
timing paths. The ted name/value pairs are:
name: launch
value: A Tcl list containing a clock object and a R or F character that indicates whether the
launching clock edge is the rising or falling edge of the clock waveform. If the launch was not
relative to a particular clock, for example at a register with no clock waveform, then unclocked
is the value.
name: capture
value: A Tcl list containing a clock object and a R or F character that indicates whether the
capturing clock edge is the rising or falling edge of the clock waveform. If the capture was not
relative to a particular clock, for example at a register with no clock waveform, then unclocked
is the value.
name: cost_group
value: The cost_group object that this particular set of timing paths is being applied to.
Unconstrained paths are always applied to the default cost group.
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Analysis Attributes--pg_hnet
name: exceptions
value: A Tcl list of exception objects that are being applied to the timing paths. The list is
empty if no timing exceptions are being applied.
name: mode
value: The mode object that the set of paths belong to. This value is provided only in the
presence of multi-mode constraints.
name: constraint
value: The timing constraint value for this set of paths is in picoseconds. If the paths are
unconstrained, then the value is listed as no_value.
name: slack
value: A Tcl list containing the worst timing slack for this set of paths for rising and falling
transitions at the pin. The values are in picoseconds. If a particular transition is unconstrained,
then the value is listed as no_value.
name: input_delay
value: A Tcl list containing the input delays in picoseconds for the rising and falling worst-
slack paths. The values are in picoseconds. If a particular input delay is not valid, then the
value is listed as no_value.
name: output_delay
value: A Tcl list containing the output delays in picoseconds for the rising and falling worst-
slack paths. The values are in picoseconds. If a particular output path is not valid, then the
value is listed as no_value.
For certain pins in the design, the timer has two sets of path information. These are pins that are
both timing startpoints and also timing endpoints. The and attributes can be used to locate such
pins, but these are typically clock inputs of sequential cells, D pins of latches, or pins at which
timing paths have been broken using the attribute. At these special pins the timing_info attribute
will return information about the paths ending at that particular pin. To query about the paths that
start at the particular pin instead, use the attribute. At pins and ports in the design that are not both
timing startpoints and endpoints, the timing_info and the timing_info_favor_startpoint attributes
return the same information.
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Analysis Attributes--pg_hnet
Related Information
Related command: report_timing
Related attribute: (pin) timing_info_favor_startpoint
timing_info_favor_startpoint
timing_info_favor_startpoint Tcl_list
Read-only pin attribute. Returns a Tcl list of information about timing paths. If the pin is both a
timing startpoint and an endpoint, then this attribute returns information from the startpoint.
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Analysis Attributes--pg_hnet
Example
The following example finds timing startpoints of paths that are disabled by the path_disable
exception called my_disable:
# find all timing startpoints (actually launch points)
foreach p {pins ports} {
get_db $p –if {.launcher} –foreach {
set seen 0
foreach path_set [get_db $object
.timing_info_favor_startpoint] {
# collect name value pairs into an array for easier processing
array set values $path_set
# loop over all exceptions here
foreach except $values(exceptions) {
if {[string equal [file tail $except] "my_disable"]} {
# found "my_disable"
puts "startpoint $object"
set seen 1
break
}
}
if {$seen} {
# already saw my_disable here
break
}
}
}
}
}
Related Information
Related command: report_timing
Related attribute: (pin) timing_info
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Analysis Attributes--pg_hnet
wire_capacitance
wire_capacitance {no_value | float}
Read-only pin attribute. Returns the net capacitance for the pin in femtofarads. Resolution is 1/10.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
wire_length
wire_length {no_value | float}
Read-only pin attribute. Returns the wire length of the net connected to the pin. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
wire_resistance
wire_resistance {no_value | float}
Read-only pin attribute. Returns the net resistance for the pin in kilohms. Resolution is 1/1000.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
wireload_model
wireload_model string
Read-only pin attribute. Retrieves the wire-load model of the parent module. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
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Analysis Attributes--pin_bus Attributes for Analysis
pin_bus Attributes for Analysis
bits
bits string
Read-only pin_bus attribute. Returns a list of individual bits that constitute the bus. This list
includes the full pathnames of each individual hport object.
inst
inst inst
Default: no_value
Read-only pin_bus attribute. Returns parent inst object.
port Attributes for Analysis
arrival_max_fall
arrival_max_rise
arrival_min_fall
arrival_min_rise
arrival_window
bus
capacitance_max_fall
capacitance_max_rise
capacitance_min_fall
capacitance_min_rise
capturer
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Analysis Attributes--pin_bus Attributes for Analysis
clock_sources_inverted
clock_sources_non_inverted
clocks
connect_delay
delay_max_fall
delay_max_rise
delay_min_fall
delay_min_rise
endpoint
exceptions
external_net_wire_capacitance
generates_clocks
hnet
is_clock_used_as_clock
is_clock_used_as_data
launcher
lib_pins
min_port_delay
net
pg_hnet
pg_net
port_delay
propagated_clocks
slack_max
slack_max_edge
slack_max_fall
slack_max_rise
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Analysis Attributes--pin_bus Attributes for Analysis
slew_by_mode
startpoint
timing_case_computed_value
timing_info
timing_info_favor_startpoint
wire_capacitance
wire_length
wire_resistance
arrival_max_fall
arrival_max_fall delay
Read-only port attribute. Returns the fall delay applied for setup analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
arrival_max_rise
arrival_max_rise delay
Read-only port attribute. Returns the rise delay applied for setup analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
arrival_min_fall
arrival_min_fall delay
Read-only port attribute. Returns the fall delay applied for hold analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
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Analysis Attributes--pin_bus Attributes for Analysis
Genus does not support hold analysis.
arrival_min_rise
arrival_min_rise delay
Read-only port attribute. Returns the rise delay applied for hold analysis. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Genus does not support hold analysis.
arrival_window
arrival_window string
Read-only port attribute. Returns a tcl list of min/max/max rise/fall arrival times through that pin
with respect to each and every clock.
bus
bus string
Read-only port attribute. Specifies the name of the bus that this port belongs to.
Related Information
Related attributes: (hport) bus
capacitance_max_fall
capacitance_max_fall max_cap
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Analysis Attributes--pin_bus Attributes for Analysis
Read-only port attribute. Returns the maximum capacitance of the net driving this port for a fall
transition on the port. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_max_rise
capacitance_max_rise max_cap
Read-only port attribute. Returns the maximum capacitance of the net driving this port for a rise
transition on the port. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_min_fall
capacitance_min_fall min_cap
Read-only port attribute. Returns the minimum capacitance of the net driving this port for a fall
transition on the port. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capacitance_min_rise
capacitance_min_rise min_cap
Read-only port attribute. Returns the minimum capacitance of the net driving this port for a rise
transition on the port. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
capturer
capturer {true | false}
Read-only port attribute. Indicates if the pin’s required time was derived through static analysis
from a setup check (false) or user-defined output delay constraint (true). This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
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Analysis Attributes--pin_bus Attributes for Analysis
Related Information
Related command: report_timing
clock_sources_inverted
clock_sources_inverted string
Read-only port attribute. Returns a Tcl list of clock objects that were applied in the inverted sense
to the specified port.
Related Information
Related attributes: (port) clock_sources_non_inverted
inverted_sources
clock_sources_non_inverted
clock_sources_non_inverted string
Read-only port attribute. Returns a Tcl list of clock objects that were applied in the non-inverted
sense to the specified port.
Related Information
Related attributes: (port) clock_sources_inverted
inverted_sources
clocks
clocks list_of_clocks
Read-only port attribute. Returns a list of clocks arriving at this port. This is a computed attribute.
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Analysis Attributes--pin_bus Attributes for Analysis
Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
connect_delay
connect_delay {{no_value no_value}| {float float}}
Read-only port attribute. Returns the rise and fall connect delay to this port in picoseconds.
Resolution is 1. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
delay_max_fall
delay_max_fall delay
Read-only port attribute. Returns the maximum delay (in picoseconds) set with the set_max_delay
command for a falling edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
delay_max_rise
delay_max_rise delay
Read-only port attribute.Returns the maximum delay (in picoseconds) set with the set_max_delay
command for a rising edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
delay_min_fall
delay_min_fall delay
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Analysis Attributes--pin_bus Attributes for Analysis
Read-only port attribute.Returns the minimum delay (in picoseconds) set with the set_min_delay
command for a falling edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
This delay is not supported by Genus.
delay_min_rise
delay_min_rise delay
Read-only port attribute.Returns the minimum delay (in picoseconds) set with the set_min_delay
command for a rising edge at this pin. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
This delay is not supported by Genus.
endpoint
endpoint {true | false}
Read-only port attribute. Indicates if the port is the endpoint of a timing path. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Related Information
Related command: report_timing
exceptions
exceptions string
Read-only port attribute. Returns a list of all the timing exceptions that were applied to the
specified port.
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Analysis Attributes--pin_bus Attributes for Analysis
Related Information
Affected by these commands: path_adjust
path_group
set_disable_timing
set_max_delay
set_multicycle_path
external_net_wire_capacitance
external_net_wire_capacitance {no_value | float}
Read-only port attribute. Returns the external wire capacitance (in femtofarad) seen at this port.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
generates_clocks
generates_clocks clock_list
Read-only port attribute. Returns the clock objects that were generated from this port using the
create_generated_clock command.
hnet
hnet hnet
Read-only port attribute. Returns the hierarchical net connected to this port.
is_clock_used_as_clock
is_clock_used_as_clock {false | true}
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Analysis Attributes--pin_bus Attributes for Analysis
Read-only port attribute. Indicates whether this port is a through-pin in the clock network and at
least one of the clocks arriving at the port is used as a clock in the downstream network of the port.
Related Information
Set by this command: set_max_transition
Related attributes: (hpin) launcher
(pin) is_clock_used_as_clock
is_clock_used_as_data
is_clock_used_as_data {false | true}
Read-only port attribute. Indicates whether this port is a through-pin in the clock network and at
least one of the clocks arriving at the port is used as data in the downstream network of the port.
Related Information
Set by this command: set_max_transition
Related attributes: (hpin) launcher
(pin) is_clock_used_as_data
launcher
launcher {true | false}
Read-only port attribute. Indicates if the arrival time at this port was derived through static analysis
from a clock signal arriving at an edge-triggered or level-sensitive point, or from a user-defined input
delay. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
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Analysis Attributes--pin_bus Attributes for Analysis
Related Information
Related command: report_timing
lib_pins
lib_pins {lib_pin | pg_lib_pin}
Read-only port attribute. Returns the library base_pin associated with a pin of a mapped instance.
min_port_delay
min_port_delay Tcl_list
Read-only port attribute. Returns a Tcl list containing the computed rise and fall minimum delay
values, respectively, in picoseconds. This attribute is only computed if the minimum delay must be
computed for this port to honor the data-to-data timing constraints.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attribute: (port) connect_delay
net
net string
Read-only port attribute. Returns the net connected to the port.
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Analysis Attributes--pin_bus Attributes for Analysis
pg_hnet
pg_hnet string
Read-only port attribute. Returns the pg_hnet connected to the port.
pg_net
pg_net string
Read-only port attribute. Returns the pg_net connected to the port.
port_delay
port_delay {rise fall}
Read-only port attribute. Returns the rise and fall delay value in picoseconds that is attributed to
this port in picoseconds. Resolution is 1. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
Related attribute: (port) connect_delay
propagated_clocks
propagated_clocks clcok
Read-only port attribute. Returns a Tcl list of clock information that has propagated to the specified
port. Each element of the list contains information about a single clock that was propagated.
The clock information contained in the Tcl list can be easily converted into an associative array
using the Tcl command array get. This provides a convenient method to query for information
about propagated clocks in a design. The keys of the associative array are:
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Analysis Attributes--pin_bus Attributes for Analysis
clock — The clock object that has been propagated.
phase — A string value indicating whether the clock has been inverted ("+" or "-").
clock_source_late_latency — A Tcl list containing any source latency values that have been
picked up from the clock_source_late_latency attribute on pins or ports in the clock network.
This does not include latency values from the clock object itself.
clock_network_late_latency — A Tcl list containing any network latency values that have
been picked up from the clock_network_late_latency attribute on pins or ports in the clock
network. This does not include latency values from the clock object itself.
clock_setup_uncertainty — A Tcl list containing any uncertainty values that have been
picked up from the clock_setup_uncertainty attribute on pins or ports in the clock network.
This does not include uncertainty values from the clock object itself.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_design -innovus
write_sdc
Related command: read_sdc
disabled_arcs
external_delays
slack_max
slack_max {no_value | float}
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Analysis Attributes--pin_bus Attributes for Analysis
Read-only port attribute. Returns the maximum slack of the hpin in picoseconds. The resolution is
1. This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related command: report_timing
slack_max_edge
slack_max_edge string
Read-only port attribute. Returns the edge (rise or fall) of the worst slack-causing path at this hpin
in late mode.in picoseconds. The resolution is 1. This is a computed attribute. Computed attributes
are potentially very time consuming to process and not listed by the vls command by default.
slack_max_fall
slack_max_fall {no_value | float}
Read-only port attribute. Returns the maximum falling slack of the hpin in picoseconds. The
resolution is 1. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
Related Information
Related command: report_timing
slack_max_rise
slack_max_rise {no_value | float}
Read-only port attribute. Returns the maximum rising slack of the hpin in picoseconds. The
resolution is 1. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
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Analysis Attributes--pin_bus Attributes for Analysis
Related Information
Related command: report_timing
slew_by_mode
slew_by_mode {{mode_name_1 rise fall} [{mode_name_2 rise fall}]...}
Read-only port attribute. Returns a Tcl list of lists. Each list contains the mode name followed by
the computed rise and fall slew values for the port for that mode, in picoseconds.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Related command: report_timing
startpoint
startpoint {true | false}
Read-only port attribute. Indicates if the pin is the startpoint of a timing path. This is a computed
attribute. Computed attributes are potentially very time consuming to process and not listed by the
vls command by default.
Related Information
Related command: report_timing
timing_case_computed_value
timing_case_computed_value {0 | 1 | no_value}
Read-only port attribute. Indicates if the value of this port was computed to have a constant logic
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Analysis Attributes--pin_bus Attributes for Analysis
value. You can use this attribute to create a case analysis report. This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls
command by default.
Related Information
Affects these commands: report_clocks
report_qor
report_timing
write_design -innovus
write_sdc
Related commands: read_sdc
timing_info
timing_info string
Read-only port attribute. Returns a Tcl list containing other Tcl lists about timing path information.
If the port is both a timing startpoint and an endpoint, then this attribute returns information from the
endpoint.The outer Tcl list corresponds to a set of timing paths that share a common set of
launching clock edge, capturing clock edge, and timing exceptions that are being applied. The
inner Tcl lists correspond to name/value pairs that provide information about that particular set of
timing paths. The ted name/value pairs are:
name: launch
value: A Tcl list containing a clock object and a R or F character that indicates whether the
launching clock edge is the rising or falling edge of the clock waveform. If the launch was not
relative to a particular clock, for example at a register with no clock waveform, then unclocked
is the value.
name: capture
value: A Tcl list containing a clock object and a R or F character that indicates whether the
capturing clock edge is the rising or falling edge of the clock waveform. If the capture was not
relative to a particular clock, for example at a register with no clock waveform, then unclocked
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Analysis Attributes--pin_bus Attributes for Analysis
is the value.
name: cost_group
value: The cost_group object that this particular set of timing paths is being applied to.
Unconstrained paths are always applied to the default cost group.
name: exceptions
value: A Tcl list of exception objects that are being applied to the timing paths. The list is
empty if no timing exceptions are being applied.
name: mode
value: The mode object that the set of paths belong to. This value is provided only in the
presence of multi-mode constraints.
name: constraint
value: The timing constraint value for this set of paths is in picoseconds. If the paths are
unconstrained, then the value is listed as no_value.
name: slack
value: A Tcl list containing the worst timing slack for this set of paths for rising and falling
transitions at the pin or port. The values are in picoseconds. The value is listed as no_value if
a particular transition is unconstrained.
name: input_delay
value: A Tcl list containing the input delays in picoseconds for the rising and falling worst-
slack paths. The values are in picoseconds. If a particular input delay is not valid, then the
value is listed as no_value.
name: output_delay
value: A Tcl list containing the output delays in picoseconds for the rising and falling worst-
slack paths. The values are in picoseconds. If a particular output path is not valid, then the
value is listed as no_value.
For certain ports in the design, the timer has two sets of path information. These are ports that are
both timing startpoints and also timing endpoints. The and attributes can be used to locate such
ports, but these are typically clock inputs of sequential cells, D pins of latches, or ports at which
timing paths have been broken using the attribute. At these special ports the timing_info attribute
will return information about the paths ending at that particular port. To query about the paths that
start at the particular port instead, use the attribute. For ports in the design that are not both timing
startpoints and endpoints, the timing_info and the timing_info_favor_startpoint attributes return
the same information.
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Analysis Attributes--pin_bus Attributes for Analysis
Related Information
Related command: report_timing
Related attribute: (port) timing_info_favor_startpoint
timing_info_favor_startpoint
timing_info_favor_startpoint Tcl_list
Read-only port attribute. Returns a Tcl list of information about timing paths. If the port is both a
timing startpoint and an endpoint, then this attribute returns information from the startpoint.
Related Information
Related command: report_timing
Related attribute: (port) timing_info
wire_capacitance
wire_capacitance {no_value | float}
Read-only port attribute. Returns the net capacitance for the port in femtofarads. Resolution is
1/10. This is a computed attribute. Computed attributes are potentially very time consuming to
process and not listed by the vls command by default.
wire_length
wire_length {no_value | float}
Read-only port attribute. Returns the wire length of the net connected to the port. This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
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Analysis Attributes--port_bus Attributes for Analysis
wire_resistance
wire_resistance {no_value | float}
Read-only port attribute. Returns the net resistance for the port in kilohms. Resolution is 1/1000.
This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
port_bus Attributes for Analysis
bits
order
bits
bits string
Read-only port_bus attribute. Returns a list of individual bits that constitute the bus. The list
includes the full pathnames of each individual port object.
Related Information
Related attributes: (hpin_bus) bits
(hport_bus) bits
order
order integer
Read-only port_bus attribute. Returns the order of the bus in the design port declaration list, the
value of the leftmost being the first. The order value of the first bus is 0.
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Analysis Attributes--timing_bin Attributes for Analysis
Related Information
Related attribute: (hport_bus) order
timing_bin Attributes for Analysis
is_sub_bin
path_count
paths
root
sub_bins
timing_bin
is_sub_bin
is_sub_bin {false | true}
Read-only timing_bin attribute. Specifies whether this timing bin is a sub-bin, that is derived from a
parent timing bin. This attribute is true for a sub-bin and false for a parent bin.
Related Information
Set by this command: create_timing_bin
Related attributes: path_count
root
path_count
path_count integer
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Analysis Attributes--timing_bin Attributes for Analysis
Read-only timing_bin attribute. Returns the number of paths in the timing bin.
Related Information
Set by this command: create_timing_bin
Related attributes: iis_sub_bin
root
paths
paths list_of_timing_paths
Read-only timing_bin attribute. Returns the list of timing_path objects in the timing_bin.This is a
computed attribute. Computed attributes are potentially very time consuming to process and not
listed by the vls command by default.
root
root string
Read-only timing_bin attribute. Returns the name of the parent timing bin, which was specified
using the -parent option of the create_timing_bin when the sub -bin was created.
This attribute applies to sub bins only. For parent timing bins, this attribute had no value
Related Information
Set by this command: create_timing_bin
Related attributes: is_sub_bin
path_count
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Analysis Attributes--timing_bin_path Attribute for Analysis
sub_bins
sub_bins list_of_timing_bins
Read-only timing_bin attribute. Returns the list of timing_bin objects in this timing_bin.
timing_bin
timing_bin timing_bin
Read-only timing_bin attribute. Returns the parent timing_bin of this timing_bin.
timing_bin_path Attribute for Analysis
startpoint
startpoint string
Read-only timing_bin_path attribute. Returns the starting point of this timing path.
Related Information
Set by this command: create_timing_bin
Related attributes: (hpin) startpoint
(pin) startpoint
(port) startpoint
timing_path Attributes for Analysis
bin
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Analysis Attributes--timing_bin_path Attribute for Analysis
capturing_clock
capturing_clock_latency
capturing_clock_pin
capturing_network_latency
capturing_point
capturing_source_latency
clock_jitter
cost_group
drive_adjustment
endpoint
exceptions
external_delay
launching_clock
launching_clock_latency
launching_clock_pin
launching_input_delay
launching_network_latency
launching_point
launching_source_latency
path_delay
path_delay_adjustment
recovery_time
required_time
time_borrowed
timing_bin
timing_points
uncertainty
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Analysis Attributes--timing_bin_path Attribute for Analysis
bin
bin string
Read-only timing_path attribute. Returns the name of the parent timing bin or sub-bin within which
this path is contained.
Related Information
Set by this command: create_timing_bin
capturing_clock
capturing_clock string
Default: no value
Read-only timing_path attribute. Returns the name of the capturing clock of the timing path.
capturing_clock_latency
capturing_clock_latency delay
Default: no value
Read-only timing_path attribute. Returns the capture clock latency of the timing path.
It is the sum of source and network latency, that is, time taken for the clock signal from clock source
to sink pin of the registers.
Example
set path [report_timing -collection]get_db $path .capturing_clock_latency 50000.0
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Analysis Attributes--timing_bin_path Attribute for Analysis
capturing_clock_pin
capturing_clock_pin {hpin | pin | constant | pg_pin | hport | port}
Default: no value
Read-only timing_path attribute. Returns the capturing clock pin of the timing path.
capturing_network_latency
capturing_network_latency delay
Default: no value
Read-only timing_path attribute. Returns the capture clock network latency of the timing path.
It is the delay that the clock signal takes from clock definition point to sink pin of the registers.
Examples
set path [report_timing -collection]get_db $path .capturing_network_latency 30000.0
capturing_point
capturing_point {hpin | pin | constant | pg_pin | hport | port}
Default: no value
Read-only timing_path attribute. Returns the capturing point of the timing path.
capturing_source_latency
capturing_source_latency delay
Default: no value
Read-only timing_path attribute. Returns the capture clock source latency of the timing path.
It is the delay that the clock signal takes from clock source to the clock definition point of the design.
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Analysis Attributes--timing_bin_path Attribute for Analysis
Example
set path [report_timing -collection]get_db $path .capturing_source_latency 20000.0
clock_jitter
clock_jitter delay
Default: no_value
Read-only timing_path attribute. Returns the clock jitter delay of the timing path. It is the deviation
of a clock edge from its ideal position in time.
cost_group
cost_group string
Default: no_value
Read-only timing_path attribute. The name of the cost group of the timing path.
drive_adjustment
drive_adjustment delay
Default: no_value
Read-only timing_path attribute. Returns the driver adjustment delay of the timing path. It is the
sum of source and network latency, that is, time taken for the clock signal from clock source to sink
pin of the registers.
endpoint
endpoint string
Read-only timing_path attribute. Returns the end point of this timing path.
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Analysis Attributes--timing_bin_path Attribute for Analysis
Related Information
Set by this command: create_timing_bin
Related attributes: (hpin) endpoint
(pin) endpoint
(port) endpoint
exceptions
exceptions string
Read-only timing_path attribute. Returns a list of all timing exceptions associated with the
specified timing path.
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Analysis Attributes--timing_bin_path Attribute for Analysis
Related Information
Set by this command: create_timing_bin
Affected by these commands: set_multicycle_path
path_adjust
set_max_delay
set_disable_timing
path_group
Related attributes: (clock) exceptions
(cost_group) exceptions
(external_delay) exceptions
(hinst) exceptions
(hpin) exceptions
(inst) exceptions
(pin) exceptions
(port) exceptions
external_delay
external_delay delay
Default: no value
Read-only timing_path attribute. Returns the external delay on the timing path.
launching_clock
launching_clock string
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Analysis Attributes--timing_bin_path Attribute for Analysis
Default: no value
Read-only timing_path attribute. Returns the name of the launching clock of the timing path.
launching_clock_latency
launching_clock_latency delay
Default: no value
Read-only timing_path attribute. Returns the launch clock latency of the timing path.
It is the sum of source and network latency, that is, time taken for the clock signal from clock source
to sink pin of the registers.
Example
set path [report_timing -collection]get_db $path .launching_clock_latency 50000.0
launching_clock_pin
launching_clock_pin {hpin | pin | constant | pg_pin | hport | port}
Default: no value
Read-only timing_path attribute. Returns the launching clock pin of the timing path.
launching_input_delay
launching_input_delay delay
Default: no value
Read-only timing_path attribute. Returns the constrained input delay across the timing path.
launching_network_latency
launching_network_latency delay
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Analysis Attributes--timing_bin_path Attribute for Analysis
Default: no value
Read-only timing_path attribute. Returns the launch clock network latency of the timing path.
It is the delay that the clock signal takes from clock definition point to sink pin of the registers.
Example
set path [report_timing -collection]get_db $path .launching_network_latency 30000.0
launching_point
launching_point {hpin | pin | constant | pg_pin | hport | port}
Default: no value
Read-only timing_path attribute. Returns the launching point of the timing path.
launching_source_latency
launching_source_latency delay
Default: no value
Read-only timing_path attribute. Returns the launch clock source latency of the timing path.
It is the delay that the clock signal takes from clock source to the clock definition point of the design.
Example
set path [report_timing -collection]get_db $path .launching_source_latency 20000.0
path_delay
path_delay delay
Default: no value
Read-only timing_path attribute. Returns the delay across the timing path.
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Analysis Attributes--timing_bin_path Attribute for Analysis
path_delay_adjustment
path_delay_adjustment delay
Default: no_value
Read-only timing_path attribute. Returns the constrained delay across the timing path.
recovery_time
recovery_time delay
Default: no_value
Read-only timing_path attribute. Returns the recovery time delay of the timing path.
Recovery time is the minimum amount of time required between the release of an asynchronous
signal from the active state to the next active clock edge.
required_time
required_time delay
Default: no value
Read-only timing_path attribute. Returns the required time of the timing path.
time_borrowed
time_borrowed delay
Read-only timing_path attribute. Returns the time borrowed across the timing path.
timing_bin
timing_bin timing_bin
Read-only timing_path attribute. Returns the parent timing_bin of this timing_path.
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Analysis Attributes--timing_bin_path Attribute for Analysis
timing_points
timing_points timing_point
Read-only timing_path attribute. Returns the list of ’timing_point’ objects.
uncertainty
uncertainty delay
Read-only timing_path attribute. Returns the uncertainty of the clock signal. Clock uncertainty is
the time difference between the arrivals of clock signals at registers.
Example
set path [report_timing -collection]get_db $path .uncertainty300.0
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Design for Test
26
Design for Test
The chapter describes the attributes of the following object types:
actual_scan_chain Attributes for DFT actual_scan_segment Attributes for DFT All Attributes in DFT
boundary_scan_segment Attributes for DFT design Attributes for DFT dft_configuration_mode Attributes for
DFT
domain_macro_parameters Attributes for DFT fuse_cell Attributes for DFT hnet Attributes for DFT
hpin Attributes for DFT hport Attributes for DFT jtag_instruction_register Attributes for
DFT
jtag_instruction Attributes for DFT jtag_macro Attributes for DFT jtag_port Attributes for DFT
mbist_clock Attributes for DFT memory_data_bit_structure Attributes for DFT memory_lib_cell Attributes for DFT
memory_lib_pin_access Attributes for DFT memory_lib_pin_action Attributes for DFT memory_lib_pin_alias Attributes for
DFT
memory_spare_column_map_address Attributes memory_spare_column_map_data Attributes for memory_spare_column Attributes for
for DFT DFT DFT
memory_spare_row_map_address Attributes for memory_spare_row Attributes for DFT opcg_domain Attributes for DFT
DFT
opcg_mode Attributes for DFT opcg_trigger Attributes for DFT osc_source_reference Attributes for
DFT
osc_source Attributes for DFT pin Attributes for DFT pmbist_port Attributes for DFT
port Attributes for DFT programmable_direct_access_function Attributes root Attributes for DFT
for DFT
scan_chain Attributes for DFT scan_segment Attributes for DFT tap_port Attributes for DFT
test_bus_port Attributes for DFT test_clock Attributes for DFT test_signal Attributes for DFT
violation Attributes for DFT write_mask_bit Attributes for DFT
See also:
location
power_domain
type
actual_scan_chain Attributes for DFT
analyzed
compressed
connected_shift_enable
ctl_defined
dft_hookup_pin_sdi
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Design for Test--actual_scan_chain Attributes for DFT
dft_hookup_pin_sdo
domain
edge
elements
head_lockup
non_shared_scan_out
other_clocks
power_domain
reg_count
scan_clock_a
scan_clock_b
scan_in
scan_out
sdi_compression_signal
shared_input
shared_output
shared_select
shift_enable
terminal_lockup
analyzed
analyzed {true | false}
Read-only actual_scan_chain attribute. Indicates that the connectivity of an existing scan chain—a scan chain created in a previous Genus session—was
analyzed in the current session.
Related Information
Set by this command: define_scan_chain
compressed
compressed {true | false}
Read-only actual_scan_chain attribute. Identifies if test compression was applied to this chain.
Although this attribute is writable, you are expected not to change this attribute value.
Related Information
Set by this command: compress_scan_chains
Related attributes: dft_mask_clock
dft_compression_signal
connected_shift_enable
connected_shift_enable {true | false}
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Design for Test--actual_scan_chain Attributes for DFT
Read-only actual_scan_chain attribute. Indicates if the chain consists exclusively of a preserved or abstract segment whose shift-enable signal was either
internally generated or driven by a non shift-enable test signal. This is a computed attribute. Computed attributes are potentially very time consuming to process
and not listed by the vls command by default.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) shift_enable
(actual_scan_segment) connected_shift_enable
(scan_segment) connected_shift_enable
ctl_defined
ctl_defined {false | true}
Default: false
Read-write actual_scan_chain attribute. Indicates whether the scan segment is defined in CTL abstract model.
dft_hookup_pin_sdi
dft_hookup_pin_sdi {pin | port}
Read-only actual_scan_chain attribute. Returns the pin or port used by the tool to make the scan data input connection to the core logic.
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
dft_hookup_pin_sdo
dft_hookup_pin_sdo {pin | port}
Read-only actual_scan_chain attribute. Returns the pin or port used by the tool to make the the scan data output connection from the core logic.
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
domain
domain string
Read-only actual_scan_chain attribute. Returns the DFT clock domain associated with the tool-created scan chain.
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Design for Test--actual_scan_chain Attributes for DFT
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attribute: (scan_chain) domain
edge
edge {rise | fall | any}
Read-only actual_scan_chain attribute. Returns the edge of the DFT clock domain associated with the tool-created scan chain.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attribute: (scan_chain) edge
elements
elements string
Read-only actual_scan_chain attribute. Returns a Tcl list of the elements in the tool-created scan chain.
Related Information
Set by these commands: connect_scan_chains
Related attributes: (actual_scan_segment) elements
(scan_segment) elements
head_lockup
head_lockup string
Read-only actual_scan_chain attribute. Returns the instance of the head lockup element inserted at the head of the actual scan chain during scan connection.
A head lockup is inserted when you set the dft_capture_clock_edge_for_head_of_scan_chains attribute to leading.
Related Information
Set by this command: connect_scan_chains
non_shared_scan_out
non_shared_scan_out {false | true}
Read-write actual_scan_chain attribute. Controls whether the scan-data output port of this scan chain will be written as an "ignored output" pin constraint to
the LEC do file. By default, it is written as an "ignored output" pin constraint in the LEC do file. You must set this attribute to true before starting formal
verification.
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Design for Test--actual_scan_chain Attributes for DFT
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_chain) other_clocks
other_clocks
other_clocks string
Read-only actual_scan_chain attribute. Returns a Tcl list containing the other clock pins of the chain and their active values.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_segment) other_clocks
(scan_segment) other_clocks
power_domain
power_domain domain
Read-only actual_scan_chain attribute. Returns the list of power domains to which this scan chain belongs.
Related Information
Set by this command: connect_scan_chains
Related command: report_scan_chains
Related attributes: (actual_scan_segment) power_domain
(scan_segment) power_domain
reg_count
reg_count integer
Read-only actual_scan_chain attribute. Returns the number of flops in the tool-created scan chain.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_segment) reg_count
(scan_segment) reg_count
(violation) reg_count
scan_clock_a
scan_clock_a string
Read-only actual_scan_chain attribute. Returns the path to the scan clock a (signal) of the scan chain.
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Design for Test--actual_scan_chain Attributes for DFT
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_segment) scan_clock_a
(scan_chain) scan_clock_a
(scan_segment) scan_clock_a
scan_clock_b
scan_clock_b string
Read-only actual_scan_chain attribute. Returns the path to the scan clock b (signal) of the scan chain.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_segment) scan_clock_b
(scan_chain) scan_clock_b
(scan_segment) scan_clock_b
scan_in
scan_in string
Read-only actual_scan_chain attribute. Returns the scan-data input pin associated with the tool-created scan chain.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attributes: (actual_scan_segment) scan_in
(scan_chain) scan_in
(scan_segment) scan_in
scan_out
scan_out string
Read-only actual_scan_chain attribute. Returns the scan-data output pin associated with the tool-created scan chain.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attributes: (actual_scan_segment) scan_out
(scan_chain) scan_out
(scan_segment) scan_out
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Design for Test--actual_scan_chain Attributes for DFT
sdi_compression_signal
sdi_compression_signal string
Read-only actual_scan_chain attribute. Indicates whether the scan data input pin of this chain is shared with the mask enable signal. If the attribute returns
mask_enable, the scan data input pin of this chain is shared with the mask enable signal.
Related Information
Set by this command: compress_scan_chains
Related attribute: (scan_chain) sdi_compression_signal
shared_input
shared_input {true | false}
Read-only actual_scan_chain attribute. Indicates if the scan-data input port of this scan chain is shared with a functional port.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attribute: (scan_chain) shared_input
shared_output
shared_output {true | false}
Read-only actual_scan_chain attribute. Indicates if the scan-data output port of this scan chain is shared with a functional port.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attribute: (scan_chain) shared_output
shared_select
shared_select string
Read-only actual_scan_chain attribute. Returns the control test signal for the mux of the shared scan data output port.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attribute: (scan_chain) shared_select
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Design for Test--actual_scan_segment Attributes for DFT
shift_enable
shift_enable string
Read-only actual_scan_chain attribute. Returns the chain-specific shift-enable port or pin for the muxed_scan scan style. This is a computed attribute.
Computed attributes are potentially very time consuming to process and not listed by the vls command by default.
This attribute has no value if the connected_shift_enable attribute of this chain is true.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attributes: (actual_scan_chain) connected_shift_enable
(actual_scan_segment) shift_enable
(scan_chain) shift_enable
(scan_segment) shift_enable
terminal_lockup
terminal_lockup string
Read-only actual_scan_chain attribute. Returns the instance of the terminal lockup element in the scan chain.
Related Information
Set by these commands: connect_scan_chains
define_scan_chain
Related attribute: (scan_chain) terminal_lockup
actual_scan_segment Attributes for DFT
active
clock
clock_edge
clock_gating_shift_enable
connected_scan_clock_a
connected_scan_clock_b
connected_shift_enable
core_wrapper
core_wrapper_type
core_wrapper_usage
dft_exclude_abstract_segment_from_los_pipeline
dft_hookup_pin_sdi
dft_hookup_pin_sdo
dft_tail_test_clock
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Design for Test--actual_scan_segment Attributes for DFT
dft_tail_test_clock_edge
dft_tail_test_clock_waveform_edge
elements
head_skew_safe
instance
other_clocks
power_domain
reg_count
reorderable
scan_clock_a
scan_clock_b
scan_in
scan_out
shift_enable
skew_safe
tail_clock
tail_clock_edge
active
active {low | high}
Read-only actual_scan_segment attribute. Returns the active value of the shift-enable port.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attributes: (scan_segment) active
(test signal) active
clock
clock string
Read-only actual_scan_segment attribute. Returns the clock port driving the flip-flops at the head (shift-in position) of this segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) clock
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Design for Test--actual_scan_segment Attributes for DFT
clock_edge
clock_edge {fall | rise}
Read-only actual_scan_segment attribute. Returns the active edge of the clock driving the flip-flops at the head (shift-in position) of this segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) clock_edge
clock_gating_shift_enable
clock_gating_shift_enable string
Read-only actual_scan_segment attribute. Returns the clock gating shift enable pin for an abstract, preserved or shift-register segment.
connected_scan_clock_a
connected_scan_clock_a {true | false}
Read-only actual_scan_segment attribute. Indicates if the scan clock a port of the module boundary is driven by external logic (preconnected) or if the scan
clock a signal is internally generated within the module boundary.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) connected_scan_clock_a
connected_scan_clock_b
connected_scan_clock_b {true | false}
Read-only actual_scan_segment attribute. Indicates if the scan clock b port of the module boundary is driven by external logic (preconnected) or if the scan
clock b signal is internally generated within the module boundary.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) connected_scan_clock_b
connected_shift_enable
connected_shift_enable {true | false}
Read-only actual_scan_segment attribute. Indicates if the shift enable port of the module boundary is driven by external logic (preconnected) or if the shift
enable signal is internally generated within the module boundary.
This applies only to abstract segments and preserved segments. For other types of segments this attribute has no value.
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Design for Test--actual_scan_segment Attributes for DFT
Related Information
Set by this command: connect_scan_chains
Related attribute: (actual_scan_chain) connected_shift_enable
(scan_segment) connected_shift_enable
core_wrapper
core_wrapper {true | false}
Read-write actual_scan_segment attribute. Indicates whether the segment was created for a core wrapper cell.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) core_wrapper
core_wrapper_type
core_wrapper_type string
Default: no_value
Read-write actual_scan_segment attribute. Indicates the type of wrapper, that is, whether the wrapper segment is shared or dedicated.
This attribute only applies to segments for which the core_wrapper attribute is set to true.
core_wrapper_usage
core_wrapper_usage string
Read-write actual_scan_segment attribute. Specifies what is the wrapper segment used for.
dft_exclude_abstract_segment_from_los_pipeline
dft_exclude_abstract_segment_from_los_pipeline {false | true}
Default: false
Read-write actual_scan_segment attribute specified on abstract segment. Avoids insertion of launch-off-shift pipelined logic to the shift enable of the actual
scan chain abstract segment.
Attribute should not be set on scan segment. It is only permitted to be set on actual scan segments.
Related Information
Affects this commands: add_los_pipeline
dft_hookup_pin_sdi
dft_hookup_pin_sdi {pin | port}
Read-only actual_scan_segment attribute. Returns the pin or port used by the tool to make the scan data input connection to the core logic.
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Design for Test--actual_scan_segment Attributes for DFT
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
dft_hookup_pin_sdo
dft_hookup_pin_sdo {pin | port}
Read-only actual_scan_segment attribute. Returns the pin or port used by the tool to make the scan data output connection from the core logic.
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
dft_tail_test_clock
dft_tail_test_clock string
Read-only actual_scan_segment attribute. Returns the top-level clock object that corresponds to the clock port driving the flip-flops at the tail (shift-out position)
of this segment.
This applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by these commands: connect_scan_chains
check_dft_rules
Related attribute: (scan_segment) dft_tail_test_clock
dft_tail_test_clock_edge
dft_tail_test_clock_edge {rise | fall}
Read-only actual_scan_segment attribute. Returns the active edge of the top-level clock object that corresponds to the clock port driving the flip-flops at the tail
(shift-out position) of this segment.
This applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by these commands: connect_scan_chains
check_dft_rules
Related attribute: (scan_segment) dft_tail_test_clock_edge
dft_tail_test_clock_waveform_edge
dft_tail_test_clock_waveform_edge {leading | trailing}
Read-only actual_scan_segment attribute. Returns the active waveform edge of the top-level clock object that corresponds to the clock port driving the flip-flops
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Design for Test--actual_scan_segment Attributes for DFT
at the tail (shift-out position) of this segment.
This applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by these commands: connect_scan_chains
check_dft_rules
Related attribute: (scan_segment) dft_tail_test_clock_waveform_edge
elements
elements string
Read-only actual_scan_segment attribute. Returns a Tcl list of the elements in the tool-created scan segment.
Related Information
Set by this command: connect_scan_chains
Related attributes: (scan_chain) elements
(scan_segment) elements
head_skew_safe
head_skew_safe {true | false}
Read-only actual_scan_segment attribute. Indicates whether the segment has a data lockup element connected at the head of its scan segment.
This applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Reporting Specific Aspects of Chains or Segments in Genus Design for Test Guide.
Set by this command: connect_scan_chains
Related attribute: (scan_segment) head_skew_safe
instance
instance string
Read-only actual_scan_segment attribute. Returns the instance name of the module for which the abstract segment was defined.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) instance
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Design for Test--actual_scan_segment Attributes for DFT
other_clocks
other_clocks string
Read-only actual_scan_segment attribute. Returns a Tcl list containing the other clock pins of the segment and their active values.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) other_clocks
(scan_segment) other_clocks
power_domain
power_domain domain
Read-only actual_scan_segment attribute. Returns the power domain of this scan segment.
This attribute applies only to segments inserted by the add_core_wrapper_cell command that also have the following actual_scan_segment attribute
settings:
core_wrapper = true
type = preserved
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (actual_scan_segment) core_wrapper
(actual_scan_segment) type
(actual_scan_chain) power_domain
(scan_segment) power_domain
reg_count
reg_count integer
Read-only actual_scan_segment attribute. Returns the number of flops in the tool-created scan segment.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) reg_count
(scan_segment) reg_count
(violation) reg_count
reorderable
reorderable {true | false}
Read-only actual_scan_segment attribute. Indicates if the preserved segment is reorderable for scanDEF purposes.
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Genus Attribute Reference
Design for Test--actual_scan_segment Attributes for DFT
This attribute applies only to preserved segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) reorderable
scan_clock_a
scan_clock_a string
Read-only actual_scan_segment attribute. Returns the scan clock A pin for an abstract segment.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) scan_clock_a
(scan_chain) scan_clock_a
(scan_segment) scan_clock_a
scan_clock_b
scan_clock_b string
Read-only actual_scan_segment attribute. Returns the scan clock B pin for an abstract segment.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) scan_clock_b
(scan_chain) scan_clock_b
(scan_segment) scan_clock_b
scan_in
scan_in string
Read-only actual_scan_segment attribute. Returns the scan-data input pin associated with the tool-created scan segment.
This applies only to abstract segments and preserved segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) scan_in
(scan_chain) scan_in
(scan_segment) scan_in
March 2025 1297 Product Version 23.1
Genus Attribute Reference
Design for Test--actual_scan_segment Attributes for DFT
scan_out
scan_out string
Read-only actual_scan_segment attribute. Returns the scan-data output pin associated with the tool-created scan segment.
This applies only to abstract segments and preserved segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) scan_out
(scan_chain) scan_out
(scan_segment) scan_out
shift_enable
shift_enable string
Read-only actual_scan_segment attribute. Returns the segment-specific shift-enable port or pin for the muxed_scan scan style.
This applies only to abstract segments and preserved segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attributes: (actual_scan_chain) shift_enable
(scan_chain) shift_enable
(scan_segment) shift_enable
skew_safe
skew_safe {true | false}
Read-only actual_scan_segment attribute. Indicates if the segment has a data lockup element connected at the end of its scan chain.
This applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) skew_safe
tail_clock
tail_clock string
Read-only actual_scan_segment attribute. Returns the clock port driving the flip-flops at the tail (shift-out position) of this segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
March 2025 1298 Product Version 23.1
Genus Attribute Reference
Design for Test--All Attributes in DFT
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) tail_clock
tail_clock_edge
tail_clock_edge {rise | fall}
Read-only actual_scan_segment attribute. Returns the active edge of the clock driving the flip-flops at the tail (shift-out position) of this segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this command: connect_scan_chains
Related attribute: (scan_segment) tail_clock_edge
All Attributes in DFT
dft_1500_child_input dft_1500_child_output dft_abstract_dont_scan
dft_custom_se dft_dont_scan dft_exclude_flop_from_los_pipeline
dft_exclude_from_shift_register dft_exclude_instance_from_wrapping dft_exempt_from_system_clock_check
dft_force_blackbox_for_atpg dft_hier_instance_for_dedicated_wrapper dft_icg_was_cloned_or_rewired
dft_is_blackbox_for_atpg dft_is_los_pipeline_flop dft_is_testpoint
dft_lockup_name_prefix dft_mapped dft_optimize_chain_wirelength_level
dft_part_of_segment dft_partition dft_scan_chain
dft_scan_chain_in_multi_mode dft_status dft_test_clock
dft_test_clock_edge dft_test_clock_source dft_test_clock_waveform_edge
dft_testpoint_type dft_tpi_no_tp dft_violation
fcu_instruction_set mode_name pin
pmbist_ffn_cell pmbist_ffsync_cell pmbist_instruction_set
pmbist_map2mux_cell pmbist_unresolved reset_icg_violation
test_enable_icg_violation
dft_1500_child_input
Syntax
dft_1500_child_input {true | false}
March 2025 1299 Product Version 23.1
Genus Attribute Reference
Design for Test--All Attributes in DFT
Applies to:
hpin
pin
Description
Default: false
Data_type: bool, read/write
Specifies whether the pin is a child block input pin.
Related Information
Affects this command: add_core_wrapper_cell
dft_1500_child_output
Syntax
dft_1500_child_output {true | false}
Applies to:
hpin
pin
Description
Default: false
Data_type: bool, read/write
Specifies whether the pin is a child block output pin.
Related Information
Affects this command: add_core_wrapper_cell
dft_abstract_dont_scan
Syntax
dft_abstract_dont_scan {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read only
March 2025 1300 Product Version 23.1
Genus Attribute Reference
Design for Test--All Attributes in DFT
Indicates whether an abstract segment was defined across the boundaries of this hierarchical instance. If an abstract segment was defined on a module or
instance for which a netlist was also read in, none of the flip-flops in this instance will be considered for scan replacement and will be excluded from scan chain
connection if they were not part of the abstract segment.
Related Information
Affects these commands: check_dft_rules
convert_to_scan
dft_custom_se
Syntax
dft_custom_se <test_signal>
Applies to:
inst
Description
Default:
Data_type: test_signal, read/write
Indicates which shift-enable signal to connect to the scan flop during scan connection.
The shift-enable signal must have been previously defined with a define_shift_enable command.
This attribute applies only to sequential instances of type flop.
Related Information
Affects these commands: connect_scan_chains
Related constraint: define_shift_enable
dft_dont_scan
Syntax
dft_dont_scan {inherited | true | false}
Applies to:
design
hinst
inst
module
scan_segment
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Genus Attribute Reference
Design for Test--All Attributes in DFT
Description
Default: inherited (design, hinst, inst, module), false (scan_segment)
Data_type: enum (design, hinst, inst, module), bool (scan_segment), read/write
design Controls scan replacement 'for the purposes of test' of flip-flops in the design.
hinst Controls scan replacement of the flip-flop instance for the purposes of test.
inst Controls scan replacement of the flip-flop instance for the purposes of test.
module Controls scan replacement 'for the purposes of test' of the flip-flops in the module.
scan_segment Controls the inclusion of the specified abstract segment into a scan chain.
This attribute can have the following values:
false Allows scan replacement of flip-flops in the design/module/instance and the abstract segment to be included in a scan chain if it passes the
DFT rule checks.
inherited Allows scan replacement of flip-flops.
At the design level, the inherited value has the same meaning as false.
At the hinst/inst/module level, the value indicates that the instance inherits the dft_dont_scan status from its parent module or hierarchical
instance.
Note: Does not apply to obj scan_segment.
true Prevents scan replacement of the flip-flops in the design/parent module or hierarchical instance and excludes the flip-flop and abstract segment
from any scan chain.
You must set this attribute prior to running the check_dft_rules command.
Related Information
Affects these commands: check_dft_rules
connect_scan_chains
syn_map
dft_exclude_flop_from_los_pipeline
Syntax
dft_exclude_flop_from_los_pipeline {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
Specifies whether to avoid insertion of launch-off-shift pipelined logic to flop's shift enable.
March 2025 1302 Product Version 23.1
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Design for Test--All Attributes in DFT
Related Information
Affects this command: add_los_pipeline
dft_exclude_from_shift_register
Syntax
dft_exclude_from_shift_register {true | false}
Applies to:
inst
Description
Default: false
Data_type: bool, read/write
Controls if a flip-flop instance should be excluded from shift register identification. By default, the flip-flop instance can be identified as a bit of a shift register.
You must enable the attribute to exclude the flip-flop instance as a bit of the shift-register segment.
Related Information
Affects these commands: identify_shift_register_scan_segments
syn_map
dft_exclude_instance_from_wrapping
Syntax
dft_exclude_instance_from_wrapping {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
When set to true, the instance will be checked in wrapper insertion and if fanin/fanout of a port hits this instance, then dedicated wrapper will not be inserted.
This attribute can be set only on blackbox hinst.
dft_exempt_from_system_clock_check
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Genus Attribute Reference
Design for Test--All Attributes in DFT
Syntax
dft_exempt_from_system_clock_check {true | false}
Applies to:
inst
Description
Default: false
Data_type: bool, read/write
Exempts the flop from the system clock violation report when reporting the clock domain information. Setting this attribute removes the flop from the report, but
does not otherwise affect how the flop is processed.
Related Information
Affects this command: report_opcg_clock_domain_info
dft_force_blackbox_for_atpg
Syntax
dft_force_blackbox_for_atpg {none | true | false}
Applies to:
hinst
inst
Description
Default: none
Data_type: enum, read/write
Controls whether the specified hierarchical instance is to be interpreted as a blackbox and a possible x-source generator by the DFT rule checker.
Related Information
Affects this command: check_dft_rules -advanced
dft_hier_instance_for_dedicated_wrapper
Syntax
dft_hier_instance_for_dedicated_wrapper {true | false}
Applies to:
hinst
March 2025 1304 Product Version 23.1
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Design for Test--All Attributes in DFT
Description
Default: false
Data_type: bool, read/write
Controls whether dedicated wrapper cells will be inserted in this hierarchical instance. These dedicated wrapper cells will inherit the power domain of the
hierarchical instance.
The hierarchical instance in which the wrapper cells will be inserted should be a module hierarchy in the user RTL or a hierarchy created using the tool.
Example
If you have a user hierarchy in the RTL, set this attribute:
set_db hinst:topModuleName/mod1 .dft_hier_instance_for_dedicated_wrapper \ true
If you need to use the tool to create this hierarchy, do the following:
create_design -name ALL_DWCs
set new_hinst [create_inst -name all_dwcs design:ALL_DWCs design:topModuleName]
delete_obj design:ALL_DWCs
set_db hinst:topModuleName/all_dwcs \ .dft_hier_instance_for_dedicated_wrapper true
dft_icg_was_cloned_or_rewired
Syntax
dft_icg_was_cloned_or_rewired {false | true}
Applies to:
hinst
inst
Description
Default: false
Data_Type: bool, read/write
By default, the clock gate is not cloned or rewired. If set to 'true', the clock gate is either 'cloned or rewired' or 'cloned and rewired'.
dft_is_blackbox_for_atpg
Syntax
dft_is_blackbox_for_atpg {true | false}
Applies to:
hinst
inst
March 2025 1305 Product Version 23.1
Genus Attribute Reference
Design for Test--All Attributes in DFT
Description
Default: false
Data_type: bool, read only
Indicates whether the specified instance is interpreted as a blackbox and a possible x-source generator by the DFT rule checker command.
Related Information
Affects this command: check_dft_rules -advanced
Related attribute: dft_force_blackbox_for_atpg
dft_is_los_pipeline_flop
Syntax
dft_is_los_pipeline_flop {true | false}
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
This attribute is set on the register associated with launch-off-shift pipelined logic.
Related Information
Affects this command: add_los_pipeline
dft_is_testpoint
Syntax
dft_is_testpoint {true | false}
Applies to:
inst
Description
Default: false
Data_type: bool, read/write
This attribute is set to true if current flop is a testpoint flop.
March 2025 1306 Product Version 23.1
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Design for Test--All Attributes in DFT
Related Information
Affected by this command: add_analyzed_test_points
dft_lockup_name_prefix
Syntax
dft_lockup_name_prefix <string>
Applies to:
root
Description
Default: DFT_
Data_type: string, read/write
Specifies the prefix for instances of added data lockup elements in the scan path. It takes precedence for lockup elements name prefix, if specified together with
dft_prefix attribute.
The base names are <prefix>lockup_latch_neg_edge, <prefix>lockup_latch_pos_edge, <prefix>lockup_flop_pos_edge, or <prefix>lockup_latch_pos_edge.
Related Information
Affects these commands: compress_scan_chains
connect_scan_chains
dft_mapped
Syntax
dft_mapped {true | false}
Applies to:
inst
Description
Default: false
Data_type: bool, read only
Indicates whether the scan flip-flop instance is mapped for DFT purposes or used for functional purposes.
A (muxed) scan flip-flop is considered mapped for DFT if its shift-enable pin is
Tied off
Floating
Connected to a shift-enable signal defined with a define_shift_enable constraint.
For scan flip-flops other than the muxed scan flip-flops, this attribute is always true, because these scan flip-flops are usually too complex to be used for
functional purposes.
March 2025 1307 Product Version 23.1
Genus Attribute Reference
Design for Test--All Attributes in DFT
Related Information
Affected by these commands: define_shift_enable
convert_to_scan
syn_map
dft_optimize_chain_wirelength_level
Syntax
dft_optimize_chain_wirelength_level {low | medium | high}
Applies to:
root
Description
Default: medium
Data_type: string, read/write
Specifies the level of optimization needed for physical scan flow, chain wirelength. Supported values for this attribute are low, medium, or high.
Related Information
Affects this command: connect_scan_chains
dft_part_of_segment
Syntax
dft_part_of_segment {abstract | fixed | floating | preserve | shift_register}
Applies to:
actual_scan_segment
hint
inst
scan_segment
Description
Default:
Data_type: enum, read only
Returns the type of scan segment a flip-flop belongs to.
This attribute has no value for instances that are not flip-flops, and for flip-flops that are not part of a scan segment.
March 2025 1308 Product Version 23.1
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Design for Test--All Attributes in DFT
dft_partition
Syntax
dft_partition <string>
Applies to:
actual_scan_chain
actual_scan_segment
hinst
hpin
inst
pin
port
scan_chain
scan_segment
Description
Default:
Data_type: string, read only
Returns the DFT partition of the specified object.
dft_scan_chain
Syntax
dft_scan_chain <string>
Applies to:
actual_scan_segment
hinst
inst
Description
Default:
Data_Type: string, read only
Returns the path to the actual scan chain that the instance belongs to.
This attribute has no value for instances that are not flip-flops.
Related Information
Set by this command: connect_scan_chains
March 2025 1309 Product Version 23.1
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Design for Test--All Attributes in DFT
dft_scan_chain_in_multi_mode
Syntax
dft_scan_chain_in_multi_mode <string>
Applies to:
hinst
inst
Description
Default:
Data_type: scan_segment*, read only
Returns the path to the actual scan chains that the hierarchical instance belongs to in case of multi mode configuration.
This attribute has no value for instances that are not flip-flops.
Related Information
Set by this command: connect_scan_chains
dft_status
Syntax
dft_status {Passes DFT rules | Fails DFT rules | Abstract Segment Dont scan | Dont scan | Misc. non scan}
Applies to:
inst
scan_segment
Description
Default:
Data_type: string, read only
Returns the DFT rule checker (scan) status of the flip-flop / segment.
Abstract Segment Dont scan
Indicates that the instance must not be mapped to a scan. The instance can be an instance of a lib_cell for which an abstract segment was defined, or
can be a flip-flop that belongs to a hierarchical instance for which an abstract segment was defined. In either case, the scan chain information for the
instance is assumed from the abstract definition.
Dont scan
Indicates that the flip-flop must not be mapped to a scan flip-flop.
Fails DFT rules
Indicates that the flip-flop failed the DFT rules.
Misc. non scan
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Design for Test--All Attributes in DFT
Indicates that the instance is a non-scan element. This applies for example to lockup elements, or clock-gating elements.
Passes DFT rules
Indicates that the flip-flop passed the DFT rules.
This attribute has no value if the DFT rule checker has not yet been run, or for instances that are not flip-flops.
Related Information
Set by these commands: check_dft_rules
fix_dft_violations
dft_test_clock
Syntax
dft_test_clock <string>
Applies to:
actual_scan_segment
inst
scan_segment
Description
Default:
Data_type: test_clock (inst) string (actual_scan_segment, scan_segment), read only
Object Description
actual_scan_segment Returns the top-level clock object that corresponds to the clock port driving the flip-flops at the head (shift-in position) of this
segment.
scan_segment
inst Returns the path to the test_clock object that was created by the check_dft_rules command when it identified the test clock for the
flip-flop.
This applies only to abstract segments. For other types of segments / instances this attribute has no value.
Related Information
Set by this command: connect_scan_chains
check_dft_rules
dft_test_clock_edge
Syntax
dft_test_clock_edge {rise | fall}
March 2025 1311 Product Version 23.1
Genus Attribute Reference
Design for Test--All Attributes in DFT
Applies to:
actual_scan_segment
inst
scan_segment
Description
Default:
Data_type: string, read only
Object Description
actual_scan_segment Returns the active edge of the top-level clock object that corresponds to the clock port driving the flip-flops at the head (shift-in
position) of this segment.
scan_segment
inst Returns the active edge of the actual source of the test clock when the test clock was associated with multiple clock sources that
were defined equivalent in test mode.
This applies only to abstract segments. For other types of segments / instances that are not flip-flops, this attribute has no value.
Related Information
Set by this command: connect_scan_chains
check_dft_rules
dft_test_clock_source
Syntax
dft_test_clock_source {pin | port | bus}
Applies to:
inst
Description
Default:
Data_type: hpin | pin | constant | pg_pin | hport | port, read only
Returns for the flip-flop the actual source of the test clock when the test clock was associated with multiple clock sources that were defined equivalent in test
mode.
For instances that are not flip-flops, this attribute has no value.
Related Information
Set by this command: define_test_clock
dft_test_clock_waveform_edge
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Design for Test--All Attributes in DFT
Syntax
dft_test_clock_waveform_edge {leading | trailing}
Applies to:
actual_scan_segment
inst
scan_segment
Description
Default:
Data_type: string, read only
Object Description
actual_scan_segment Returns the active waveform edge of the top-level clock object that corresponds to the clock port driving the flip- flops at the head
(shift-in position) of this segment.
scan_segment
inst Returns the active waveform edge of the actual source of the test clock when the test clock was associated with multiple clock
sources that were defined equivalent in test mode.
This applies only to abstract segments. For other types of segments / instances that are not flip-flops, this attribute has no value.
Related Information
Set by this command: connect_scan_chains
check_dft_rules
dft_testpoint_type
Syntax
dft_testpoint_type { }
Applies to:
inst
Description
Default:
Data_type: string, read/write
Returns the test point type if the instance is a testpoint flop, otherwise it is empty.
Related Information
Affected by this command: add_analyzed_test_points
March 2025 1313 Product Version 23.1
Genus Attribute Reference
Design for Test--All Attributes in DFT
dft_tpi_no_tp
Syntax
dft_tpi_no_tp {false | true}
Applies to:
hinst
hnet
hpin
inst
module
net
pin
Description
Default: false
Data_Type: bool, read/write
Set this attribute to true to prevent test point identification/insertion on the assigned object. The object will be added automatically to the design.noTpfile file,
which is used by the write_dft_deterministic_test_points, write_dft_compression_test_points, and write_dft_lbist_test_points commands for Modus
testpoint analysis. The attribute requires MOD400 license.
Related Information
Affected by these commands: add_analyzed_test_points
write_dft_compression_test_points
write_dft_deterministic_test_points
write_dft_lbist_test_points
dft_violation
Syntax 1
dft_violation {clock | async set | async reset} #(violation_Id_number)
Applies to:
inst
Description
Default:
Data_type: string, read only
Returns the type of violation (clock or asynch) for the flip-flop together with the violation ID number given by the check_dft_rules command.
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Design for Test--All Attributes in DFT
For instances that are not flip-flops, this attribute has no value.
Syntax 2
dft_violation {abstract_testmode | clock | async set | async reset} #(violation_Id_number)
Applies to:
scan_segment
Description
Default:
Data_type: string, read only
Returns the type of violation (abstract segment test mode rule violation, clock rule violation or asynch rule violation) for the abstract segment together with the
violation ID number given by the check_dft_rules command.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
This attribute has no value if the DFT rule checker has not yet been run, or for segments that are not abstract segments.
Related Information
Set by this command: check_dft_rules
fcu_instruction_set
Syntax
fcu_instruction_set <string>
Applies to:
hinst
inst
Description
Default:
Data_type: string, read/write
Defines repair-specific instructions for this instance.
This attribute only applies to instances of a block in which a PMBIST fuse control unit (FCU) has been inserted.
Related Information
Set by this command: add_hard_repair
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Design for Test--All Attributes in DFT
mode_name
Syntax
mode_name <string>
Applies to:
actual_scan_chain
Description
Default:
Data_Type: string, read only
Returns the configuration mode to which the scan chain belongs.
Related Information
Set by these commands: connect_serial_scan_chains
connect_scan_chains
pin
Syntax
pin {pin | port}
Applies to:
jtag_port
opcg_trigger
osc_source
tap_port
test_bus_port
test_signal
timing_point
Description
Default:
Object Data_type Description
jtag_port hpin | pin | constant | pg_pin | hport Specifies the name of the corresponding top-level port.
| port, read only
opcg_trigger hpin | pin | constant | pg_pin | hport Returns the name of the driving pin or port of the trigger signal, which was specified using the -pin
| port, read only option of the define_opcg_trigger command.
osc_source hpin | pin | constant | pg_pin | hport Returns the output pin of the PLL, which was specified using the -pin option of the
| port, read-only define_opcg_osc_source command.
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Design for Test--All Attributes in DFT
tap_port hpin | pin | constant | pg_pin | hport Returns the port or hierarchical pin associated with the TAP signal.
| port, read only
test_bus_port hpin | pin | constant | pg_pin | hport Returns the pin or port on which the test bus port is defined.
| port, read only
test_signal hpin | pin | constant | pg_pin | hport Specifies the port or hierarchical pin associated with the test signal.
| port, read/write
timing_point hpin | pin | constant | pg_pin | hport Returns the pin or port of the timing point.
| port, read only
Related Information
Set by these constraints: define_jtag_tap_port
define_opcg_osc_source
define_shift_enable
define_test_bus_port
define_test_mode
Set by these commands: add_jtag_boundary_scan
check_dft_rules
read_dft_jtag_boundary_file
Affects these commands: define_opcg_domain
define_opcg_mode
define_opcg_trigger
pmbist_ffn_cell
Syntax
pmbist_ffn_cell <lib_cell>
Applies to:
design
module
Description
Default:
Data_Type: string, read/write
Controls the mapping of programmable MBIST negative active flops in a design/module. Specify the library cell to which the negative active flops must be
mapped.
Related Information
Affects this command: map_pmbist_ffn
March 2025 1317 Product Version 23.1
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Design for Test--All Attributes in DFT
pmbist_ffsync_cell
Syntax
pmbist_ffsync_cell <lib_cell>
Applies to:
design
module
Description
Default:
Data_Type: string, read/write
Controls the mapping of programmable MBIST synchronizer flops in a design/module. Specify the library cell to which the synchronizer flops must be mapped.
Related Information
Affects this command: map_pmbist_ffsync
pmbist_instruction_set
Syntax
pmbist_instruction_set <string>
Applies to:
hinst
inst
Description
Default:
Data_type: string, read/write
Defines the user-specific PMBIST instructions to be used for a block instance in which PMBIST logic has been inserted.
string has the following format:
"instruction_option instruction [instruction_option instruction]..."
where:
instruction_option corresponds to the name of an add_pmbist command option that specifies the user-defined instruction name and a corresponding test data
register
instruction is the name of the user-specific instruction.
Use this attribute to specify which PMBIST instruction set must be used for design blocks with PMBIST logic inserted, when more than one PMBIST
instruction set is defined. This is only needed in a bottom-up PMBIST flow when a block with PMBIST logic is instantiated multiple times and you want to
assign separate MBIST instruction sets to these instances. Otherwise all instances of the block will be connected into a single MBIST instruction set at
the current processing level or will be assigned to the PMBIST instruction set defined during PMBIST insertion.
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Design for Test--All Attributes in DFT
Related Information
Affects this command: add_pmbist
pmbist_map2mux_cell
Syntax
pmbist_map2mux_cell <lib_cell>
Applies to:
design
module
Description
Default:
Data_Type: string, read/write
Controls the mapping of programmable MBIST multiplexer modules in a design/module. Specify the library cell to which the multiplexer modules must be
mapped.
Related Information
Affects this command: map_pmbist_map2mux
pmbist_unresolved
Syntax
pmbist_unresolved {false | true}
Applies to:
hinst
inst
Description
Default: false
Data_Type: bool, read/write
Marks the instance as unresolved (or as black-box) for PMBIST perspective. This setting is required to perform logic equivalence checking for hard repair so
that the module definition is still present inside the gate-level netlist when compared against the back-annotated RTL.
Related Information
Affects this command: write_do_lec
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Design for Test--All Attributes in DFT
reset_icg_violation
Syntax
reset_icg_violation {true | false}
Applies to:
violation
Description
Default: false
Data_Type: bool, read only
Indicates whether the violation Is because of ICG reset pin. This attribute value is only set to true when ICG reset pin is not properly configured and because of
same ICG is giving violation.
Example
get_db [vfind designs/top -violation vid_0_clock] .reset_icg_violation
false
Related Information
Set by this command: check_dft_rules
Related attribute: dft_status
test_enable_icg_violation
Syntax
test_enable_icg_violation {true | false}
Applies to:
violation
Description
Default: false
Data_Type: bool, read only
Indicates whether the violation Is because of ICG test enable pin. This attribute value will be set to true, when there is ICG violation on test enable pin.
Example
get_db [vfind designs/top -violation vid_0_clock] .test_enable_icg_violation
false
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Design for Test--boundary_scan_segment Attributes for DFT
Related Information
Set by this command: check_dft_rules
Related attribute: dft_status
boundary_scan_segment Attributes for DFT
acdcsel_11496
acpclk_11496
acpsen_11496
acptrenbl_11496
acpulse_11496
bsdl
capturedr
clockdr
differential_pairs
highz
instance
mode_a
mode_b
mode_c
shiftdr
tdi
tdo
updatedr
acdcsel_11496
acdcsel_11496 {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the JTAG_ACDCSEL pin on
the IEEE 1149.6 JTAG_MACRO.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
acpclk_11496
acpclk_11496 {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the JTAG_ACPSCLK pin on
the IEEE 1149.6 JTAG_MACRO.
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Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
acpsen_11496
acpsen_11496 {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the JTAG_ACPSEN pin on
the IEEE 1149.6 JTAG_MACRO.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
acptrenbl_11496
acptrenbl_11496 {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the JTAG_ACTRENBL pin on
the IEEE 1149.6 JTAG_MACRO.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
acpulse_11496
acpulse_11496 {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the JTAG_ACPULSE pin on
the IEEE 1149.6 JTAG_MACRO.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
bsdl
bsdl string
Read-write boundary_scan_segment attribute. Stores the bsdl abstract information that describes the function and position of the boundary cells embedded
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Design for Test--boundary_scan_segment Attributes for DFT
within a boundary-scan segment and their associated ports.
The attribute value corresponds to the information derived from the file specified for the -bsdl_file option when the boundary-scan segment was
defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
capturedr
capturedr {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the JTAG_CAPTUREDR pin
on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -capturedr option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
clockdr
clockdr {constant | hpin | hport | pg_pin | pin | port}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the
JTAG_BOUNDARY_CLOCKDR pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -clockdr option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
differential_pairs
differential_pairs string
Read-write boundary_scan_segment attribute. Specifies the full list of differential pin pairs on the boundary-scan segment.
The attribute value corresponds to the value(s) specified for the -differential_pair option(s) when the boundary-scan segment was defined.
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Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
highz
highz {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the
JTAG_INSTRUCTION_DECODE_CTRL_HIGHZ pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -highz option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
instance
instance string
Read-write boundary_scan_segment attribute. Specifies the name of the hierarchical instance associated to the boundary-scan segment.
The attribute value corresponds to the value specified for the -instance option when the boundary-scan segment was defined. Alternatively, if a
boundary-scan segment has been defined on either a lib_cell or a module, boundary-scan segment objects are created for each instantiation and this
attribute set for each boundary-scan segment with the appropriate instance value.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
mode_a
mode_a {pin | port}
Read-write boundary_scan_segment attribute.Specifies the name of the pin on the boundary-scan segment that must be connected to the
JTAG_INSTRUCTION_DECODE_MODE_A pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -mode_a option when the boundary-scan segment was defined.
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Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
mode_b
mode_b {pin | port}
Read-write boundary_scan_segment attribute.Specifies the name of the pin on the boundary-scan segment that must be connected to the
JTAG_INSTRUCTION_DECODE_MODE_B pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -mode_b option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
mode_c
mode_c {pin | port}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the
JTAG_INSTRUCTION_DECODE_MODE_C pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -mode_c option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
shiftdr
shiftdr {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the
JTAG_BOUNDARY_SHIFTDR pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -shiftdr option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
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Design for Test--design Attributes for DFT
tdi
tdi {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the TDI pin on the boundary-scan segment that must be connected in the boundary-scan
register.
The attribute value corresponds to the value specified for the -tdi option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
tdo
tdo {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the TDO pin on the boundary-scan segment that must be connected in the boundary-scan
register.
The attribute value corresponds to the value specified for the -tdo option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
updatedr
updatedr {constant | pin | hpin | pgpin | port | hport}
Read-write boundary_scan_segment attribute. Specifies the name of the pin on the boundary-scan segment that must be connected to the
JTAG_BOUNDARY_UPDATEDR pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -updatedr option when the boundary-scan segment was defined.
Related Information
Set by this command: define_jtag_boundary_scan_segment
Affects these commands: add_jtag_boundary_scan
write_dft_bsdl
design Attributes for DFT
actual_scan_chains actual_scan_segments boundary_scan
boundary_scan_segments boundary_type dft_boundary_scan_exists
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Design for Test--design Attributes for DFT
dft_clock_edge_for_head_of_scan_chains dft_clock_edge_for_tail_of_scan_chains dft_compression_inside_hierarchy
dft_configuration_modes dft_connect_scan_data_pins_during_mapping dft_connect_shift_enable_during_mapping
dft_core_max_pipe_depth dft_locations_for_shared_wrapper_processing dft_lockup_element_type
dft_lockup_element_type_for_tail_of_scan_chains dft_max_length_of_scan_chains dft_min_number_of_scan_chains
dft_mix_clock_edges_in_scan_chains dft_opcg_edge_mode dft_scan_map_mode
dft_scan_output_preference dft_shared_wrapper_exclude_port dft_shared_wrapper_input_threshold
dft_shared_wrapper_output_threshold dft_tap_tck_period direct_access
domain_macro_parameters formal_verification_constraints fuse_cells
insert_pmbist_without_liberty_files jtag_instructions jtag_macros
jtag_ports mbist_clock_domains mbist_enable_shared_library_domain_set
memory_lib_cells opcg_domains opcg_modes
opcg_triggers osc_sources pmbist_block_stitching_order
pmbist_hri_async_reset pmbist_ports scan_chains
scan_in_pipeline_clock_edge scan_out_pipeline_clock_edge scan_segments
tap_ports test_bus_interfaces test_bus_ports
test_clock_domains test_signals violations
actual_scan_chains
actual_scan_chains <list_of_actual_scan_chains>
Applies to:
design
Description
Default:
Data_type: actual_scan_chain*, read only
Returns a list of all actual_scan_chain objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by this command: connect_scan_chains
Affects these commands: define_scan_chain
connect_serial_scan_chains
actual_scan_segments
actual_scan_segments list_of_actual_scan_segments
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Read-only design attribute. Returns a list of all actual_scan_segment objects in the design. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
boundary_scan
boundary_scan list_of jtag_instruction_registers
Read-only design attribute. Returns a list of all jtag_instruction_register objects in the design. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
boundary_scan_segments
boundary_scan_segments list_of boundary_scan_segments
Read-only design attribute. Returns a list of all boundary_scan_segment objects in the design. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
boundary_type
boundary_type {IEEE_11491 | IEEE_11496}
Default: none
Read-write design attribute. Specifies either an IEEE 1149.1 or IEEE 1149.6 IEEE boundary-scan architecture.
This attribute can have the following values:
IEEE_11491 Specifies an IEEE 1149.1 JTAG_Macro and boundary-scan architecture
IEEE_11496 Specifies an IEEE 1149.6 JTAG_Macro and boundary-scan architecture.
Related Information
Affects these commands: add_jtag_boundary_scan
add_jtag_macro
dft_boundary_scan_exists
dft_boundary_scan_exists {false | true}
Default: false
Read-write design attribute. Indicates whether boundary-scan logic was inserted into the design.
Related Information
Set by this command: add_jtag_boundary_scan
Affects this command: add_jtag_boundary_scan
dft_clock_edge_for_head_of_scan_chains
dft_clock_edge_for_head_of_scan_chains {"" | leading}
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Default: ""
Read-write design attribute. Specifies the triggering edge of the first element of the actual scan chains to build.
If the triggering edge of the first element of an actual scan chain does not match the value specified for this attribute, the tool inserts a lockup flop at the
beginning of the actual scan chain. This lockup flop will be driven by the same clock that drives the first element in the chain and will be triggered by the clock
edge specified with this attribute.
For RTZ clock waveforms, leading edge refers to the rising edge.
For RT1 clock waveforms, leading edge refers to the falling edge.
This attribute can have the following values:
"" Does not insert a lockup flop at the head of any actual scan chain.
leading Inserts a leading edge-triggered lockup flop at the head of all actual scan chains for which the first element is not leading edge-triggered.
Related Information
Affects these commands: connect_scan_chains
write_dft_abstract_model
Related attributes: dft_clock_edge_for_tail_of_scan_chains
dft_lockup_element_type_for_tail_of_scan_chains
dft_clock_edge_for_tail_of_scan_chains
dft_clock_edge_for_tail_of_scan_chains {"" | leading | trailing}
Default: ""
Read-write design attribute. Specifies the triggering edge of the last element of the actual scan chains to be built.
If the triggering edge of the last element of an actual scan chain does not match the value specified for this attribute, the tool inserts a lockup element (flop or
latch) at the end of the actual scan chain. This lockup element will be driven by the same clock that drives the last element in the chain and will be triggered by
the clock edge specified with this attribute.
For RTZ clock waveforms, leading refers to the rising edge and trailing to the falling edge.
For RT1 clock waveforms, leading refers to the falling edge and trailing to the rising edge.
This attribute can have the following values:
"" Does not insert a lockup element at the end of an actual scan chain, unless the chain is built from a user-defined chain that is defined with the -
terminal_lockup option.
leading Inserts a leading edge-triggered lockup element at the end of all actual scan chains for which the last element is not leading edge-triggered.
trailing Inserts a trailing edge-triggered lockup element at the end of all actual scan chains for which the last element is not trailing edge-triggered.
Related Information
Affects these commands: connect_scan_chains
write_dft_abstract_model
Related attributes: dft_clock_edge_for_head_of_scan_chains
dft_lockup_element_type_for_tail_of_scan_chains
dft_compression_inside_hierarchy
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dft_compression_inside_hierarchy string
Read-write design attribute. Specifies the hierarchical instance into which to insert compression.
dft_configuration_modes
dft_configuration_modes list_of_dft_configuration_modes
Read-only design attribute. Returns a list of all dft_configuration_mode objects in the design. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
dft_connect_scan_data_pins_during_mapping
dft_connect_scan_data_pins_during_mapping {loopback | floating | ground | high}
Default: loopback
Read-write design attribute. Starting from RTL, this attribute controls the connections of the scan-data pins during an initial synthesis run (syn_map), when
mapping generic flops to their scan-equivalent flops.
Starting from a gate-level netlist, this attribute controls the connections of the scan-data pins during an incremental synthesis run (syn_opt), when remapping
non-scan flops to their scan-equivalent flops.
This attribute can have the following values:
floating Leaves the scan-data input pins of the scan flops unconnected.
ground Connects the scan-data input pins of the scan flops to logic 0. If available, a logic 0 net or equivalent library cell is used. Otherwise a constant
(1’b0) is used.
high Connects the scan-data input pins of the scan flops to logic 1. If available, a logic 1 net or equivalent library cell is used. Otherwise a constant
(1’b1) is used.
loopback Connects a scan-data output pin of the scan flops to its own scan-data input pin, emulating the loading effect on the scan-data output without
connecting the chain.
The recommended use model is to use loopback mode. This approach emulates a single standard load seen by the timing engine during synthesis. This load
emulates the additional resistance and capacitance on the network, when the scan chains are subsequently connected in the circuit using the
connect_scan_chains command.
Connection of the shift-enable pins is controlled by the dft_connect_shift_enable_during_mapping attribute.
Related Information
Affects this command: syn_map
Related attribute: dft_scan_map_mode
dft_connect_shift_enable_during_mapping
dft_connect_shift_enable_during_mapping {tie_off | floating}
Default: tie_off
Read-write design attribute. Controls the connection of the following pins during an initial synthesis run (syn_map), when mapping generic flops to their scan-
equivalent flops:
Shift-enable pins of the scan flip-flops (when using the muxed scan style)
Scan clock pins of the scan flip-flops (when using the clocked LSSD scan style)
This attribute can have the following values:
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floating Shift-enable (scan clock) pins are left unconnected.
tie_off Shift-enable (scan clock) pins are connected to their off state (tied-to a low for active high enables, tied-to a high for active low enables).
Related Information
Affects this command: syn_map
Related attribute: dft_scan_map_mode
dft_core_max_pipe_depth
dft_core_max_pipe_depth integer
Read-write design attribute. Specifies the maximum pipeline depth of a core.
This attribute affects the hierarchical test IEEE P 1687 flow.
When the attribute is set to N, the following line will be added to the Modus pin assign file:
coremaxpipedepth=N
Related Information
Affects this command: write_dft_atpg
dft_locations_for_shared_wrapper_processing
dft_locations_for_shared_wrapper_processing list_of_ports
Read-write design attribute. Specifies the ports for which shared wrapper flops must be identified. If not set, then every port in the design will be processed.
Related Information
Affects this command: identify_shared_wrapper_cells_in_design
dft_lockup_element_type
dft_lockup_element_type {preferred_level_sensitive | preferred_edge_sensitive
| edge_sensitive | level_sensitive}
Default: preferred_level_sensitive
Read-write design attribute. Controls the type of component to be used as lockup element when combining scan flops triggered by different clocks, or different
edges of a test clock in the same chain. This attribute can have the following values:
edge_sensitive Requests to insert an edge-sensitive component (D-flop).
This could cause skew problems.
level_sensitive Requests to insert a level-sensitive component (latch).
This could cause skew problems.
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preferred_edge_sensitive Requests to insert lockup flops where possible, but latches when required to avoid skew concerns between the different test
clocks.
preferred_level_sensitive Requests to insert lockup latches where possible, but flops when required to avoid skew concerns between the different test
clocks.
This attribute applies only to the muxed scan style.
Related Information
Affects this command: connect_scan_chains
Related attribute: dft_mix_clock_edges_in_scan_chains
dft_lockup_element_type_for_tail_of_scan_chains
dft_lockup_element_type_for_tail_of_scan_chains {level_sensitive | edge_sensitive}
Default: level_sensitive
Read-write design attribute. Specifies the lockup element type to be added at the end of actual scan chains when the
dft_clock_edge_for_tail_of_scan_chains attribute is set to a non null value. This attribute has no effect when the dft_clock_edge_for_tail_of_scan_chains
is not set.
For actual scan chains derived from user-defined scan chains defined with the -terminal_lockup option, the lockup element type specified with the -
terminal_lockup option will override the lockup element type specified with this attribute.
This attribute can have the following values:
edge_sensitive Inserts a lockup flop at the end of actual scan chain during scan chain connection.
level_sensitive Inserts a lockup latch at the end of actual scan chain during scan chain connection.
Related Information
Affects these commands: connect_scan_chains
write_dft_abstract_model
Related attributes: dft_clock_edge_for_head_of_scan_chains
dft_clock_edge_for_tail_of_scan_chains
dft_max_length_of_scan_chains
dft_max_length_of_scan_chains integer
Default : no_value
Read-write design attribute. Specifies the maximum length of any scan chain. If necessary, the test synthesis engine creates additional scan chains to keep
each scan chain at or below the required maximum length. By default, there is no limit to the maximum length of a scan chain, unless you specified the
maximum scan chain length explicitly using the define_scan_chain constraint. The maximum length for a specific scan chain takes precedence over the
design-specific maximum scan chain length.
Related Information
Affects this command: connect_scan_chains
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dft_min_number_of_scan_chains
dft_min_number_of_scan_chains integer
Default : no_value
Read-write design attribute. Specifies the minimum number of scan chains to be created.
Related Information
Affects this command: connect_scan_chains
dft_mix_clock_edges_in_scan_chains
dft_mix_clock_edges_in_scan_chains {false | true}
Default: false
Read-write design attribute. Controls combining flip-flops from the same DFT domain—which are triggered by either edge of the same test clock—on the same
scan chain.
You can specify DFT domains and their assumed test clock waveforms during test mode using the define_test_clock constraint. In the absence of defining the
DFT domains explicitly, the assignment of scan flops to their DFT domains is performed by running the check_dft_rules command. By default, all rising and all
falling edge-triggered scan flops driven by the same logical clock source belong to the same DFT domain. A separate DFT domain is created for each uniquely
identified logical clock source.
The test synthesis engine evaluates the test clock waveforms when deciding how to order the scan flops along the scan chain (rise-to-fall, fall-to-rise). It also
evaluates where to include a data lockup element when combining scan chain segments triggered by the different active edges of the test clocks belonging to
the same DFT domain. The type of lockup element inserted into the scan chain is defined using the dft_lockup_element_type attribute.
Set this attribute to true if you want a single scan chain mixing edges from the same test clock onto the same scan chain.
Set this attribute to false if you want a single scan chain per active clock edge per DFT domain.
This attribute applies only to the muxed scan style.
Related Information
Affects this command: connect_scan_chains
Related attribute: dft_lockup_element_type
dft_opcg_edge_mode
dft_opcg_edge_mode string
Read-write design attribute. Specifies the test signal to use to control the OPCG edge mode. This is equivalent to specifying a test signal to be used as the
value of option -edge_mode for command convert_to_opcg_scan.
Related Information
Related command: convert_to_opcg_scan
dft_scan_map_mode
dft_scan_map_mode {tdrc_pass | force_all | preserve}
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Default: tdrc_pass
Read-write design attribute. Controls the mapping of the flip-flops to their scan-equivalent flip-flops.
Non-scan flip-flops marked with either a dft_dont_scan attribute or a preserve attribute, or non-scan flip-flops instantiated in blocks marked with either a
preserve or a dft_dont_scan attribute, are not affected by the setting of the dft_scan_map_mode attribute—these flip-flops will not be mapped to scan flip-
flops.
force_all Controls mapping of all (non attributed) non-scan flip-flops to their scan-equivalent flip-flops. Even though these flip-flops are
now mapped to scan flip-flops, only those flip-flops that pass the DFT rule checks, are connected into a scan chain during scan connection.
You should only use this setting if you plan to fix the violations.
Since a subsequent synthesis run will not unmap a scan flop which fails the DFT rule checks to its non-scan equivalent flop, this
approach can result in a Quality of Silicon (QoS) degradation over the tdrc_pass approach.
preserve Preserves the flip-flop type (non-scan and scan) of previously mapped flip-flops.
During synthesis scan mapping is bypassed.To prevent inferred flip-flops from being mapped to scan flip-flops for functional use, set the
use_scan_seqs_for_non_dft root attribute to false before you run initial synthesis on the design.
tdrc_pass Allows only flip-flops that pass the DFT rule checks to be mapped during synthesis. Use this value when
Synthesizing from RTL. To maximize fault coverage, fix any outstanding DFT violations using the fix_dft_violations command, prior to
mapping (syn_map).
Performing an incremental optimization (syn_opt) on a mapped netlist with the intent to replace any flip-flop which passes the DFT rule
checks with scan flops.
You need to run the check_dft_rules command to determine the DFT status of the flip-flops.
Related Information
Affected by this command: check_dft_rules
Affects these commands: convert_to_scan
syn_map
Related attributes: dft_connect_scan_data_pins_during_mapping
dft_connect_shift_enable_during_mapping
dft_scan_output_preference
dft_scan_output_preference {auto | non_inverted | inverted}
Default: auto
Read-write design attribute. Controls which scan flip-flop output pin to use for the scan-data path connection.
auto Lets the tool choose the output pin based on the pin load or impact on the timing.
inverted Selects the output pin with the test_scan_out_inverted attribute or QB pin.
non_inverted Selects the output pin with the test_scan_out attribute or Q pin.
Depending on the scan flip-flop selected by the technology mapper during synthesis, a scan flop can potentially have three output pins:
Q: a functional non-inverted output pin
QB: a functional inverted output pin
SO: a dedicated scan-data output pin
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Design for Test--design Attributes for DFT
Whether a scan flip-flop output pin can be used for scan-data purposes is controlled through a test attribute defined for each scan flip-flop in the technology
library.
The test attributes defined in Liberty format are:
test_scan_out Specifies an output scan pin.
test_scan_out_inverted Specifies an output scan pin having inverted polarity.
Related Information
Affects this command: syn_map
dft_shared_wrapper_exclude_port
dft_shared_wrapper_exclude_port list_of_ports
Read-write design attribute. Specifies the ports to be excluded from processing while identifying shared wrapper flops for ports.
Related Information
Affects this command: identify_shared_wrapper_cells_in_design
dft_shared_wrapper_input_threshold
dft_shared_wrapper_input_threshold integer
Default: 10
Read-write design attribute. Specifies the maximum number of scannable flops at the fanout of an input port which can be shared as wrapper cells for the input
port.
Related Information
Affects this command: identify_shared_wrapper_cells_in_design
dft_shared_wrapper_output_threshold
dft_shared_wrapper_output_threshold integer
Default: 10
Read-write design attribute. Specifies the maximum number of scannable flops at the fanin of an output port which can be shared as wrapper cells for the
output port.
Related Information
Affects this command: identify_shared_wrapper_cells_in_design
dft_tap_tck_period
dft_tap_tck_period integer
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Design for Test--design Attributes for DFT
Default: 50000
Read-write design attribute. Specifies the period of the Test Clock (TCK) on the TAP Controller in picoseconds.
You can set this attribute directly, or the attribute value can be set through the -tck_period option of the define_jtag_tap_port command.
The write_dft_bsdl command will write out the TCK frequency in Hz in the BSDL file. The default frequency is 20 MHz.
direct_access
direct_access list_of_programmable_direct_access_functions
Read-only design attribute. Returns a list of domain macro parameters (objects) in the design. This is a computed attribute. Computed attributes are potentially
very time consuming to process and not listed by the vls command by default.
domain_macro_parameters
domain_macro_parameters list_of_domain_macro_parameters
Read-only design attribute. Returns a list of programmable_direct_access_function objects in the design. This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
Related Information
Set by this command: define_jtag_tap_port
Affects this command: write_dft_bsdl
formal_verification_constraints
formal_verification_constraints list_of_formal_verification_constraints
Read-only design attribute. Returns a list of all formal_verification_constraint objects in the design.This is a computed attribute. Computed attributes are
potentially very time consuming to process and not listed by the vls command by default.
fuse_cells
fuse_cells list_of_fuse_cells
Read-only design attribute. Returns a list of fuse_cell objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
insert_pmbist_without_liberty_files
insert_pmbist_without_liberty_files {false | true}
Default: false
Read-write design attribute. Enables to perform PMBIST insertion without memory liberty files,
Related Information
Inserting Programmable MBIST Logic in Genus PMBIST Guide.
Affects this command: add_pmbist
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Design for Test--design Attributes for DFT
jtag_instructions
jtag_instructions list_of_jtag_instructions
Read-only design attribute. Returns a list of all jtag_instruction objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
jtag_macros
jtag_macros list_of_jtag_macros
Read-only design attribute. Returns a list of all jtag_macro objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
jtag_ports
jtag_ports list_of_jtag_ports
Read-only design attribute. Returns a list of all jtag_port objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
mbist_clock_domains
mbist_clock_domains list_of_mbist_clock_domains
Read-only design attribute. Returns a list of all mbist_clock_domain objects in the design. This is a computed attribute. Computed attributes are potentially very
time consuming to process and not listed by the vls command by default.
mbist_enable_shared_library_domain_set
mbist_enable_shared_library_domain_set {""|list_of_lists|all}
Default: no_value
Read-write design attribute. Controls whether memories that have the same module name but that belong to different library domains can share the same
engine. By default, memories present in different library domains cannot share an MBIST or PMBIST engine.
The value for this attribute is a list. Each element in this list is a list of library domains. The memories present in this list of library domains can share an MBIST
or PMBIST engine.
Related Information
Affects this command: add_pmbist
memory_lib_cells
memory_lib_cells list_of_memory_lib_cells
Read-only design attribute. Returns a list of all memory_lib_cell objects in the design. This is a computed attribute. Computed attributes are potentially very
time consuming to process and not listed by the vls command by default.
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opcg_domains
opcg_domains list_of_opcg_domains
Read-only design attribute. Returns a list of all opcg_domain objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
opcg_modes
opcg_modes list_of_opcg_modes
Read-only design attribute. Returns a list of all opcg_mode objects in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
opcg_triggers
opcg_triggers list_of_opcg_triggers
Read-only design attribute. Returns a list of all opcg_trigger objects in the design.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
osc_sources
osc_sources list_of_osc_sources
Read-only design attribute. Returns a list of all osc_sources in the design. This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
pmbist_block_stitching_order
pmbist_block_stitching_order string
Read-write design attribute. Stitches the list of PMBIST inserted block instances in the specified order at current level. The specified order of blocks must be
from TDO to TDI, first instance being closest to TDO and last being closest to TDI.
Example
In the following example, the instances (within "") are instances of PMBIST inserted blocks from previous sessions. In the current session, the instances will be
stitched (from TDO to TDI) in the order specified by pmbist_block_stitching_oder.
set_db design:TOP_bts .pmbist_block_stitching_order "TOP_CORE_1/mod_A_inst TOP_CORE_1/mod_B_inst TOP_CORE_1/mod_C_inst TOP_CORE_2/mod_A_inst
TOP_CORE_2/mod_B_inst TOP_CORE_2/mod_C_inst"
Related Information
Affects this command: add_pmbist
map_pmbist_ffn
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pmbist_hri_async_reset
pmbist_hri_async_reset string
Read-write design attribute. Specifies asynchronous reset port/pin along with the active state for repair used by programmable MBIST, in the following format:
{<pin/port name> active_<high|low>}
Related Information
Affects this command: add_pmbist
pmbist_ports
pmbist_ports list_of_ports
Read-only design attribute. Returns a list of all pmbist_port objects in the design.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
scan_chains
Syntax
scan_chains <list_of_scan_chains>
Applies to:
design
Description
Default:
Data_type: scan_chain*, read only
Returns a list of all scan_chain objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls command by default.
Related Information
Set by this command: define_scan_chain
Affects this command: connect_scan_chains
scan_in_pipeline_clock_edge
scan_in_pipeline_clock_edge {rise | fall}
Default: rise
Read-write design attribute. Specifies the clock edge triggering pipelines inserting at the scan inputs.
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Related Information
Affects this command: add_test_compression
scan_out_pipeline_clock_edge
scan_out_pipeline_clock_edge {fall | rise}
Default: fall
Read-write design attribute. Specifies the clock edge triggering pipelines inserting at the scan outputs.
Related Information
Affects this command: add_test_compression
scan_segments
scan_segments list_of_scan_segments
Read-only design attribute. Returns a list of all scan_segment objects in the design.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
tap_ports
tap_ports list_of_tap_ports
Read-only design attribute. Returns a list of all tap_port objects in the design.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
test_bus_interfaces
test_bus_interfaces list_of_test_bus_interfaces
Read-only design attribute. Returns a list of all test_bus_interface objects in the design.This is a computed attribute. Computed attributes are potentially very
time consuming to process and not listed by the vls command by default.
test_bus_ports
test_bus_ports list_of_test_bus_ports
Read-only design attribute. Returns a list of all test_bus_port objects in the design.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
test_clock_domains
test_clock_domains list_of_clock_domains
Read-only design attribute. Returns a list of all test_clock_domain objects in the design.This is a computed attribute. Computed attributes are potentially very
time consuming to process and not listed by the vls command by default.
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Design for Test--dft_configuration_mode Attributes for DFT
test_signals
test_signals list_of_test_signals
Read-only design attribute. Returns a list of all test_signal objects in the design.This is a computed attribute. Computed attributes are potentially very time
consuming to process and not listed by the vls command by default.
violations
violations list_of_violations
Read-only design attribute. Returns a list of all violation objects in the design. This is a computed attribute. Computed attribcp utes are potentially very time
consuming to process and not listed by the vls command by default.
dft_configuration_mode Attributes for DFT
current_mode
decoded_pin
jtag_instruction
mode_enable_high
mode_enable_low
usage
current_mode
current_mode {false | true}
Default: false
Read-only dft_configuration_mode attribute. Indicates if the queried scan mode is the current mode.
Related Information
Set by this command: define_dft_cfg_mode
Affects these commands: check_dft_rules
compress_scan_chains
connect_serial_scan_chains
connect_scan_chains
decoded_pin
decoded_pin {pin | port}
Read-write dft_configuration_mode attribute. Specifies the output pin of the decoder logic that will be activated when all the test signals that define this
configuration mode (of type wrapper) attain the value specified in the definition of this configuration mode.
This attribute is set to NULL when no decoder logic was inserted or if the configuration mode is not of type wrapper.
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Related Information
Affects these commands: connect_serial_scan_chains
connect_scan_chains
add_core_wrapper_cell
jtag_instruction
jtag_instruction instruction_name
Read-only dft_configuration_mode attribute. Returns the name of the user-defined JTAG instruction associated with the configuration mode.
Related Information
Set by this command: define_dft_cfg_mode
compress_scan_chains
Related command: define_jtag_instruction
mode_enable_high
mode_enable_high test_signal
Read-only dft_configuration_mode attribute. Specifies the test signals that are held to active high value for the mode.
Related Information
Set by this command: define_dft_cfg_mode
Affects these commands: check_dft_rules
compress_scan_chains
connect_serial_scan_chains
connect_scan_chains
define_scan_abstract_segment
write_dft_atpg_other_vendor_files
write_dft_abstract_model
write_dft_atpg
write_scandef
mode_enable_low
mode_enable_low test_signal
Read-only dft_configuration_mode attribute. Specifies the test signals that are held to active low value for the mode.
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Related Information
Set by this command: define_dft_cfg_mode
Affects these commands: check_dft_rules
compress_scan_chains
connect_serial_scan_chains
connect_scan_chains
define_scan_abstract_segment
write_dft_atpg_other_vendor_files
write_dft_abstract_model
write_dft_atpg
write_scandef
usage
usage string
Read-only dft_configuration_mode attribute. Returns the usage if the configuration mode is of type wrapper. Possible values are mission, intest and extest.
The attribute value corresponds to the value specified for the -usage option when the wrapper configuration mode was defined.
Related Information
Set by this command: define_dft_cfg_mode
Affects these commands: connect_serial_scan_chains
connect_scan_chains
add_core_wrapper_cell
domain_macro_parameters Attributes for DFT
counter_length
max_num_pulses
target_period
trigger_delay
counter_length
counter_length integer
Read-only domain_macro_parameter attribute. Returns the number of bits in the down counter in the domain macro, which was specified using the -
counter_length option of the define_opcg_domain_macro_parameters command.
Related Information
Set by this constraint: define_opcg_domain_macro_parameters
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max_num_pulses
max_num_pulses integer
Read-only domain_macro_parameter attribute. Returns the number of pulses generated by the domain macro, which was specified using the -max_num_pulses
option of the define_opcg_domain_macro_parameters command.
Related Information
Set by this constraint: define_opcg_domain_macro_parameters
target_period
target_period float
Read-only domain_macro_parameter attribute. Returns the operating target period for the domain macro in picoseconds, which was specified using the -
min_target_period option of the define_opcg_domain_macro_parameters command.
Related Information
Set by this constraint: define_opcg_domain_macro_parameters
trigger_delay
trigger_delay float
Read-only domain_macro_parameter attribute. Returns the time (in picoseconds) after which the first pulse must be issued by the domain macro after receipt of
the TRIGGERRUN signal from the trigger macro, which was specified using the -max_trigger_delay option of the define_opcg_domain_macro_parameters
command.
Related Information
Set by this constraint: define_opcg_domain_macro_parameters
fuse_cell Attributes for DFT
address_limit
data_order
memory_lib_cell
port_access
port_action
port_alias
read_delay
wrapper
address_limit
address_limit integer
Read-only fuse_cell attribute. Returns the number of used or addressable words in the memory, which was specified using the address_limit specification in
the PMBIST configuration file.
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Related Information
Set by this command: read_pmbist_memory_view
data_order
data_order string
Read-only fuse_cell attribute. Returns the physical order of the data-bits within the memory word, which was specified using the data_order specification in
the PMBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_lib_cell
memory_lib_cell string
Read-only fuse_cell attribute. Returns the path to the corresponding memory lib cell in the library.
Related Information
Set by this command: read_pmbist_memory_view
port_access
port_access list_of_memory_lib_pin_access
Read-only fuse_cell attribute. Returns the list of all memory_lib_pin_access objects for this fuse_cell.
port_action
port_action list_of_memory_lib_pin_actions
Read-only fuse_cell attribute. Returns the list of all memory_lib_pin_action objects for this fuse_cell.
port_alias
port_alias list_of_memory_lib_pin_alias
Read-only fuse_cell attribute. Returns the list of all memory_lib_pin_alias objects for this fuse_cell.
read_delay
read_delay integer
Read-only fuse_cell attribute. Returns the intrinsic read delay of the selected memory modules, which was specified using the read_delay specification in the
PMBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
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wrapper
wrapper string
Read-only fuse_cell attribute. Returns the wrapper module that contains the actual fuse cell, which was specified using the fuse_wrapper specification in the
MBIST view file.
Related Information
Set by this command: read_pmbist_memory_view
hnet Attributes for DFT
dft_clock_domain_info
dft_clock_domain_info {UNKNOWN | pin_list}
Read-only hnet attribute. Returns the clock domain information that is propagated during the scan connection step when the dft_opcg_domain_blocking root
attribute is set to true.
The value can be UNKNOWN if you set the dft_opcg_block_input_to_flop_paths root attribute to true, allowing propagation of unknown clock information.
Related Information
Affected by this command: connect_scan_chains
Affect by these attributes: dft_opcg_domain_blocking
dft_opcg_block_input_to_flop_paths
dft_constant_value
dft_constant_value {logic_0|logic_1|logic_z|no_value}
Read-only hnet attribute. Indicates whether the value of the net was propagated from a test signal or a logic constant. A logic_z value indicates that the net is
being driven by a tristate buffer whose control signal is not active. A no_value value indicates that the net is not in the path of a test signal or logic constant. The
specified test signal value is propagated by running the check_dft_rules command.
Related Information
Affected by these constraints: define_shift_enable
define_test_mode
Related attribute: (pin) dft_constant_value
hpin Attributes for DFT
dft_cloned_port_master
dft_constant_value
dft_controllable
dft_dedicated_wrapper_reason
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Design for Test--hnet Attributes for DFT
dft_driven_by_clock
dft_opcg_domain_clock_pin
dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
pmbist_dft_controllable
user_differential_negative_pin
user_from_core_data
user_from_core_enable
user_test_receiver_acmode
user_test_receiver_data_output
user_test_receiver_init_clock
user_test_receiver_init_data
user_to_core_data
user_to_core_enable
wrapper_control
wrapper_segment
wrapper_type
dft_cloned_port_master
dft_cloned_port_master {hpin | pin | constant | pg_pin | hport | port}
Default: no value
Read-only hpin attribute. Specifies the master pin of a cloned DFT port.
dft_constant_value
dft_constant_value {logic_0 | logic_1 | logic_z | no_value}
Read-only hpin attribute. Indicates whether the value of the pin was propagated from a test signal or a logic constant. A logic_z value indicates that the pin is
being driven by a tristate buffer whose control signal is not active. A no_value value indicates that the pin is not in the path of a test signal or logic constant. The
specified test signal value is propagated by running the check_dft_rules command.
Related Information
Affected by these constraints: define_shift_enable
define_test_mode
Related attribute: (net) dft_constant_value
dft_controllable
dft_controllable string
Read-write hpin attribute. Specifies the logical connectivity across the pins of a blackbox module, from an input port to an output port. Otherwise, when your
design has blackbox modules on the test control path, such as the path to the clock, or asynchronous set/reset pins, the check_dft_rules command cannot
detect whether a direct path exists from a primary input to the flip-flop’s clock pin, set pins, or reset pins of the module; and it reports a DFT violation.
This attribute is set on the output pin of a direct path from an input port to an output port of a blackbox. The attribute value has the following format:
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"input_pin_name {non_inverting | inverting}"
The value specifies the name of the input pin followed by an indication of whether the path to the output pin is inverted or not.
You must define this attribute prior to running the check_dft_rules command.
Related Information
Affects this command: check_dft_rules
Related attribute: (pin) dft_controllable
dft_dedicated_wrapper_reason
dft_dedicated_wrapper_reason string
Read-Write hpin attribute. Specifies the reason behind putting dedicated wrapper.
dft_driven_by_clock
dft_driven_by_clock {false | true}
Read-only hpin attribute. Indicates whether this pin is driven by a clock.
Example
genus:/designs/test> get_db [get_db pins */g471/A] .dft_driven_by_clockfalse
Related Information
Affected by this command: connect_scan_chains
Related attributes: (port) dft_driven_by_clock
(hport) dft_driven_by_clock
dft_opcg_domain_clock_pin
dft_opcg_domain_clock_pin {false | true}
Default: false
Read-write hpin attribute. This attribute is set in the scan abstract and specifies whether this input pin is connected to an OPCG test clock.
This attribute applies only to input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (port) dft_opcg_domain_clock_pin
(hport) dft_opcg_domain_clock_pin
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dft_opcg_domain_fanout_pin
dft_opcg_domain_fanout_pin pin_list
Read-write hpin attribute. This attribute is set in the scan abstract and returns a list of input pins or ports that are directly feeding the output pin.
In this case, the clock domains propagated from this output port will be the same as the clock domains from the corresponding input ports.
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hport) dft_opcg_domain_fanout_pin
(pin) dft_opcg_domain_fanout_pin
(port) dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_launch_clock pin_list
Read-write hpin attribute. This attribute is set in the scan abstract and returns a list of clock pins that correspond to the clock domain that launch the data on
this output pin. The information is used to propagate the clock domain from this output port of the abstract model.
If the data is launched by an internal clock domain that has no corresponding output port, an empty string will be included. In this case, UNKNOWN will be
propagated from this output port of the abstract model.
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hport) dft_opcg_domain_launch_clock
(pin) dft_opcg_domain_launch_clock
(port) dft_opcg_domain_launch_clock
dft_opcg_domain_se_input_pin
dft_opcg_domain_se_input_pin se_pin
Read-write hpin attribute. This attribute is set in the scan abstract and specifies the input pin of the blocking shift enable signal that corresponds to this clock
pin.
This attribute applies only to clock input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
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Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hport) dft_opcg_domain_se_input_pin
(pin) dft_opcg_domain_se_input_pin
(port) dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
dft_opcg_domain_unfenced_capture {clock_pin_list | NONE | INTERNAL | ""}
Read-write hpin attribute. This attribute is set in the scan abstract and indicates whether additional domain blocking is required at this input pin of the abstract
model.
The attribute can have the following values:
clock_pin_list Specifies the list of clock pins which capture the data without fencing. When the pin is driven by a clock domain other than the ones listed,
additional fencing logic is required.
INTERNAL Indicates that the data is captured by an internal clock domain that has no corresponding output port. In this case, additional domain
blocking will be required.
NONE Indicates that the data is not captured by any flop. It implies that all endpoints of this pin are fenced.
"" An empty string will be treated like INTERNAL.
This attribute applies only to input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hport) dft_opcg_domain_unfenced_capture
(pin) dft_opcg_domain_unfenced_capture
(port) dft_opcg_domain_unfenced_capture
pmbist_dft_controllable
pmbist_dft_controllable string
Read-write hpin attribute. Defines the controllability of clocks through the clock gates for the PMBIST logic.
The attribute value has the following format:
"input_pin_name {non_inverting | inverting}"
The value specifies the name of the input pin followed by an indication of whether the path to the output pin is inverted or not.
This attribute is set by the tool. You should not change its value.
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Related Information
Affects this command: check_dft_rules
(pin) pmbist_dft_controllable
user_differential_negative_pin
user_differential_negative_pin string
Read-write hpin attribute. Specifies the negative-leg pad pin that is associated with the pad cell instance positive-leg pad pin.
negative-leg_pad_pin_name pad_cell_instance_positive-leg_pad_pin_name
Related Information
Affects this command: add_jtag_boundary_scan
user_from_core_data
user_from_core_data string
Read-write hpin attribute. Specify the name of the corresponding from-core data pin of a pad pin on an I/O pad instance. It is possible to specify different from-
core data pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of multi-
pad instances such as SERDES blocks.
from_core_data_pin_name pad_cell_instance_pad_pin_name
Related Information
Affects this command: add_jtag_boundary_scan
user_from_core_enable
user_from_core_enable string
Read-write hpin attribute. Specify the name of the corresponding from-core enable pin of a pad pin on an I/O pad instance. It is possible to specify different
from-core enable pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of
multi-pad instances such as SERDES blocks.
An active low output enable is specified using the! character in front of the output_enable pin name.
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_acmode
user_test_receiver_acmode string
Read-write hpin attribute. Specifies the name of the test receiver pin for AC and DC mode control.
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Design for Test--hnet Attributes for DFT
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_data_output
user_test_receiver_data_output string
Read-write hpin attribute. Specifies the name of the test receiver input from the boundary cell.
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_init_clock
user_test_receiver_init_clock string
Read-write hpin attribute. Specifies the name of the test receiver clock to latch data from the boundary cell.
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_init_data
user_test_receiver_init_data string
Read-write hpin attribute. Specifies the name of the test receiver input from the boundary cell.
Related Information
Affects this command: add_jtag_boundary_scan
user_to_core_data
user_to_core_data string
Read-write hpin attribute. Specify the name of the corresponding to-core data pin of a pad pin on an I/O pad instance. It is possible to specify different to-core
data pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of multi-pad
instances such as SERDES blocks.
to_core_data_pin_name pad_cell_instance_pad_pin_name
An inversion on the data path is specified using the! character in front of the to_core pin name.
Related Information
Affects this command: add_jtag_boundary_scan
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Design for Test--hnet Attributes for DFT
user_to_core_enable
user_to_core_enable string
Default: none
Read-write hpin attribute. Specify the name of the corresponding to-core enable pin of a pad pin on an I/O pad instance. It is possible to specify different to-core
enable pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of multi-pad
instances such as SERDES blocks.
Related Information
Affects this command: add_jtag_boundary_scan
wrapper_control
wrapper_control {false | true }
Default: false
Read-write hpin attribute. Specifies that a wrapper control signal is applied to the pin.
Related Information
Related attributes: (hport) wrapper_control
(pin) wrapper_control
(port) wrapper_control
wrapper_segment
wrapper_segment string
Read-write hpin attribute. Lists the wrapper segments associated with the pin.
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hport) wrapper_control
(pin) wrapper_control
(port) wrapper_control
wrapper_type
wrapper_type {dedicated | shared}
Read-write hpin attribute. Specifies whether the wrapper segment associated with the pin is a dedicated or shared wrapper segment.
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Design for Test--hport Attributes for DFT
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hport) wrapper_control
(pin) wrapper_control
(port) wrapper_control
hport Attributes for DFT
dft_dedicated_wrapper_reason
dft_driven_by_clock
dft_opcg_domain_clock_pin
dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
wrapper_control
wrapper_segment
wrapper_type
dft_dedicated_wrapper_reason
dft_dedicated_wrapper_reason string
Read-Write hport attribute. Specifies the reason behind putting dedicated wrapper.
dft_driven_by_clock
dft_driven_by_clock {false | true}
Read-only hport attribute. Indicates whether this hierarchical port is driven by a clock.
Related Information
Affected by this command: connect_scan_chains
Related attributes: (pin) dft_driven_by_clock
(port) dft_driven_by_clock
dft_opcg_domain_clock_pin
dft_opcg_domain_clock_pin {false | true}
Default: false
Read-write hport attribute. This attribute is set in the scan abstract and specifies whether this input port is connected to an OPCG test clock.
This attribute applies only to input pins or ports.
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Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (pin) dft_opcg_domain_clock_pin
(port) dft_opcg_domain_fanout_pin
dft_opcg_domain_fanout_pin
dft_opcg_domain_fanout_pin pin_list
Read-write hport attribute. This attribute is set in the scan abstract and returns a list of input pins or ports that are directly feeding the output port.
In this case, the clock domain propagated from this output port should be the same as the clock domain from the corresponding input ports.
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_fanout_pin
(pin) dft_opcg_domain_fanout_pin
(port) dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_launch_clock pin_list
Read-write hport attribute. This attribute is set in the scan abstract and returns a list of clock pins that correspond to the clock domain that launch the data on
this output port. The information is used to propagate the clock domain from this output port of the abstract model. If the data is launched by an internal clock
domain that has no corresponding output port, an empty string will be included. In this case, UNKNOWN will be propagated from this output port of the abstract
model.
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_launch_clock
(pin) dft_opcg_domain_launch_clock
(port) dft_opcg_domain_launch_clock
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Design for Test--hport Attributes for DFT
dft_opcg_domain_se_input_pin
dft_opcg_domain_se_input_pin se_pin
Read-write hport attribute. This attribute is set in the scan abstract and specifies the input pin of the blocking shift enable signal that corresponds to this clock
port.
This attribute applies only to clock input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_se_input_pin
(pin) dft_opcg_domain_se_input_pin
(port) dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
dft_opcg_domain_unfenced_capture {clock_pin_list | NONE | INTERNAL | ""}
Read-write hport attribute. This attribute is set in the scan abstract and indicates whether additional domain blocking is required at this input port of the
abstract model.
The attribute can have the following values:
clock_pin_list Specifies the list of clock pins which capture the data without fencing. When the pin is driven by a clock domain other than the ones listed,
additional fencing logic is required.
INTERNAL Indicates that the data is captured by an internal clock domain that has no corresponding output port. In this case, additional domain
blocking will be required.
NONE Indicates that the data is not captured by any flop. It implies that all endpoints of this pin are fenced.
"" An empty string will be treated like INTERNAL.
This attribute applies only to input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_unfenced_capture
(pin) dft_opcg_domain_unfenced_capture
(port) dft_opcg_domain_unfenced_capture
wrapper_control
wrapper_control {false | true }
Default: false
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Read-write hport attribute. Specifies that a wrapper control signal is applied to the hierarchical port.
Related Information
Related attributes: (hpin) wrapper_control
(pin) wrapper_control
(port) wrapper_control
wrapper_segment
wrapper_segment string
Read-write hport attribute. Lists the wrapper segments associated with the hierarchical port.
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hpin) wrapper_segment
(pin) wrapper_segment
(port) wrapper_segment
wrapper_type
wrapper_type {dedicated | shared}
Read-write hport attribute. Specifies whether the wrapper segment associated with the hport is a dedicated or shared wrapper segment.
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hpin) wrapper_type
(pin) wrapper_type
(port) wrapper_type
jtag_instruction_register Attributes for DFT
capture
capture string
Read-write jtag_instruction_register attribute. Specifies the values that must be captured into the instruction register.
The attribute value corresponds to the value specified for the -capture option when the instruction register was defined.
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Design for Test--jtag_instruction Attributes for DFT
Related Information
Set by this command: define_jtag_instruction_register
Related attribute: (jtag_instruction)capture
length
length integer
Read-write jtag_instruction_register attribute. Specifies the length of the instruction register.
The attribute value corresponds to the value specified for the -length option when the instruction register was defined.
Related Information
Set by this command: define_jtag_instruction_register
Related attribute: (jtag_instruction)length
jtag_instruction Attributes for DFT
capture
length
opcode
private
register
register_capturedr
register_capturedr_state
register_clockdr
register_decode
register_reset
register_reset_polarity
register_runidle
register_shiftdr
register_shiftdr_polarity
register_shiftdr_state
register_tck
register_tdi
register_tdo
register_updatedr
register_updatedr_state
tap_decode
tap_tdi
tap_tdo
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Design for Test--jtag_instruction Attributes for DFT
capture
capture string
Read-write jtag_instruction attribute. Specifies the values that must be captured into the register listed in the register attribute during the CaptureDR state.
The attribute value corresponds to the value specified for the -capture option when the instruction was defined.
length
length integer
Read-write jtag_instruction attribute attribute. Specifies the length of the register listed in the register attribute.
The attribute value corresponds to the value specified for the -length option when the instruction was defined.
opcode
opcode string
Read-only jtag_instruction attribute. Returns the binary code for this instruction. The number of bits in the opcode is determined by the length of the
instruction register.
The attribute value corresponds to the value specified for the -opcode option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
private
private {false | true}
Default: false
Read-write jtag_instruction attribute. Indicates whether the instruction is defined for a private register.
The attribute value corresponds to the value specified for the -private option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register
register string
Read-write jtag_instruction attribute. Specifies the name of the custom test data register (TDR) for which the instruction is defined.
The attribute value corresponds to the value specified for the -register option when the instruction was defined. The attribute has no value for
mandatory instructions.
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Related Information
Set by this command: define_jtag_instruction
register_capturedr
register_capturedr {constant | pin | pgpin | port | subport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_CAPTUREDR pin
on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_capturedr option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_capturedr_state
register_capturedr_state {constant | pin | pgpin | port | subport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the
JTAG_CAPTUREDR_STATE pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_capturedr_state option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_clockdr
register_clockdr {constant | pin | pgpin | port | subport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_CLOCKDR pin on
the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_clockdr option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_decode
register_decode {constant | pin | pgpin | port | subport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the
JTAG_INSTRUCTION_DECODE_instruction pin on the JTAG_MACRO, where instruction is the name of the defined instruction.
The attribute value corresponds to the value specified for the -register_decode option when the instruction was defined.
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Related Information
Set by this command: define_jtag_instruction
register_reset
register_reset {constant | pin | pgpin | port | subport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_RESET pin on
the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_reset option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_reset_polarity
register_reset_polarity {high | low}
Read-write jtag_instruction attribute. Specifies the polarity of the pin on the custom test data register (TDR) that must be connected to the JTAG_RESET pin on
the JTAG_MACRO.
Related Information
Set by this command: define_jtag_instruction
register_runidle
register_runidle {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_RUNIDLE pin on
the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_runidle option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_shiftdr
register_shiftdr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_SHIFTDR pin on
the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_shiftdr option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
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Design for Test--jtag_instruction Attributes for DFT
register_shiftdr_polarity
register_shiftdr_polarity {high | low}
Read-write jtag_instruction attribute. Specifies the polarity of the pin on the custom test data register (TDR) that must be connected to the JTAG_SHIFTDR pin
on the JTAG_MACRO.
Related Information
Set by this command: define_jtag_instruction
register_shiftdr_state
register_shiftdr_state {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_SHIFTDR_STATE
pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_shiftdr_state option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_tck
register_tck {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_instructionattribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_TCK pin on the
JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_tck option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_tdi
register_tdi {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_TDI pin on the
JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_tdi option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_tdo
register_tdo {constant | pin | hpin | pgpin | port | hport}
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Design for Test--jtag_instruction Attributes for DFT
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_register_TDO
pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_tdo option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_updatedr
register_updatedr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the JTAG_UPDATEDR pin
on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_updatedr option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
register_updatedr_state
register_updatedr_state {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_instruction attribute. Specifies the name of the pin on the custom test data register (TDR) that must be connected to the
JTAG_UPDATEDR_STATE pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -register_updatedr_state option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
tap_decode
tap_decode {constant | pin | hpin | pgpin | port | hport}
Default: JTAG_INSTRUCTION_DECODE_instruction
Read-write jtag_instruction attribute. Specifies the name of the instruction-specific decode pin that must be created on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -tap_decode option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
tap_tdi
tap_tdi {constant | pin | hpin | pgpin | port | hport}
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Design for Test--jtag_macro Attributes for DFT
Default: JTAG_TDI
Read-write jtag_instruction attribute. Specifies the name of the test data input pin on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -tap_tdi option when the instruction was defined.
Related Information
Set by this command: define_jtag_instruction
tap_tdo
tap_tdo {constant | pin | hpin | pgpin | port | hport}
Default: JTAG_register_TDO
Read-write jtag_instruction attribute. Specifies the name of the instruction-specific test data output (TDO) pin that must be created on the JTAG_MACRO.
The attribute value corresponds to the value specified for the -tap_tdo option when the instruction was defined. The attribute has no value for mandatory
instructions.
Related Information
Set by this command: define_jtag_instruction
jtag_macro Attributes for DFT
boundary_tdo
bsr_clockdr
bsr_shiftdr
bsr_updatedr
capturedr
capturedr_state
clockdr
dot6_acdcsel
dot6_acpulse
dot6_preset_clock
dot6_trcell_enable
exitdr
highz
instance
mode_a
mode_b
mode_c
por
reset
runidle
select_wir
shiftdr
shiftdr_state
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Design for Test--jtag_macro Attributes for DFT
tck
tdi
tdo
tdo_enable
tms
trst
updatedr
updatedr_state
user_defined_macro
boundary_tdo
boundary_tdo {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the boundary-register TDO input pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
bsr_clockdr
bsr_clockdr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the clock data register (CLOCKDR) output pin for the boundary-scan register.
Related Information
Set by this command: define_jtag_macro
bsr_shiftdr
bsr_shiftdr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the shift data register (SHIFTDR) output pin for the boundary-scan register.
Related Information
Set by this command: define_jtag_macro
bsr_updatedr
bsr_updatedr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the update data register (UPDATEDR) output pin for the boundary-scan register.
Related Information
Set by this command: define_jtag_macro
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Design for Test--jtag_macro Attributes for DFT
capturedr
capturedr {constant | hpin | hport | pg_pin | pin | port}
Read-write jtag_macro attribute. Specifies the capture data register (CAPTUREDR) output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
capturedr_state
capturedr_state {constant | hpin | hport | pg_pin | pin | port}
Read-write jtag_macro attribute. Specifies the capture data register (CAPTUREDR_STATE) output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
clockdr
clockdr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the clock data register (CLOCKDR) output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
dot6_acdcsel
dot6_acdcsel {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the logical OR of the decoded EXTEST_PULSE and EXTEST_TRAIN instructions.
Related Information
Set by this command: define_jtag_macro
dot6_acpulse
dot6_acpulse {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the AC test signal output of the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
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Design for Test--jtag_macro Attributes for DFT
dot6_preset_clock
dot6_preset_clock {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the positive-active edge-sensitive clock signal to test receivers that have edge-sensitive initialization.
Related Information
Set by this command: define_jtag_macro
dot6_trcell_enable
dot6_trcell_enable {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the logical OR of EXTEST, EXTEST_PULSE and EXTEST_TRAIN used to enable the test receiver cells
Related Information
Set by this command: define_jtag_macro
exitdr
exitdr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the EXIT1DR data register output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
highz
highz {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the highz output pin to place the I/O pads in their HIGHZ state.
Related Information
Set by this command: define_jtag_macro
instance
instance string
Read-write jtag_macro attribute. Specifies the instance of the module where the JTAG_Macro resides.
Related Information
Set by this command: define_jtag_macro
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Design for Test--jtag_macro Attributes for DFT
mode_a
mode_a {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the mode_a output pin to configure boundary-cells in the boundary-scan register.
Related Information
Set by this command: define_jtag_macro
mode_b
mode_b {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the mode_b output pin to configure boundary-cells in the boundary-scan register.
Related Information
Set by this command: define_jtag_macro
mode_c
mode_c {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the mode_c output pin to configure boundary-cells in the boundary-scan register.
Related Information
Set by this command: define_jtag_macro
por
por {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the power-on reset input pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
reset
reset {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the reset output pin indicating the JTAG_Macro is in the Test-Logic-Reset state.
Related Information
Set by this command: define_jtag_macro
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Design for Test--jtag_macro Attributes for DFT
runidle
runidle {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the runidle output pin indicating the JTAG_Macro is in the Run-Test-Idle state.
Related Information
Set by this command: define_jtag_macro
select_wir
select_wir {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the JTAG_SELECTWIR pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
shiftdr
shiftdr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the shift data register (SHIFTDR) output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
shiftdr_state
shiftdr_state {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the shift data register (SHIFTDR_STATE) output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
tck
tck {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the TAP controller TCK input pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
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Design for Test--jtag_macro Attributes for DFT
tdi
tdi {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the TAP controller TDI input pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
tdo
tdo {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the TAP controller TDO input pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
tdo_enable
tdo_enable {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the the enable output pin that drives the JTAG TDO output enable pin.
Related Information
Set by this command: define_jtag_macro
tms
tms_enable {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the TAP controller TMS input pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
trst
trst {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the TAP controller TRST input pin on the JTAG_Macro.
Related Information
Set by this command: define_jtag_macro
March 2025 1370 Product Version 23.1
Genus Attribute Reference
Design for Test--jtag_port Attributes for DFT
updatedr
updatedr {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the update data register (UPDATEDR) output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
updatedr_state
updatedr_state {constant | pin | hpin | pgpin | port | hport}
Read-write jtag_macro attribute. Specifies the update data register (UPDATEDR_STATE) output pin for the custom test data register.
Related Information
Set by this command: define_jtag_macro
user_defined_macro
user_defined_macro {true | false}
Default: true
Read-write jtag_macro attribute. Indicates whether the JTAG_Macro has been defined by the user.
This attribute can have the following values:
true Indicates that an existing JTAG_Macro has been defined by the user.
false Indicates that the JTAG_Macro has been inserted by the tool.
Related Information
Set by this command: define_jtag_macro
jtag_port Attributes for DFT
aio_pin
bcell_location
bcell_required
bcell_segment
bcell_type
bdy_enable
bdy_in
bdy_out
bsr_dummy_after
bsr_dummy_before
cell
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Genus Attribute Reference
Design for Test--jtag_port Attributes for DFT
comp_enable
custom_bcell
differential
pinmap
sys_enable
sys_use
test_use
tr_bdy_in
tr_cell
trcell_acmode
trcell_clock
trcell_enable
aio_pin
aio_pin {false | true}
Default: false
Read-write jtag_port attribute. Specifies whether a JTAG port is an advanced I/O port per the IEEE1149.6 standard.
bcell_location
bcell_location string
Read-write jtag_port attribute. Specifies the location of the boundary cell for this port.
Related Information
Set by these commands: add_jtag_boundary_scan
bcell_required
bcell_required {false | true}
Default: false
Read-write jtag_port attribute. Specifies whether a boundary cell is required for this type of port.
Related Information
Set by these commands: add_jtag_boundary_scan
bcell_segment
bcell_segment string
Default: none
Read-write jtag_port attribute. Specifies the name of the boundary-scan segment that is connected to the port.
March 2025 1372 Product Version 23.1
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Design for Test--jtag_port Attributes for DFT
Related Information
Affects these commands: define_jtag_boundary_scan_segment
add_jtag_boundary_scan
add_jtag_macro
bcell_type
bcell_type string
Default: bc_undefined
Read-write jtag_port attribute. Specifies the name of the boundary cell associated with the port. Initially the attribute value defaults to bc_undefined. The
attribute value is updated to reflect the boundary cell name when boundary-scan cells are inserted for the functional ports. For TAP ports and dedicated test
ports, the attribute value remains as bc_undefined.
Possible values are: bc_undefined, bc_in, bc_in_nt, bc_in_sio, bc_in_ti, bc_out, bc_out_nt, bc_out_ti, bc_out_to, bc_out_to_oo, bc_bidir,
bc_bidir_obs, bc_bidir_ti, bc_bidir_to, bc_bidir_to_oo, bc_bidir_od, bc_clkin, bc_clkin_nt, bc_enab_nt, bc_11496_out, bc_11496_out_nt,
bc_11496_out_ti, bc_11496_out_to, bc_11496_out_to_oo, bc_11496_bidir, bc_11496_bidir_ti, bc_11496_bidir_to, bc_11496_bidir_to_oo,
bc_11496_actr
Related Information
Set by these commands: add_jtag_boundary_scan
bdy_enable
bdy_enable {pin|port}
Read-write jtag_port attribute. Specifies the name of the pin on which the enable boundary cell for the port is inserted. This attribute is only be set on ports
with bidirectional and tristate pads.
A port that was excluded for boundary-scan insertion, will have an attribute value of NULL.
Related Information
Set by these commands: add_jtag_boundary_scan
bdy_in
bdy_in {pin|port}
Read-write jtag_port attribute. Specifies the name of the pin on which the boundary cell is or must be inserted. The pin is an output pin of an input pad cell.
A port that was excluded for boundary-scan insertion, will have an attribute value of NULL.
Related Information
Set by these commands: add_jtag_boundary_scan
bdy_out
bdy_out {pin|port}
Read-write jtag_port attribute. Specifies the name of the pin on which the boundary cell is or must be inserted. The pin is an input pin of an output pad cell.
A port that was excluded for boundary-scan insertion, will have an attribute value of NULL.
March 2025 1373 Product Version 23.1
Genus Attribute Reference
Design for Test--jtag_port Attributes for DFT
Related Information
Set by these commands: add_jtag_boundary_scan
bsr_dummy_after
bsr_dummy_after integer
Default: 0
Read-write jtag_port attribute. Specifies the number of dummy boundary cells to add after the boundary cell for this JTAG port (toward the TDI port) in the
BSDL description.
Use this attribute when the (custom) boundary-scan macro has more than one SHIFT/CAPTURE latch associated with the I/O.
Related Information
bsr_dummy_before
bsr_dummy_before integer
Default: 0
Read-write jtag_port attribute. Specifies the number of dummy boundary cells to add before the boundary cell for this JTAG port (toward the tdo port) in the
BSDL description.
Use this attribute when the (custom) boundary-scan macro has more than one SHIFT/CAPTURE latch associated with the I/O.
Related Information
cell
cell lib_cell
Read-write jtag_port attribute. Specifies the name of the pad cell inserted on this port.
Related Information
Set by these commands: add_jtag_boundary_scan
comp_enable
comp_enable {low|high}
Read-write jtag_port attribute. Specifies the compliance enable value of this port.
This attribute applies only for dedicated test-related signals such as the test-mode and shift-enable signals.
Related Information
Set by these commands: add_jtag_boundary_scan
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Design for Test--jtag_port Attributes for DFT
custom_bcell
custom_bcell string
Read-write jtag_port attribute. Specifies the name of custom boundary cell (to be) inserted on this port.
Related Information
Set by these commands: add_jtag_boundary_scan
differential
differential port_name
Read-write jtag_port attribute. Specifies the name of the negative leg port that is associated with the positive leg port (of a differential port) on which it is
defined.
Related Information
Set by this command: add_jtag_boundary_scan
Related command: define_jtag_boundary_scan_segment
pinmap
pinmap string
Read-write jtag_port attribute. Specifies the name of the corresponding package pin.
This attribute value will be empty if no pinmap file was specified when inserting boundary scan.
Related Information
Set by these commands: add_jtag_boundary_scan
sys_enable
sys_enable {pin|port}
Read-write jtag_port attribute. Specifies the pin used to control the enable pin on bidirectional and tristate pads. System or functional I/O enables can be
driven either from internal core logic or from another signal coming on-chip through a top-level port.
Related Information
Set by these commands: add_jtag_boundary_scan
sys_use
sys_use string
Read-write jtag_port attribute. Specifies the functional use of the port.
Possible values are clock, input, output, enable, none or undefined.
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Design for Test--jtag_port Attributes for DFT
For each unique sys_enable statement in the IOSpecList input file, a separate sys_use=ENABLE statement is also specified to indicate that a boundary cell
is to be inserted for the output enable or tristate control pins for output3 or bidirectional pads, and to define boundary_cell position in the boundary-scan
register.
A port that was excluded for boundary-scan insertion, will have an attribute value of none. A TAP port has an attribute value of undefined.
Related Information
Set by these commands: add_jtag_boundary_scan
test_use
test_use string
Read-write jtag_port attribute. Specifies the test use of the port.
This attribute can have the following values:
cme Port is used for channel mask enable
cmle Port is used for channel mask load enable
cust_clock Port has special use for test clock
cust_enable Port has special use for test enable
mrd Port is used for misr read
mre Port is used for misr enable
mrst Port is used for misr reset
mtc Reserved for future usage
none Port has no test usage
observe_in Port is used to observe on an input
observe_out Port is used to observe on an output
opmisr Port is used to enable opmisr compression
opmisr_plus Port is used to enable opmisr_plus compression
opplus Port is used to enable opmisr_plus compression
scan_enable Port is used for scan enable
scan_in Port is used for scan_in
scan_out Port is used for scan_out
sclk Port is used for scan clock positive edge
sclkneg Port is used for scan clock negative edge
scomp Port is used for compression enable
spread Port is used for spread enable
tclk Port is used for test clock positive edge
tclkasy Port is used for test clock asynchronous positive edge
tclkasyneg Port is used for test clock asynchronous negative edge
tclkneg Port is used for test clock negative edge
test_enable Port is used for test enable
March 2025 1376 Product Version 23.1
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Design for Test--jtag_port Attributes for DFT
A port that was excluded for boundary-scan insertion, will have an attribute value of none. A TAP port has an attribute value of undefined.
Related Information
Set by these commands: add_jtag_boundary_scan
tr_bdy_in
tr_bdy_in {pin|port|bus}
Read-write jtag_port attribute. Specifies the test receiver output pin associated with the JTAG port. This is this the pin on which the BC_11496_ACTR boundary
cell is or must be inserted.
Related Information
Set by these commands: add_jtag_boundary_scan
tr_cell
trcell string
Read-write jtag_port attribute. Specifies the test receiver cell for the port.
Related Information
Set by these commands: add_jtag_boundary_scan
trcell_acmode
trcell_acmode {pin|port|bus}
Read-write jtag_port attribute. Specifies the test AC mode pin associated with the JTAG port.
Related Information
Set by these commands: add_jtag_boundary_scan
trcell_clock
trcell_clock {pin|port|bus}
Read-write jtag_port attribute. Specifies the test receiver clock pin associated with the JTAG port.
Related Information
Set by these commands: add_jtag_boundary_scan
trcell_enable
trcell_enable {pin|port|bus}
Read-write jtag_port attribute. Specifies the test receiver enable pin associated with the JTAG port.
March 2025 1377 Product Version 23.1
Genus Attribute Reference
Design for Test--mbist_clock Attributes for DFT
Related Information
Set by these commands: add_jtag_boundary_scan
mbist_clock Attributes for DFT
dft_hookup_pin
dft_hookup_polarity
hookup_period
internal
is_jtag_tck
is_srclk
period
pmbist_amu_siu_pipeline_controls
pmbist_fcu_ciu_pipeline_controls
sources
dft_hookup_pin
dft_hookup_pin {pin | port}
Read-only mbist_clock attribute. Returns the path to the pin or port where the mbist clock actually hooks up inside the core.
Example
geus:/designs/test> get_db [get_db mbist_clocks clk] .dft_hookup_pin
/designs/test/instances_comb/clk_mux/pins_out/Y
Related Information
Set by this constraint: define_mbist_clock
dft_hookup_polarity
dft_hookup_polarity {inverted | non_inverted}
Read-only mbist_clock attribute. Indicates whether the test signal is inverted or not at the hookup pin or port.
Related Information
Set by this constraint: define_mbist_clock
hookup_period
hookup_period integer
Default: same value as period
Read-only mbist_clock attribute. Returns the value specified using the -hookup_period option of the define_mbist_clock command.
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Design for Test--mbist_clock Attributes for DFT
Related Information
Set by this constraint: define_mbist_clock
internal
internal {false|true}
Read-only mbist_clock attribute. Indicates whether the source of the MBIST clock is internal to the design (for example, from an analog block). Set by the -
internal_clock_source option of the define_mbist_clock command.
Related Information
Set by this constraint: define_mbist_clock
is_jtag_tck
is_jtag_tck {false| true}
Read-only mbist_clock attribute. Indicates whether this MBIST clock is defined as a JTAG clock.
Related Information
Set by this constraint: define_mbist_clock
is_srclk
is_srclk {false| true}
Read-only mbist_clock attribute. Indicates whether this MBIST clock is defined as a repair clock.
Related Information
Set by this constraint: define_mbist_clock
period
period integer
Read-only mbist_clock attribute. Returns the value specified using the -period option of the define_mbist_clock command.
Related Information
Set by this constraint: define_mbist_clock
pmbist_amu_siu_pipeline_controls
pmbist_amu_siu_pipeline_controls {<integer1> <integer2>}
Read-write mbist_clock attribute. Controls whether inter-block signal pipeline is requested between algorithm memory unit(AMU) and sequence iterator
unit(SIU).
When value is set, the pipelining is implemented between signals of AMU and SIU.
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Design for Test--memory_data_bit_structure Attributes for DFT
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affects these commands: add_pmbist
add_hard_repair
pmbist_fcu_ciu_pipeline_controls
pmbist_fcu_ciu_pipeline_controls string
Read-write mbist_clock attribute. Specifies the maximum fanout for intermediate pipelines and receivers for signals between fuse control unit and channel
interface unit.
sources
sources string
Read-only mbist_clock attribute. Returns the port that is the source or test time control for an internal clock of the MBIST clock waveform.
Related Information
Set by this constraint: define_mbist_clock
memory_data_bit_structure Attributes for DFT
column_order
column_order string
Read-only memory_data_bit_structure attribute. Returns the order of columns in this data-bit of the memory, which was specified using the address_partition
specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
partial_row_order
partial_row_order string
Read-only memory_data_bit_structure attribute. Returns the order of rows in the last row group in this data-bit of the memory, which was specified using the
address_partition specification in the PMBIST configuration file. It differs from the row_order attribute, only when the last row group is not fully populated.
Related Information
Set by this command: read_pmbist_memory_view
row_order
row_order string
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Design for Test--memory_lib_cell Attributes for DFT
Read-only memory_data_bit_structure attribute. Returns the order of rows in this data-bit of the memory, which was specified using the address_partition
specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_lib_cell Attributes for DFT
address_limit
data_order
memory_lib_cell
parallel_access_groups
port_action
port_access
port_alias
read_delay
redundancy
wrapper
write_mask_binding
address_limit
address_limit integer
Read-only memory_lib_cell attribute. Returns the number of used or addressable words in the memory, which was specified using the address_limit
specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
data_order
data_order string
Read-only memory_lib_cell attribute. Returns the physical order of the data-bits within the memory word, which was specified using the data_order
specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_lib_cell
memory_lib_cell string
Read-only memory_lib_cell attribute. Returns the path to the corresponding memory lib_cell in the library.
March 2025 1381 Product Version 23.1
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Design for Test--memory_lib_cell Attributes for DFT
Related Information
Set by this command: read_pmbist_memory_view
parallel_access_groups
parallel_access_groups list_of_physical_memories
Read-only memory_lib_cell attribute. Returns the list of all physical memories inside a logical memory, that can be accessed in parallel.
port_action
port_action list_of_memory_lib_pin_actions
Read-only memory_lib_cell attribute. Returns the list of all memory_lib_pin_action objects for this memory_lib_cell.
port_access
port_access list_of_memory_lib_pin_access
Read-only memory_lib_cell attribute. Returns the list of all memory_lib_pin_access objects for this memory_lib_cell.
port_alias
port_alias list_of_memory_lib_pin_alias
Read-only memory_lib_cell attribute. Returns the list of all memory_lib_pin_alias objects for this memory_lib_cell.
read_delay
read_delay integer
Read-only memory_lib_cell attribute. Returns the intrinsic read delay of the selected memory modules, which was specified using the read_delay specification
in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
redundancy
redundancy list_of_memory_spare_rows
Read-only memory_lib_cell attribute. Returns the list of memory_spare_row objects for this memory_lib_cell.
wrapper
wrapper string
Read-only memory_lib_cell attribute. Returns the wrapper module that contains the actual memory module, which was specified using the wrapper
specification in the MBIST configuration file.
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Design for Test--memory_lib_pin_access Attributes for DFT
Related Information
Set by this command: read_pmbist_memory_view
write_mask_binding
write_mask_binding list_of_write_mask_bits
Read-only memory_lib_cell attribute. Returns the list of write_mask_bit objects for this memory_lib_cell.
memory_lib_pin_access Attributes for DFT
fuse_cell
is_assign
memory_lib_cell
port_test
value
fuse_cell
fuse_cell string
Read-only memory_lib_pin_access attribute. Returns the parent fuse_cell with which these port_access pins are associated.
is_assign
is_assign {false | true}
Read-only memory_lib_pin_access attribute. Indicates whether the pin will be used to assign or sample a value during memory testing.
This is only supported for macro/core testing like ARM cores.
memory_lib_cell
memory_lib_cell string
Read-only memory_lib_pin_access attribute. Returns the parent memory_lib_cell with which these port_access pins are associated. The port_access pins can
have hierarchical references. These hierarchical references can have ".." type of constructs or "../.." (that is, multiple uses of ".."). The latter indicates that the pin
exists on a parent hierarchy of the memory_lib_cell instance (which can be multiple levels above the current hierarchy).
port_test
port_test objects
Read-only memory_lib_cell attribute. Specifies the list of memory_lib_pin_test objects.
value
value string
Read-only memory_lib_pin_access attribute. Returns the default inactive value provided by the user for the pin in the port_acess specification in the MBIST
configuration file..
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Design for Test--memory_lib_pin_action Attributes for DFT
memory_lib_pin_action Attributes for DFT
fuse_cell
fuse_cell string
Read-only memory_lib_pin_action attribute. Returns the parent fuse_cell with which these port_action pins are associated.
memory_lib_cell
memory_lib_cell string
Read-only memory_lib_pin_action attribute. Returns the parent memory_lib_cell with which these port_action pins are associated.
value
value string
Read-only memory_lib_pin_action attribute. Returns the value to which the memory port is controlled, which was specified using the port_action specification
in the MBIST configuration file. This value remains constant for the duration of the memory testing port.
memory_lib_pin_alias Attributes for DFT
base_port_name
fuse_cell
memory_lib_cell
base_port_name
base_port_name string
Read-only memory_lib_pin_alias attribute. Returns the recognized Liberty file base port name, which was specified using the port_alias specification in the
MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
fuse_cell
fuse_cell string
Read-only memory_lib_pin_action attribute. Returns the parent fuse_cell.
memory_lib_cell
memory_lib_cell string
Read-only memory_lib_pin_alias attribute. Returns the parent memory_lib_cell.
March 2025 1384 Product Version 23.1
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Design for Test--memory_spare_column_map_address Attributes for DFT
memory_spare_column_map_address Attributes for DFT
address_logical_value
address_logical_value string
Read-only memory_spare_column_map_address attribute. Returns the logical value for the address field, which was specified using the map keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
address_port
address_port string
Read-only memory_spare_column_map_address attribute. Returns the name of the address port, which was specified using the map keyword of the redundancy
specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_spare_column_map_data Attributes for DFT
data_logical_value
data_logical_value string
Read-only memory_spare_column_map_data attribute. Returns the logical value for the data field, which was specified using the data keyword of the redundancy
specification in the MBIST configuration file.
data_port
data_port string
Read-only memory_spare_column_map_data attribute. Returns the name of the data port, which was specified using the data keyword of the redundancy
specification in the MBIST configuration file.
memory_spare_column Attributes for DFT
address_bits
banks
bankspan
data_bits
db_block_size
enable
March 2025 1385 Product Version 23.1
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Design for Test--memory_spare_column_map_address Attributes for DFT
memory_lib_cell
srclk
sre
srsi
srso
srst
Note: These attributes contain information about spare column resources and are normally set when the configuration view file is read using the
read_memory_view command.
The attributes are read-only attributes, so you cannot set their values.
address_bits
address_bits string
Read-only memory_spare_column attribute. Returns the logical address bits used to specify spare columns or blocks of columns of the memory, which was
specified using the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
banks
banks string
Read-only memory_spare_column attribute. Returns the banks associated with this spare column resource, which was specified using the banks keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
bankspan
bankspan string
Read-only memory_spare_column attribute. Returns the bank span associated with this spare column resource which was specified using the bank_range
keyword of the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
data_bits
data_bits string
Read-only memory_spare_column attribute. Returns the data bits associated with this spare column resource, which was specified using the data keyword of the
redundancy specification in the MBIST configuration file.
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Design for Test--memory_spare_column_map_address Attributes for DFT
Related Information
Set by this command: read_pmbist_memory_view
db_block_size
db_block_size integer
Read-only memory_spare_column attribute. Returns the size of the spare data-bit block.
Related Information
Set by this command: read_pmbist_memory_view
enable
enable string
Read-only memory_spare_column attribute. Returns the enable signal associated with the repair register, which was specified using the map keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_lib_cell
memory_lib_cell string
Read-only memory_spare_column attribute. Returns the memory_lib_cell to which this spare column belongs.
srclk
srclk string
Read-only memory_spare_column attribute. Returns the register shift clock associated with the serial repair shift register, which was specified using the map
keyword of the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
sre
sre string
Read-only memory_spare_column attribute. Returns the enable input associated with the serial repair shift register, which was specified using the map keyword of
the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
March 2025 1387 Product Version 23.1
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Design for Test--memory_spare_row_map_address Attributes for DFT
srsi
srsi string
Read-only memory_spare_column attribute. Returns the shift input associated with the serial repair shift register, which was specified using the map keyword of
the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
srso
srso string
Read-only memory_spare_column attribute. Returns the shift output associated with the the serial repair register, which was specified using the map keyword of
the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
srst
srst string
Read-only memory_spare_column attribute. Returns the asynchronous reset input associated with the serial repair shift register, which was specified using the
map keyword of the redundancy specification in the MBIST configuration file.
memory_spare_row_map_address Attributes for DFT
address_logical_value
address_port
address_port_value
memory_spare_row
address_logical_value
address_logical_value string
Read-only memory_spare_row_map_address attribute. Returns the logical value for the address field, which was specified using the map keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
address_port
address_port string
Read-only memory_spare_row_map_address attribute. Returns the name of the address port, which was specified using the map keyword of the redundancy
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Design for Test--memory_spare_row Attributes for DFT
specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
address_port_value
address_port_value string
Read-only memory_spare_row_map_address attribute. Returns the enable value of the address port, which was specified using the map keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_spare_row
memory_spare_row string
Read-only memory_spare_row_map_address attribute. Returns the parent memory_spare_row object.
memory_spare_row Attributes for DFT
address_bits
banks
bankspan
data_bits
enable
memory_lib_cell
memory_spare_row_map
srclk
sre
srsi
srso
srst
address_bits
address_bits string
Read-only memory_spare_row attribute. Returns the logical address bits used to specify spare rows or blocks of rows of the memory, which was specified using
the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
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Genus Attribute Reference
Design for Test--memory_spare_row Attributes for DFT
banks
banks string
Read-only memory_spare_row attribute. Returns the banks associated with this spare row resource, which was specified using the banks keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
bankspan
bankspan string
Read-only memory_spare_row attribute. Returns the bank span associated with this spare row resource which was specified using the bank_range keyword of
the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
data_bits
data_bits string
Read-only memory_spare_row attribute. Returns the data bits associated with this spare row resource, which was specified using the data keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
enable
enable string
Read-only memory_spare_row attribute. Returns the enable signal associated with the repair register, which was specified using the map keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_lib_cell
memory_lib_cell string
Read-only memory_spare_row attribute. Returns the memory_lib_cell to which this spare row belongs.
memory_spare_row_map
memory_spare_row_map string
March 2025 1390 Product Version 23.1
Genus Attribute Reference
Design for Test--memory_spare_row Attributes for DFT
Read-only memory_spare_row attribute. Returns a list of memory_spare_row_map_address objects.
srclk
srclk string
Read-only memory_spare_row attribute. Returns the register shift clock associated with the serial repair shift register, which was specified using the map keyword
of the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
sre
sre string
Read-only memory_spare_row attribute. Returns the enable input associated with the serial repair shift register, which was specified using the map keyword of
the redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
srsi
srsi string
Read-only memory_spare_row attribute. Returns the shift input associated with the serial repair shift register, which was specified using the map keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
srso
srso string
Read-only memory_spare_row attribute. Returns the shift output associated with the serial repair shift register, which was specified using the map keyword of the
redundancy specification in the MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
srst
srst string
Read-only memory_spare_row attribute. Returns the asynchronous reset input associated with the serial repair shift register, which was specified using the map
keyword of the redundancy specification in the MBIST configuration file.
March 2025 1391 Product Version 23.1
Genus Attribute Reference
Design for Test--opcg_domain Attributes for DFT
Related Information
Set by this command: read_pmbist_memory_view
Related attribute: srst
opcg_domain Attributes for DFT
counter_length
divide_by
instance
max_num_pulses
min_domain_period
opcg_trigger
osc_source
scan_clock
shift_enable
counter_length
counter_length integer
Read-only opcg_domain attribute. Returns the number of bits in the down counter in the domain macro, which was specified using the -counter_length option
of the define_opcg_domain command.
Related Information
Set by this constraint: define_opcg_domain
divide_by
divide_by integer
Read-only opcg_domain attribute. Returns the value by which to divide the oscillator source frequency, which was specified using the -divide_by option of the
define_opcg_domain command.
Related Information
Set by this constraint: define_opcg_domain
instance
instance instance_name
Read-only opcg_domain attribute. Returns the name of the OPCG instance name, which was specified using the -instance option of the define_opcg_domain
command.
Related Information
Set by this constraint: define_opcg_domain
March 2025 1392 Product Version 23.1
Genus Attribute Reference
Design for Test--opcg_domain Attributes for DFT
max_num_pulses
max_num_pulses integer
Read-only opcg_domain attribute. Returns the number of pulses generated by the domain macro, which was specified using the -max_num_pulses option of the
define_opcg_domain_macro_parameters command.
Related Information
Set by this constraint: define_opcg_domain
min_domain_period
min_domain_period float
Read-only opcg_domain attribute. Returns the minimum period (in picoseconds) at which this OPCG domain can operate, which was specified using the -
min_domain_period option of the define_opcg_domain command.
Related Information
Set by this constraint: define_opcg_domain
opcg_trigger
opcg_trigger opcg_trigger
Read-only opcg_domain attribute. Returns the OPCG trigger for this OPCG domain, which was specified using the -opcg_trigger option of the define_opcg_domain
command.
Related Information
Set by this constraint: define_opcg_domain
osc_source
osc_source osc_source
Read-only opcg_domain attribute. Returns the oscillator source for this OPCG domain, which was specified using the -osc_source option of the
define_opcg_domain command.
Related Information
Set by this constraint: define_opcg_domain
scan_clock
scan_clock test_clock
Read-only opcg_domain attribute. Specifies the test clock that must drive the flops inside the domain macro during full scan mode.
March 2025 1393 Product Version 23.1
Genus Attribute Reference
Design for Test--opcg_mode Attributes for DFT
Related Information
Set by this constraint: define_opcg_trigger
Related command: define_test_clock
shift_enable
shift_enable test_clock
Read-only opcg_domain attribute. Returns the shift-enable signal to be connected to the OPCG domain when OPCG is inserted.
Related Information
Set by this constraint: define_opcg_domain
Related command: define_test_signal
opcg_mode Attributes for DFT
jtag_controlled
mode_init
osc_source_references
jtag_controlled
jtag_controlled {false |true}
Default: false
Read-write opcg_mode attribute. Specifies whether a JTAG instruction is used to lock the PLLs for OPCG operation, which was specified using the -
jtag_controlled option of the define_opcg_mode command.
Related Information
Set by this constraint: define_opcg_mode
mode_init
mode_init file
Read-write opcg_mode attribute. Returns the initialization sequence file for this OPCG mode, which was specified using the -mode_init option of the
define_opcg_mode command.
Related Information
Set by this constraint: define_opcg_mode
osc_source_references
osc_source_references list_of_osc_source_references
Read-only opcg_mode attribute. Returns a list of osc_source_reference objects. This is a computed attribute. Computed attributes are potentially very time
March 2025 1394 Product Version 23.1
Genus Attribute Reference
Design for Test--opcg_trigger Attributes for DFT
consuming to process and not listed by the vls command by default.
opcg_trigger Attributes for DFT
active
delay_cycles
inside_inst
instance
osc_source
scan_clock
test_signal
active
active {low | high}
Read-only opcg_trigger attribute. Returns the active value for the OPCG trigger signal, which was specified using the -active option of the
define_opcg_trigger command.
Related Information
Set by this constraint: define_opcg_trigger
Related attributes: (active_scan_segment) active
scan_segment) active
(test signal) active
delay_cycles
delay_cycles integer
Read-only opcg_trigger attribute. Returns an additional OPCG trigger delay that is applied internally to ensure that the scan enable has fully propagated in the
design before any OPCG domain clocks are pulsed when the scan enable signal is re-used as the OPCG trigger.
Related Information
Set by this constraint: define_opcg_trigger
inside_inst
inside_inst hier_instance
Read-only opcg_trigger attribute. Returns the name of the hierarchal instance in which the OPCG trigger macro must be inserted. This was specified using the -
inside option of the define_opcg_trigger command.
Related Information
Set by this constraint: define_opcg_trigger
March 2025 1395 Product Version 23.1
Genus Attribute Reference
Design for Test--osc_source_reference Attributes for DFT
instance
instance instance_name
Read-only opcg_trigger attribute. Returns the name of the OPCG trigger instance, which was specified using the -instance option of the define_dft
opcg_trigger command.
Related Information
Set by this constraint: define_opcg_trigger
osc_source
osc_source osc_source
Read-only opcg_trigger attribute. Returns the name of the oscillator source, which was specified using the -osc_source option of the define_opcg_trigger
command.
Related Information
Set by this constraint: define_opcg_trigger
scan_clock
scan_clock test_clock
Read-only opcg_trigger attribute. Specifies the test clock that must drive the flops inside the trigger macro during full scan mode.
Related Information
Set by this constraint: define_opcg_trigger
Related command: define_test_clock
test_signal
test_signal test_signal
Read-only opcg_trigger attribute. Specifies the test signal that must have function opcg_trigger or shift_enable.
Related Information
Set by this constraint: define_opcg_trigger
osc_source_reference Attributes for DFT
opcg_mode
opcg_mode string
Read-only osc_source_reference attribute. Returns the opcg_mode with which the oscillator source is associated.
March 2025 1396 Product Version 23.1
Genus Attribute Reference
Design for Test--osc_source Attributes for DFT
osc_source_period
osc_source_period float
Read-only osc_source_reference attribute. Returns the period of the oscillator source, which was specified using the -osc_source_parameters option of the
define_opcg_mode command.
Related Information
Set by this constraint: define_opcg_mode
ref_clk_period
ref_clk_period float
Read-only osc_source_reference attribute. Returns the period of the reference clock, which was specified using the -osc_source_parameters option of the
define_opcg_mode command.
Related Information
Set by this constraint: define_opcg_mode
osc_source Attributes for DFT
max_input_period
max_output_period
min_input_period
min_output_period
ref_clock_pin
max_input_period
max_input_period float
Read-only osc_source attribute. Returns the maximum period of the input clock of the PLL, which was specified using the -max_input_period option of the
define_opcg_osc_source command.
Related Information
Set by this constraint: define_opcg_osc_source
Affects these commands define_opcg_domain
define_opcg_mode
define_opcg_trigger
max_output_period
max_output_period float
Read-only osc_source attribute. Returns the maximum period of the output clock of the PLL, which was specified using the -max_output_period option of the
define_opcg_osc_source command.
March 2025 1397 Product Version 23.1
Genus Attribute Reference
Design for Test--osc_source Attributes for DFT
Related Information
Set by this constraint: define_opcg_osc_source
Affects these commands define_opcg_domain
define_opcg_mode
define_opcg_trigger
min_input_period
min_input_period float
Read-only osc_source attribute. Returns the minimum period of the input clock of the PLL, which was specified using the -min_input_period option of the
define_opcg_osc_source command.
Related Information
Set by this constraint: define_opcg_osc_source
Affects these commands define_opcg_domain
define_opcg_mode
define_opcg_trigger
min_output_period
min_output_period float
Read-only osc_source attribute. Returns the minimum period of the output clock of the PLL, which was specified using the -min_output_period option of the
define_opcg_osc_source command.
Related Information
Set by this constraint: define_opcg_osc_source
Affects these commands define_opcg_domain
define_opcg_mode
define_opcg_trigger
ref_clock_pin
ref_clock_pin {pin|port}
Read-only osc_source attribute. Returns the reference (input) clock pin or port for the PLL, which was specified using the -ref_clock_pin option of the
define_opcg_osc_source command.
Related Information
Set by this constraint: define_opcg_osc_source
Affects these commands define_opcg_domain
define_opcg_mode
define_opcg_trigger
March 2025 1398 Product Version 23.1
Genus Attribute Reference
Design for Test--pin Attributes for DFT
pin Attributes for DFT
dft_constant_value
dft_controllable
dft_dedicated_wrapper_reason
dft_driven_by_clock
dft_multibit_abstract_segment_present
dft_multibit_input_is_io_bound
dft_multibit_output_is_io_bound
dft_opcg_domain_clock_pin
dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
pmbist_dft_controllable
user_differential_negative_pin
user_from_core_data
user_from_core_enable
user_test_receiver_acmode
user_test_receiver_data_output
user_test_receiver_init_clock
user_test_receiver_init_data
user_to_core_data
user_to_core_enable
wrapper_control
wrapper_segment
wrapper_type
dft_constant_value
dft_constant_value {logic_0 | logic_1 | logic_z | no_value}
Read-only pin attribute. Indicates whether the value of the pin was propagated from a test signal or a logic constant. A logic_z value indicates that the pin is
being driven by a tristate buffer whose control signal is not active. A no_value value indicates that the pin is not in the path of a test signal or logic constant. The
specified test signal value is propagated by running the check_dft_rules command.
Related Information
Affected by these constraints: define_shift_enable
define_test_mode
Related attribute: (net) dft_constant_value
March 2025 1399 Product Version 23.1
Genus Attribute Reference
Design for Test--pin Attributes for DFT
dft_controllable
dft_controllable string
Read-write pin attribute. Specifies the logical connectivity across the pins of a blackbox module, from an input port to an output port. Otherwise, when your
design has blackbox modules on the test control path, such as the path to the clock, or asynchronous set/reset pins, the check_dft_rules command cannot
detect whether a direct path exists from a primary input to the flip-flop’s clock pin, set pins, or reset pins of the module; and it reports a DFT violation.
This attribute is set on the output pin of a direct path from an input port to an output port of a blackbox. The attribute value has the following format:
"input_pin_name {non_inverting|inverting}"
The value specifies the name of the input pin followed by an indication of whether the path to the output pin is inverted or not.
You must define this attribute prior to running the check_dft_rules command.
Related Information
Affects this command: check_dft_rules
Related attribute: (hpin) dft_controllable
dft_dedicated_wrapper_reason
dft_dedicated_wrapper_reason string
Read-Write pin attribute. Specifies the reason behind putting dedicated wrapper.
dft_driven_by_clock
dft_driven_by_clock {false | true}
Read-only pin attribute. Indicates whether this pin is driven by a clock.
Related Information
Affected by this command: connect_scan_chains
Related attributes: (port) dft_driven_by_clock
(hport) dft_driven_by_clock
dft_multibit_abstract_segment_present
dft_multibit_abstract_segment_present {false | true}
Default: false
Read-Write pin attribute. Indicates whether the multibit abstract segment for shared wrapper is present on the pin.
dft_multibit_input_is_io_bound
dft_multibit_input_is_io_bound {false | true}
Default: false
Read-Write pin attribute. Indicates whether the multibit pin is input or output bound.
March 2025 1400 Product Version 23.1
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Design for Test--pin Attributes for DFT
dft_multibit_output_is_io_bound
dft_multibit_output_is_io_bound {false | true}
Default: false
Read-Write pin attribute. Indicates whether the multibit pin is input or output bound.
dft_opcg_domain_clock_pin
dft_opcg_domain_clock_pin {false | true}
Default: false
Read-write pin attribute. This attribute is set in the scan abstract and specifies whether this input pin is connected to an OPCG test clock.
This attribute applies only to input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (port) dft_opcg_domain_clock_pin
(hport) dft_opcg_domain_clock_pin
dft_opcg_domain_fanout_pin
dft_opcg_domain_fanout_pin pin_list
Read-write pin attribute. This attribute is set in the scan abstract and returns a list of input pins or ports that are directly feeding the output pin.
In this case, the clock domains propagated from this output port will be the same as the clock domains from the corresponding input ports.
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_fanout_pin
(hport) dft_opcg_domain_fanout_pin
(port) dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_launch_clock pin_list
Read-write pin attribute. This attribute is set in the scan abstract and returns a list of clock pins that correspond to the clock domain that launch the data on this
output pin. The information is used to propagate the clock domain from this output port of the abstract model.
If the data is launched by an internal clock domain that has no corresponding output port, an empty string will be included. In this case, UNKNOWN will be
propagated from this output port of the abstract model.
March 2025 1401 Product Version 23.1
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Design for Test--pin Attributes for DFT
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_launch_clock
(hport) dft_opcg_domain_launch_clock
(port) dft_opcg_domain_launch_clock
dft_opcg_domain_se_input_pin
dft_opcg_domain_se_input_pin se_pin
Read-write pin attribute. This attribute is set in the scan abstract and specifies the input pin of the blocking shift enable signal that corresponds to this clock pin.
This attribute applies only to clock input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_se_input_pin
(hport) dft_opcg_domain_se_input_pin
(port) dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
dft_opcg_domain_unfenced_capture {clock_pin_list | NONE | INTERNAL | ""}
Read-write pin attribute. This attribute is set in the scan abstract and indicates whether additional domain blocking is required at this input pin of the abstract
model.
The attribute can have the following values:
clock_pin_list Specifies the list of clock pins which capture the data without fencing. When the pin is driven by a clock domain other than the ones listed,
additional fencing logic is required.
INTERNAL Indicates that the data is captured by an internal clock domain that has no corresponding output port. In this case, additional domain
blocking will be required.
NONE Indicates that the data is not captured by any flop. It implies that all endpoints of this pin are fenced.
"" An empty string will be treated like INTERNAL.
This attribute applies only to input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
March 2025 1402 Product Version 23.1
Genus Attribute Reference
Design for Test--pin Attributes for DFT
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_unfenced_capture
(hport) dft_opcg_domain_unfenced_capture
(port) dft_opcg_domain_unfenced_capture
pmbist_dft_controllable
pmbist_dft_controllable string
Read-write pin attribute. Defines the controllability of clocks through the clock gates for the PMBIST logic.
The attribute value has the following format:
"input_pin_name {non_inverting|inverting}"
The value specifies the name of the input pin followed by an indication of whether the path to the output pin is inverted or not.
This attribute is set by the tool. You should not change its value.
Related Information
Affects this command: check_dft_rules
Related attribute: (hpin) pmbist_dft_controllable
user_differential_negative_pin
user_differential_negative_pin string
Read-write pin attribute. Specifies the negative-leg pad pin that is associated with the pad cell instance positive-leg pad pin.
negative-leg_pad_pin_name pad_cell_instance_positive-leg_pad_pin_name
Related Information
Affects this command: add_jtag_boundary_scan
user_from_core_data
user_from_core_data string
Read-write pin attribute. Specify the name of the corresponding from-core data pin of a pad pin on an I/O pad instance. It is possible to specify different from-
core data pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of multi-
pad instances such as SERDES blocks.
from_core_data_pin_name pad_cell_instance_pad_pin_name
Related Information
Affects this command: add_jtag_boundary_scan
March 2025 1403 Product Version 23.1
Genus Attribute Reference
Design for Test--pin Attributes for DFT
user_from_core_enable
user_from_core_enable string
Read-write pin attribute. Specify the name of the corresponding from-core enable pin of a pad pin on an I/O pad instance. It is possible to specify different from-
core enable pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of
multi-pad instances such as SERDES blocks.
An active low output enable is specified using the ! character in front of the output_enable pin name.
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_acmode
user_test_receiver_acmode string
Read-write pin attribute. Specifies the name of the test receiver pin for AC and DC mode control.
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_data_output
user_test_receiver_data_output string
Read-write pin attribute. Specifies the name of the test receiver input from the boundary cell.
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_init_clock
user_test_receiver_init_clock string
Read-write pin attribute. Specifies the name of the test receiver clock to latch data from the boundary cell.
Related Information
Affects this command: add_jtag_boundary_scan
user_test_receiver_init_data
user_test_receiver_init_data string
Read-write pin attribute. Specifies the name of the test receiver input from the boundary cell.
Related Information
Affects this command: add_jtag_boundary_scan
March 2025 1404 Product Version 23.1
Genus Attribute Reference
Design for Test--pin Attributes for DFT
user_to_core_data
user_to_core_data string
Read-write pin attribute. Specify the name of the corresponding to-core data pin of a pad pin on an I/O pad instance. It is possible to specify different to-core
data pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of multi-pad
instances such as SERDES blocks.
to_core_data_pin_name pad_cell_instance_pad_pin_name
An inversion on the data path is specified using the ! character in front of the to_core pin name.
Related Information
Affects this command: add_jtag_boundary_scan
user_to_core_enable
user_to_core_enable string
Default: none
Read-write pin attribute. Specify the name of the corresponding to-core enable pin of a pad pin on an I/O pad instance. It is possible to specify different to-core
enable pins for I/O pad cells that have more that one pad pin by setting this attribute on each of the I/O cells pad pins. This can be useful in the case of multi-pad
instances such as SERDES blocks.
Related Information
Affects this command: add_jtag_boundary_scan
wrapper_control
wrapper_control {false | true }
Default: false
Read-write pin attribute. Specifies that a wrapper control signal is applied to the pin.
Related Information
Related attributes: (hpin) wrapper_control
(hport) wrapper_control
wrapper_segment
wrapper_segment string
Read-write pin attribute. Lists the wrapper segments associated with the pin.
March 2025 1405 Product Version 23.1
Genus Attribute Reference
Design for Test--pmbist_port Attributes for DFT
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hpin) wrapper_segment
(hport) wrapper_segment
wrapper_type
wrapper_type {dedicated | shared}
Read-write pin attribute. Specifies whether the wrapper segment associated with the pin is a dedicated or shared wrapper segment.
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hpin) wrapper_type
(hport) wrapper_type
pmbist_port Attributes for DFT
pmbist_port_name
pmbist_port_name string
Read-only pmbist_port attribute. Specify the name to be used for a specific type of port.
Related Information
Related attribute: function
function
function string
Read-only pmbist_port attribute. Specify the type of port that is defined.
Related Information
Related attribute: pmbist_port_name
port Attributes for DFT
dft_dedicated_wrapper_reason
dft_driven_by_clock
March 2025 1406 Product Version 23.1
Genus Attribute Reference
Design for Test--pmbist_port Attributes for DFT
dft_enable_hookup_pin
dft_enable_hookup_polarity
dft_opcg_domain_clock_pin
dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
dft_sdi_output_hookup_pin
dft_sdo_input_hookup_pin
wrapper_control
wrapper_segment
wrapper_type
dft_dedicated_wrapper_reason
dft_dedicated_wrapper_reason string
Read-Write port attribute. Specifies the reason behind putting dedicated wrapper.
dft_driven_by_clock
dft_driven_by_clock {false | true}
Read-only port attribute. Indicates whether this port is driven by a clock.
Related Information
Affected by this command: connect_scan_chains
Related attributes: (pin) dft_driven_by_clock
(hport) dft_driven_by_clock
dft_enable_hookup_pin
dft_enable_hookup_pin pin
Read-write port attribute. Specifies the enable hookup pin for a bidirectional port with a bidrectional pad attached to it.
When a bidirectional pad is attached to a bidirectional port, the pad must be configured in the proper direction during test. Usually this is done by inserting a test
point at the from_core_enable or to_core_enable pin of the pad.
The test point is inserted using the fix_pad_cfg command, or using the -configure_pad option when defining the scan chains, and the shift-enable and test-
mode test signals. You can use this attribute to specify the hookup pin to be used when the test point is inserted.
Usually during bidirectional compression, the misr_read signal is connected to the from_core_enable pin of the pad cell connected to the bidirectional scan
data input port. You can use this attribute to specify the hookup pin to which the misr_read signal must be connected.
Related Information
Related commands: fix_pad_cfg
define_scan_chain
define_shift_enable
define_test_mode
March 2025 1407 Product Version 23.1
Genus Attribute Reference
Design for Test--pmbist_port Attributes for DFT
dft_enable_hookup_polarity
dft_enable_hookup_polarity {low | high}
Read-write port attribute. Indicates the value to drive the dft_enable_hookup_pin to configure the pad in output mode.
In the case of bidirectional compression, if the polarity is low, the misr_read signal is inverted before connecting it to the dft_enable_hookup_pin.
In the case of pad configuration for test, if the polarity is low, the test point required to activate or block the from_core_enable pin will be inverted when the test
point is inserted.
Related Information
Related commands: fix_pad_cfg
define_scan_chain
define_shift_enable
define_test_mode
dft_opcg_domain_clock_pin
dft_opcg_domain_clock_pin {false | true}
Default: false
Read-write port attribute. This attribute is set in the scan abstract and specifies whether this input port is connected to an OPCG test clock.
This attribute applies only to input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (pin) dft_opcg_domain_clock_pin
(hport) dft_opcg_domain_clock_pin
dft_opcg_domain_fanout_pin
dft_opcg_domain_fanout_pin pin_list
Read-write port attribute. This attribute is set in the scan abstract and returns a list of input pins or ports that are directly feeding the output port.
In this case, the clock domain propagated from this output port should be the same as the clock domain from the corresponding input ports.
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
March 2025 1408 Product Version 23.1
Genus Attribute Reference
Design for Test--pmbist_port Attributes for DFT
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_fanout_pin
(hport) dft_opcg_domain_fanout_pin
(pin) dft_opcg_domain_fanout_pin
dft_opcg_domain_launch_clock
dft_opcg_domain_launch_clock pin_list
Read-write port attribute. This attribute is set in the scan abstract and returns a list of clock pins that correspond to the clock domain that launch the data on
this output port. The information is used to propagate the clock domain from this output port of the abstract model.
If the data is launched by an internal clock domain that has no corresponding output port, an empty string will be included. In this case, UNKNOWN will be
propagated from this output port of the abstract model.
This attribute applies only to output pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_launch_clock
(hport) dft_opcg_domain_launch_clock
(pin) dft_opcg_domain_launch_clock
dft_opcg_domain_se_input_pin
dft_opcg_domain_se_input_pin se_pin
Read-write port attribute. This attribute is set in the scan abstract and specifies the input pin of the blocking shift enable signal that corresponds to this clock
port.
This attribute applies only to clock input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_se_input_pin
(hport) dft_opcg_domain_se_input_pin
(pin) dft_opcg_domain_se_input_pin
dft_opcg_domain_unfenced_capture
dft_opcg_domain_unfenced_capture {clock_pin_list | NONE | INTERNAL | ""}
March 2025 1409 Product Version 23.1
Genus Attribute Reference
Design for Test--pmbist_port Attributes for DFT
Read-write port attribute. This attribute is set in the scan abstract and indicates whether additional domain blocking is required at this input port of the abstract
model.
The attribute can have the following values:
clock_pin_list Specifies the list of clock pins which capture the data without fencing. When the pin is driven by a clock domain other than the ones listed,
additional fencing logic is required.
INTERNAL Indicates that the data is captured by an internal clock domain that has no corresponding output port. In this case, additional domain
blocking will be required.
NONE Indicates that the data is not captured by any flop. It implies that all endpoints of this pin are fenced.
"" An empty string will be treated like INTERNAL.
This attribute applies only to input pins or ports.
Even though this is a read-write attribute, this attribute is set by the tool and you should not change its value.
Related Information
Set by this command: write_dft_abstract_model
Related attributes: (hpin) dft_opcg_domain_unfenced_capture
(hport) dft_opcg_domain_unfenced_capture
(pin) dft_opcg_domain_unfenced_capture
dft_sdi_output_hookup_pin
dft_sdi_output_hookup_pin
Read-write port attribute. Specifies the output hookup pin of the bidirectional scan data input port when it functions as an output port while reading out the MISR
signature during compression.
This attribute applies to a bidirectional port that serves as a scan-in of a compressed scan chain.
Related Information
dft_sdo_input_hookup_pin
dft_sdi_input_hookup_pin
Read-write port attribute. Specifies the input hookup pin of the bidirectional scan data output port when it functions as an input port for the scan unloading
operation during compression.
This attribute applies only to a bidirectional port that serves as a scan-out of a compressed scan chain.
Related Information
March 2025 1410 Product Version 23.1
Genus Attribute Reference
Design for Test--programmable_direct_access_function Attributes for DFT
wrapper_control
wrapper_control {false | true }
Default: false
Read-write port attribute. Specifies that a wrapper control signal is applied to the port.
Related Information
Related attributes: (hpin) wrapper_control
(hport) wrapper_control
(pin) wrapper_control
wrapper_segment
wrapper_segment string
Read-write port attribute. Lists the wrapper segments associated with the port.
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hpin) wrapper_segment
(hport) wrapper_segment
(pin) wrapper_segment
wrapper_type
wrapper_type {dedicated | shared}
Read-write port attribute. Specifies whether the wrapper segment associated with the port is a dedicated or shared wrapper segment.
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (hpin) wrapper_type
(hport) wrapper_type
(pin) wrapper_type
programmable_direct_access_function Attributes for DFT
active
connection
dft_hookup_pin
dft_hookup_polarity
instance
March 2025 1411 Product Version 23.1
Genus Attribute Reference
Design for Test--programmable_direct_access_function Attributes for DFT
source
active
active {high | low}
Read-only programmable_direct_access_function attribute. Returns the active value of the PMBIST direct access function signal at the hook-up point.
Related Information
Set by this constraint: define_pmbist_direct_access
Related attributes: source
connection
connection string
Default: no value
Read-only programmable_direct_access_function attribute. Returns the connection type.
dft_hookup_pin
dft_hookup_pin {pin | port}
Read-only programmable_direct_access_function attribute. Returns the path to the pin or port where the direct access function actually hooks up inside the
core.
Related Information
Set by this constraint: define_pmbist_direct_access
dft_hookup_polarity
dft_hookup_polarity {inverted | non_inverted}
Read-only programmable_direct_access_function attribute. Returns the polarity of the hookup pin of the direct access function.
Related Information
Set by this constraint: define_pmbist_direct_access
instance
instance string
Read-only programmable_direct_access_function attribute. Returns the associated instance name.
source
source {pin | port}
Read-only programmable_direct_access_function attribute. Returns the hook-up pin or port from where to make the connection for this PMBIST direct access
function.
March 2025 1412 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Set by this constraint: define_pmbist_direct_access
Related attributes: active
root Attributes for DFT
dft_1500_hierarchical_parent_child_wrapping dft_1500_hierarchical_softcore_wrapping dft_add_mux_on_pre_connected_ctl_si
dft_allow_dwc_in_top dft_apply_sdc_constraints dft_atpg_executable
dft_auto_create_chains_as_internal dft_auto_identify_shift_register dft_boundary_cell_module_prefix
dft_boundary_scan_timing_mode_name dft_capture_11496_reciever_output dft_capture_timing_mode_name
dft_check_cfg_mode_aware dft_clock_waveform_divide_fall dft_clock_waveform_divide_period
dft_clock_waveform_divide_rise dft_clock_waveform_fall dft_clock_waveform_period
dft_clock_waveform_rise dft_compression_2d_aspect_ratio dft_compression_2d_decomp_pipeline_d
dft_compression_2d_grid_max_x dft_compression_2d_grid_max_y dft_compression_2d_grid_min_x
dft_compression_2d_grid_min_y dft_compression_auto_create dft_compression_channel_length
dft_compression_comp_pipeline_max_xor_depth dft_compression_compressor_type dft_compression_decomp_pipeline_max_
dft_compression_decompressor_type dft_compression_elasticity_ratio dft_compression_extest_decompressor_ty
dft_compression_fullscan_support dft_compression_lp_gating_sharing_ratio dft_compression_lp_gating_support
dft_compression_mask_and_lp_gating_unload_support dft_compression_mask_sharing_ratio dft_compression_mask_support
dft_compression_masken_pipeline_depth dft_compression_num_extest_scanin dft_compression_num_extest_scanout
dft_compression_num_scanin dft_compression_num_scanout dft_compression_opcg_unload_support
dft_compression_post_2d_sdc_file dft_compression_post_2d_sdc_mode_name dft_compression_ratio
dft_compression_scanin_pipeline_depth dft_compression_scanout_pipeline_depth dft_compression_serial_load_support
dft_cross_lp_cells_for_lockup_clk_driver dft_disable_wrapper_inside_non_scan_elem dft_dont_merge_multibit_lockup
dft_dont_wrap_if_shared_threshold_exceed dft_enable_flop_placement_in_test_point_insertion dft_enable_wir_function_check
dft_exclude_internal_flops_from_shared_wrapper_threshold dft_exclude_tdrc_fail_seg dft_extended_scandef
dft_fence_slow_speed_domains dft_generate_atpg_no_testpoint_file dft_get_balanced_chains_assignment
dft_identify_internal_test_clocks dft_identify_non_boundary_shift_registers dft_identify_shared_wrapper_cells
dft_identify_test_signals dft_identify_top_level_test_clocks dft_identify_xsource_violations_from_timin
dft_ignore_dont_scan_for_shared_wrapper_processing dft_ignore_non_scan_for_wrapper_processing dft_include_controllable_pins_in_abstract
dft_include_test_signal_outputs_in_abstract_model dft_insert_dedicated_inside_sink_hierarchy dft_jtag_instance_name
dft_jtag_module_name dft_lbist_capture_timing_mode_name dft_lbist_shift_timing_mode_name
dft_license_scheme dft_modedef_internal dft_modus_version
dft_opcg_block_input_to_flop_paths dft_opcg_domain_blocking dft_opcg_timing_mode_name
dft_physical_aware_test_points dft_physical_pd_aware_scan_connection dft_pmbist_jtag_timing_mode_name
dft_pmbist_mda_timing_mode_name dft_power_aware_lockup_clock_driver dft_power_aware_wrapper_insertion
March 2025 1413 Product Version 23.1
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Design for Test--root Attributes for DFT
dft_prefix dft_process_multibit_for_shared_wrapper dft_propagate_test_signals_from_hookup
dft_report_empty_test_clocks dft_report_scan_register_quiet dft_rtl_insertion
dft_run_test_point_analysis_for_compression dft_run_test_point_analysis_for_lbist dft_scan_power_domain_crossing_lockup
dft_scan_style dft_scanbit_waveform_analysis dft_sdc_input_port_delay
dft_sdc_output_port_delay dft_shared_common_logic_threshold dft_shared_wrapper_through
dft_shift_register_identification_mode dft_shift_register_max_length dft_shift_register_min_length
dft_shift_register_with_mbci dft_shift_timing_mode_name dft_tap_lockup_clock_from_adjacent
dft_tpi_sharing_scope dft_true_time_flow dft_use_abstract_segment_instance_pow
dft_use_multibit_register_width_for_threshold dft_use_wck_as_default_wrapper_clock dft_wait_for_license
non_dft_timing_mode_name pmbist_enable_multiple_views pmbist_full_async_reset
unmap_scan_flops
dft_1500_hierarchical_parent_child_wrapping
Syntax
dft_1500_hierarchical_parent_child_wrapping {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
If set to true, wraps the parent in the presence of wrapped child hierarchy.
Related Information
Affects this command: add_core_wrapper_cell
dft_1500_hierarchical_softcore_wrapping
Syntax
dft_1500_hierarchical_softcore_wrapping {false | true}
Applies to:
root
Description
Default: false
Data_Type: bool, read/write
March 2025 1414 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Ignores wrapped softcores while wrapping the top-level ports if the attribute is set to 'true'.
Related Information
Affects this command: add_core_wrapper_cell
dft_add_mux_on_pre_connected_ctl_si
Syntax
dft_add_mux_on_pre_connected_ctl_si {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Inserts a Mux whenever SI pin of a User Defined CTL Abstract Segment is connected to a functional output.
Related Information
Affects this command: connect_scan_chains
dft_allow_dwc_in_top
Syntax
dft_allow_dwc_in_top {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether to allow DFT wrapper cells to be inserted at the top-level.
Related Information
Affects this command: add_core_wrapper_cell
dft_apply_sdc_constraints
March 2025 1415 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_apply_sdc_constraints {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, SDC constraints for DFT constructs are applied during boundary-scan insertion, scan connection, and xor compression without masking. The
SDC constraints are applied when the relevant commands to insert those DFT constructs are run. The SDC constraints can be written out using the write_sdc
command.
Related Information
Affects these commands: compress_scan_chains
connect_scan_chains
add_jtag_boundary_scan
add_jtag_macro
dft_atpg_executable
Syntax
dft_atpg_executable <path>
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the path to the Modus or Encounter Test executable to be called from Genus.
dft_auto_create_chains_as_internal
dft_auto_create_chains_as_internal {true | false}
Description
Default: false
Data_type: bool, read/write
Designates scan chains as internal. For the unified compression flows, user-connected channels are built as internal scan chains, and then used with 1D
compression flow.
Setting this attribute is equivalent to specifying the -internal option for the define_scan_chain command.
March 2025 1416 Product Version 23.1
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Design for Test--root Attributes for DFT
Example
set_db dft_auto_create_chains_as_internal true;
connect_scan_chains -auto_create_chains
add_test_compression; #to insert 1D compression
Applies to:
root
Information
Related commands: connect_scan_chains
dft_auto_identify_shift_register
Syntax
dft_auto_identify_shift_register {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, automatically identifies functional shift register segments.
Related Information
dft_boundary_cell_module_prefix
dft_boundary_cell_module_prefix string
Description
Default:
Data_type: string, read/write
Specifies the prefix for the module names of boundary-scan cells added during the insertion of the boundary-scan logic.
Applies to:
root
Related Information
March 2025 1417 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
dft_boundary_scan_timing_mode_name
Syntax
dft_boundary_scan_timing_mode_name <string>
Applies to:
root
Description
Default: DFT_BOUNDARY_SCAN_MODE
Data_type: string, read/write
Specifies the name of the timing mode where the SDC constraints for the DFT boundary scan mode are stored.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affects this command: add_jtag_boundary_scan
dft_capture_11496_reciever_output
Syntax
dft_capture_11496_reciever_output {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
When set to false, avoids inserting 11496 bsr capture logic on receiver output.
Related Information
Affects this command: add_jtag_boundary_scan
dft_capture_timing_mode_name
Syntax
dft_capture_timing_mode_name {string}
March 2025 1418 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Applies to:
root
Description
Default: DFT_CAPTURE_MODE
Data_type: string, read/write
Specifies the DFT capture timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
dft_check_cfg_mode_aware
dft_check_cfg_mode_aware {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, runs check_dft_rules on all scannable elements for all dft_cfg_mode.
Related Information
Affects this command: check_dft_rules
dft_clock_waveform_divide_fall
dft_clock_waveform_divide_fall integer
Applies to:
root
Description
Default: 100
Data_type: int, read/write
Used with the dft_clock_waveform_fall attribute to specify the time that the falling edge occurs with respect to the beginning of the clock period. The time is
specified as a percentage of the period and is derived by dividing dft_clock_waveform_fall by dft_clock_waveform_divide_fall.
The attribute value is applied by the define_test_clock command instead of specifying the command option divide_fall and is used by all auto-generated
test-clocks defined by using the check_dft_rules command.
Related Information
Affects this command: define_test_clock
March 2025 1419 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
dft_clock_waveform_divide_period
dft_clock_waveform_divide_period integer
Description
Default: 1
Data_type: int, read/write
Used with the dft_clock_waveform_divide attribute to specify the clock period interval. The clock period is specified in picoseconds and is derived by dividing
dft_clock_waveform_period by dft_clock_waveform_divide_period.
The attribute value is applied by the define_test_clock command instead of specifying the command option divide_period and is used by all auto-generated
test-clocks defined by using the check_dft_rules command.
Applies to:
root
Related Information
Affects this command: define_test_clock
dft_clock_waveform_divide_rise
dft_clock_waveform_divide_rise integer
Applies to:
root
Description
Default: 100
Data_type: int, read/write
Used with the dft_clock_waveform_rise attribute to specify the time that the rising edge occurs with respect to the beginning of the clock period. The time is
specified as a percentage of the period and is derived by dividing dft_clock_waveform_rise by dft_clock_waveform_divide_rise.
The attribute value is applied by the define_test_clock command instead of specifying the command option divide_rise and is used by all auto-generated
test-clocks defined by using the check_dft_rules command.
Related Information
Affects this command: define_test_clock
dft_clock_waveform_fall
dft_clock_waveform_fall integer
Applies to:
root
March 2025 1420 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Description
Default: 90
Data_type: int, read/write
Used with the dft_clock_waveform_divide_fall to specify the time that the falling edge occurs with respect to the beginning of the clock period. The time is
specified as a percentage of the period and is derived by dividing dft_clock_waveform_fall by dft_clock_waveform_divide_fall.
The attribute value is applied by the define_test_clock command instead of specifying the command option -fall and is used by all auto-generated test-
clocks defined by using the check_dft_rules command.
Related Information
Affects this command: define_test_clock
dft_clock_waveform_period
Syntax
dft_clock_waveform_period <integer>
Applies to:
root
Description
Default: 50000
Data_type: int, read/write
Used with the dft_clock_waveform_divide_period attribute to specify the clock period interval. The clock period is specified in picoseconds and is derived by
dividing dft_clock_waveform_period by dft_clock_waveform_divide_period.
The attribute value is applied by the define_test_clock command instead of specifying the command option -period and is used by all auto-generated test-
clocks defined by using the check_dft_rules command.
Related Information
Affects this command: define_test_clock
dft_clock_waveform_rise
dft_clock_waveform_rise integer
Applies to:
root
Description
Default: 50
Data_type: int, read/write
Used with the dft_clock_waveform_divide_rise attribute to specify the time that the rising edge occurs with respect to the beginning of the clock period interval.
The time is specified as a percentage of the period and is derived by dividing dft_clock_waveform_rise by dft_clock_waveform_divide_rise.
March 2025 1421 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
The attribute value is applied by the define_test_clock command instead of specifying the command option -rise and is used by all auto-generated test-
clocks defined by using the check_dft_rules command.
Related Information
Affects this command: define_test_clock
dft_compression_2d_aspect_ratio
Syntax
dft_compression_2d_aspect_ratio <float>
Applies to:
root
Description
Default:
Data_type: double, read/write
Specifies the aspect ratio of the 2D compression grid to insert.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_2d_decomp_pipeline_distance
Syntax
dft_compression_2d_decomp_pipeline_distance <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the number of 2D compression grid cells between two decompressor pipelines.
Related Information
Affects these commands: check_dft_setup
add_test_compression
March 2025 1422 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
dft_compression_2d_grid_max_x
Syntax
dft_compression_2d_grid_max_x <float>
Applies to:
root
Description
Default:
Data_type: coord, read/write
Specifies the x-coordinate to the left of which the 2D compression grid will be inserted.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_2d_grid_max_y
Syntax
dft_compression_2d_grid_max_y <float>
Applies to:
root
Description
Default:
Data_type: coord, read/write
Specifies the y-coordinate below which the 2D compression grid will be inserted.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_2d_grid_min_x
Syntax
dft_compression_2d_grid_min_x <float>
March 2025 1423 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Applies to:
root
Description
Default:
Data_type: coord, read/write
Specifies the x-coordinate to the right of which the 2D compression grid will be inserted.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_2d_grid_min_y
Syntax
dft_compression_2d_grid_min_y <float>
Applies to:
root
Description
Default:
Data_type: coord, read/write
Specifies the y-coordinate above which the 2D compression grid will be inserted.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_auto_create
Syntax
dft_compression_auto_create {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether or not to auto create the missing compression test signals.
March 2025 1424 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_channel_length
Syntax
dft_compression_channel_length <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the length of the compression channel to insert.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_comp_pipeline_max_xor_depth
Syntax
dft_compression_comp_pipeline_max_xor_depth <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the maximum XOR depth between two compressor pipelines.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_compressor_type
March 2025 1425 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_compression_compressor_type <xor | misr>
Applies to:
root
Description
Default: xor
Data_type: string, read/write
Specifies the compressor type to insert.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_decomp_pipeline_max_xor_depth
Syntax
dft_compression_decomp_pipeline_max_xor_depth <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the the maximum XOR depth between two decompressor pipelines.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_decompressor_type
Syntax
dft_compression_decompressor_type <elastic | xor>
Applies to:
root
March 2025 1426 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Description
Default: elastic
Data_type: string, read/write
Specifies the decompressor type to insert.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_elasticity_ratio
Syntax
dft_compression_elasticity_ratio <integer>
Applies to:
root
Description
Default: 1
Data_type: int, read/write
Specifies the SmartScan Deserializer ratio to insert for elastic decompression.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_extest_decompressor_type
Syntax
dft_compression_extest_decompressor_type <elastic | xor>
Applies to:
root
Description
Default: elastic
Data_type: string, read/write
Specifies the extest decompressor type to insert.
March 2025 1427 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_fullscan_support
Syntax
dft_compression_fullscan_support {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether or not to insert fullscan muxing to concatenate the compression channels.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_lp_gating_sharing_ratio
Syntax
dft_compression_lp_gating_sharing_ratio <integer>
Applies to:
root
Description
Default: 1
Data_type: int, read/write
Specifies the number of compression channels to share a common low power gating register.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_lp_gating_support
March 2025 1428 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_compression_lp_gating_support {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether to insert low power compression channel gating.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_mask_and_lp_gating_unload_support
Syntax
dft_compression_mask_and_lp_gating_unload_support {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Specifies whether to build unload paths for mask and low power gating registers.
dft_compression_mask_sharing_ratio
Syntax
dft_compression_mask_sharing_ratio <integer>
Applies to:
root
Description
Default: 1
Data_type: int, read/write
Specifies the the number of compression channels to share a common mask register.
March 2025 1429 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_mask_support
Syntax
dft_compression_mask_support {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether or not to insert compression (wide1) masking.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_masken_pipeline_depth
Syntax
dft_compression_masken_pipeline_depth <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the number of pipeline stages to insert on the compression mask enable signal.
Related Information
Affects these commands: check_dft_setup
add_test_compression
March 2025 1430 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
dft_compression_num_extest_scanin
Syntax
dft_compression_num_extest_scanin <integer>
Applies to:
root
Description
Default: 0
Data_Type: integer, read/write
Specifies the number of scan inputs to use for extest compression.
Related Information
Related commands: check_dft_setup
add_test_compression
dft_compression_num_extest_scanout
Syntax
dft_compression_num_extest_scanout <integer>
Applies to:
root
Description
Default: 0
Data_Type: integer, read/write
Specifies the number of scan outputs to use for extest compression.
Related Information
Related commands: check_dft_setup
add_test_compression
dft_compression_num_scanin
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Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_compression_num_scanin <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the number of scan inputs to auto create for compression.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_num_scanout
Syntax
dft_compression_num_scanout <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the number of scan outputs to auto create for compression.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_opcg_unload_support
Syntax
dft_compression_opcg_unload_support {true | false}
Applies to:
root
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Design for Test--root Attributes for DFT
Description
Default: true
Data_type: bool, read/write
Specifies whether to build unload paths for OPCG programming registers.
dft_compression_post_2d_sdc_file
Syntax
dft_compression_post_2d_sdc_file <in_file>
Applies to:
root
Description
Default:
Data_type: in_file, read/write
Specifies the the SDC file to read in after 2D compression is inserted.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_post_2d_sdc_mode_name
Syntax
dft_compression_post_2d_sdc_mode_name {string}
Applies to:
root
Description
Default:
Data_type: string, read/write
Specifies the timing mode to which the specified SDC file will be applied.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_ratio
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Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_compression_ratio <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the compression ratio to insert.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_scanin_pipeline_depth
Syntax
dft_compression_scanin_pipeline_depth <integer>
Applies to:
root
Description
Default: 0
Data_type: int, read/write
Specifies the number of pipeline stages to insert on each compression scan input.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_scanout_pipeline_depth
Syntax
dft_compression_scanout_pipeline_depth <integer>
Applies to:
root
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Design for Test--root Attributes for DFT
Description
Default: 0
Data_type: int, read/write
Specifies the the number of pipeline stages to insert on each compression scan output.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_compression_serial_load_support
Syntax
dft_compression_serial_load_support {true | false}
Applies to:
hpin
hport
pg_pin
pin
port
Description
Default: false
Data_type: bool, read/write
Enables loading/unloading the Elastic decompressor, the MISR, the mask register, or the low power gating register serially.
Related Information
Affects these commands: check_dft_setup
add_test_compression
dft_cross_lp_cells_for_lockup_clk_driver
Syntax
dft_cross_lp_cells_for_lockup_clk_driver {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
March 2025 1435 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Cross low power cells to find lockup clock driver when the attribute is set to true.
Related Information
Affects this command: connect_scan_chains
dft_disable_wrapper_inside_non_scan_elem
Syntax
dft_disable_wrapper_inside_non_scan_elem {false | true}
Applies to:
root
Description
Default: false
Data_Type: bool, read/write
When set to true, disables the wrapper from being inserted inside a 'dft_dont_scan' hierarchy.
Related Information
Affects this command: add_core_wrapper_cell
dft_dont_merge_multibit_lockup
Syntax
dft_dont_merge_multibit_lockup {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether the lockups inserted by connect_scan_chains, add_lockup_element should be avoided during multibit merging.
As shown in the following table, Genus avoids multibit merging for the lockups only when the root attribute merge_multibit is not set:
dft_dont_merge_multibit_lockup merge_multibit Multibit merging is...
false false Attempted, if use_multibit_cells is set to true.
false true Attempted.
true false Not attempted.
true true Attempted and the dont_merge_multibit attribute value is ignored.
March 2025 1436 Product Version 23.1
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Design for Test--root Attributes for DFT
Related Information
Related commands: syn_opt
connect_scan_chains
add_lockup_element
Related Attributes: use_multibit_cells
merge_multibit
dont_merge_multibit
dft_dont_wrap_if_shared_threshold_exceed
Syntax
dft_dont_wrap_if_shared_threshold_exceed {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Stops port wrapping instead of adding DWC if the value of port shared_threshold exceeds the value specified.
Related Information
Affects this command: add_core_wrapper_cell
dft_enable_flop_placement_in_test_point_insertion
Syntax
dft_enable_flop_placement_in_test_point_insertion {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enable physical placement of testpoint flop during testpoint insertion. Requires MOD400 license.
Related Information
Affects this command: add_analyzed_test_points
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Genus Attribute Reference
Design for Test--root Attributes for DFT
dft_enable_wir_function_check
Syntax
dft_enable_wir_function_check {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls whether test signals with types other than compression_enable, spread_enable, wint, wext, select_serial, select_bypass, or custom should be allowed
to be implemented as Wrapper Instruction Register (WIR) bits.
When you disable this check by setting the attribute to false, you are responsible for adding the WIR test signals with valid functions and for programming them.
dft_exclude_internal_flops_from_shared_wrapper_threshold
dft_exclude_internal_flops_from_shared_wrapper_threshold {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, excludes internal flops while calculating shared wrapper threshold. These flops will be converted to shared wrapper flops if they meet the
criteria for shared conversion.
dft_exclude_tdrc_fail_seg
Syntax
dft_exclude_tdrc_fail_seg {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, automatically excludes abstract segments that fail the DFT rules from scan chain connection.
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Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Affects this command: connect_scan_chains
dft_extended_scandef
Syntax
dft_extended_scandef {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Produces extended scanDEF output to encompass almost all the scan bits in a design.
Related Information
Affects this command: write_scandef
dft_fence_slow_speed_domains
Syntax
dft_fence_slow_speed_domains {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls addition of blocking logic for slow clock domains.
Related Information
Affects this command: connect_scan_chains
dft_generate_atpg_no_testpoint_file
March 2025 1439 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_generate_atpg_no_testpoint_file {auto | auto_plus_user <file> | user_only <file> | none | false | true}
Applies to:
root
Description
Default: auto
Data_type: string, read/write
Controls the automatic generation of the design.noTpfile by the write_dft_deterministic_test_points and write_dft_lbist_test_points commands. This
file contains a list of modules, instances, nets, and pins that have been constrained, thus preventing test point insertion on them.
This noTpfile file is passed to Modus via the notpfile keyword of the analyze_random_resistance and analyze_deterministic_faults commands.
This attribute can have the following values:
auto Instructs to use the tool-generated noTpfile file for Modus.
auto_plus_user file Instructs to append the user-created noTpfile file to the tool-generated noTpfile file for use by Modus.
user_only file Instructs to use the user-created noTpfile file for Modus.
none Prevents Genus from generating a noTpfile file.
false Equivalent to setting the attribute to none.
true Equivalent to setting the attribute to auto.
Examples
set_db / .dft_generate_atpg_no_testpoint_file "user_only user.notp"
set_db / .dft_generate_atpg_no_testpoint_file "auto_plus_user user.notp"
Related Information
Affects these commands: add_analyzed_test_points
write_dft_deterministic_test_points
write_dft_lbist_test_points
dft_get_balanced_chains_assignment
Syntax
dft_get_balanced_chains_assignment
Applies to:
root
Description
Default: false
Data_type: bool, read/write
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Design for Test--root Attributes for DFT
Controls the even distribution of balanced scan chains among all scan groups when the max length of scan chain is not defined.
Related Information
Affects this command: connect_scan_chains
dft_identify_internal_test_clocks
Syntax
dft_identify_internal_test_clocks {false | true | no_cgic_hier}
Applies to:
root
Description
Default: false
Data_type: enum, read/write
Indicates whether the DFT rule checker must identify the output pins of multi-input combinational gates and the clock output pins of the clock-gating instances in
the clock path as separate test clocks in the same DFT clock domain as its root-level test clock.
This attribute can have the following values:
false Ensures that the output pins of multi-input combinational gates and the clock output pins of the clock-gating instances in the clock path are
not identified as separate test clocks.
true Ensures that the output pins of multi-input combinational gates and the clock output pins of the clock-gating instances in the clock path are
identified as separate test clocks.
no_cgic_hier Ensures that the clock output pins of the clock-gating instances are not identified as separate test clocks. However, output pins of multi-input
combinational gates in the clock path are identified as separate test clocks.
The internal test clocks and their associated combinational logic gates are listed in the report generated by the report_scan_setup command.
The internal test clocks are only identified for those multi-input combinational cells that are mapped to a technology component.
Related Information
Affects this command: check_dft_rules
dft_identify_non_boundary_shift_registers
Syntax
dft_identify_non_boundary_shift_registers {false | true}
Applies to:
root
Description
Default: false
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Design for Test--root Attributes for DFT
Data_type: bool, read/write
Controls whether or not identify_shift_register_scan_segments should exclude boundary registers, which can be converted to shared IEEE 1500 wrappers
by identifying shift registers.
Related Information
Affects this command: identify_shift_register_scan_segments
dft_identify_shared_wrapper_cells
Syntax
dft_identify_shared_wrapper_cells {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether the IEEE 1500 wrapper analysis code will trace through the boundary logic to identify the functional flop(s) to be used as the test flop in the
IEEE 1500 shared wrapper cells.
The wrapper analysis is run during synthesis when you set this attribute set to true, or when you use the identify_shared_wrapper_cells_in_design
command. During mapping, boundary flops will be mapped to scan flops for DFT and will be excluded from automatic shift-register identification and multi-bit
cell merging.
Related Information
Affects these commands: identify_shared_wrapper_cells_in_design
syn_map
dft_identify_test_signals
Syntax
dft_identify_test_signals {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Indicates whether the DFT rule checker can automatically assign a test mode signal for each top-level pin that is traceable from the async set or reset pin of a
flip-flop. To prevent auto identification, set this attribute to false.
March 2025 1442 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Affects this command: check_dft_rules
dft_identify_top_level_test_clocks
Syntax
dft_identify_top_level_test_clocks {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Indicates whether the DFT rule checker can automatically assign a test clock for each top-level clock pin that is traceable from the clock pin of a flip-flop, and a
corresponding test-clock domain. To prevent auto identification, set this attribute to false.
Related Information
Affects this command: check_dft_rules
dft_identify_xsource_violations_from_timing_models
Syntax
dft_identify_xsource_violations_from_timing_models {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Indicates whether the DFT rule checker can automatically identify x-source violations from output pins of timing models. To enable automatic identification, set
this attribute to true.
Related Information
Affects this command: check_dft_rules -advanced
dft_ignore_dont_scan_for_shared_wrapper_processing
March 2025 1443 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_ignore_dont_scan_for_shared_wrapper_processing {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether or not to exclude non scan flops while marking wrapper cells.
dft_ignore_non_scan_for_wrapper_processing
Syntax
dft_ignore_non_scan_for_wrapper_processing {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, does not include shared wrapper cell on non-scan elements during 1500 processing. Also, it is not included in threshold calculation.
dft_include_controllable_pins_in_abstract_model
Syntax
dft_include_controllable_pins_in_abstract_model {allmodes | none | test_setup}
Applies to:
root
Description
Default: allmodes
Data_type: enum, read/write
Controls how design output pins which are controllable from design input pins under tied-constant propagation setup and test setup propagation are written to
the native or CTL abstract models.
This attribute can have the following values:
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Design for Test--root Attributes for DFT
allmodes Defines all design-level output signals which can be traced back to a design-level input signal for both tied-constant propagation setup run
separately from test setup propagation as DFT controllable by that input signal. If the output signal cannot be traced back to an input signal
and if the output pin is a constant, the test signal is defined on it.
Test setup propagation is also referred to as test_setup.
none Prevents writing out any additional information for design-level output signals which can be traced back to a design-level input signal for all
propagation analysis modes.
test_setup Defines all design-level output signals which can be traced back to a design-level input signal under test setup propagation as DFT
controllable by that input signal. If the output signal cannot be traced back to an input signal because the output pin is a constant under
test_setup, a test signal is defined for the output pin.
The dft_include_test_signal_outputs_in_abstract_model root attribute (default true) controls the writing of output signals to the
abstract models for outputs signals
whose values are constant under test_setup propagation
assigned to tied constant values
Test setup propagation refers to the propagation of tied-constants, test-mode and shift-enable signals.
Related Information
Affects this command: write_dft_abstract_model
Affected by this attribute: dft_include_test_signal_outputs_in_abstract_model
dft_include_test_signal_outputs_in_abstract_model
Syntax
dft_include_test_signal_outputs_in_abstract_model {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Enables writing output signals whose values are constant in test setup, and output signals assigned to tied constant values, as test mode signals in the native
abstract model and as constants in the CTL abstract models.
Related Information
Affects this command: write_dft_abstract_model
Affects this attribute: dft_include_controllable_pins_in_abstract_model
dft_insert_dedicated_inside_sink_hierarchy
March 2025 1445 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_insert_dedicated_inside_sink_hierarchy {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Inserts dedicated wrapper inside sink hierarchy.
dft_jtag_instance_name
dft_jtag_instance_name string
Description
Default: JTAG_MODULE
Data_type: string, read/write
Specifies the instance name of the JTAG macro.
Applies to:
root
Related Information
Affects these commands: add_jtag_boundary_scan
add_jtag_macro
dft_jtag_module_name
dft_jtag_module_name string
Description
Default: JTAG_MACRO
Data_type: string, read/write
Specifies the module name of the JTAG macro.
Applies to:
root
Related Information
Affects these commands: add_jtag_boundary_scan
add_jtag_macro
March 2025 1446 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
dft_lbist_capture_timing_mode_name
Syntax
dft_lbist_capture_timing_mode_name <string>
Applies to:
root
Description
Default: DFT_LBIST_CAPTURE_MODE
Data_type: string, read/write
Specifies the LBIST capture timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affects this command: add_lbist
dft_lbist_shift_timing_mode_name
Syntax
dft_lbist_shift_timing_mode_name <string>
Applies to:
root
Description
Default: DFT_LBIST_SHIFT_MODE
Data_type: string, read/write
Specifies the LBIST shift timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affects this command: add_lbist
dft_license_scheme
Syntax
dft_license_scheme {Modus | Encounter_Test}
March 2025 1447 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Applies to:
root
Description
Default: MODUS
Data_type: enum, read/write
Selects which license to use with DFT in the tool. By default, a Modus license is used to launch the Modus executable from the tool. To use an Encounter
Test license, set the attribute to 'Encounter_Test'.
dft_modedef_internal
Syntax
dft_modedef_internal {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies the use of the INTERNAL version of Modus’ MODEDEF files. These files should be used when the functional pins of the chip will not be tester contacted.
Related Information
Affects these commands: analyze_atpg_testability
write_dft_atpg
dft_modus_version
Syntax
dft_modus_version <version>
Applies to:
root
Description
Default: 22.11
Data_type: double, read/write
Specifies the Modus version for which to generate pin assign files.
March 2025 1448 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Affects these commands: analyze_atpg_testability
write_dft_atpg
write_dft_lbist_testbench
dft_opcg_block_input_to_flop_paths
Syntax
dft_opcg_block_input_to_flop_paths {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether to the block input ports to the flop paths.
When you perform synthesis on a block In a bottom-up test synthesis flow, and you apply test clocks to the block that are generated by OPCG domain macros
located outside the block, you must set this attribute to true. In this case, the input data is typically coming from a different clock domain. When this attribute is
enabled, the tool propagates unknown clocks from the primary inputs that are not defined as test clocks.
When you process the top level in test synthesis flow with OPCG logic insertion, the input data typically comes from the tester, which is static. In that case,
blocking is not required on the sink of an input port to the flop path.
Related Information
Affects this command: connect_scan_chains
dft_opcg_domain_blocking
Syntax
dft_opcg_domain_blocking {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enables OPCG domain blocking.
March 2025 1449 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Related Information
Affects this command: add_opcg
Related command: define_opcg_domain
dft_opcg_timing_mode_name
Syntax
dft_opcg_timing_mode_name <string>
Applies to:
root
Description
Default: DFT_OPCG_MODE
Data_type: string, read/write
Specifies the OPCG timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affects this command: add_opcg
dft_physical_aware_test_points
Syntax
dft_physical_aware_test_points {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
When true, enables physically aware test point sharing.
Related Information
Affects these commands: add_analyzed_test_points
syn_opt
dft_physical_pd_aware_scan_connection
March 2025 1450 Product Version 23.1
Genus Attribute Reference
Design for Test--root Attributes for DFT
Syntax
dft_physical_pd_aware_scan_connection {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, connect_scan_chains use physically aware power domain information while doing connection in a design.
Related Information
Affects these commands: connect_scan_chains
dft_pmbist_jtag_timing_mode_name
Syntax
dft_pmbist_jtag_timing_mode_name <string>
Applies to:
root
Description
Default: DFT_PMBIST_JTAG_MODE
Data_type: string, read/write
Specifies the PMBIST jtag timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affects these commands: add_jtag_boundary_scan
add_jtag_macro
add_pmbist
dft_pmbist_mda_timing_mode_name
Syntax
dft_pmbist_mda_timing_mode_name <string>
Applies to:
root
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Genus Attribute Reference
Design for Test--root Attributes for DFT
Description
Default: DFT_PMBIST_MDA_MODE
Data_type: bool, read/write
Specifies the PMBIST mda timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affects this command: add_pmbist
dft_power_aware_lockup_clock_driver
Syntax
dft_power_aware_lockup_clock_driver {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, enables power domain aware clock driver for lockup element.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
Affected by this command: connect_scan_chains
dft_power_aware_wrapper_insertion
Syntax
dft_power_aware_wrapper_insertion {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
When set to true, enables the power-aware wrapper insertion.
dft_prefix
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Design for Test--root Attributes for DFT
Syntax
dft_prefix <string>
Applies to:
root
Description
Default: DFT_
Data_type: bool, read/write
Specifies the prefix for instances of added control logic, and the base names for any scan-data input, scan-data output, shift-enable, scan_clock_a and
scan_clock_b ports or ports for compression test signals created during test synthesis.
The base names are prefixSDI_, prefixSDO_, prefixSEN_, prefixsclk_a_ or prefixsclk_b_, prefixcompression_enable, prefixspreader, prefixmask_load,
prefixmask_enable, prefixmask_sdi, prefixmask_sdo (depending on the pin type).
Related Information
Affects these commands: compress_scan_chains
connect_scan_chains
define_scan_chain
dft_process_multibit_for_shared_wrapper
Syntax
dft_process_multibit_for_shared_wrapper {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether or not to process multibit cells for shared wrapper cells.
dft_propagate_test_signals_from_hookup_pins_only
Syntax
dft_propagate_test_signals_from_hookup_pins_only {false | true}
Applies to:
root
Description
Default: false
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Design for Test--root Attributes for DFT
Data_type: bool, read/write
Controls constant propagation from the pin specified by a test signal’s pin attribute. Set this attribute to true to disable constant propagation from the pin
specified by the pin test_signal attribute.
Related Information
Affects this command: check_dft_rules
Related constraints: define_shift_enable
define_test_mode
dft_report_empty_test_clocks
Syntax
dft_report_empty_test_clocks {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Determines whether the DFT rule checker and the report_scan_setup command should report information on test clocks and their edges that do not drive any
registers. By default, this information is not reported.
Related Information
Affects these commands: check_dft_rules
report_scan_setup
dft_report_scan_register_quiet
Syntax
dft_report_scan_register_quiet {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, instance and segment information will not be printed.
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Design for Test--root Attributes for DFT
Related Information
Affects this command: report_scan_registers
dft_rtl_insertion
dft_rtl_insertion {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Enables the DFT RTL insertion flow. When set to true, the user-supplied RTL files will be updated with the RTL constructs for the inserted JTAG macro and
MBIST structures using the write_dft_rtl_model command.
Related Information
Inserting Programmable MBIST Logic in Genus PMBIST Guide.
Affects these commands: add_jtag_macro
add_pmbist
dft_run_test_point_analysis_for_compression
Syntax
dft_run_test_point_analysis_for_compression {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Run compression testpoint analysis directly from Genus when the attribute is set to true. Requires MOD400 license. When the attribute is false, you need to
launch Modus separately to perform testpoint analysis.
Related Information
Affected by this command: write_dft_compression_test_points
dft_run_test_point_analysis_for_lbist
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Design for Test--root Attributes for DFT
Syntax
dft_run_test_point_analysis_for_lbist {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Runs LBIST testpoint analysis directly from Genus when the attribute is set to true. Requires MOD400 license. When the attribute is false, you need to launch
Modus separately to perform testpoint analysis.
Related Information
Affected by this command: write_dft_lbist_test_points
dft_scan_power_domain_crossing_lockup_latch
Syntax
dft_scan_power_domain_crossing_lockup_latch {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, connect_scan_chains adds lockup latch at power domain crossing which are not skew safe.
Related Information
Affects these commands: connect_scan_chains
add_pmbist
dft_scan_style
dft_scan_style {muxed_scan | clocked_lssd_scan}
Description
Default: muxed_scan
Data_type: enum, read/write
Specifies the scan style for all designs read in.
This attribute can have the following values:
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Design for Test--root Attributes for DFT
clocked_lssd_scan Selects the clocked LSSD scan style.
muxed_scan Selects the muxed scan style.
Set the appropriate scan style before running check_dft_rules since the DFT rules vary with different scan styles.
Applies to:
root
Related Information
Affects these commands: check_dft_rules
connect_scan_chains
report_scan_registers
syn_map
dft_scanbit_waveform_analysis
Syntax
dft_scanbit_waveform_analysis {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, additional analysis of the test clock waveforms is performed to determine if a non-scan flop in an analyzed preserved segment or analyzed
scan chain is a scan-bit or a lockup flop.
To determine whether a non-scan flop is a scan-bit or lockup flop, the registers of the scan chain segment must pass the DFT rule checks.
Related Information
Affects these commands: define_scan_preserved_segment -analyze
define_scan_chain -analyze
dft_sdc_input_port_delay
Syntax
dft_sdc_input_port_delay <float>
Applies to:
root
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Design for Test--root Attributes for DFT
Description
Default: 0.0
Data_type: double, read/write
Specifies the I/O delay (in ps) to be applied through the set_input_delay command on all DFT-related input ports when DFT SDC generation is enabled.
dft_sdc_output_port_delay
Syntax
dft_sdc_output_port_delay <float>
Applies to:
root
Description
Default: 0.0
Data_type: double, read/write
Specifies the I/O delay (in ps) to be applied through the set_output_delay command on all DFT-related output ports when DFT SDC generation is enabled.
dft_shared_common_logic_threshold
Syntax
dft_shared_common_logic_threshold <integer>
Applies to:
root
Description
Default: 2
Data_type: int, read/write
Specifies the threshold for common logic to be included in shared threshold calculation.
dft_shared_wrapper_through
Syntax
dft_shared_wrapper_through {buffers | combinational | inverters_and_buffers}
Applies to:
root
Description
Default:
Data_type: string, read/write
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Design for Test--root Attributes for DFT
Specifies whether the 1500 wrapper analysis code will trace through the boundary logic to identify the functional flop(s) to be used as the test flop in the IEEE
1500 shared wrapper cells.
You must specify the value that is appropriate for your flow before running the 1500 wrapper analysis.
This attribute can have the following values:
buffers Identifies a functional flop as the boundary flop if it is mapped to a scan flop for DFT and is directly connected to the core pin
through a series of buffers.
combinational Identifies a functional flop as the boundary flop if it is mapped to a scan flop for DFT and is directly connected to the core pin
through complex combinational logic.
inverters_and_buffers Identifies a functional flop as the boundary flop if it is mapped to a scan flop for DFT and is directly connected to the core pin
through a series of inverters and buffers
dft_shift_register_identification_mode
Syntax
dft_shift_register_identification_mode {test_setup_shiftenable | test_setup | logical_only | testmode_only | testmode_shiftenable}
Applies to:
root
Description
Default: test_setup_shiftenable
Data_type: enum, red/write
Controls propagation of constants and test signals when identifying shift registers.
This attribute can have the following values:
logical_only Does not perform any constant value propagation.
test_setup Propagates constant values and test signal values.
test_setup_shiftenable Propagates logical constants, test-mode and shift-enable signal values.
testmode_only Propagates test-mode signal values only.
testmode_shiftenable Propagates test-mode and shift-enable signal values.
Related Information
Affects these commands: identify_shift_register_scan_segments
syn_map
Affected by this attribute: dft_auto_identify_shift_register
dft_shift_register_max_length
Syntax
dft_shift_register_max_length <integer>
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Design for Test--root Attributes for DFT
Applies to:
root
Description
Default: inf
Data_type: int, read/write
Specifies the maximum sequential length of the shift register for auto-identification.
Related Information
Affects this command: syn_map
Affected by this attribute: dft_auto_identify_shift_register
dft_shift_register_min_length
Syntax
dft_shift_register_min_length <integer>
Applies to:
root
Description
Default: 2
Data_type: int, read/write
Specifies the minimum sequential length of the shift register for auto-identification.
Related Information
Affects this command: syn_map
Affected by this attribute: dft_auto_identify_shift_register
dft_shift_register_with_mbci
Syntax
dft_shift_register_with_mbci {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the replacement of the higher order bits in the shift-register segment with multi-bit cells.
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Design for Test--root Attributes for DFT
dft_shift_timing_mode_name
Syntax
dft_shift_timing_mode_name <string>
Applies to:
root
Description
Default: DFT_SHIFT_MODE
Data_type: string, read/write
Specifies the the DFT shift timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
dft_tap_lockup_clock_from_adjacent
Syntax
dft_tap_lockup_clock_from_adjacent {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Connects lockup element clock to adjacent element clock pin.
Related Information
Affects this command: connect_scan_chains
dft_tpi_sharing_scope
Syntax
dft_tpi_sharing_scope {within_hier_only | within_power_domains_only | across_power_domains}
Applies to:
root
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Design for Test--root Attributes for DFT
Description
Default: within_hier_only
Data_type: string, read/write
Controls the scope of sharing for the inserted test points.
Related Information
Set by this command: add_analyzed_test_points
dft_true_time_flow
Syntax
dft_true_time_flow {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls generation of the Modus true time use model script, which allows access to all flows supported by the true time script.
Related Information
Affects this command: write_dft_atpg
dft_use_abstract_segment_instance_power_domain_for_scan_connection
Syntax
dft_use_abstract_segment_instance_power_domain_for_scan_connection {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, allows scan connection to use abstract segment instance power domain instead of pin power domain.
Related Information
Affects this command: connect_scan_chains
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Design for Test--root Attributes for DFT
dft_use_multibit_register_width_for_threshold
Syntax
dft_use_multibit_register_width_for_threshold {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, counts multibit cell length towards threshold for shared wrapper insertion.
dft_use_wck_as_default_wrapper_clock
Syntax
dft_use_wck_as_default_wrapper_clock {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
When set to true, fanin/fanout analysis clock is used if found else wck clock will be used if present.
Related Information
Affected by this command: add_core_wrapper_cell
dft_wait_for_license
Syntax
dft_wait_for_license {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
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Design for Test--root Attributes for DFT
Specifies that the DFT commands, which require a Modus license, must wait for a license to become available. By default, the command will fail if the required
license is not available.
The time that a command can wait for a license is controlled by the value of the 'genus -wait' command.
non_dft_timing_mode_name
Syntax
non_dft_timing_mode_name <string>
Applies to:
root
Description
Default: NON_DFT_MODE
Data_type: bool, read/write
Specifies the non-DFT timing mode name.
Related Information
Generating SDC Constraints in DFT in Genus Design for Test Guide.
pmbist_enable_multiple_views
Syntax
pmbist_enable_multiple_views {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls whether more than one view of a memory can be specified as a target for PMBIST.
When set to true, a logical wrapper and either a memory wrapper or a memory module can be the two different views of a given memory that must be included
in a common target group within the configuration file for PMBIST insertion to allow both views to be tested by PMBIST.
Related Information
Modus Product Requirements for Advanced Features in Genus Design for Test Guide.
Affects this command: add_pmbist
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Design for Test--root Attributes for DFT
pmbist_full_async_reset
Syntax
pmbist_full_async_reset {false | true}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls whether full PMBIST asynchronous reset is requested. When set to true, the full PMBIST asynchronous reset is implemented for all PMBIST logic.
Related Information
Modus Product Requirements for Advanced Features in Genus Design for Test Guide.
Affects this command: add_pmbist
unmap_scan_flops
unmap_scan_flops {false | true | not_mapped_for_dft}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls the selective unmapping and remapping of scan flip-flops during synthesis (during synthesis optimization, a mapped instance can be unmapped to
generic logic and then be remapped to a cell from one of the technology libraries).
This attribute can have the following values:
false Prevents unmapping of scan flip-flops. However, during optimization a scan register instance can still be replaced by a different
library cell to meet synthesis constraints. Using this setting, you can retain the scan chain connectivity while still allowing
optimization of the scan registers.
true Allows unmapping of all scan flip-flops. This implies that during optimization the flip-flops can loose their scan connectivity.
Therefore, you must run the connect_scan_chains command to recreate any scan chains in the design.
not_mapped_for_dft Allows unmapping and remapping of scan flip-flops that were not mapped for DFT.
Related Information
Affects these commands: syn_generic
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Design for Test--scan_chain Attributes for DFT
scan_chain Attributes for DFT
body
complete
compressed
dft_hookup_pin_sdi
dft_hookup_pin_sdo
domain
edge
head
max_length
non_shared_scan_out
scan_clock_a
scan_clock_b
scan_in
scan_out
sdi_compression_signal
shared_input
shared_output
shared_select
shift_enable
tail
terminal_lockup
body
body string
Read-only scan_chain attribute. Returns the name of the body segment of the user-specified scan chain.
Related Information
Set by this constraint: define_scan_chain
complete
complete {true | false}
Read-only scan_chain attribute. Indicates if the user-defined scan chain was completely user-specified (true) or was completed by analysis (false).
If a scan chain is marked complete, it means that all its components were specified through options of the define_scan_chain constraint, that is, the scan-data
input and output, and the head, tail, and body segments were all specified by the user.
Related Information
Set by this constraint: define_scan_chain
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Design for Test--scan_chain Attributes for DFT
compressed
compressed {true | false}
Read-only scan_chain attribute. Identifies if test compression will be applied to this chain.
Although this attribute is writable, you are expected not to change this attribute value.
Related Information
Set by this command: compress_scan_chains
Related attributes: dft_mask_clock
dft_compression_signal
dft_hookup_pin_sdi
dft_hookup_pin_sdi {pin|port}
Read-only scan_chain attribute. Returns the pin or port used by the tool to make the scan data input connection to the core logic.
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
dft_hookup_pin_sdo
dft_hookup_pin_sdo {pin|port}
Read-only scan_chain attribute. Returns the pin or port used by the tool to make the the scan data output connection from the core logic.
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
domain
domain string
Read-only scan_chain attribute. Returns the DFT clock domain associated with the user-specified scan chain.
Related Information
Set by this constraint: define_scan_chain
Related attribute: (actual_scan_chain) domain
edge
edge {rise | fall | any}
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Design for Test--scan_chain Attributes for DFT
Read-only scan_chain attribute. Returns the edge of the DFT clock domain associated with the user-specified scan chain.
Related Information
Set by this constraint: define_scan_chain
Related attribute: (actual_scan_chain) edge
head
head string
Read-only scan_chain attribute. Returns the name of the head segment of the user-specified scan chain.
Related Information
Set by this constraint: define_scan_chain
max_length
max_length integer
Read-only scan_chain attribute. Returns the maximum length that was allowed for this user-specified scan chain. This length might be slightly different than the
actual length.
Related Information
Set by this constraint: define_scan_chain
non_shared_scan_out
non_shared_scan_out {false | true}
Read-only scan_chain attribute. Controls whether the non-shared scan-data output port of this scan chain will be written as an "ignored output" pin constraint to
the LEC do file. By default, it is written as an "ignored output" pin constraint in the LEC do file.
You must set this attribute to true before connecting the scan chains.
Related Information
Set by this command: connect_scan_chains
Related attribute: (actual_scan_chain) non_shared_scan_out
scan_clock_a
scan_clock_a string
Read-only scan_chain attribute. Returns the path to the scan clock a (signal) of the scan chain.
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Design for Test--scan_chain Attributes for DFT
Related Information
Set by this constraint: define_scan_chain
Related attributes: (actual_scan_chain) scan_clock_a
(actual_scan_segment) scan_clock_a
(scan_segment) scan_clock_a
scan_clock_b
scan_clock_b string
Read-only scan_chain attribute. Returns the path to the scan clock b (signal) of the scan chain.
Related Information
Set by this constraint: define_scan_chain
Related attributes: (actual_scan_chain) scan_clock_b
(actual_scan_segment) scan_clock_b
(scan_segment) scan_clock_b
scan_in
scan_in string
Read-only scan_chain attribute. Returns the scan-data input pin of the user-specified scan chain.
Related Information
Set by this constraint: define_scan_chain
Related attributes: (actual_scan_chain) scan_in
(actual_scan_segment) scan_in
(scan_segment) scan_in
scan_out
scan_out string
Read-only scan_chain attribute. Returns the scan-data output pin of the user-specified scan chain.
Related Information
Set by this constraint: define_scan_chain
Related attributes: (actual_scan_chain) scan_out
(actual_scan_segment) scan_out
(scan_segment) scan_out
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Design for Test--scan_chain Attributes for DFT
sdi_compression_signal
sdi_compression_signal string
Read-only scan_chain attribute. If the attribute returns mask_enable, the scan data input pin of this chain is shared with the mask enable signal.
Related Information
Set by this command: compress_scan_chains
Related attribute: (actual_scan_chain) sdi_compression_signal
shared_input
shared_input {true | false}
Read-only scan_chain attribute. Indicates if the scan-data input port of this user-specified scan chain is shared with a functional port.
Related Information
Set by this constraint: define_scan_chain
Related attribute: (actual_scan_chain) shared_input
shared_output
shared_output {true | false}
Read-only scan_chain attribute. Indicates if the scan-data output port of this user-specified scan chain is shared with a functional port.
Related Information
Set by this constraint: define_scan_chain
Related attribute: (actual_scan_chain) shared_output
shared_select
shared_select string
Read-only scan_chain attribute. Returns the control test signal for the mux of the shared scan data output port.
Related Information
Set by these commands: define_scan_chain
Related attribute: (actual_scan_chain) shared_select
shift_enable
shift_enable string
Read-only scan_chain attribute. Returns the chain-specific shift-enable port or pin for the muxed_scan scan style. This is a computed attribute. Computed
attributes are potentially very time consuming to process and not listed by the vls command by default.
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Design for Test--scan_segment Attributes for DFT
Related Information
Set by this constraint: define_scan_chain
Related attributes: (actual_scan_chain) shift_enable
(actual_scan_segment) shift_enable
(scan_segment) shift_enable
tail
tail string
Read-only scan_chain attribute. Returns the name of the tail segment of the user-specified scan chain.
Related Information
Set by this constraint: define_scan_chain
terminal_lockup
terminal_lockup {none | level_sensitive | edge_sensitive}
Read-only scan_chain attribute. Returns the type of the terminal lockup element inserted at the tail end of the user-specified chain.
This attribute can have the following values:
edge-sensitive Indicates that the terminal lockup element inserted is a flip-flop.
level-sensitive Indicates that the terminal lockup element inserted is a latch.
none Indicates that a scan chain does not have a terminal lockup.
Related Information
Set by this constraint: define_scan_chain
Related attribute: (actual_scan_chain) terminal_lockup
scan_segment Attributes for DFT
active
clock
clock_edge
clock_gating_shift_enable
connected_scan_clock_a
connected_scan_clock_b
connected_shift_enable
core_wrapper
core_wrapper_ports
core_wrapper_type
core_wrapper_usage
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Design for Test--scan_segment Attributes for DFT
ctl_defined
dft_hookup_pin_sdi
dft_hookup_pin_sdo
dft_tail_test_clock
dft_tail_test_clock_edge
dft_tail_test_clock_waveform_edge
elements
head_skew_safe
instance
model_defined
other_clocks
power_domain
reg_count
reorderable
scan_clock_a
scan_clock_b
scan_in
scan_out
shift_enable
skew_safe
tail_clock
tail_clock_edge
test_modes
user_defined_segment
active
active {low | high}
Read-only scan_segment attribute. Specifies the active value of the shift-enable port at the boundary of the blackbox in which this segment is defined.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Informaion
Set by this constraint: define_scan_abstract_segment
Related attributes: (actual_scan_segment) active
(test signal) active
clock
clock string
Read-only scan_segment attribute. Returns the clock port driving the flip-flops at the head (shift-in position) of this user-defined scan segment.
This attribute applies only to abstract scan segments. For other types of segments this attribute has no value.
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Design for Test--scan_segment Attributes for DFT
Related Information
Set by this constraint: define_scan_abstract_segment
Related attribute: (actual_scan_segment) clock
clock_edge
clock_edge {fall | rise}
Read-only scan_segment attribute. Returns the active edge of the clock driving the flip-flops at the head (shift-in position) of this user-defined scan segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this constraint: define_scan_abstract_segment
Related attribute: (actual_scan_segment) clock_edge
clock_gating_shift_enable
clock_gating_shift_enable string
Read-only scan_segment attribute. Returns the clock gating shift enable pin for an abstract, preserved or shift-register segment.
connected_scan_clock_a
connected_scan_clock_a {true | false}
Read-only scan_segment attribute. Indicates if the scan clock a port of the module boundary is driven by external logic (preconnected) or if the scan clock a
signal is internally generated within the module boundary.
Related Information
Set by this constraint: define_scan_preserved_segment
Related attribute: (actual_scan_segment) connected_scan_clock_a
connected_scan_clock_b
connected_scan_clock_b {true | false}
Read-only scan_segment attribute. Indicates if the scan clock b port of the module boundary is driven by external logic (preconnected) or if the scan clock b
signal is internally generated within the module boundary.
Related Information
Set by this constraint: define_scan_preserved_segment
Related attribute: (actual_scan_segment) connected_scan_clock_b
connected_shift_enable
connected_shift_enable {true | false}
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Design for Test--scan_segment Attributes for DFT
Read-only scan_segment attribute. Indicates if the shift enable port of the module boundary is driven by external logic (preconnected) or if the shift enable signal
is internally generated within the module boundary.
This attribute applies only to abstract segments and preserved segments. For other types of segments this attribute has no value.
Related Information
Set by these constraints: define_scan_abstract_segment
define_scan_preserved_segment
Related attribute: (actual_scan_chain) connected_shift_enable
(actual_scan_segment) connected_shift_enable
core_wrapper
core_wrapper {true | false}
Read-write scan_segment attribute. Indicates whether the segment was created for a core wrapper cell.
Related Information
Set by this command: add_core_wrapper_cell
Related attribute: (active scan segment) core_wrapper
core_wrapper_ports
core_wrapper_ports {pins | ports}
Read-write scan_segment attribute. Specifies the pins or ports associated with this wrapper segment. More than one port can be associated with a shared
wrapper segment.
This attribute only applies to segments for which the core_wrapper attribute is set to true.
Related Information
Set by this command: add_core_wrapper_cell
core_wrapper_type
core_wrapper_type string
Read-write scan_segment attribute. Indicates whether this wrapper segment is shared or dedicated.
This attribute only applies to segments for which the core_wrapper attribute is set to true.
Related Information
Set by this command: add_core_wrapper_cell
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Design for Test--scan_segment Attributes for DFT
core_wrapper_usage
core_wrapper_usage string
Read-write scan_segment attribute. Specifies what is the wrapper segment used for.
Based on the fanout analysis from an input port or fanin analysis from an output port, the tool identifies which sets of functional flops are used for input bounding
(meaning that the wrapper cells will load the test data when WINT=1 to test the core logic), or for output bounding (meaning that the wrapper cell will load the
test data when WEXT=1 to provide test data external to the core to test the interconnect and surrounding logic. WINT and WEXT are mutually exclusive signals.
This attribute only applies to segments for which the core_wrapper attribute is set to true.
Related Information
Set by this command: add_core_wrapper_cell
ctl_defined
ctl_defined {false | true}
Default: false
Read-Write scan_segment attribute. Indicates whether the scan segment is defined in CTL abstract model.
dft_hookup_pin_sdi
dft_hookup_pin_sdi {pin | port}
Read-only scan_segment attribute. Returns the pin or port used by the tool to make the scan data input connection to the core logic.
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
dft_hookup_pin_sdo
dft_hookup_pin_sdo {pin | port}
Read-only scan_segment attribute. Returns the pin or port used by the tool to make the scan data output connection from the core logic.
Related Information
Affected by these commands: define_scan_abstract_segment
define_scan_chain
dft_tail_test_clock
dft_tail_test_clock string
Read-only scan_segment attribute. Returns the top-level clock object that corresponds to the clock port driving the flip-flops at the tail (shift-out position) of this
segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
March 2025 1475 Product Version 23.1
Genus Attribute Reference
Design for Test--scan_segment Attributes for DFT
Related Information
Set by this command: check_dft_rules
Related attribute: (actual_scan_segment) dft_tail_test_clock
dft_tail_test_clock_edge
dft_tail_test_clock_edge {rise | fall}
Read-only scan_segment attribute. Returns the active edge of the top-level clock object that corresponds to the clock port driving the flip-flops at the tail (shift-out
position) of this segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this command: check_dft_rules
Related attribute: (actual_scan_segment) dft_tail_test_clock_edge
dft_tail_test_clock_waveform_edge
dft_tail_test_clock_waveform_edge {leading | trailing}
Read-only scan_segment attribute. Returns the active waveform edge of the top-level clock object that corresponds to the clock port driving the flip-flops at the
tail (shift-out position) of this segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this command: check_dft_rules
Related attribute: (actual_scan_segment) dft_tail_test_clock_waveform_edge
elements
elements string
Read-only scan_segment attribute. Returns a Tcl list of the elements in this user-defined scan segment.
Related Information
Set by these constraints: define_scan_abstract_segment
define_scan_fixed_segment
define_scan_floating_segment
define_scan_preserved_segment
define_shift_register_segment
Related attribute: (actual_scan_chain) elements
(actual_scan_segment) elements
March 2025 1476 Product Version 23.1
Genus Attribute Reference
Design for Test--scan_segment Attributes for DFT
head_skew_safe
head_skew_safe {true | false}
Read-only scan_segment attribute. Indicates if the segment has a data lockup element connected at the head of its scan segment.
This applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Reporting Specific Aspects of Chains or Segments in Genus Design for Test Guide.
Set by this command: connect_scan_chains
Related attribute: (actual_scan_segment) head_skew_safe
instance
instance string
Read-only scan_segment attribute. Returns the instance name of the module for which the abstract segment was defined.
Related Information
Set by this constraint: define_scan_abstract_segment
Related attribute: (actual_scan_segment) instance
model_defined
model_defined {false | true}
Default: false
Read-Write scan_segment attribute. Indicates whether the scan segment is defined in abstract model.
other_clocks
other_clocks string
Read-only scan_segment attribute. Returns a Tcl list containing the other clock pins of the segment and their active values.
Related Information
Set by these constraints: define_scan_abstract_segment
define_scan_fixed_segment
define_scan_floating_segment
define_scan_preserved_segment
define_shift_register_segment
Related attributes: (actual_scan_chain) other_clocks
(actual_scan_segment) other_clocks
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Genus Attribute Reference
Design for Test--scan_segment Attributes for DFT
power_domain
power_domain domain
Read-only scan_segment attribute. Returns the power domain of this scan segment.
This attribute applies only to segments inserted by the add_core_wrapper_cell command that also have the following scan_segment attribute settings:
core_wrapper = true
type = preserved
Related Information
Set by this command: add_core_wrapper_cell
Related attributes: (scan_segment) core_wrapper
(scan_segment) type
Related attributes: (actual_scan_chain) power_domain
(actual_scan_segment) power_domain
reg_count
reg_count integer
Read-only scan_segment attribute. Returns the number of flops in this user-defined scan segment.
Related Information
Set by these constraints: define_scan_abstract_segment
define_scan_fixed_segment
define_scan_floating_segment
define_scan_preserved_segment
define_shift_register_segment
Related attributes: (actual_scan_chain) reg_count
(actual_scan_segment) reg_count
(violation) reg_count
reorderable
reorderable {true | false}
Read-only scan_segment attribute. Indicates if the preserved segment is reorderable for scanDEF purposes.
This attribute applies only to preserved segments. For other types of segments this attribute has no value.
Related Information
Set by this command: define_scan_preserved_segment
Related attribute: (actual_scan_segment) reorderable
March 2025 1478 Product Version 23.1
Genus Attribute Reference
Design for Test--scan_segment Attributes for DFT
scan_clock_a
scan_clock_a string
Read-only scan_segment attribute. Returns the scan clock A pin for an abstract segment.
Related Information
Set by this constraint: define_scan_abstract_segment
Related attributes: (actual_scan_chain) scan_clock_a
(actual_scan_segment) scan_clock_a
(scan_chain) scan_clock_a
scan_clock_b
scan_clock_b string
Read-only scan_segment attribute. Returns the scan clock B pin for an abstract segment.
Related Information
Set by this command: define_scan_abstract_segment
Related attributes: (actual_scan_chain) scan_clock_b
(actual_scan_segment) scan_clock_b
(scan_chain) scan_clock_b
scan_in
scan_in string
Read-only scan_segment attribute. Returns the scan-data input of this user-defined scan segment.
This attribute applies only to abstract segments and preserved segments. For other types of segments this attribute has no value.
Related Information
Set by these constraints: define_scan_abstract_segment
define_scan_preserved_segment
Related attributes: (actual_scan_chain) scan_in
(actual_scan_segment) scan_in
(scan_chain) scan_in
scan_out
scan_out string
Read-only scan_segment attribute. Returns the scan-data output of this user-defined scan segment.
This attribute applies only to abstract segments and preserved segments. For other types of segments this attribute has no value.
March 2025 1479 Product Version 23.1
Genus Attribute Reference
Design for Test--scan_segment Attributes for DFT
Related Information
Set by this constraint: define_scan_abstract_segment
Related attributes: (actual_scan_chain) scan_out
(actual_scan_segment) scan_out
(scan_chain) scan_out
shift_enable
shift_enable string
Read-only scan_segment attribute. Returns the shift-enable port at the boundary of the blackbox in which this segment is defined.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this constraint: define_scan_abstract_segment
Related attributes: (actual_scan_chain) shift_enable
(actual_scan_segment) shift_enable
(scan_chain) shift_enable
skew_safe
skew_safe {true | false}
Read-only scan_segment attribute. Indicates if this user-defined scan segment has a data lockup element connected at the end of its scan chain.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by these constraints: define_scan_abstract_segment
Related attribute: (actual_scan_segment) skew_safe
tail_clock
tail_clock string
Read-only scan_segment attribute. Returns the clock port driving the flip-flops at the tail (shift-out position) of this user-defined scan segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this constraint: define_scan_abstract_segment
Related attribute: (actual_scan_segment) tail_clock
March 2025 1480 Product Version 23.1
Genus Attribute Reference
Design for Test--tap_port Attributes for DFT
tail_clock_edge
tail_clock_edge {rise | fall}
Read-only scan_segment attribute. Returns the active edge of the clock driving the flip-flops at the tail (shift-out position) of this user-defined scan segment.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this constraint: define_scan_abstract_segment
Related attribute: (actual_scan_segment) tail_clock_edge
test_modes
test_modes string
Read-only scan_segment attribute. Returns a Tcl list containing the test mode pins of the segment and their active values.
This attribute applies only to abstract segments. For other types of segments this attribute has no value.
Related Information
Set by this constraint: define_scan_abstract_segment
user_defined_segment
user_defined_segment {true | false}
Read-only scan_segment attribute. Indicates whether the segment is a user-defined segment or a shift register segment that was automatically identified by
Genus.
Related Information
Set by these constraints: define_scan_abstract_segment
define_scan_fixed_segment
define_scan_floating_segment
define_scan_preserved_segment
define_shift_register_segment
Set by this command: identify_shift_register_scan_segments
tap_port Attributes for DFT
dft_hookup_pin
dft_hookup_polarity
March 2025 1481 Product Version 23.1
Genus Attribute Reference
Design for Test--test_bus_port Attributes for DFT
dft_hookup_pin
dft_hookup_pin {hpin | pin | constant | pg_pin | hport | port}
Read-only tap_port attribute. Returns the path to the pin or port where the TAP signal actually hooks up inside the core.
Related Information
Set by this constraint: define_jtag_tap_port
dft_hookup_polarity
dft_hookup_polarity {inverted | non_inverted}
Read-only tap_port attribute. Indicates whether the TAP signal is inverted or not at the hookup pin or port.
Related Information
Set by this constraint: define_jtag_tap_port
test_bus_port Attributes for DFT
active
dft_hookup_pin
function
active
active {low | high}
Read-write test_bus_port attribute. Specifies the active value of test bus port.
dft_hookup_pin
dft_hookup_pin {hpin | pin | constant | pg_pin | hport | port}
Read-only test_bus_port attribute. Returns the path to the pin or port where the test signal actually hooks up inside the core.
Related Information
Set by this constraint: define_test_bus_port
function
function string
Read-only test_bus_port attribute. Returns the function of the test bus port.
For a list of possible functions refer to the define_test_bus_port command in the Genus Command Reference.
March 2025 1482 Product Version 23.1
Genus Attribute Reference
Design for Test--test_clock Attributes for DFT
Related Information
Set by this constraint: define_test_bus_port
test_clock Attributes for DFT
at_speed
atpg_use
blocking_se
controllable
controllable_from
dft_hookup_pin
dft_hookup_polarity
dft_mask_clock
dft_misr_clock
divide_fall
divide_period
divide_rise
domain_se
fall
function
off_state
period
rise
root_source_pins
root_source_polarity
sources
user_defined_signal
at_speed
at_speed {false | true}
Default: false
Read-write test_clock attribute. Specifies whether the test clock is an at-speed test clock.
When you use a test synthesis flow with OPCG logic insertion, the tool automatically identifies the test clocks generated by the OPCG domain macros and sets
the at_speed attribute to true for these test clocks.
When you perform synthesis on a block In a bottom-up test synthesis flow, and you apply a test clock to the block that is generated by an OPCG domain macro
located outside the block, you must set this attribute manually on the clock input pin.
When you perform synthesis on a block In a bottom-up test synthesis flow, and a test clock is internally generated in the block and connected to an output pin or
port of the block, the write_dft_abstract_model command will set this attribute to true for this test clock and add it to the scan abstract model.
Related Information
Related commands: add_opcg
write_dft_abstract_model
March 2025 1483 Product Version 23.1
Genus Attribute Reference
Design for Test--test_clock Attributes for DFT
atpg_use
atpg_use {none | master_test_enable | misr_reset_clock | opcg_blocking_se | opcg_custom_se | opcg_enable | opcg_edge_mode | opcg_trigger}
Default: none
Read-write test_clock attribute. Specifies the ATPG purpose of the test signal.
This attribute can have the following values:
master_test_enable Signal is used to gate the compression enable signal used for compression.
misr_reset_clock Signal is used to asynchronously reset the MISR.
none Signal has no special ATPG purpose.
opcg_blocking_se Signal is used as domain blocking scan enable.
opcg_custome_se Signal is used as special blocking scan enable generated by that OPCG domain’s domain macro. OPCG domain macro.
opcg_enable Signal is used to enable the on-product clock generation logic.
opcg_edge_mode Signal is used to connect to the toggle muxes added to the input flops of an OPCG domain.
opcg_trigger Signal is used to trigger the generation of delay test pulses.
Related Information
Set by these commands: compress_scan_chains
connect_scan_chains
define_opcg_trigger
define_opcg_osc_source
add_opcg
blocking_se
blocking_se test_signal
Read-write test_clock attribute. Specifies the blocking shift-enable signal to be used for the specified test clock.
When you use a test synthesis flow with OPCG logic insertion, the tool automatically identifies the blocking shift-enable signal for the generated test clocks and
sets the blocking_se attribute on the test clocks.
When you perform synthesis on a block In a bottom-up test synthesis flow, and you apply a test clock to the block that is generated by an OPCG domain macro
located outside the block, you must set this attribute manually on the clock input pin.
When you perform synthesis on a block In a bottom-up test synthesis flow, and a test clock is internally generated in the block and connected to an output pin or
port of the block, the write_dft_abstract_model command will set this attribute for this test clock and add it to the scan abstract model.
Related Information
Related commands: add_opcg
write_dft_abstract_model
controllable
controllable {true | false}
Default: true
Read-write test_clock attribute. Indicates whether the test clock is controllable in test mode.
March 2025 1484 Product Version 23.1
Genus Attribute Reference
Design for Test--test_clock Attributes for DFT
controllable_from
controllable_from {hpin |pin | constant | pg_pin | hport | port}
Default: no_value
Read-only test_clock attribute. Indicates the source from where the test clock is controllable.
dft_hookup_pin
dft_hookup_pin {hpin |pin | constant | pg_pin | hport | port}
Read-only test_clock attribute. Returns the path to the pin or port where the test signal or scan data input or output actually hooks up inside the core.
dft_hookup_polarity
dft_hookup_polarity {inverted | non_inverted}
Read-only test_clock attribute. Indicates whether the test signal is inverted or not at the hookup pin or port.
Related Information
Affected by these commands: define_test_clock
Related attribute: (test_signal) dft_hookup_polarity
dft_mask_clock
dft_mask_clock {false | true}
Default: false
Read-write test_clock attribute. Indicates whether the test clock is used for compression mask logic. This attribute is used by the
write_dft_atpg_other_vendor_files and write_et commands to produce the correct assign files when a different clock is used to control the mask.
Related Information
Set by this command: compress_scan_chains
Related attributes: compressed
dft_compression_signal
dft_misr_clock
dft_misr_clock {false | true}
Default: false
Read-write test_clock attribute. Indicates whether the test clock is used for compression misr logic. This attribute is used by the
write_dft_atpg_other_vendor_files and write_et commands to produce the correct assign files when a different clock is used to control the misr.
Related Information
Set by this command: compress_scan_chains
Related attributes: compressed
dft_compression_signal
March 2025 1485 Product Version 23.1
Genus Attribute Reference
Design for Test--test_clock Attributes for DFT
divide_fall
divide_fall integer
Read-only test_clock attribute. Returns the value specified using the -divide_fall option of the define_test_clock command.
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
Related attribute: (test_signal) divide_fall
divide_period
divide_period integer
Read-only test_clock attribute. Returns the value specified using the -divide_period option of the define_test_clock command.
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
Related attribute: (test_signal) divide_period
divide_rise
divide_rise integer
Read-only test_clock attribute. Returns the value specified using the -divide_rise option of the define_test_clock command.
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
Related attribute: (test_signal) divide_rise
domain_se
domain_se test_signal
Read-write test_clock attribute. Specifies the shift-enable signal to be used for all elements of a domain that are not domain-crossing or belong to abstract
segments.
By default, this attribute points to an internal shift-enable that is defined on the OPCG domain macro output pin SCANEN_OUT.
When OPCG Launch-Off-Shift (LOS) is implemented, this output is connected to the output of the OR gate between the shift-enable (SE) and the pipelined
SE.
When LOS is not implemented, this output does a simple feedthrough of the SE.
In all cases, the connection of the SE signal of all elements clocked by an OPCG domain will always be domain-specific.
March 2025 1486 Product Version 23.1
Genus Attribute Reference
Design for Test--test_clock Attributes for DFT
Related Information
Block-Level Domain-Blocking Flow in Genus Design for Test Guide.
Related commands: add_opcg
fall
fall integer
Read-only test_clock attribute. Returns the value specified using the -fall option of the define_test_clock command.
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
Related attribute: (test_signal) fall
function
function {test_clock | dft_clock | compressor_clock}
Read-only test_clock attribute. Returns the value specified using the -function option of the define_test_clock command.
Related Information
Set by this constraint: define_test_clock
off_state
off_state {0 | 1}
Read-only test_clock attribute. Indicates the off-state of the system clock in scan-shift mode.
This attribute applies only to the clocked LSSD scan style. For other scan styles this attribute has no value.
Related Information
Set by this command: check_dft_rules
Affected by this attribute: dft_scan_style
period
period integer
Default: 50000 (in picoseconds, corresponds to a clock frequency of 20MHz)
Read-only test_clock attribute. Returns the value specified using the -period option of the define_test_clock command.
Even when you did not define any test clock, they are automatically identified by the check_dft_rules command and given default values for the clock.
March 2025 1487 Product Version 23.1
Genus Attribute Reference
Design for Test--test_clock Attributes for DFT
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
Related attribute: (test_signal) period
rise
rise integer
Default: 50 (rising edge at 50 percent of the cycle period)
Read-only test_clock attribute. Returns the value specified using the -rise option of the define_test_clock command.
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
Related attribute: (test_signal) rise
root_source_pins
root_source_pins list
Read-only test_clock attribute. Returns a Tcl list of the ports and pins that correspond to the drivers of the clock.
For a primary clock, or an internal test clock defined with the -controllable option, the value of this attribute is the same as that of the sources attribute.
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
root_source_polarity
root_source_polarity {inverting | non_inverting}
Read-only test_clock attribute. Returns the polarity between the internal clock pin and its root pin.
For a primary clock, or an internal test clock defined with the -controllable option, the value of this attribute is always non_inverting.
Related Information
Set by this constraint: define_test_clock
Set by this command: check_dft_rules
sources
sources string
Read-only test_clock attribute. Returns a Tcl list of the ports and pins that are sources of the test clock waveform.
March 2025 1488 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
user_defined_signal
user_defined_signal {true|false}
Read-write test_clock attribute. Indicates whether the test clock was user-defined (through a define_test_clock constraint) or determined by the DFT rule
checker.
Although this attribute is writable, you are expected not to change this attribute value.
Related Information
Affected by this constraint: define_test_clock
Affected by this command: check_dft_rules
Related attribute: (test signal) user_defined_signal
test_signal Attributes for DFT
active
atpg_use
dedicated_pin
default_shift_enable
dft_compression_signal
dft_hookup_pin
dft_hookup_polarity
divide_fall
divide_period
divide_rise
fall
function
has_fanout
ideal
lec_value
master_signal
period
pmbist_use
rise
scan_shift
user_defined_signal
wir_reset_value
wir_signal
wir_tm_value
active
active dft_active_value
March 2025 1489 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
Read-write test_signal attribute. Specifies the active value of the test signal. The value can be either high or low.
Related Information
Set by these constraints: define_shift_enable
define_test_mode
Set by this command: check_dft_rules
Related attributes: (actual_scan_segment) active
(scan_segment) active
atpg_use
atpg_use {none | master_test_enable | misr_reset_clock | opcg_blocking_se | opcg_custom_se | opcg_enable | opcg_edge_mode | opcg_trigger}
Default: none
Read-write test_signal attribute. Specifies the ATPG purpose of the test signal.
This attribute can have the following values:
master_test_enable Signal is used to gate the compression enable signal used for compression.
misr_reset_clock Signal is used to asynchronously reset the MISR.
none Signal has no special ATPG purpose.
opcg_blocking_se Signal is used as domain blocking scan enable.
opcg_custome_se Signal is used as special blocking scan enable generated by that OPCG domain’s domain macro. OPCG domain macro.
opcg_enable Signal is used to enable the on-product clock generation logic.
opcg_edge_mode Signal is used to connect to the toggle muxes added to the input flops of an OPCG domain.
opcg_trigger Signal is used to trigger the generation of delay test pulses.
Related Information
Set by these commands: compress_scan_chains
connect_scan_chains
define_opcg_trigger
define_opcg_osc_source
add_opcg
dedicated_pin
dedicated_pin {false | true}
Default: false
Read-write test_signal attribute. Indicates whether the driving pin (port) of a test signal is considered dedicated for test. The driving port is considered
dedicated for test if the port was created by the Genus-DFT engine, or if the existing port was not specified as a shared functional data port when defining the
test signal.
March 2025 1490 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
Related Information
Set by these constraints: define_shift_enable
define_test_mode
default_shift_enable
default_shift_enable {false | true}
Default: false
Read-write test_signal attribute. Indicates if this test signal is the default shift-enable signal.
This attribute applies only to test signals of type shift_enable. For other types of test signals this attribute has no value.
Related Information
Set by this constraint: define_shift_enable
Set by this command: check_dft_rules
dft_compression_signal
dft_compression_signal {none | mask_enable | mask_load | compression_enable |spreader}
Default: none
Read-write test_signal attribute. Indicates the type of the compression signal.
This attribute can have the following values:
compression_enable Indicates that the test signal is the compression (space compactor) enable signal.
mask_enable Indicates that the test signal is the channel mask enable signal.
mask_load Indicates that the test signal is the channel mask load signal.
none Indicates that the test signal is not related to chain compression.
spreader Indicates that the test signal is the decompressor spread enable signal.
Related Information
Set by this command: compress_scan_chains
Related attributes: compressed
dft_mask_clock
dft_hookup_pin
dft_hookup_pin {hpin|pin|constant|pg_pin|hport|port}
Read-only test_signal attribute. Returns the path to the pin or port where the test signal or scan data input or output actually hooks up inside the core.
March 2025 1491 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
Related Information
Affected by these constraints: define_shift_enable
define_test_mode
Related attribute: (test_clock) dft_hookup_pin
dft_hookup_polarity
dft_hookup_polarity {inverted | non_inverted}
Read-only test_signal attribute. Indicates whether the test signal is inverted or not at the hookup pin or port.
Example
genus@root:> get_db [get_db test_signals SE] .dft_hookup_polaritynon_inverted
Related Information
Affected by these constraints define_shift_enable
define_test_mode
Related attribute: (test_clock) dft_hookup_polarity
divide_fall
divide_fall integer
Default:100
Read-write test_signal attribute. Returns the value specified using the -divide_fall option of the define_lssd_scan_clock_a or define_lssd_scan_clock_b
command.
Related Information
Related attribute: (test_clock) divide_fall
divide_period
divide_period integer
Default: 1
Read-write test_signal attribute. Returns the value specified using the -divide_period option of the define_lssd_scan_clock_a or define_lssd_scan_clock_b
command.
Related Information
Related attribute: (test_clock) divide_period
divide_rise
divide_rise integer
Default: 100
March 2025 1492 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
Read-write test_signal attribute. Returns the value specified using the -divide_rise option of the define_lssd_scan_clock_a or define_lssd_scan_clock_b
command.
Related Information
Related attribute: (test_clock) divide_rise
fall
fall integer
Default: 60 (80) for a test signal of type scan_clock_a (scan_clock_b)
Read-write test_signal attribute. Returns the value specified using the -fall option of the define_lssd_scan_clock_a or define_lssd_scan_clock_b
command.
Related Information
Related attribute: (test_clock) fall
function
function string
Read-only test_signal attribute. Returns the function of the test signal.
For a list of possible functions refer to the define_test_signal command in the Genus Command Reference.
Related Information
Set by this constraint: define_test_signal
has_fanout
has_fanout {false | true | test_only}
Read-write test_signal attribute. Specifies whether the test_mode pin has a fanout to timing endpoints when the test signal was defined. If the test signal was
defined with the -test_only option, this attribute will be set to test_only.
Related Information
Set by these constraints: define_test_mode
Set by this command: check_dft_rules
ideal
ideal {true| false}
Default: true
Read-write test_signal attribute. Indicates if this test signal is marked as ideal. Marking a test signal as ideal, prevents buffering of the shift-enable or test-
mode network during optimization.
March 2025 1493 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
Related Information
Set by these constraints: define_shift_enable
define_test_mode
Set by this command: check_dft_rules
lec_value
lec_value {auto | 0 | 1 | no_value}
Default: auto
Read-write test_signal attribute. Specifies how to constrain the test pin for LEC validation with the write_do_lec command. This attribute can have the
following values:
0 Indicates that a logic 0 will be specified for the add pin constraint command in the do file.
1 Indicates that a logic 1 will be specified for the add pin constraint command in the do file.
auto Indicates that the opposite of the test mode active value will be specified for the add pin constraint command in the do file.
no_value Indicates that no add pin constraint command will be written for this test signal in the do file.
Related Information
Set by these constraints: define_shift_enable
define_test_mode
Affects this command: write_do_lec
master_signal
master_signal {true| false}
Default: true
Read-write test_signal attribute. Specifies whether this test signal is a master test signal.
This attribute is relevant when multiple test signals are defined on a pin.
period
period integer
Default: 50000 (in picoseconds, corresponds to a clock frequency of 20MHz)
Read-write test_signal attribute. Returns the value specified using the -period option of the define_lssd_scan_clock_a or define_lssd_scan_clock_b
command.
Related Information
Related attribute: (test_clock) period
March 2025 1494 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
pmbist_use
pmbist_use {none | retention_pause_active
| retention_pause_continue| test_block_async_reset
| test_clock_select | test_rambypass | test_ramsequential}
Read-write test_signal attribute. Specifies how the test signal should be used to control the programmable MBIST logic during ATPG. Following controls can
be used for the PMBIST logic during ATPG: test_block_async_reset, test_clock_reset, test_rambypass and test_ramsequential. This attribute can have the
following values:
none Does not use this test signal to control PMBIST during ATPG.
retention_pause_active Applies this test signal to the output of the PMBIST logic which monitors the pause interval of the retention test. An observing
signal from the PMBIST logic which is active high. When asserted, it indicates that the PMBIST logic is in the pause state in all
active clock domains.
retention_pause_continue Applies this test signal to the input of the PMBIST logic which controls the pause interval of the retention test. A control signal
input to the PMBIST logic which is active high. When asserted, the PMBIST logic remains in pause state once entered until
pause_duration completes and retention_pause_continue has been de-asserted. The PMBIST logic starts sampling
retention_pause_continue once the pause_duration period has expired within each clock domain. Without specification, the
retention_pause_continue signal is tied to constant-0 by default to get current behavior.
test_block_async_reset Applies this test signal to the input of the PMBIST logic which controls the async reset register inputs used within the design.
When asserted, the test signal blocks the async reset input to registers within the PMBIST logic, allowing some control in
testing these async reset paths. You must specify this control.
test_clock_select Applies this test signal to the input of the PMBIST logic which controls the selection of the clock source for the PMBIST test
data registers which are shared by the JTAG and direct access functions.
Selection of the clock source may be required for ATPG true time analysis. When you use the JTAG access and direct access
with two different clock sources for these access methods, you must specify the control. When this test signal is set to its active
state, it selects the PMBIST direct access mda_tck clock source; otherwise the JTAG clock source is selected.
test_rambypass Applies this test signal to the input of the PMBIST logic which is necessary for SRAMs which lack internal ATPG bypass logic.
The tool inserts such logic to support logic testing around the SRAMs during ATPG. The test signal is only required when
such bypass logic is requested at the time of PMBIST logic insertion. When this test signal is set to its active state, it forces the
memory data inputs to bypass the memory and be routed to the data outputs.
test_ramsequential Applies this test signal to the input of the PMBIST logic that controls the inserted MUXes (on the input side) to allow RAM
sequential testing. Since the RAM sequential require to go through the memory, if specified, the test signal specified with
test_ramsequential use must be different from the test signal specified with the test_rambypass use as they are incompatible.
Related Information
Affects this command: add_pmbist
rise
rise integer
Default: 50 (70) for a test signal of type scan_clock_a (scan_clock_b)
Read-write test_signal attribute. Returns the value specified using the -rise option of the define_lssd_scan_clock_a or define_lssd_scan_clock_b
command.
Related Information
Related attribute: (test_clock) rise
March 2025 1495 Product Version 23.1
Genus Attribute Reference
Design for Test--test_signal Attributes for DFT
scan_shift
scan_shift {false | true}
Default: false
Read-write test_signal attribute. Specifies whether this signal will be captured as a clock for ATPG
Related Information
Set by this constraint: define_test_mode
user_defined_signal
user_defined_signal {true|false|simulated}
Default: true
Read-write test_signal attribute. Indicates whether the test signal was user-defined (through a dft constraint), determined by the DFT rule checker, or
identified by simulating a mode initialization sequence.
Although this attribute is writable, you are expected not to change this attribute value.
Related Information
Set by this constraint: define_test_mode
identify_test_mode_registers
Set by this command: check_dft_rules
Related attribute: (test clock) user_defined_signal
wir_reset_value
wir_reset_value {low|high}
Read-write test_signal attribute. Specifies the value that the test signal will be driven to when the wrapper instruction register (WIR) is reset.
This attribute only applies if the wir_signal attribute is true.
Related Information
Set by this constraint: define_test_signal
wir_signal
wir_signal {false|true}
Read-write test_signal attribute. Specifies whether the test signal is driven by a wrapper instruction register (WIR) signal.
Related Information
Set by this constraint: define_test_signal
March 2025 1496 Product Version 23.1
Genus Attribute Reference
Design for Test--violation Attributes for DFT
wir_tm_value
wir_tm_value {low|high}
Read-write test_signal attribute. Specifies the value that the test signal will be forced to when the wrapper instruction register is scan tested.
This attribute only applies if the wir_signal attribute is true.
Related Information
Set by this constraint: define_test_signal
violation Attributes for DFT
description
endpoints
file_name
fixed
id
line_number
reg_count
registers
root_node
segments
tristate_net_drivers
tristate_net_load
description
description string
Read-only violation attribute. Returns the description of the violation. Possible values are listed in the table below.
Asynchronous Signal Violations
[ASYNC-01] detected a loop while tracing async signal
[ASYNC-02] async signal driven to a constant active value, possibly due to a polarity conflict
[ASYNC-03] async signal has no driver
[ASYNC-04] internal or gated async signal
[ASYNC-05] async signal driven by a sequential element
[ASYNC-06] async signal has multiple drivers
[ASYNC-07] async signal also used as a clock signal
[ASYNC-08] misc. async signal violation
[ASYNC-09] async signal is not controllable
[ASYNC-10] async signal driven by a primary input (not defined as a test_mode signal)
Abstract Segment Test Mode Signal Violations
March 2025 1497 Product Version 23.1
Genus Attribute Reference
Design for Test--violation Attributes for DFT
[ABS-TM-01] detected a loop while tracing abstract segment test mode signal
[ABS-TM-02] abstract segment test mode signal driven to a constant active value, possibly due to a polarity conflict
[ABS-TM-03] abstract segment test mode signal has no driver
[ABS-TM-04] internal or gated abstract segment test mode signal
[ABS-TM-05] abstract segment test mode signal driven by a sequential element
[ABS-TM-06] abstract segment test mode signal has multiple drivers
[ABS-TM-07] conflict in abstract segment test mode signal driver which is driven by test signal of opposite polarity
[ABS-TM-08] misc. abstract segment test mode signal violation
[ABS-TM-09] Abstract Segment Test Mode signal is not controllable
Clock and Data Race Violations
[RACE-01] test clock either directly or indirectly drives a non-clock input pin of a sequential instance.
Clock Signal Violations
[CLOCK-01] detected a loop while tracing clock signal
[CLOCK-02] clock signal driven to a constant value
[CLOCK-03] controlled to opposite of required off-state of clock signal
[CLOCK-04] clock signal has no driver
[CLOCK-05] internal or gated clock signal
[CLOCK-06] clock signal driven by a sequential element
[CLOCK-07] clock signal has multiple drivers
[CLOCK-08] clock signal driven by a BlackBox (unresolved) element
[CLOCK-09] misc. clock signal violation
[CLOCK-10] clock signal driven by a primary input (not defined as a test clock signal)
Same Asynchronous Set and Reset Violations
[RACE-02] test signal drives both the asynchronous set and reset pins of same register.
Shift Register Violations
[SHIFTREG-01] Synchronous pins of flop are not appropriately controlled in test mode.
[SHIFTREG-02] Output of flop driven to a constant value 0, possibly due to settings of synchronous pins in test mode.
[SHIFTREG-03] Output of flop driven to a constant value 1, possibly due to settings of synchronous pins in test mode.
[SHIFTREG-04] Shift register segment not connected properly, could not trace back to a register from flop.
[SHIFTREG-05] Could not trace back to a register from flop.
Tristate Net Contention Violations
[TRISTATE_NET-01] tristate net netName connected to pin pinName potentially driven by conflicting values.
X-Source Violations
[BBOX-01] output pin of unresolved instance or timing model drives an input pin of a sequential instance.
March 2025 1498 Product Version 23.1
Genus Attribute Reference
Design for Test--violation Attributes for DFT
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
Related attributes: dft_violation
endpoints
endpoints string
Read-only violation attribute. Returns a Tcl list of test-mode pins and ports of abstraction models that are affected by the same test-mode violation.
This attribute applies only to abstract segment violations.
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
file_name
file_name string
Read-only violation attribute. Returns the name of the file in which the problem was detected. You need to set the hdl_track_filename_row_col root attribute
to true before you run the DFT rule checker, otherwise an empty string is returned.
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
Affected by this attribute: hdl_track_filename_row_col
fixed
fixed {true | false}
Read-only violation attribute. Indicates whether the violation has been fixed with the fix_dft_violations command.
This attribute value is only set to true when you run the fix_dft_violations command with the -dont_check_dft_rules option. If you omit this option, the entire
violations directory is updated and only true violations are kept.
You can also fix a violation using add_test_point or add_user_test_point commands. However, these commands have no information about the
violation ID that is being fixed and therefore they do not affect the value of the attribute.
Example
genus@root:> get_db [get_db violations top/vid_1_async] .fixed
false
March 2025 1499 Product Version 23.1
Genus Attribute Reference
Design for Test--violation Attributes for DFT
Related Information
Set by this command: check_dft_rules
Related attributes: dft_status
id
Refer to this: id
line_number
line_number integer
Read-only violation attribute. Returns the line number at which the problem was detected. You need to set the hdl_track_filename_row_col root attribute to
true before you run the DFT rule checker, otherwise the value is set to 0.
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
Affected by this attribute: hdl_track_filename_row_col
reg_count
reg_count integer
Read-only violation attribute. Returns the number of registers this violation affects. If the violation also affects abstract segments, the count also includes the
length of the abstract segments.
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
Related attributes: (actual_scan_chain) reg_count
(actual_scan_segment) reg_count
(scan_segment) reg_count
registers
registers instance_list
Read-only violation attribute. Returns a list of the instance names of the registers affected by this violation.
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
March 2025 1500 Product Version 23.1
Genus Attribute Reference
Design for Test--write_mask_bit Attributes for DFT
root_node
root_node {hpin | pin | constant | pg_pin | hport | port}
Read-only violation attribute. Returns the pin, port or bus at which the violation originates.
Related Information
Set by this command: check_dft_rules
segments
segments list_of_abstract_segments
Read-only violation attribute. Returns a list of the abstract segments affected by this violation.
Related Information
Set by this command: check_dft_rules
Affects this command: report_dft_violations
tristate_net_drivers
tristate_net_drivers {hpin | pin | constant | pg_pin | hport | port}
Read-only violation attribute. Returns the tristate net driver pins where the violation originates.
tristate_net_load
tristate_net_load {hpin | pin | constant | pg_pin | hport | port}
Read-only violation attribute. Returns the load pin for tristate net where the violation originates.
write_mask_bit Attributes for DFT
masked_bits
masked_bits string
Read-only write_mask_bit attribute. Returns the masked data bits of the memory word, which was specified using the write_mask_binding specification in the
MBIST configuration file.
Related Information
Set by this command: read_pmbist_memory_view
memory_lib_cell
memory_lib_cell string
March 2025 1501 Product Version 23.1
Genus Attribute Reference
Design for Test--write_mask_bit Attributes for DFT
Read-only write_mask_bit attribute. Returns the parent memory_lib_cell.
March 2025 1502 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)
27
Low Power Synthesis (LPS)
The chapter describes the attributes of the following object types:
1801 cpf incr_joules_instance_threshold_count_MT
instance_internal_power instance_leakage_power isolation_rules
joules_incremental_silent joules_silent leakage_power
level_shifter_rules lp_asserted_probability lp_asserted_toggle_rate
lp_clock_tree_buffers lp_clock_tree_leaf_max_fanout lp_computed_probability
lp_computed_toggle_rate lp_display_negative_internal_power lp_dynamic_analysis_scope
lp_get_state_dependent_lkg_pow lp_internal_power lp_leakage_power
lp_net_power lp_power_unit lp_probability_type
lp_pso_aware_estimation lp_pso_aware_tcf lp_system_asserted_probability
lp_system_asserted_toggle_rate lp_toggle_rate_type lp_toggle_rate_unit
lp_x_transition_probability_count lp_x_transition_toggle_count lp_z_transition_probability_count
lp_z_transition_toggle_count macro_isolation_rules macro_model
macro_models macro_power_domains nominal_conditions
opt_leakage_to_dynamic_ratio power_engine power_model
power_models power_modes power_scope
power_scopes repeater_rules state_retention_rules
See also:
power_domains
1801
Syntax
1801 {list_of_power_intent_commands}
March 2025 1503 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--cpf
Applies to:
design
power_model
power_scope
Description
Default:
Data_type: power_intent_command*, read only
Returns the list of 1801 power_intent_command objects for the design/1801 power_model/1801 scope.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
cpf
Syntax
cpf {list_of_power_intent_commands}
Applies to:
design
power_model
power_scope
Description
Default:
Data_type: power_intent_command*, read only
Returns the list of cpf power_intent_command objects for the design/cpf power_model/cpf scope.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
incr_joules_instance_threshold_count_MT
March 2025 1504 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--instance_internal_power
Syntax
incr_joules_instance_threshold_count_MT <integer>
Applies to:
root
Description
Default: 1000
Data_type: integer, read/write
Specifies the minimum instance count for incremental power to be multi-threaded.
instance_internal_power
Syntax
instance_internal_power <float>
Applies to:
hinst
inst
Description
Default:
Data_type: double, read/write
Specifies the internal power of this instance. The unit of the power value is determined by the value of the lp_power_unit attribute.
Use this attribute to specify the internal power of a blackbox, abstract model, or timing model.
By default, an instance inherits the internal power of the corresponding lib_cell.
March 2025 1505 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--instance_leakage_power
Related Information
Reporting Power on Specific Components for Specific Objects in Genus Low Power Guide.
Related commands: report_gates -power
report_power
Affected by this attribute: lp_power_unit
Related attributes: internal_power
leakage_power
instance_leakage_power
instance_leakage_power
Syntax
instance_leakage_power <float>
Applies to:
hinst
inst
Description
Default:
Data_type: double, read/write
Specifies the leakage power of this instance. The unit of the power value is determined by the value of the lp_power_unit attribute.
Use this attribute to specify the leakage power of a sequential cell, combinational cell, blackbox, abstract model, or timing model.
By default, an instance inherits the leakage power of the corresponding lib_cell.
Related Information
Related commands: report_gates -power
report_power
Affected by this attribute: lp_power_unit
Related attributes: internal_power
leakage_power
instance_internal_power
March 2025 1506 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--isolation_rules
isolation_rules
Syntax
isolation_rules
Applies to:
design
power_scope
Description
Default:
Data_type: isolation_rule*, read only
Returns the list of isolation_rule objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
joules_incremental_silent
Syntax
joules_incremental_silent {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Specifies whether or not to silence the incremental joules info/warning messages.
joules_silent
March 2025 1507 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--leakage_power
Syntax
joules_silent {true | false}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Specifies whether or not to silence the joules info/warning messages.
leakage_power
Syntax
leakage_power {no_value | <float>}
Applies to:
Object Default Data_type
design 0.000000 double, read only
hinst 0.000000 double, read only
inst 0.000000 double, read only
lib_cell no_value double, read/write
March 2025 1508 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--level_shifter_rules
Description
Object
design Computes the total leakage power of all instances in the design. The unit of the power value is determined by the
value of the lp_power_unit attribute.
hinst Computes the leakage power of the instance. The unit of the power value is determined by the value of the
lp_power_unit attribute.
You can only get this attribute value on a unique hierarchical instance.
inst Computes the leakage power of the instance. The unit of the power value is determined by the value of the
lp_power_unit attribute.
You can only get this attribute value on a unique hierarchical or leaf instance.
lib_cell Specifies the leakage power of the lib_cell. The unit of the power value is determined by the value of the
leakage_power_scale_in_nw attribute.
Example
If the value of leakage_power_scale_in_nW is 0.01 and the value of cell_leakage_power is 1000, the leakage power
of this cell is 10 nW.
Related Information
Related commands: report_gates -power
report_power
syn_generic
syn_map
syn_opt
Affected by this attribute: lp_power_unit
leakage_power_scale_in_nW
level_shifter_rules
Syntax
level_shifter_rules <list_of_level_shifter_rules>
March 2025 1509 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_asserted_probability
Applies to:
design
power_scope
Description
Default:
Data_type: level_shifter_rule*, read only
Returns the list of level_shifter_rules in the design or the list of level_shifter_rule objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
lp_asserted_probability
Syntax
lp_asserted_probability <float>
Applies to:
hnet
hpin
hport
pin
port
Description
Default:
Data_type: double, read/write
Specifies the probability value of this net/hpin/hport/pin/port being high for power estimation. You can specify any value between 0
and 1.
Both lp_asserted_probability and lp_asserted_toggle_rate need to be set on a pin for it to be considered for activity
propagation. If only one attribute is set on the pin, then that value will not be considered.
March 2025 1510 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_asserted_toggle_rate
Related Information
Set by one of these commands: read_saif
read_tcf
Affects these commands: report_gates -power
report_power
lp_asserted_toggle_rate
Syntax
lp_asserted_toggle_rate <float>
Applies to:
hnet
hpin
hport
pin
port
Description
Default:
Data_type: double, read/write
Specifies the toggle rate (toggle count per toggle rate unit) of this net/hpin/hport/pin/port for the purpose of power estimation. You
can specify any positive value, including zero.
Related Information
Set by one of these commands: read_saif
read_tcf
Affects these commands: report_gates -power
report_power
Affected by this attribute: lp_toggle_rate_unit
March 2025 1511 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_clock_tree_buffers
lp_clock_tree_buffers
Syntax
lp_clock_tree_buffers <lib_cell_list>
Applies to:
design
Description
Default:
Data_type: lib_cell*, read/write
Specifies a list of valid lib_cell buffers and inverters that can be used for clock tree synthesis. If the design has multiple library
domains, specify the buffers and inverters that belong to the default library domain.
This attribute is only available with the Genus_Low_Power_Opt License Key.
Related Information
Affects this command: report_power
Related attribute: lp_clock_tree_leaf_max_fanout
lp_clock_tree_leaf_max_fanout
Syntax
lp_clock_tree_leaf_max_fanout <integer>
Applies to:
design
Description
Default: 0
Data_type: int, read/write
Specifies the maximum number of flip-flops that can be driven by a leaf clock buffer. You must specify a positive integer.
March 2025 1512 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_computed_probability
This attribute is only available with the Genus_Low_Power_Opt License Key.
Related Information
Affects this command: report_power
Related attribute: lp_clock_tree_buffers
lp_computed_probability
Syntax
lp_computed_probability <float>
Applies to:
constant
hnet
hpin
hport
pin
port
Description
Default:
Data_type: double, read only
Retrieves the probability of the constant/net/pin/hport/port. The probability can be asserted or computed.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
March 2025 1513 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_computed_toggle_rate
Related Information
Affected by these commands: read_saif
read_tcf
Related commands: report_gates -power
report_power
Affected by these attributes: lp_asserted_probability
lp_computed_toggle_rate
Syntax
lp_computed_toggle_rate <float>
Applies to:
constant
hnet
hpin
hport
pin
port
Description
Default:
Data_type: double, read only
Retrieves the toggle rate (toggle count per toggle rate unit) of this constant/net/pin/hport/port for power estimation. The toggle rate
can be asserted or computed.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
March 2025 1514 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_display_negative_internal_power
Related Information
Affected by these commands: read_saif
read_tcf
Related commands: report_gates -power
report_power
Affected by these attributes: lp_asserted_toggle_rate
lp_display_negative_internal_power
lp_display_negative_internal_power {true | false}
Description
Controls how negative internal power results are reported. By default, negative internal power results are reported. Set this attribute
to false, to report negative internal power as zero.
Default: true
Data_type: bool, read/write
Applies to:
root
Related Information
Power Analysis in Genus Low Power Guide.
Affects these commands: report_power
report_gates -power
report_instance -power
report_qor
Affects these attributes: lp_internal_power
lp_dynamic_analysis_scope
Syntax
lp_dynamic_analysis_scope {false | true}
March 2025 1515 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_get_state_dependent_lkg_pow
Applies to:
hinst
inst
Description
Default: false
Data_type: bool, read/write
Specifies whether the instance should be added to the scope that impacts activity profiling.
Related Information
Sources of Switching Activity Information in Genus Low Power Guide.
Affects this command: read_vcd
lp_get_state_dependent_lkg_pow
Syntax
lp_get_state_dependent_lkg_pow {true | false}
Applies to:
root
Description
Default: true
Data_type: bool, read/write
Controls whether the leakage power calculation is state-dependent. Set this attribute to false to make the leakage power
calculation state-independent.
This attribute is supported only in power_engine legacy.
lp_internal_power
Syntax
lp_internal_power <float>
March 2025 1516 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_leakage_power
lp_internal_power <float>
Applies to:
design
hinst
inst
Description
Default: 0.000000
Data_type: double, read only
design Computes the total internal cell power of all instances in the design.
hinst Computes the total internal cell power of the instance.
You can only get this attribute value on a unique hierarchical instance.
inst Computes the total internal cell power of the instance.
You can only get this attribute value on a unique hierarchical or leaf instance.
The unit of the power value is determined by the value of the lp_power_unit attribute.
Related Information
Reporting Power on Specific Components for Specific Objects in Genus Low Power Guide.
Related commands: report_gates -power
report_power
Affected by this attribute: lp_power_unit
lp_leakage_power
Syntax
lp_leakage_power <float>
March 2025 1517 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_net_power
Applies to:
design
hinst
inst
Description
Default: 0.000000 (for design, hinst, and inst)
Data_type: double, read only
design Computes the total leakage power of all instances in the design.
hinst Computes the leakage power of the instance.
You can only get this attribute value on a unique hierarchical instance.
inst Computes the leakage power of the instance.
You can only get this attribute value on a unique hierarchical or leaf instance.
The unit of the power value is determined by the value of the lp_power_unit attribute.
Related Information
Reporting Power on Specific Components for Specific Objects in Genus Low Power Guide.
Reporting Power in Genus Low Power Guide.
Related commands: report_gates -power
report_power
Affected by this attribute: lp_power_unit
lp_net_power
Syntax
lp_net_power <float>
March 2025 1518 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_net_power
Applies to:
design hinst
hnet hpin
hport inst
pin port
Description
Default: 0.000000
Data_type: double, read only
design Computes the total switching power of all nets in the design.
hinst
hnet Computes the switching power dissipated on the net.
hpin Computes the switching power dissipated on the net connected to this hpin.
hport Computes the switching power dissipated on the net connected to this hport.
inst Computes the sum of the net power of all output nets for a flat instance and the total output net power within a
hierarchical instance excluding the nets whose drivers are not part of the hierarchical instance.
You can only get this attribute value on a unique hierarchical or leaf instance.
pin Computes the switching power dissipated on the net connected to this pin.
port Computes the switching power dissipated on the net connected to this port.
The unit of the power value is determined by the value of the lp_power_unit attribute.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
Related Information
Reporting Power on Specific Components for Specific Objects in Genus Low Power Guide.
Related commands: report_gates -power
report_power
Affected by this attribute: lp_power_unit
March 2025 1519 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_power_unit
lp_power_unit
lp_power_unit {nW | mW | pW | uW | W}}
Description
Specifies the power unit to be used when analyzing net power, cell internal power, or cell leakage power. The power units are case
sensitive.
To get more precise results, use a smaller unit.
Default: nW
Data_type: string, read/write
Applies to:
root
Related Information
Power Analysis in Genus Low Power Guide.
Affects this command: report_gates -power
report_power
Affects these attributes: lp_internal_power
lp_leakage_power
lp_net_power
lp_probability_type
Syntax
lp_probability_type {asserted | clock | computed | constant | default | invalid}
March 2025 1520 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_pso_aware_estimation
Applies to:
constant
hnet
hpin
hport
pin
port
Description
Default: invalid
Data_type: enum, read only
Indicates the source of the probability value. This attribute can have the following values:
asserted Indicates that the constant/net/pin/hport/port value is user-specified. You either specified the value through the
lp_asserted_probability attribute or in a switching activity file (TCF or SAIF file).
clock Indicates that the constant/net/pin/hport/port is connected to a clock net and that the value is derived from the clock
waveform.
computed Indicates that the constant/net/pin/hport/port value is computed by propagating the internal switching activities.
constant Indicates that the constant/net/pin/hport/port is driven by a constant value. In this case, the value of the
lp_asserted_probability attribute is set to 1 if it is driven by a logic 1, or 0 if it is driven by a logic 0.
default Indicates that the constant/net/pin/hport/port value is not user-specified, but determined by the value of the
lp_default_probability attribute.
invalid
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
Related Information
Affected by these commands: read_saif
read_tcf
Affected by these attributes: lp_asserted_probability
lp_pso_aware_estimation
lp_pso_aware_estimation {true | false}
March 2025 1521 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_pso_aware_tcf
Description
Specifies if the power estimation must be power domain-aware.
true Estimates the average power of the design based on the probability of the power domains being powered on. To make
the power estimation power domain-aware, you must assert the probability of the enable signals that power down the
power domains. The RC-LP engine will consider a power domain to be always on if the probability of the shutoff enable
signal is not user-asserted.
false Estimates the power assuming that all power domains are always powered on.
Default: true
Data_type: bool, read/write
Applies to:
root
Related Information
Affects these commands: report_gates -power
report_power
Related attribute: lp_pso_aware_tcf
lp_pso_aware_tcf
Syntax
lp_pso_aware_tcf {false | true}
Applies to:
design
Description
Default: false
Data_type: bool, read/write
Specifies whether the switching activities were generated by simulating the design while taking into account when the power
domains are shut off.
March 2025 1522 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_system_asserted_probability
Related Information
Related commands: report_gates -power
report_power
Related attribute: lp_pso_aware_estimation
lp_system_asserted_probability
Syntax
lp_system_asserted_probability <float>
Applies to:
hnet
hpin
hport
pin
port
Description
Default:
Data_type: double, read/write
Specifies the System/Internal asserted probability.
lp_system_asserted_toggle_rate
Syntax
lp_system_asserted_probability <float>
March 2025 1523 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_toggle_rate_type
Applies to:
hpin
hport
pin
port
Description
Default:
Data_type: double, read/write
Specifies the System/Internal asserted toggle rate.
lp_toggle_rate_type
Syntax
lp_toggle_rate_type {asserted | clock | computed | constant | default | invalid}
Applies to:
constant
hnet
hpin
hport
pin
port
Description
Default: invalid
Data_type: enum, read only
Indicates the source of the toggle rate value. This attribute can have the following values:
asserted Indicates that the constant/net/pin/hport/port value is user-specified. You either specified the value through the
lp_asserted_toggle_rate attribute or in a switching activity file (TCF or SAIF file).
clock Indicates that the constant/net/pin/hport/port is a connected to a clock net and that the value is derived from the clock
waveform.
computed Indicates that the constant/net/pin/hport/port value is computed by propagating the internal switching activities.
March 2025 1524 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_toggle_rate_unit
constant Indicates that the constant/net/pin/hport/port is driven by a constant value. In this case, the value of the
lp_asserted_toggle_rate attribute is set to 0.
default Indicates that the constant/net/pin/hport/port value is not user-specified, but determined by the value of the
lp_default_toggle_rate attribute.
invalid
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
Example
The following example checks the source of the toggle rate value of a net driven by a clock:
get_att lp_toggle_rate_type */nets/clock
clock
Related Information
Reporting Power on Specific Components for Specific Objects in Genus Low Power Guide for Legacy UI.
Affected by these commands: read_saif
read_tcf
Affected by these attributes: lp_asserted_toggle_rate
lp_toggle_rate_unit
lp_toggle_rate_unit {/ns | /us | /ms | /s}
Description
Specifies the time unit used for the toggle rate in the software.
Default: /ns
Data_type: string, read/write
Applies to:
root
March 2025 1525 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_x_transition_probability_count
Related Information
Affects this command: report_power
Affects these attributes: lp_asserted_toggle_rate
lp_computed_toggle_rate
lp_x_transition_probability_count
Syntax
lp_x_transition_probability_count <float>
Applies to:
root
Description
Default: 0.500
Data_type: double, read/write
Specifies the weight of the probability count for each transition from X. You can specify any value between 0 and 1.
To ignore the X transitions, you can set this attribute or the lp_x_transition_toggle_count attribute to -1.
Related Information
Affects these commands: read_vcd
report_power
Affects these attributes: lp_asserted_probability
lp_computed_probability
lp_x_transition_toggle_count
Syntax
lp_x_transition_toggle_count <float>
March 2025 1526 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_z_transition_probability_count
Applies to:
root
Description
Default: 0.500
Data_type: double, read/write
Specifies the weight of the toggle count for each transition from and to X. You can specify any value between 0 and 1.
To ignore the X transitions, you can set this attribute or the lp_x_transition_probability_count attribute to -1.
Related Information
Affects these commands: read_vcd
report_power
Affects these attributes: lp_asserted_toggle_rate
lp_computed_toggle_rate
lp_z_transition_probability_count
Syntax
lp_z_transition_probability_count <float>
Applies to:
root
Description
Default: 0.250
Data_type: double, read/write
Specifies the the weight of the probability count for each transition from Z. You can specify any value between 0 and 1.
To ignore the Z transitions, you can set this attribute or the lp_z_transition_toggle_count attribute to -1.
March 2025 1527 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--lp_z_transition_toggle_count
Related Information
Affects these commands: read_vcd
report_power
Affects these attributes: lp_asserted_probability
lp_computed_probability
lp_z_transition_toggle_count
Syntax
lp_z_transition_toggle_count <float>
Applies to:
root
Description
Default: 0.250
Data_type: double, read/write
Specifies the the weight of the toggle count for each transition from and to Z. You can specify any value between 0 and 1.
To ignore the Z transitions, you can set this attribute or the lp_z_transition_probability_count attribute to -1.
Related Information
Affects these commands: read_vcd
report_power
Affects these attributes: lp_asserted_toggle_rate
lp_computed_toggle_rate
macro_isolation_rules
Syntax
macro_isolation_rules <list_of_isolation_rules>
March 2025 1528 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--macro_model
Applies to:
macro_model
Description
Default:
Data_type: macro_isolation_rule*, read only
Returns the list of isolation rules for this macro model.
macro_model
macro_model <macro_model>
Applies to:
macro_isolation_rule
macro_power_domain
Description
Default:
Data_type: macro_model, read only
Returns the macro_model to which this macro_isolation_rule / macro_power_domain belongs.
macro_models
Syntax
macro_models <list_of_macro_models>
Applies to:
design
Description
Default:
Data_type: macro_model *, read only
Returns the list of all 'macro_model' objects in the design.
March 2025 1529 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--macro_power_domains
macro_power_domains
Syntax
macro_power_domains <list_of_power_domains>
Applies to:
macro_model
Description
Default:
Data_type: macro_power_domain*, read only
Returns the list of power domains for this macro model.
nominal_conditions
Syntax
nominal_conditions <list_of_nominal_conditions>
Applies to:
design
power_scope
Description
Default:
Data_type: nominal_condition*, read only
Returns the list of 'nominal_condition' objects.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
opt_leakage_to_dynamic_ratio
March 2025 1530 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--power_engine
Syntax
opt_leakage_to_dynamic_ratio <float>
Applies to:
root
Description
Default: 1.0
Data_type: double, read/write
Controls the weight factors to be used when optimizing leakage power and dynamic power simultaneously during mapping and
incremental optimization. Specify a value between 0 and 1. Total power is computed as follows, assuming the attribute is set to 'w':
Total power = w x leakage_power + (1-w) x dynamic_power
The weight factor will only be taken into account if design_power_effort is set to 'low' or 'high'. It is recommended to specify
values with a single decimal digit. Also, using the default 1.0 value means that only leakage power will be optimized.
Specifying 0.0 value means that only dynamic power will be optimized. Value 0.5 is recommended as a default starting value
for total power optimization.
Related Information
Affects these commands: syn_map
syn_opt
Related commands: report_power
report_gates -power
Related attribute: design_power_effort
power_engine
power_engine {legacy | joules}
Description
Specifies the power engine to use - the Genus power engine or the Joules power engine.
Default: joules
Data_type: enum, read/write
March 2025 1531 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--power_model
Applies to:
root
Related Information
Affects this command: report_power
power_model
Syntax
power_model <power_model>
Applies to:
power_intent_command
Description
Default:
Data_type: power_model, read only
Returns the power_model that this command belongs to.
power_models
Syntax
power_models <list_of_power_models>
Applies to:
design
power_scope
Description
Default:
Data_type: power_model *, read only
Returns the list of 'power_model' objects in the design.
March 2025 1532 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--power_modes
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
power_modes
Syntax
power_modes <list_of_power_modes>
Applies to:
analysis_view
design
power_scope
Description
Default:
Data_type: power_mode* (design and power_scope), string (analysis_view), read only
Returns the list of 'power_mode' objects in the analysis view or in the design.
power_scope
Syntax
power_scope <power_scope>
March 2025 1533 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--power_scopes
Applies to:
isolation_rule
level_shifter_rule
nominal_condition
power_domain
power_intent_command
power_mode
power_model
power_scope
repeater_rule
state_retention_rule
Description
Default:
Data_type: power_scope, read only
Returns the power_scope that this object belongs to.
power_scopes
Syntax
power_scopes <list_of_power_scopes>
Applies to:
design
power_scope
Description
Default:
Data_type: power_scope*, read only
Returns the list of power_scope objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
March 2025 1534 Product Version 23.1
Genus Attribute Reference
Low Power Synthesis (LPS)--repeater_rules
repeater_rules
Syntax
repeater_rules <list_of_repeater_rules>
Applies to:
design
power_scope
Description
Default:
Data_type: repeater_rule*, read only
Returns the list of repeater_rule objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
state_retention_rules
Syntax
state_retention_rules <list_of_state_retention_rules>
Applies to:
design
power_scope
Description
Default:
Data_type: state_retention_rule*, read only
Returns the list of all state_retention_rule objects in the design.
This is a computed attribute. Computed attributes are potentially very time consuming to process and not listed by the ls/vls
command by default.
March 2025 1535 Product Version 23.1
Genus Attribute Reference
Advanced Low Power
28
Advanced Low Power
The chapter describes the attributes of the following object types:
hnet Attributes for Adv hpin Attributes for Adv LPS hport Attributes for Adv LPS
LPS
isolation_rule Attributes level_shifter_rule Attributes nominal_condition
for Adv LPS for Adv LPS Attributes for Adv LPS
pin Attributes for Adv port Attributes for Adv LPS power_domain Attributes for
LPS Adv LPS
power_mode Attributes state_retention_rule
for Adv LPS Attributes for Adv LPS
hnet Attributes for Adv LPS
power_duty_cycle
power_switching
power_toggle_rate
power_toggle_rate_source
power_duty_cycle
power_duty_cycle double
March 2025 1536 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--hpin Attributes for Adv LPS
Computed hnet attribute. Returns the static probability of the signal to stay high during one clock
cycle. It is a value between 0.0 and 1.0. no_value is returned if it cannot be computed.
power_switching
power_switching double
Default: 0.000000
Read-only hnet attribute. Returns the switching power of the net computed by report_power. A
value of no_value is treated as 0.
power_toggle_rate
power_toggle_rate double
Computed hnet attribute. Returns the number of toggles read from VCD, TCF, SAIF or from
propagation in lp_toggle_rate_unit duration (default is per ns).
power_toggle_rate_source
power_toggle_rate_source {invalid | default | computed | clock | constant | asserted}
Default: invalid
Computed hnet attribute. Returns the source of power_toggle_rate value.
hpin Attributes for Adv LPS
isolation_rule
isolation_rule rules
Read-only hpin attribute. Returns the isolation rules that apply to this hpin.
March 2025 1537 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--hport Attributes for Adv LPS
Related Information
Affected by this command: read_power_intent
Related attributes: (hport) isolation_rule
(pin) isolation_rule
(port) isolation_rule
level_shifter_rule
level_shifter_rule rules
Read-only hpin attribute. Returns the level shifter rules that apply to this hpin.
Related Information
Affected by this command: read_power_intent
Related attributes: (hport) level_shifter_rule
(pin) level_shifter_rule
(port) level_shifter_rule
hport Attributes for Adv LPS
isolation_rule
isolation_rule rules
Read-only hport attribute. Returns the isolation rules that apply to this hport.
March 2025 1538 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--isolation_rule Attributes for Adv LPS
Related Information
Affected by this command: read_power_intent
Related attributes: (hpin) isolation_rule
(pin) isolation_rule
(port) isolation_rule
level_shifter_rule
level_shifter_rule rules
Read-only hport attribute. Returns the level shifter rules that apply to this hport.
Related Information
Affected by this command: read_power_intent
Related attributes: (hpin) level_shifter_rule
(pin) level_shifter_rule
(port) level_shifter_rule
isolation_rule Attributes for Adv LPS
cells
cpf_pins
enable_driver
enable_polarity
exclude_pins
from_power_domain
March 2025 1539 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--isolation_rule Attributes for Adv LPS
off_domain
output_value
pins
prefix
to_power_domain
within_hierarchy
cells
cells lib_cell_list
Read-only isolation_rule attribute. Returns the list of cells that can be used to insert isolation
logic according to this isolation rule.
Related Information
Affected by this command: read_power_intent
Related attributes: (level_shifter_rule) cells
(state_retention_rule) cells
cpf_pins
cpf_pins {hpin* | pin* | constant* | pg_pin* | hport* | port*}
Read-write isolation_rule attribute. Returns the list of pins that was specified with the -pins
option of the create_isolation_rule CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_rule) cpf_pins
March 2025 1540 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--isolation_rule Attributes for Adv LPS
enable_driver
enable_driver {pin | port}
Read-write isolation_rule attribute. Specifies the driver of the enable signal which controls when
the isolation cells are in isolation mode.
Related Information
Affected by this command: read_power_intent
enable_polarity
enable_polarity {active_high | active_low}
Default: active_high
Read-write isolation_rule attribute. Specifies the polarity of the enable signal which controls
when the isolation cells are in isolation mode.
Related Information
Affected by this command: read_power_intent
exclude_pins
exclude_pins pin_list
Read-only isolation_rule attribute. Returns the list of pins that was specified with the -exclude
option of the create_isolation_rule CPF command.
March 2025 1541 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--isolation_rule Attributes for Adv LPS
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_rule) exclude_pins
from_power_domain
from_power_domain domain_list
Read-write isolation_rule attribute. Returns the list of power domains specified with the -from
option of the create_isolation_rule CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_rule) from_power_domain
off_domain
off_domain {from | to}
Default: from
Read-write isolation_rule attribute. Specifies which power domain is powered down.
Related Information
Affected by this command: read_power_intent
output_value
output_value {low | high | hold | complex | mux | tristate | any}
March 2025 1542 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--isolation_rule Attributes for Adv LPS
Read-only isolation_rule attribute. Specifies the required output state of the isolation cells.
Related Information
Affected by this command: read_power_intent
pins
pins {hpin* | pin* | constant* | pg_pin* | hport* | port*}
Read-only isolation_rule attribute. Returns the list of pins to which this isolation rule applies.
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_rule) pins
prefix
prefix string
Read-only isolation_rule attribute. Specifies the prefix used to name the isolation modules and
hierarchical instances inserted according to the isolation rule.
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_rule) prefix
March 2025 1543 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--level_shifter_rule Attributes for Adv LPS
to_power_domain
to_power_domain domain_list
Read-write isolation_rule attribute. Returns the list of power domains specified with the -to
option of the create_isolation_rule CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_rule) to_power_domain
within_hierarchy
within_hierarchy {design | instance}
Read-only isolation_rule attribute. Returns the design or instance in which the isolation logic
(with or without wrapper) must be inserted.
Related Information
Affected by this command: read_power_intent
Related attribute: (level_shifter_rule) within_hierarchy
level_shifter_rule Attributes for Adv LPS
cells
cpf_pins
exclude_pins
from_power_domain
March 2025 1544 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--level_shifter_rule Attributes for Adv LPS
pins
prefix
to_power_domain
within_hierarchy
cells
cells lib_cell_list
Read-only level_shifter_rule attribute. Returns the list of cells that can be used to insert level
shifters according to this level-shifter rule.
Related Information
Affected by this command: read_power_intent
Related attributes: (isolation_rule) cells
(state_retention_rule) cells
cpf_pins
cpf_pins {hpin* | pin* | constant* | pg_pin* | hport* | port*}
Read-write level_shifter_rule attribute. Returns the list of pins that was specified with the -pins
option of the create_level_shifter_rule CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (isolation_rule) cpf_pins
March 2025 1545 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--level_shifter_rule Attributes for Adv LPS
exclude_pins
exclude_pins {hpin* | pin* | constant* | pg_pin* | hport* | port*}
Read-only level_shifter_rule attribute. Returns the list of pins that was specified with the -
exclude option of the create_level_shifter_rule CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (isolation_rule) exclude_pins
from_power_domain
from_power_domain domain_list
Read-write level_shifter_rule attribute. Returns the list of power domains specified with the -
from option of the create_level_shifter_rule CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (isolation_rule) from_power_domain
pins
pins {hpin* | pin* | constant* | pg_pin* | hport* | port*}
Read-only level_shifter_rule attribute. Returns the list of pins to which the rule defined with the
create_level_shifter_rule CPF command is applicable.
March 2025 1546 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--level_shifter_rule Attributes for Adv LPS
Related Information
Affected by this command: read_power_intent
Related attribute: (isolation_rule) pins
prefix
prefix string
Read-only level_shifter_rule attribute. Returns the prefix that was specified with the -prefix
option of the update_level_shifter_rules CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (isolation_rule) prefix
to_power_domain
to_power_domain domain_list
Read-write level_shifter_rule attribute. Returns the list of power domains specified with the -to
option of the create_level_shifter_rule CPF command.
Related Information
Affected by this command: read_power_intent
Related attribute: (isolation_rule) to_power_domain
March 2025 1547 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--nominal_condition Attributes for Adv LPS
within_hierarchy
within_hierarchy {design | instance}
Read-only level_shifter_rule attribute. Returns the design or instance in which the level shifter
(with or without wrapper) must be inserted.
Related Information
Affected by this command: read_power_intent
Related attribute: (isolation_rule) within_hierarchy
nominal_condition Attributes for Adv LPS
ground_voltage
library_set
ground_voltage
ground_voltage voltage_list
Read-write nominal_condition attribute. Specifies the ground supply voltage(s) for this nominal
condition. This value corresponds to the value specified for the -ground_voltage option of the
create_nominal_condition CPF command specified for this nominal condition. The list can contain
up to three voltages: minimum, nominal, and maximum voltages. The list must contain increasing
values.
Related Information
create_nominal_condition in the Common Power Format Language Reference.
Affected by this command: read_power_intent
March 2025 1548 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--pin Attributes for Adv LPS
library_set
library_set library_domain
Read-write nominal_condition attribute. Returns the library set associated with the specified
condition. The value corresponds to the value specified for the -library_set option of the
update_nominal_condition CPF command specified for this nominal condition.
In Genus, the library sets correspond to library domains.
Related Information
Affected by this command: read_power_intent
pin Attributes for Adv LPS
isolation_rule
level_shifter_rule
related_ground_pin
related_power_pin
isolation_rule
isolation_rule rules
Read-only pin attribute. Returns the isolation rules that apply to this pin.
March 2025 1549 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--pin Attributes for Adv LPS
Related Information
Affected by this command: read_power_intent
Related attributes: (hpin) isolation_rule
(hport) isolation_rule
(port) isolation_rule
level_shifter_rule
level_shifter_rule rules
Read-only pin attribute. Returns the level shifter rules that apply to this pin.
Related Information
Affected by this command: read_power_intent
Related attributes: (hpin) level_shifter_rule
(hport) level_shifter_rule
(port) level_shifter_rule
related_ground_pin
related_ground_pin (constant | hpin | pin | pg_pin | hport | port}
Read-only pin attribute. Returns pin corresponding to related_ground_pin of pin's lib_pin.
related_power_pin
related_power_pin (constant | hpin | pin | pg_pin | hport | port}
Read-only pin attribute. Returns pin corresponding to related_power_pin of pin's lib_pin.
March 2025 1550 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--port Attributes for Adv LPS
port Attributes for Adv LPS
isolation_rule
isolation_rule rules
Read-only port attribute. Returns the isolation rules that apply to this port.
Related Information
Affected by this command: read_power_intent
Related attributes: (hpin) isolation_rule
(hport) isolation_rule
(pin) isolation_rule
level_shifter_rule
level_shifter_rule rules
Read-only port attribute. Returns the level shifter rules that apply to this port.
Related Information
Affected by this command: read_power_intent
Related attributes: (hpin) level_shifter_rule
(hport) level_shifter_rule
(pin) level_shifter_rule
March 2025 1551 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--power_domain Attributes for Adv LPS
power_domain Attributes for Adv LPS
available_supply_nets
available_supply_sets
base_domains
core_to_bottom
core_to_left
core_to_right
core_to_top
default_tech_site
dft_iso_rule
is_default
is_virtual
primary_ground_is_always_on
primary_ground_net
primary_power_is_always_on
primary_power_net
shutoff_condition
shutoff_condition_inputs
available_supply_nets
available_supply_nets net_list
Read-only power_domain attribute. Returns the list of supply nets that are directly or indirectly
available in this power domain.
A supply which is connected to any supply which is explicitly or locally available in this domain is
also considered to be available in this domain.
March 2025 1552 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--power_domain Attributes for Adv LPS
available_supply_sets
available_supply_sets net_list
Read-only power_domain attribute. Returns the list of supply sets that are explicitly or locally
available in this power domain.
base_domains
base_domains domain_list
Read-only power_domain attribute. Returns the list of base domains associated with this power
domain. These power (base) domains supply external power to the primary domain through some
power switch network.
Related Information
Set by this command: read_power_intent
core_to_bottom
core_to_bottom <coordinate>
Read-write power_domain attribute. Specify the distance between the power domain bottom edge
and its core box.
core_to_left
core_to_left <coordinate>
Read-write power_domain attribute. Specify the distance between the power domain left edge and
its core box.
March 2025 1553 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--power_domain Attributes for Adv LPS
core_to_right
core_to_right <coordinate>
Read-write power_domain attribute. Specify the distance between the power domain right edge and
its core box.
core_to_top
core_to_top <coordinate>
Read-write power_domain attribute. Specify the distance between the power domain top edge and
its core box.
default_tech_site
default_tech_site <site>
Read-write power_domain attribute. Specify the default tech site for power_domain.
dft_iso_rule
dft_iso_rule isolation_rule
Read-write power_domain attribute. Specifies the isolation rule to be associated with any pins or
ports created by DFT in this power domain.
is_default
is_default {false | true}
Default: false
Read-only power_domain attribute. Indicates whether the power domain is the default power
domain. By default, the first created power domain becomes the default power domain. Set this
attribute to true for the desired domain.
March 2025 1554 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--power_domain Attributes for Adv LPS
Only one power domain can be the default domain.
Related Information
Affected by this command: read_power_intent
Related attributes: default
library_domain
is_virtual
is_virtual {false | true}
Read-only power_domain attribute. Indicates whether the power domain is a virtual power domain
without any instances.
Related Information
Affected by this command: read_power_intent
primary_ground_is_always_on
primary_ground_is_always_on {true | false}
Default: true
Read-only power_domain attribute. Specifies whether the primary ground of the power domain is
always on.
primary_ground_net
primary_ground_net string
Read-only power_domain attribute. Returns the name of the primary ground net of this power
March 2025 1555 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--power_mode Attributes for Adv LPS
domain.
primary_power_is_always_on
primary_power_is_always_on {true | false}
Default: true
Read-only power_domain attribute. Specifies whether the primary power of the power domain is
always on.
primary_power_net
primary_power_net string
Read-only power_domain attribute. Returns the name of the primary power net of this power domain.
shutoff_condition
shutoff_condition string
Read-only power_domain attribute. Returns the condition when a power domain is shut off.
shutoff_condition_inputs
shutoff_condition_inputs {hpin | pin | constant | pgpin | hport | port}...
Read-only power_domain attribute. Returns the pins and ports used in the condition when a power
domain is shut off.
power_mode Attributes for Adv LPS
constraint_mode
domain_conditions
March 2025 1556 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--state_retention_rule Attributes for Adv LPS
constraint_mode
constraint_mode mode
Read-write power_mode attribute. Specifies the timing constraint mode for this power mode.
domain_conditions
domain_conditions domain_conditions
Read-only power_mode attribute. Specifies the domain conditions of the power mode. The value
contains a Tcl list for each power domain in the power mode. Each list contains the path to the
power domain name and to the nominal condition for the power domain in this power mode. The
information corresponds to the value for the -domain_conditions option of the create_power_mode
command for this power mode.
state_retention_rule Attributes for Adv LPS
cell_type
cells
restore
restore_phase
save
save_phase
cell_type
cell_type string
Read-write state_retention_rule attribute. Specifies the type of library cells that can be used to
map the sequential cells of this rule.
March 2025 1557 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--state_retention_rule Attributes for Adv LPS
The specified cell type must correspond to a cell type specified in a
define_state_retention_cell command in the CPF file.
Related Information
Affected by this command: read_power_intent
cells
cells lib_cell_list
Read-write state_retention_rule attribute. Specifies a list of library cells that can be used to map
the sequential cells of this rule.
Related Information
Affected by this command: read_power_intent
Related attributes: (isolation_rule) cells
(level_shifter_rule) cells
restore
restore {pin | port | bus}
Read-write state_retention_rule attribute. Specifies the restore signal for the state retention
registers of this rule.
Related Information
Affected by this command: read_power_intent
March 2025 1558 Product Version 23.1
Genus Attribute Reference
Advanced Low Power--state_retention_rule Attributes for Adv LPS
restore_phase
restore_phase string
Read-only state_retention_rule attribute. Returns the phase of the restore signal for the state
retention registers of this rule.
Related Information
Affected by this command: read_power_intent
save
save {pin | port | bus}
Read-write state_retention_rule attribute. Specifies the save signal for the state retention
registers of this rule.
Related Information
Affected by this command: read_power_intent
save_phase
save_phase string
Read-only state_retention_rule attribute. Returns the phase of the save signal for the state
retention registers of this rule.
Related Information
Affected by this command: read_power_intent
March 2025 1559 Product Version 23.1
Genus Attribute Reference
Joules
29
Joules
The chapter describes the attributes in the category 'joules':
cglar_da_threshold cglar_max_distance
cglar_min_slack_threshold cglar_ps_threshold
enable_xor_gating_during_map xedebug_executable
cglar_da_threshold
Syntax
cglar_da_threshold { }
Applies to:
root
Description
Default: 0.10 = 10% of flop clock
Data_type: double, read/write
Specifies the data-clock activity ratio threshold to identify low activity flops for the 'compute_cglar'
command. Values are between 0 and 1.
March 2025 1560 Product Version 23.1
Genus Attribute Reference
Joules--cglar_max_distance
Related Information
Related commands: syn_map
apply_cglar
cglar_max_distance
Syntax
cglar_max_distance integer
Applies to:
root
Description
Default: -1
Data_type: integer, read/write
Sets CGLAR's max distance in Joules. Banks low activity flops based on proximity, with the given
max distance between the flops for the 'compute_cglar' command. The attribute value is in microns
and can only be greater that 0.
Related Information
Related commands: syn_map
apply_cglar
March 2025 1561 Product Version 23.1
Genus Attribute Reference
Joules--cglar_min_slack_threshold
cglar_min_slack_threshold
Syntax
cglar_min_slack_threshold integer
Applies to:
root
Description
Default: -1
Data_type: integer, read/write
Sets CGAL's min slack threshold in Joules. Specifies the minimum slack on data pin for a flop to be
considered for XOR gating by the 'compute_cglar' command. All flops with a smaller slack are not
considered. The attribute value is in pico seconds (ps).
Related Information
Related commands: syn_map
apply_cglar
cglar_ps_threshold
Syntax
cglar_ps_threshold { }
March 2025 1562 Product Version 23.1
Genus Attribute Reference
Joules--enable_xor_gating_during_map
Applies to:
root
Description
Default: -1.0
Data_type: double, read/write
Sets CGLAR's ps threshold in Joules. Specifies the minimum power savings threshold per
cluster/bank for the 'compute_cglar' command.
Related Information
Related commands: syn_map
apply_cglar
enable_xor_gating_during_map
Syntax
enable_xor_gating_during_map {false | true}
Applies to:
root
Description
Default: false
Data_type: bool, read/write
Controls xor-based clock gating during 'syn_map'.
March 2025 1563 Product Version 23.1
Genus Attribute Reference
Joules--xedebug_executable
Related Information
Related commands: syn_map
set_cglar_specification
apply_cglar
xedebug_executable
Syntax
xedebug_executable <path>
Applies to:
root
Description
Default: " "
Data_type: string, read/write
Sets the path of xeDebug to run 'read_stimulus' with which the PHY database being used as an
input was generated.
March 2025 1564 Product Version 23.1
Genus Attribute Reference
Innovus
30
Innovus
The chapter describes the following attributes of the 'root' object type:
innovus.add_fillers
innovus.delaycal
innovus.design
innovus.floorplan
innovus.ilm
innovus.init
innovus.opt
innovus.place
innovus.power_intent
innovus.rc_extraction
innovus.reorder_scan
innovus.route
innovus.route_early_global
innovus.timing
The attributes described in this chapter are not directly used by Genus but instead, when set,
are shared with Innovus.
March 2025 1565 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.add_fillers
innovus.add_fillers
add_fillers_cell_name_style
Syntax
add_fillers_cell_name_style {hier | flat}
Applies to:
root
Description
Default: hier
Data_type: enum, read/write
Adds physical cells into hierarchical modules or as top level cells (flat).
Related Information
Affects this command: syn_opt
innovus.delaycal
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.delaycal
March 2025 1566 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.add_fillers
The following attributes are supported in Genus:
delaycal_accuracy_level
delaycal_advanced_accuracy_mode
delaycal_advanced_calculation_mode
delaycal_advanced_node_pin_cap_settings
delaycal_advanced_pin_cap_mode
delaycal_combine_mmmc
delaycal_degrade_slew_on_early_nets
delaycal_early_irdrop_data_type
delaycal_enable_quiet_receivers_for_hold
delaycal_enable_input_slew_sensitivity_on_constraint
delaycal_enable_si
delaycal_equivalent_waveform_model_for_timing_check
delaycal_equivalent_waveform_type
delaycal_honor_slew_propagate_constraint
delaycal_ignore_net_load
delaycal_irdrop_data_type
delaycal_irdrop_window_based
delaycal_late_irdrop_data_type
delaycal_nonlinear_voltage_scaling_improvements
delaycal_report_out_bound
delaycal_signoff_alignment_settings
delaycal_skip_slew_merge_from_disabled_path
delaycal_slew_out_bound_limit_high
delaycal_slew_out_bound_limit_low
delaycal_socv_accuracy_mode
March 2025 1567 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.design
delaycal_socv_machine_learning_level
delaycal_support_output_pin_cap
delaycal_use_top_interface_delay_in_context
delaycal_voltage_scaling_compatibility_mode
delaycal_wire_variation_correlation_mode
delaycal_wire_variation_rc_correlation
delaycal_write_set_inst_voltage_cmd
For details, see 'delaycal Category Attributes' in the Innovus Common UI Text Command
Reference.
innovus.design
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.design
The following attributes are supported in Genus:
design_backside_top_routing_layer
design_bottom_routing_layer
design_compressed_pg_db
design_cong_effort
design_dual_rail_via_pitch
design_early_clock_flow
design_early_pba_mode
design_express_route
March 2025 1568 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.floorplan
design_ideal_hold_fixing
design_ignore_followpin_vias
design_merge_trim_shapes
design_optimization_density_screen_margin
design_pessimistic_mode
design_slack_weighting_method
design_tech_node
design_trim_grid_group
For details, see 'design Category Attributes' in the Innovus Common UI Text Command
Reference.
innovus.floorplan
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.floorplan
The following attributes are supported in Genus:
floorplan_check_types
floorplan_cut_off_place_blockage_outside_die
floorplan_cut_off_route_blockage_outside_die
floorplan_enable_rectilinear_design
floorplan_extra_row_pattern
floorplan_extra_sites
floorplan_finfet_inst_grid
March 2025 1569 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.floorplan
floorplan_finfet_placement_grid
floorplan_first_row_site_index
floorplan_inst_grid
floorplan_last_row_site_index
floorplan_layer_track_grid
floorplan_max_io_height
floorplan_move_child_constraint_with_constraint
floorplan_move_macros_with_constraint
floorplan_move_preplaced_std_cell_only
floorplan_move_std_cell_with_constraint
floorplan_narrow_channel_threshold
floorplan_no_cut_row
floorplan_placement_grid
floorplan_power_rail_layer
floorplan_row_height_increment_in_corner_to_corner
floorplan_row_height_increment_in_corner_to_in_corner
floorplan_row_site_height
floorplan_skip_violations
floorplan_snap_all_corners_to_grid
floorplan_snap_constraint_grid
floorplan_snap_die_grid
floorplan_snap_io_grid
floorplan_snap_place_blockage_grid
floorplan_snap_place_blockage_type
floorplan_user_define_grid
floorplan_finfet_manufacturing_grid
floorplan_row_site_width
March 2025 1570 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.ilm
floorplan_cells_for_extra_sites
floorplan_snap_block_grid
floorplan_auto_sync_master_clone
floorplan_row_height_multiple
floorplan_initial_all_compatible_core_site_rows
floorplan_snap_core_grid
floorplan_row_height_increment_corner_to_corner
floorplan_include_io_when_init_area
floorplan_minimum_sites
floorplan_default_power_domain_site
floorplan_keep_rows_when_moving_power_domain
floorplan_default_row_pattern_site
floorplan_manufacturing_grid
For details, see 'floorplan Category Attributes' in the Innovus Common UI Text Command
Reference.
innovus.ilm
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.ilm
The following attributes are supported in Genus:
ilm_keep_flatten
ilm_keep_high_fanout_ports
March 2025 1571 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.init
ilm_keep_inst_in_sdc
ilm_keep_loopback
ilm_max_num_insts
ilm_max_num_registers
ilm_slack_driven
For details, see 'ilm Category Attributes' in the Innovus Common UI Text Command Reference.
innovus.init
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.init
The following attributes are supported in Genus:
init_delete_floating_hnets
init_keep_empty_modules
init_sync_relative_path
For details, see 'init Category Attributes' in the Innovus Common UI Text Command Reference.
innovus.opt
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
March 2025 1572 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.init
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.opt
The following attributes are supported in Genus:
opt_activity_refresh_args
opt_add_always_on_feed_through_buffers
opt_add_insts
opt_add_ports
opt_add_repeater_report_failure_reason
opt_all_end_points
opt_allow_multi_bit_on_flop_with_sdc
opt_allow_only_cell_swapping
opt_area_recovery
opt_area_recovery_setup_target_slack
opt_clone_insts_list
opt_concatenate_default_and_user_prefixes
opt_consider_routing_congestion
opt_constant_inputs
opt_constant_nets
opt_delete_insts
opt_detail_drv_failure_reason
opt_detail_drv_failure_reason_max_num_nets
opt_down_size_insts
opt_drv
opt_drv_margin
opt_drv_with_miller_cap
March 2025 1573 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.init
opt_duplicate_cte_constrained_hport
opt_early_hold_fixing
opt_enable_clock_pulse_width_checks
opt_enable_data_to_data_checks
opt_enable_restructure
opt_enable_targeted_synthesis
opt_fix_fanout_load
opt_flop_pins_report
opt_flops_report
opt_hold_allow_overlap
opt_hold_allow_resize
opt_hold_allow_setup_tns_degradation
opt_hold_cells
opt_hold_ignore_path_groups
opt_hold_on_excluded_clock_nets
opt_hold_slack_threshold
opt_hold_target_slack
opt_honor_density_screen
opt_honor_fences
opt_icg_enable_pin_rebuffering
opt_max_density
opt_max_length
opt_move_insts
opt_multi_bit_combinational_merge_timing_effort
opt_multi_bit_combinational_mode
opt_multi_bit_combinational_opt
opt_multi_bit_combinational_split_timing_effort
March 2025 1574 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.init
opt_multi_bit_flop_merge_bank_label_inference
opt_multi_bit_flop_merge_timing_effort
opt_multi_bit_flop_name_prefix
opt_multi_bit_flop_name_separator
opt_multi_bit_flop_name_suffix
opt_multi_bit_flop_opt
opt_multi_bit_flop_reorder_bits
opt_multi_bit_flop_split_report_failure_reason
opt_multi_bit_flop_split_timing_effort
opt_multi_bit_unused_bit_count
opt_multi_bit_unused_bits
opt_new_inst_prefix
opt_new_net_prefix
opt_pin_swapping
opt_post_route_allow_overlap
opt_post_route_area_reclaim
opt_post_route_art_flow
opt_post_route_check_antenna_rules
opt_post_route_drv_recovery
opt_post_route_fix_clock_drv
opt_post_route_fix_glitch
opt_post_route_fix_si_transitions
opt_post_route_hold_recovery
opt_post_route_setup_recovery
opt_power_effort
opt_pre_route_ndr_aware
opt_preserve_all_sequential
March 2025 1575 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.init
opt_preserve_hpin_function
opt_remove_redundant_insts
opt_report_multi_bit_unmerged_reasons
opt_resize_flip_flops
opt_resize_level_shifter_and_iso_insts
opt_resize_power_switch_insts
opt_route_opt_recovery
opt_sequential_genus_restructure_report_failure_reason
opt_setup_target_slack
opt_skew
opt_skew_apply_delay_limits_to_full_flow
opt_skew_ccopt
opt_skew_delay_pre_cts
opt_skew_macro_only
opt_skew_max_allowed_delay
opt_skew_min_allowed_delay
opt_skew_no_boundary
opt_skew_post_route
opt_skew_pre_cts
opt_target_based_opt_file
opt_target_based_opt_file_only
opt_target_based_opt_hold_file
opt_tied_inputs
opt_time_design_compress_reports
opt_time_design_num_paths
opt_time_design_report_net
opt_time_design_vertical_timing_summary
March 2025 1576 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.place
opt_unfix_clock_insts
opt_verbose
For details, see 'opt Category Attributes' in the Innovus Common UI Text Command Reference.
innovus.place
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.place
The following attributes are supported in Genus:
place_design_enable_3d
place_design_floorplan_mode
place_design_integrity_ir_fix_effort
place_design_refine_macro
place_design_refine_place
place_detail_activity_power_driven
place_detail_allow_border_pin_abut
place_detail_allow_single_height_row_symmetry_x
place_detail_check_cut_spacing
place_detail_check_inst_space_group
place_detail_check_route
place_detail_color_aware_legal
place_detail_context_aware_legal
March 2025 1577 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.place
place_detail_eco_max_distance
place_detail_eco_priority_insts
place_detail_fixed_shifter
place_detail_honor_inst_pad
place_detail_io_pin_blockage
place_detail_ir_aware_max_drive_strength
place_detail_irdrop_aware_effort
place_detail_irdrop_aware_timing_effort
place_detail_irdrop_region_number
place_detail_legalization_inst_gap
place_detail_max_shifter_column_depth
place_detail_max_shifter_depth
place_detail_max_shifter_row_depth
place_detail_no_filler_without_implant
place_detail_pad_fixed_insts
place_detail_pad_physical_cells
place_detail_pgftv_insertion_cell_list
place_detail_preroute_as_obs
place_detail_preserve_routing
place_detail_remove_affected_routing
place_detail_swap_eeq_cells
place_detail_use_check_drc
place_detail_use_diffusion_transition_fill
place_detail_use_gate_array_filler_groups
place_detail_use_no_diffusion_one_site_filler
place_detail_wire_length_opt_effort
place_global_activity_power_driven
March 2025 1578 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.place
place_global_activity_power_driven_effort
place_global_align_macro
place_global_allow_3d_stack
place_global_auto_blockage_in_channel
place_global_clock_gate_aware
place_global_clock_power_driven
place_global_clock_power_driven_effort
place_global_cong_effort
place_global_cpg_effort
place_global_cpg_file
place_global_enable_advanced_pipeline
place_global_enable_distributed_place
place_global_ignore_scan
place_global_ignore_spare
place_global_max_density
place_global_module_aware_spare
place_global_module_padding
place_global_place_io_pins
place_global_reorder_scan
place_global_soft_guide_strength
place_global_timing_effort
place_global_uniform_density
place_hard_fence
place_hierarchical_flow
place_opt_post_place_tcl
place_opt_run_global_place
place_spare_update_timing_graph
March 2025 1579 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.power_intent
For details, see 'place Category Attributes' in the Innovus Common UI Text Command Reference.
innovus.power_intent
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.power_intent
The following attributes are supported in Genus:
power_intent_allow_back_to_back_isolation
power_intent_allow_nested_default_domain
power_intent_allow_power_domain_min_gap_zero
power_intent_assume_iso_enable_pin_is_always_on
power_intent_check_all_nets_for_domain_crossing
power_intent_do_not_use_top_domain_for_port_voltage
power_intent_honor_power_domain_for_domain_crossing_route
power_intent_honor_power_domain_for_intra_domain_route
power_intent_include_dot_lib_related_pg_pin
power_intent_share_well_always_on_buffering_support
power_intent_upf_insert_on_floating_pins
power_intent_use_cpf_global_connect_for_always_on_buffer
power_intent_use_cpf_global_connect_for_shifter
power_intent_use_effective_domain_for_iso_shifter_insertion
March 2025 1580 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.rc_extraction
For details, see 'power_intent Category Attributes' in the Innovus Common UI Text Command
Reference.
innovus.rc_extraction
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.extract_rc
The following attributes are supported in Genus:
extract_rc_cap_filter_mode
extract_rc_cerebrus_license_only
extract_rc_compress_rcdb
extract_rc_coupled
extract_rc_coupling_cap_threshold
extract_rc_def_via_cap
extract_rc_effort_level
extract_rc_engine
extract_rc_extra_cmd_file
extract_rc_hard_block_obs
extract_rc_incremental
extract_rc_layer_independent
extract_rc_local_cpu
extract_rc_pvs_fill
extract_rc_qrc_cmd_file
extract_rc_qrc_cmd_type
March 2025 1581 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.reorder_scan
extract_rc_qrc_output_mode
extract_rc_qrc_run_mode
extract_rc_qrc_stream_map_file
extract_rc_quantus_executable
extract_rc_relative_cap_threshold
extract_rc_signoff_stream_layer_map
extract_rc_total_cap_threshold
extract_rc_tquantus_model_file
extract_rc_tsv_subckt_file
extract_rc_turbo_reduce
extract_rc_use_qrc_oa_interface
extract_rc_use_shielding_in_detail_mode
extract_rc_via_cap
extract_rc_write_def_options_for_signoff_extract
For details, see 'extract_rc Category Attributes' in the Innovus Common UI Text Command
Reference.
innovus.reorder_scan
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.reorder_scan
The following attributes are supported in Genus:
reorder_scan_add_scan_port_prefix
March 2025 1582 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.route
reorder_scan_clock_aware
reorder_scan_comp_logic
reorder_scan_effort
reorder_scan_enable_for_partition
reorder_scan_keep_hinst_port_name
reorder_scan_keep_hport
reorder_scan_prefer_horizontal
reorder_scan_prefer_vertical
reorder_scan_skip_mode
reorder_scan_swap_effort
For details, see 'reorder_scan Category Attributes' in the Innovus Common UI Text Command
Reference.
innovus.route
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.route
The following attributes are supported in Genus:
route_add_antenna_inst_prefix
route_adjust_auto_via_weight
route_allow_inst_overlaps
route_allow_pin_as_feedthru
route_antenna_cell_name
March 2025 1583 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.route
route_antenna_diode_insertion
route_concurrent_minimize_via_count_effort
route_connect_to_bumps
route_design_high_freq_bus_mixed_layer
route_detail_add_passive_fill_only_on_layers
route_detail_allow_passive_fill_only_in_layers
route_detail_antenna_eco_list_file
route_detail_auto_stop
route_detail_check_mar_on_cell_pin
route_detail_end_iteration
route_detail_fix_antenna
route_detail_fix_antenna_on_secondary_pg_nets
route_detail_fix_antenna_with_gate_array_filler_mode
route_detail_merge_abutting_cut
route_detail_min_length_for_spread_wire
route_detail_min_length_for_widen_wire
route_detail_min_slack_for_opt_wire
route_detail_no_taper_in_layers
route_detail_no_taper_on_output_pin
route_detail_on_grid_only
route_detail_post_route_litho_repair
route_detail_post_route_spread_wire
route_detail_post_route_swap_via
route_detail_post_route_via_pillar_effort
route_detail_postroute_via_priority
route_detail_post_route_wire_widen
route_detail_post_route_wire_widen_rule
March 2025 1584 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.route
route_detail_search_and_repair
route_detail_signoff_effort
route_detail_stub_routing_in_first_layer
route_detail_use_multi_cut_via_effort
route_diode_insertion_for_clock_nets
route_disable_route_rule_on_via_pillar_to_special_net_wire
route_eco_ignore_existing_route
route_enable_route_rule_si_limit_length
route_enforce_route_rule_on_special_net_wire
route_extra_via_enclosure
route_fix_clock_nets
route_high_freq_constraint_groups
route_high_freq_match_report_file
route_high_freq_num_reserved_layers
route_high_freq_remove_floating_shield
route_high_freq_search_repair
route_high_freq_shield_trim_length
route_honor_exclusive_region
route_honor_power_domain
route_ignore_antenna_top_cell_pin
route_ignore_follow_pin_shapes
route_interposer_allow_diagonal_trunk
route_interposer_control_options
route_interposer_interlayer_shielding_layers
route_interposer_interlayer_shielding_nets
route_interposer_interlayer_shielding_offsets
route_interposer_interlayer_shielding_widths
March 2025 1585 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.route
route_interposer_same_layer_shielding_net
route_interposer_same_layer_shielding_width_spacing
route_interposer_trunk_routing_layers
route_interposer_trunk_routing_width_spacing
route_number_fail_limit
route_number_thread
route_number_warning_limit
route_process_node
route_rc_extraction_corner
route_relaxed_route_rule_spacing_to_power_ground_nets
route_reserve_space_for_multi_cut
route_reverse_direction
route_route_clock_nets_first
route_rules
route_selected_net_only
route_shield_crosstie_offset
route_shield_length_threshold
route_shield_report_skip_status
route_shield_stripe_layer_range
route_shield_tap_cell_insertion
route_shield_tap_cell_name
route_skip_analog
route_strict_honor_route_rule
route_strictly_honor_1d_routing
route_stripe_layer_range
route_third_party_data
route_tieoff_to_shapes
March 2025 1586 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.route_early_global
route_trim_pull_back_distance_from_boundary
route_trunk_with_cluster_target_size
route_use_auto_via
route_via_weight
route_with_eco
route_with_litho_driven
route_with_si_driven
route_with_timing_driven
route_with_trim_metal
route_with_via_in_pin
route_with_via_only_for_block_cell_pin
route_with_via_only_for_stdcell_pin
For details, see 'route Category Attributes' in the Innovus Common UI Text Command Reference.
innovus.route_early_global
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.route_early_global
The following attributes are supported in Genus:
route_early_global_effort_level
route_early_global_honor_partition_allow_feedthru
route_early_global_honor_partition_fence
March 2025 1587 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
route_early_global_honor_partition_pin
route_early_global_honor_partition_pin_guide
route_early_global_honor_power_domain
route_early_global_reverse_direction_regions
route_early_global_route_bump_nets
route_early_global_route_selected_net_only
route_early_global_secondary_pg_max_fanout
route_early_global_stripe_layer_range
For details, see 'route_early_global Category Attributes' in the Innovus Common UI Text
Command Reference.
innovus.timing
To set the value of any root attribute, use the following command:
set_db attribute_name value
To get the current value of any root attribute, use the following command:
get_db attribute_name
To get the current value of all attributes in this category, use the following command:
get_db -category innovus.timing
The following attributes are supported in Genus:
timing_analysis_* timing_aocv_*
timing_apply_* timing_check_*
timing_clock_* timing_collection_*
timing_constraint_* timing_context_*
timing_cppr_* timing_derate_*
March 2025 1588 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_disable_* timing_enable_*
timing_extract_model_* timing_generate_*
timing_library_* timing_path_based_*
timing_property_* timing_report_*
timing_use_* Other timing_*
For details, see 'timing Category Attributes' in the Innovus Common UI Text Command
Reference.
timing_analysis_*
The following attributes are supported:
timing_analysis_aging
timing_analysis_case_analysis
timing_analysis_check_type
timing_analysis_clock_gating
timing_analysis_clock_net_marking_mode
timing_analysis_cppr
timing_analysis_enable_robustness_mode
timing_analysis_engine
timing_analysis_honor_active_logic_view
timing_analysis_multi_input_switching_mode
timing_analysis_precision_ps
timing_analysis_self_loops_paths_no_skew
March 2025 1589 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_aocv_*
The following attributes are supported:
timing_aocv_analysis_mode
timing_aocv_chip_size
timing_aocv_core_size
timing_aocv_derate_mode
timing_aocv_stage_count_update_on_timing_reset
timing_apply_*
The following attributes are supported:
timing_apply_default_primary_input_assertion
timing_apply_exceptions_to_data_check_related_pin
timing_apply_setup_hold_exceptions_to_data_check_related_pin
timing_check_*
The following attributes are supported:
timing_check_timing_report_all_checks
timing_check_timing_signal_level_high_to_low_threshold
timing_check_timing_signal_level_low_to_high_threshold
timing_clock_*
The following attributes are supported:
timing_clock_phase_propagation
timing_clock_pulse_width_sensitivity_checks_threshold
timing_clock_source_paths_unconstrained_mark_clock_used_as_data
timing_clock_source_use_driving_cell
timing_clock_uncertainty_from_to_precedence
March 2025 1590 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_collection_*
The following attributes are supported:
timing_collection_all_fanin_fanout_traversal_mode
timing_collection_result_display_limit
timing_collection_variable_assignment_compatibility
timing_constraint_*
The following attributes are supported:
timing_constraint_disable_min_max_input_delay_worst_casing
timing_constraint_enable_detailed_report_invalid_begin_end_points
timing_constraint_enable_drv_limit_override
timing_constraint_enable_logging
timing_constraint_enable_report_invalid_begin_end_points
timing_constraint_enable_search_path
timing_constraint_enable_separate_multicycle_data_checks
timing_constraint_path_delay_exclude_io_delay_from_ignore_clock_latency
timing_constraint_path_delay_exclude_unconstrained_endpoints
timing_constraint_path_delay_include_clock_pin_endpoints
timing_constraints_enable_path_exception_efficient_file_line_debug_mode
timing_constraint_update_io_latency_averaging_mode
timing_constraint_warn_for_timing_derate_exceeding_max_limit
timing_context_*
The following attributes are supported:
timing_context_apply_port_sdc_exceptions
timing_context_clock_mapping_check_waveform
timing_context_clock_mapping_percentage_tolerance
March 2025 1591 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_context_clock_phase_based_clock_mapping
timing_context_data_phase_based_clock_mapping
timing_context_enable_unmapped_clock_analysis
timing_context_port_based_clock_mapping
timing_cppr_*
The following attributes are supported:
timing_cppr_enable_mismatch_transition_mode
timing_cppr_opposite_edge_mean_scale_factor
timing_cppr_opposite_edge_sigma_scale_factor
timing_cppr_opposite_edge_sigma_scale_factor_cell
timing_cppr_opposite_edge_sigma_scale_factor_net
timing_cppr_propagate_thru_latches
timing_cppr_remove_clock_to_data_pessimism
timing_cppr_self_loop_mode
timing_cppr_skip_clock_reconvergence
timing_cppr_skip_clock_reconvergence_for_unmatched_clocks
timing_cppr_threshold_ps
timing_cppr_transition_sense
timing_derate_*
The following attributes are supported:
timing_derate_aocv_dynamic_delays
timing_derate_aocv_reference_point
timing_derate_dynamic_compatibility
timing_derate_incremental_multiply_accumulative_mode
timing_derate_negative_delay_backward_compatibility
timing_derate_ocv_reference_point
March 2025 1592 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_derate_spatial_distance_unit
timing_derate_voltage_scaling_mode
timing_disable_*
The following attributes are supported:
timing_disable_bus_contention_check
timing_disable_clock_period_checks
timing_disable_constant_propagation_for_sequential_cells
timing_disable_drv_report_on_constant_nets
timing_disable_floating_bus_check
timing_disable_genclk_combinational_blocking
timing_disable_inout_output_side_timing_checks
timing_disable_internal_inout_cell_paths
timing_disable_internal_inout_net_arcs
timing_disable_lib_pulse_width_checks
timing_disable_netlist_constants
timing_disable_nochange_checks
timing_disable_output_as_clock_port
timing_disable_parallel_arcs
timing_disable_pulse_width_same_edge_si_cppr_mode
timing_disable_report_header_info
timing_disable_retime_clock_path_slew_propagation
timing_disable_sdf_retain_arc_merging
timing_disable_skew_checks
timing_disable_test_signal_arc
timing_disable_timing_model_latch_inferencing
timing_disable_tristate_disable_arcs
March 2025 1593 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_enable_*
The following attributes are supported:
timing_enable_aocv_slack_based
timing_enable_case_analysis_conflict_warning
timing_enable_clock_phase_based_rise_fall_derating
timing_enable_derating_for_pulse_width_checks
timing_enable_early_late_data_slews_for_setuphold_mode_checks
timing_enable_edge_based_path_adjust_group_mode
timing_enable_genclk_divide_by_inherit_parent_duty_cycle
timing_enable_genclk_source_path_register_limit
timing_enable_generated_clock_edge_based_source_latency
timing_enable_get_objects_regexp_compatibility
timing_enable_get_obj_escaped_name_backward_compatible
timing_enable_get_pins_of_lib_cell_pins
timing_enable_hier_context_unmapped_clock_analysis
timing_enable_hierarchical_get_nets_support
timing_enable_latch_thru_mode
timing_enable_latency_through_clock_gating
timing_enable_minimal_constraints_loading_for_opt_signoff
timing_enable_mmmc_loop_breaking
timing_enable_multicycle_data_check_compatibility
timing_enable_multi_drive_net_reduction_with_assertions
timing_enable_multi_frequency_latch_analysis
timing_enable_path_delay_to_unconstrained_endpoints_compatibility
timing_enable_pessimistic_cppr_for_reconvergent_clock_paths
timing_enable_power_ground_constants
March 2025 1594 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_enable_preset_clear_arcs
timing_enable_pulse_latch
timing_enable_si_cppr
timing_enable_simultaneous_setup_hold_mode
timing_enable_timing_window_pessimism_removal
timing_enable_tristate_clock_gating
timing_enable_uncertainty_for_clock_checks
timing_enable_uncertainty_for_pulse_width_checks
timing_enable_unique_vt_mode_for_gba
timing_enable_vtskew_derate_mode
timing_enable_zero_delay_analysis_mode
timing_extract_model_*
The following attributes are supported:
timing_extract_model_aocv_mode
timing_extract_model_case_analysis_in_library
timing_extract_model_check_arcs_as_lvf
timing_extract_model_consider_design_level_drv
timing_extract_model_disable_cycle_adjustment
timing_extract_model_enable_combinational_arc_to_clock_source_on_output_ports
timing_extract_model_exhaustive_validation_dir
timing_extract_model_exhaustive_validation_mode
timing_extract_model_gating_as_nochange_arc
timing_extract_model_half_cycle_non_interface_paths
timing_extract_model_ideal_clock_latency_arc
timing_extract_model_include_applied_load_in_characterization_range
timing_extract_model_include_applied_slew_in_characterization_range
March 2025 1595 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_extract_model_max_feedthru_characterization_load
timing_extract_model_non_borrowing_latch_path_as_setup
timing_extract_model_slew_propagation_mode
timing_extract_model_write_clock_checks_as_arc
timing_extract_model_write_clock_checks_as_scalar_tables
timing_extract_model_write_lvf
timing_extract_model_write_min_max_clock_tree_path
timing_generate_*
The following attributes are supported:
timing_generate_normalized_driver_waveform
timing_generated_clocks_allow_nested_assertions
timing_generated_clocks_inherit_ideal_latency
timing_library_*
The following attributes are supported:
timing_library_build_async_deassert_arc
timing_library_convert_async_setuphold_to_recrem
timing_library_generated_clock_use_group_name
timing_library_hold_constraint_corner_sigma_multiplier
timing_library_hold_sigma_multiplier
timing_library_infer_async_pins_from_timing_arcs
timing_library_infer_cap_range_from_ccs_receiver_model
timing_library_infer_cap_range_from_ecsm_receiver_model
timing_library_infer_socv_from_aocv
timing_library_interpolate_drv_values
timing_library_read_ccs_noise_data
timing_library_read_without_ecsm
March 2025 1596 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_library_read_without_sensitivity
timing_library_scale_aocv_to_socv_to_n_sigma
timing_library_setup_constraint_corner_sigma_multiplier
timing_library_setup_sigma_multiplier
timing_library_term_voltage_from_lib_pin
timing_library_zero_negative_timing_check_arcs
timing_path_based_*
The following attributes are supported:
timing_path_based_enable_bounding_box_for_io_paths
timing_path_based_enable_closest_common_pin_driver_for_bounding_box
timing_path_based_enable_exhaustive_depth_bounded_by_gba
timing_path_based_enable_report_launch_clock_path
timing_path_based_enable_verbose_mode
timing_path_based_exhaustive_enable_design_coverage
timing_path_based_exhaustive_max_paths_limit
timing_path_based_low_memory_mode
timing_path_based_report_analysis_summary_max_paths_limit
timing_property_*
The following attributes are supported:
timing_property_arrival_clocks_consider_clock_source_data_phase
timing_property_arrival_clocks_consider_data_phase
timing_property_arrival_clocks_consider_latency_phase
timing_property_arrival_window_enable_tcl_dict_format
timing_property_return_null_collection_with_quiet
March 2025 1597 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_report_*
The following attributes are supported:
timing_report_analysis_summary_csv_extended_new_format
timing_report_arrival_property_worstcase_mode
timing_report_begin_end_pair_max_path_limit
timing_report_check_timing_unconstrained_endpoints_due_to_constants
timing_report_clock_pin_as_begin_point
timing_report_constraint_enable_extended_drv_format
timing_report_constraint_extended_cell_em_flow
timing_report_constraint_format
timing_report_constraint_rise_fall_clock_period_check
timing_report_constraint_use_infinity_slack_for_unconstrained
timing_report_default_frequency_for_unconstrained_nets
timing_report_disable_max_paths_per_group
timing_report_drv_enable_clock_source_as_clock
timing_report_drv_enable_frequency_per_view
timing_report_drv_enable_ghz_notation_for_drv_fields
timing_report_drv_enable_slew_threshold_scaling
timing_report_drv_per_frequency
timing_report_drv_use_worst_timing_slack
timing_report_enable_clock_to_for_unconstrained_paths
timing_report_enable_cppr_point
timing_report_enable_em_index_clipping_report
timing_report_enable_flag_field_symbols
timing_report_enable_lead_trail_to_rise_fall_map
timing_report_enable_markers
timing_report_enable_max_capacitance_drv_for_constant_nets
March 2025 1598 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_report_enable_max_path_limit_warning
timing_report_enable_report_clock_timing_across_clock_pin
timing_report_enable_si_debug
timing_report_enable_unique_pins_multiple_capture_clock_paths
timing_report_enable_verbose_ssta_mode
timing_report_generated_clock_info
timing_report_group_based_mode
timing_report_max_transition_check_using_nsigma_slew
timing_report_property_fastest_clock_consider_data_phase
timing_report_pulse_width_matching_launch_capture_paths
timing_report_redirect_message_types
timing_report_retime_formatting_mode
timing_report_skip_constraint_loop_check
timing_report_socv_summary_mean_sigma
timing_report_split_other_end_arrival
timing_report_timing_header_detail_info
timing_report_unconstrained_path_early_late_header
timing_report_unconstrained_paths
timing_report_use_receiver_model_capacitance
timing_report_use_worst_parallel_cell_arc
timing_use_*
The following attributes are supported:
timing_use_clock_pin_attribute_for_clock_net_marking
timing_use_incremental_si_transition
timing_use_latch_early_launch_edge
timing_use_latch_time_borrow
March 2025 1599 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_use_verilog_for_model_netlist
Other timing_*
The following attributes are supported:
timing_allow_input_delay_on_clock_source
timing_all_registers_filter_clock_pins_by_clock
timing_all_registers_identify_macros_include_is_macro_cell
timing_all_registers_include_icg_cells
timing_context_continue_on_invalid_module_list
timing_continue_on_error
timing_create_clock_default_propagated
timing_default_opcond_per_lib
timing_driving_cell_override_library
timing_get_of_objects_hier_compatibility
timing_hier_obj_name_compatibility
timing_ignore_lumped_rc_assertions
timing_io_use_clock_network_latency
timing_ipd_allow_paths_for_asynchronous_clocks
timing_max_transition_use_si_transition
timing_multi_frequency_clock_rounding_factor
timing_normalized_driver_waveform_clip_linear_part
timing_normalized_driver_waveform_weight_factor
timing_null_collection_return_compatibility
timing_pba_exhaustive_path_nworst_limit
timing_pll_clock_use_driving_cell
timing_prefix_module_name_with_library_generated_clock
timing_rail_swing_checks_high_voltage_threshold
March 2025 1600 Product Version 23.1
Genus Attribute Reference
Innovus--innovus.timing
timing_rail_swing_checks_low_voltage_threshold
timing_rcdb_allow_mismatch_option
timing_recompute_sdf_in_setuphold_mode
timing_reduce_multi_drive_net_arcs
timing_reduce_multi_drive_net_arcs_threshold
timing_resolve_driver_conflicts
timing_scaling_for_negative_checks
timing_scaling_for_negative_delays
timing_sdf_adjust_negative_setuphold
timing_sdf_enable_setuphold_scond_ccond
timing_self_loop_paths_no_skew_max_depth
timing_self_loop_paths_no_skew_max_slack
timing_set_clock_source_to_output_as_data
timing_socv_preserve_variation_with_annotations
timing_spatial_derate_distance_mode
timing_suppress_escape_characters
timing_suppress_ilm_constraint_mismatches
timing_waveform_aware_pulse_width_checks_high_voltage_level
timing_waveform_aware_pulse_width_checks_low_voltage_level
timing_write_sdf_no_escape_backslash
March 2025 1601 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes
31
Alphabetical List of Attributes
A B C D E F G H I J L M N O P Q R S T U V W X
Numerics
1801
A
accept_user_defined_attributes
active_operating_conditions
actual_scan_chains
add_pin_name_to_lp_instance
adjust_derate
adjust_derate
alias_names
allow_invalid_primary_power_pins_libcell
allow_multiple_sync_ctrls
analysis
aocv_library
apply_booth_encoding
arch_filename
arch_name
arrival
aspect_ratio
assemble_design_generic_hier
assigned_library_set
attribute_path
attributes
auto_library_domain
auto_library_domain_threshold
auto_partition
auto_super_thread
March 2025 1602 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
auto_ungroup
auto_ungroup_max_threshold
avoid
avoid_no_row_libcell
avoid_tied_inputs
B
bank_based_multibit_inferencing
base_cell_sets
base_cells
base_name
bbox
beta_feature
bit_blasted_port_style
bit_width
blackbox
blackboxes
blockages
boundary
boundary_optimize_constant_hpins
boundary_optimize_equal_opposite_hpins
boundary_optimize_feedthrough_hpins
boundary_optimize_invert_hpins
boundary_optimize_invert_hpins_rename_nets
boundary_optimize_invert_hpins_renaming_extension
box_has_aocv_derate
box_has_ocv_derate
bumps
bus_naming_style
bussed_pin_of_single_bitwidth_as_pin
C
candidate_impls
cap_table_file
case_analysis_multi_driver_propagation
case_analysis_propagation_for_icg
case_analysis_sequential_propagation
categories
causes_ideal_net
ccd_executable
cglar_da_threshold
cglar_max_distance
March 2025 1603 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
cglar_min_slack_threshold
cglar_ps_threshold
change_cap_precision
clock_gate_enable_pin
clock_gate_enable_polarity
clock_gating_integrated_cell
clp_enable_1801_hierarchical_bbox
clp_ignore_ls_high_to_low
clp_treat_errors_as_warnings
clusters
cmd_file
comb_seq_merge_message_threshold
command_log
commands
commit_delete_invalid_iso_ls
common_ui
congestion_effort
constant_0_loads
constant_0_nets
constant_1_loads
constant_1_nets
constants
constraint
continue_on_error
continuous_fast_report_timing
control_logic_optimization
convert_rising_falling_arcs_to_combo_arcs
corresponding_q_or_qn_pin
count
cpf
cpf_macro_inherit_parent_power_domain
cpi_allow_avoided_cells
cpi_allow_dont_touch_cells
cpi_allow_inverted_ls
cpi_enable_third_domain_buffering
cpi_insert_on_switch_network
cpi_invert_preserved_net
cpi_inverter_name_prefix
cpi_iso_ls_skip_const_prop_loads
cpi_output_net_name_prefix
cpu_runtime
cross_probe_frc_value
March 2025 1604 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
cts_buffer_cells
cts_clock_gating_cells
cts_inverter_cells
cts_logic_cells
current_design
cw_library_version
cwd_setup_file
D
db_units
def_component_mask_shift
def_extension
def_file
def_history
def_output_escape_multibit
def_output_version
def_pins
def_technology
def_version
default
define_clock_with_new_cost_group
delay
delay_corner_pd_at_tc_no_timing_derate
delaycal_enable_high_fanout
delaycal_equivalent_waveform_model
delaycal_library_interpolation_mode
delaycal_socv_lvf_mode
delaycal_socv_use_lvf_tables
delete_flops_on_preserved_net
delete_hier_insts_on_preserved_net
delete_unloaded_insts
delete_unloaded_seqs
derive_bussed_pins
design
design_bottom_routing_layer
design_flow_effort
design_power_effort
design_process_node
design_top_routing_layer
designs
designware_compatibility
detailed_sdc_messages
March 2025 1605 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
dft_1500_child_input
dft_1500_child_output
dft_1500_hierarchical_parent_child_wrapping
dft_1500_hierarchical_softcore_wrapping
dft_abstract_dont_scan
dft_add_mux_on_pre_connected_ctl_si
dft_allow_dwc_in_top
dft_apply_sdc_constraints
dft_atpg_executable
dft_auto_create_chains_as_internal
dft_auto_identify_shift_register
dft_boundary_cell_module_prefix
dft_boundary_scan_timing_mode_name
dft_capture_11496_reciever_output
dft_capture_timing_mode_name
dft_check_cfg_mode_aware
dft_clock_waveform_divide_fall
dft_clock_waveform_divide_period
dft_clock_waveform_divide_rise
dft_clock_waveform_fall
dft_clock_waveform_period
dft_clock_waveform_rise
dft_compression_2d_aspect_ratio
dft_compression_2d_decomp_pipeline_distance
dft_compression_2d_grid_max_x
dft_compression_2d_grid_max_y
dft_compression_2d_grid_min_x
dft_compression_2d_grid_min_y
dft_compression_auto_create
dft_compression_channel_length
dft_compression_comp_pipeline_max_xor_depth
dft_compression_compressor_type
dft_compression_decomp_pipeline_max_xor_depth
dft_compression_decompressor_type
dft_compression_elasticity_ratio
dft_compression_extest_decompressor_type
dft_compression_fullscan_support
dft_compression_lp_gating_sharing_ratio
dft_compression_lp_gating_support
dft_compression_mask_and_lp_gating_unload_support
dft_compression_mask_sharing_ratio
dft_compression_mask_support
March 2025 1606 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
dft_compression_masken_pipeline_depth
dft_compression_num_extest_scanin
dft_compression_num_extest_scanout
dft_compression_num_scanin
dft_compression_num_scanout
dft_compression_opcg_unload_support
dft_compression_post_2d_sdc_file
dft_compression_post_2d_sdc_mode_name
dft_compression_ratio
dft_compression_scanin_pipeline_depth
dft_compression_scanout_pipeline_depth
dft_compression_serial_load_support
dft_cross_lp_cells_for_lockup_clk_driver
dft_custom_se
dft_disable_wrapper_inside_non_scan_elem
dft_dont_merge_multibit_lockup
dft_dont_scan
dft_dont_wrap_if_shared_threshold_exceed
dft_enable_flop_placement_in_test_point_insertion
dft_enable_wir_function_check
dft_exclude_flop_from_los_pipeline
dft_exclude_from_shift_register
dft_exclude_instance_from_wrapping
dft_exclude_internal_flops_from_shared_wrapper_threshold
dft_exclude_tdrc_fail_seg
dft_exempt_from_system_clock_check
dft_extended_scandef
dft_fence_slow_speed_domains
dft_force_blackbox_for_atpg
dft_generate_atpg_no_testpoint_file
dft_get_balanced_chains_assignment
dft_hier_instance_for_dedicated_wrapper
dft_icg_was_cloned_or_rewired
dft_identify_internal_test_clocks
dft_identify_non_boundary_shift_registers
dft_identify_shared_wrapper_cells
dft_identify_test_signals
dft_identify_top_level_test_clocks
dft_identify_xsource_violations_from_timing_models
dft_ignore_dont_scan_for_shared_wrapper_processing
dft_ignore_non_scan_for_wrapper_processing
dft_include_controllable_pins_in_abstract_model
March 2025 1607 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
dft_include_test_signal_outputs_in_abstract_model
dft_insert_dedicated_inside_sink_hierarchy
dft_is_blackbox_for_atpg
dft_is_los_pipeline_flop
dft_is_testpoint
dft_jtag_instance_name
dft_jtag_module_name
dft_lbist_capture_timing_mode_name
dft_lbist_shift_timing_mode_name
dft_license_scheme
dft_lockup_name_prefix
dft_mapped
dft_modedef_internal
dft_modus_version
dft_opcg_block_input_to_flop_paths
dft_opcg_domain_blocking
dft_opcg_timing_mode_name
dft_optimize_chain_wirelength_level
dft_part_of_segment
dft_partition
dft_physical_aware_test_points
dft_physical_pd_aware_scan_connection
dft_pmbist_jtag_timing_mode_name
dft_pmbist_mda_timing_mode_name
dft_power_aware_lockup_clock_driver
dft_power_aware_wrapper_insertion
dft_prefix
dft_process_multibit_for_shared_wrapper
dft_propagate_test_signals_from_hookup_pins_only
dft_report_empty_test_clocks
dft_report_scan_register_quiet
dft_rtl_insertion
dft_run_test_point_analysis_for_compression
dft_run_test_point_analysis_for_lbist
dft_scan_chain
dft_scan_chain_in_multi_mode
dft_scan_power_domain_crossing_lockup_latch
dft_scan_style
dft_scanbit_waveform_analysis
dft_sdc_input_port_delay
dft_sdc_output_port_delay
dft_shared_common_logic_threshold
March 2025 1608 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
dft_shared_wrapper_through
dft_shift_register_identification_mode
dft_shift_register_max_length
dft_shift_register_min_length
dft_shift_register_with_mbci
dft_shift_timing_mode_name
dft_status
dft_tap_lockup_clock_from_adjacent
dft_test_clock
dft_test_clock_edge
dft_test_clock_source
dft_test_clock_waveform_edge
dft_testpoint_type
dft_tpi_no_tp
dft_tpi_sharing_scope
dft_true_time_flow
dft_use_abstract_segment_instance_power_domain_for_scan_connection
dft_use_multibit_register_width_for_threshold
dft_use_wck_as_default_wrapper_clock
dft_violation
dft_wait_for_license
die_area
direction
disable_ungroup_for_hierarchy
disable_when_checks
display_information_of_edit_netlist
dont_break_combo_loops_thr_c_to_q
dont_break_combo_loops_thr_c_to_q_macro
dont_break_combo_loops_thr_en_to_q
dont_report_library
dont_report_operating_conditions
dont_retime
dont_touch
dont_touch_effective
dont_touch_file
dont_touch_hports
dont_touch_reason
dont_use_base_cell_set
dont_use_cells
dont_use_cells_effective
dont_use_qbar_seq_pins
double_cell_search_pattern
March 2025 1609 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
dp_analytical_opt
dp_area_mode
dp_csa
dp_csa_factorize
dp_rewriting
dp_sharing
dp_speculation
dp_ungroup_during_syn_map
dp_ungroup_separator
dpopt_instance_constant_input_based_speculation
dpopt_power_opto
dpopt_power_opto_scaling
dpopt_toggle_skew_threshold_for_booth_encoding
drc_first
drc_max_cap_first
drc_max_fanout_first
drc_max_trans_first
driver_for_unloaded_hier_pins
dummy_scmr_iw_cell_in_all_lds
E
early_estimated_worst_irdrop_factor
early_irdrop_data
elapsed_runtime
embedded_script
enable_aon_type_in_remove_assign
enable_break_timing_paths_by_mode
enable_data_check
enable_library_pins_sorting_in_mmmc
enable_strict_percent_control
enable_ui_precision
enable_xor_gating_during_map
encrypted
entity_filename
entity_name
error_on_lib_lef_pin_inconsistency
escaped_name
establish_library_during_lef_loading
exact_match_seq_async_ctrls
exact_match_seq_sync_ctrls
exclusive_group_gap
exclusive_group_type
March 2025 1610 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
exclusive_groups
external_delays
external_non_tristate_drivers
extract_rc_lef_tech_file_map
F
fail_on_error_mesg
fcu_instruction_set
fills
fix_min_drcs
floorplan_default_blockage_name_prefix
floorplan_default_row_pattern_site
floorplan_first_row_site_index
floorplan_last_row_site_index
flow_branch
flow_caller_data
flow_db_directory
flow_error_errorinfo
flow_error_message
flow_error_write_db
flow_exclude_time_for_init_flow
flow_exit_when_done
flow_feature_values
flow_features
flow_footer_tcl
flow_header_tcl
flow_hier_path
flow_history
flow_log_directory
flow_log_prefix_generator
flow_mail_on_error
flow_mail_to
flow_metrics_file
flow_metrics_snapshot_parent_uuid
flow_metrics_snapshot_uuid
flow_overwrite_db
flow_plugin_names
flow_plugin_steps
flow_post_db_overwrite
flow_remark
flow_report_directory
flow_run_tag
March 2025 1611 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
flow_schedule
flow_starting_db
flow_startup_directory
flow_status_file
flow_step_begin_tcl
flow_step_canonical_current
flow_step_check_tcl
flow_step_current
flow_step_end_tcl
flow_step_last
flow_step_last_msg
flow_step_last_status
flow_step_next
flow_steps
flow_summary_tcl
flow_template_feature_definition
flow_template_tools
flow_template_type
flow_template_version
flow_top
flow_user_templates
flow_verbose
flow_working_directory
flow_write_db_snapshot
flow_write_db_snapshot_exclude_time
flow_yamllint_exec
flows
flowtool_exit_timeout
flowtool_extra_arguments
flowtool_metrics_qor_excel
flowtool_metrics_qor_html
flowtool_metrics_qor_text
flowtool_metrics_qor_vivid
flowtool_predict_full_names
flowtool_schedule_flow_immediate
flowtool_summary_tcl
force_merge_combos_into_multibit_cells
force_merge_isos_into_multibit_cells
force_merge_seqs_into_multibit_cells
force_via_resistance
force_wireload
formula
March 2025 1612 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
frc_treat_modules_as_leaf_insts
free_global_vars_set_by_read_sdc
G
gcells
gen_module_prefix
get_db_display_limit
group
group_generate_portname_from_netname
group_instance_suffix
groups
gui_auto_update
gui_enabled
gui_hv_phys_threshold
gui_hv_threshold
gui_pv_highlight_hier_instances_show_legend
gui_show_old_legend
gui_sv_threshold
gui_sv_update
gui_visible
H
handle_ungroup_names
hard_region
hdl_all_filelist
hdl_allow_inout_const_port_connect
hdl_allow_instance_name_conflict
hdl_allow_positional_connections_for_pg_inst
hdl_append_generic_ports
hdl_array_naming_style
hdl_async_set_reset
hdl_auto_async_set_reset
hdl_auto_exec_sdc_scripts
hdl_auto_sync_set_reset
hdl_bidirectional_assign
hdl_bidirectional_wand_wor_assign
hdl_bus_wire_naming_style
hdl_case_mux_threshold
hdl_case_sensitive_instances
hdl_cdfg_early_redundancy_removal
hdl_config_name
hdl_convert_onebit_vector_to_scalar
March 2025 1613 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
hdl_convert_onebit_vector_wire_to_scalar
hdl_create_label_for_unlabeled_generate
hdl_cw_list
hdl_decimal_parameter_name
hdl_delete_transparent_latch
hdl_elab_command_params
hdl_enable_proc_name
hdl_enable_real_support
hdl_error_on_blackbox
hdl_error_on_latch
hdl_error_on_logic_abstract
hdl_error_on_negedge
hdl_exclude_params_in_cell_search
hdl_ff_keep_explicit_feedback
hdl_ff_keep_feedback
hdl_filelist
hdl_flatten_complex_port
hdl_flatten_complex_port_in_bottom_up_flow
hdl_generate_index_style
hdl_generate_separator
hdl_ignore_pragma_names
hdl_index_mux_threshold
hdl_instance_array_naming_style
hdl_interface_separator
hdl_keep_first_module_definition
hdl_keep_wand_wor_type
hdl_language
hdl_latch_keep_feedback
hdl_libraries
hdl_link_from_any_lib
hdl_max_loop_limit
hdl_max_map_to_mux_control_width
hdl_max_memory_address_range
hdl_max_recursion_limit
hdl_module_definition_resolution
hdl_nc_compatible_module_linking
hdl_new_bidirectional_assign
hdl_overwrite_command_line_macros
hdl_parameter
hdl_parameter_naming_style
hdl_parameterize_module_name
hdl_parameters
March 2025 1614 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
hdl_pipeline_comp
hdl_preserve_async_sr_priority_logic
hdl_preserve_dangling_output_nets
hdl_preserve_signals
hdl_preserve_supply_nets
hdl_preserve_sync_ctrl_logic
hdl_preserve_sync_set_reset
hdl_preserve_unused_flop
hdl_preserve_unused_latch
hdl_preserve_unused_registers
hdl_primitive_input_multibit
hdl_proc_name
hdl_record_naming_style
hdl_reg_array_naming_style
hdl_reg_naming_style
hdl_reg_record_naming_style
hdl_rename_cdn_flop_pins
hdl_rename_cdn_latch_pins
hdl_report_case_info
hdl_resolve_instance_with_libcell
hdl_resolve_parameterized_instance_with_structural_module
hdl_sv_module_wrapper
hdl_sync_set_reset
hdl_track_filename_row_col
hdl_track_module_elab_memory_and_runtime
hdl_unconnected_value
hdl_use_block_prefix
hdl_use_case_generate_prefix
hdl_use_current_dir_before_hdl_search_path
hdl_use_cw_first
hdl_use_default_parameter_values_in_name
hdl_use_for_generate_prefix
hdl_use_if_generate_prefix
hdl_use_port_default_value
hdl_user_name
hdl_v2001
hdl_vdp_list
hdl_verilog_defines
hdl_vhdl_assign_width_mismatch
hdl_vhdl_case
hdl_vhdl_environment
hdl_vhdl_lrm_compliance
March 2025 1615 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
hdl_vhdl_preferred_architecture
hdl_vhdl_range_opto
hdl_vhdl_read_version
hdl_zero_replicate_is_null
heartbeat
heartbeat_print_date
help
help_always_visible
hide_mmmc_lib_clones
hierarchical_name
highlighted
hinsts
hnets
honor_valid_location
hpins
I
id
ideal_seq_async_pins
ignore_attribute_check_during_pin_conversion
ignore_library_drc
ignore_library_max_fanout
ignore_pin_error_in_test_cell_function
ignore_preserve_in_tiecell_insertion
ignore_scan_combinational_arcs
ignore_sigma_arc_inconsistency
ilm_filter_internal_path
ilm_keep_async
imm_block_view_brightness
incr_joules_instance_threshold_count_MT
index
information_level
init_blackbox_for_undefined
init_design_mmmc_skip_inactive
init_ground_nets
init_hdl_search_path
init_lef_files
init_lib_phys_consistency_checks
init_lib_search_path
init_min_dbu_per_micron
init_mmmc_version
init_oa_abstract_views
March 2025 1616 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
init_oa_default_rule
init_oa_foundry_rule
init_oa_layout_views
init_oa_ref_libs
init_oa_search_libs
init_oa_special_rule
init_physical_only
init_power_intent_files
init_power_nets
init_prototype_design
init_state
init_timing_enabled
innovus_executable
input_assert_one_cold_pragma
input_assert_one_hot_pragma
input_asynchro_reset_blk_pragma
input_asynchro_reset_pragma
input_case_cover_pragma
input_case_decode_pragma
input_map_to_mux_pragma
input_pragma_keyword
input_synchro_enable_blk_pragma
input_synchro_enable_pragma
input_synchro_reset_blk_pragma
input_synchro_reset_pragma
inst_prefix
instance_internal_power
instance_leakage_power
instances
insts
insts_area
interconnect_mode
internal_power
invs_add_io_buffers
invs_add_io_buffers_base_name
invs_add_io_buffers_exclude_clock_net
invs_add_io_buffers_exclude_nets
invs_add_io_buffers_honor_dont_touch
invs_add_io_buffers_in_cells
invs_add_io_buffers_include_nets
invs_add_io_buffers_out_cells
invs_add_io_buffers_port
March 2025 1617 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
invs_add_io_buffers_pre_place
invs_add_io_buffers_skip_refine_place
invs_add_io_buffers_status
invs_add_io_buffers_suffix
invs_assign_buffer
invs_assign_removal
invs_clk_gate_recloning
invs_enable_useful_skew
invs_init_core_row
invs_launch_servers
invs_memory_usage
invs_opt_leakage
invs_opt_leakage_options
invs_place_opt_design
invs_postexport_report_script
invs_postload_script
invs_power_library_flow
invs_pre_place_opt
invs_preload_script
invs_scanreorder_keepport
invs_set_lib_unit
invs_spatial_place_connected
invs_temp_dir
invs_timing_driven_place
invs_to_genus_colorized_lef_path
invs_write_path_groups
invs_write_scandef_options
iopt_allow_inst_dup
iopt_allow_tiecell_with_inversion
iopt_enable_floating_output_check
iopt_force_constant_removal
iopt_remap_avoided_cells
iopt_sequential_duplication
iopt_sequential_resynthesis
iopt_sequential_resynthesis_min_effort
iopt_temp_directory
iopt_ultra_optimization
is_auto_library_domain
is_backside
is_booth_encoded
is_buffer
is_clock_gate_clock
March 2025 1618 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
is_clock_gate_enable
is_clock_gate_obs
is_clock_gate_out
is_clock_gate_reset
is_clock_gate_test
is_combinational
is_cw_component
is_dont_touch
is_fixed_mask
is_flop
is_hierarchical
is_ilm
is_integrated_clock_gating
is_inverter
is_isolation
is_latch
is_level_shifter
is_no_flop
is_phase_inverted
is_retention
is_synthesis_clock_gate
is_usable
isolate_zero_pin_retention
isolation_rules
isonor_2017
J
joules_incremental_silent
joules_silent
L
language
large_cell_arc_threshold
latch_borrow
latch_max_borrow
latch_max_borrow_interface
late_estimated_worst_irdrop_factor
late_irdrop_data
layers
lbr_convert_n_piece_cap_to_2_piece
lbr_convert_nochange_arcs
lbr_ignore_disable_libarc
March 2025 1619 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
lbr_infer_cap_range_from_c1cn_dynamic_pincap_model
lbr_infer_cap_range_from_dynamic_pincap_model
lbr_mmmc_enable_init_design_speedup
lbr_respect_async_controls_priority
lbr_seq_in_out_phase_opto
lbr_timing_library_optimize_table_data
lbr_use_test_cell_seq
leakage_power
leakage_power_scale_in_nw
lec_executable
lef_add_logical_pins
lef_add_power_and_ground_pins
lef_library
lef_manufacturing_grid
lef_stop_on_error
lef_units
legacy_preserve_sdc_object_name
legal
level_shifter_groups
level_shifter_rules
lib_avoid_existing_eeq_cell
lib_cell
libraries
library
library_domain
library_domains
library_name
library_sets
library_setup_lightweight
limit_lbr_messages
limited_access_feature
link_library
load_average
load_libraries_of_inactive_views
local_hinsts
local_hnets
local_hpins
local_insts
local_pins
location
location_x
location_y
March 2025 1620 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
log_command_error
log_file
logic_abstract
logical_hier
lp_asserted_probability
lp_asserted_toggle_rate
lp_clock_gating_add_obs_port
lp_clock_gating_auto_cost_group_initial_target
lp_clock_gating_auto_cost_grouping
lp_clock_gating_auto_path_adjust
lp_clock_gating_auto_path_adjust_fixed_delay
lp_clock_gating_auto_path_adjust_modes
lp_clock_gating_auto_path_adjust_multiplier
lp_clock_gating_cell
lp_clock_gating_connect_test_clock_gate_types
lp_clock_gating_connect_test_consider_constant_enabled_as_connected
lp_clock_gating_control_point
lp_clock_gating_coverage_effort
lp_clock_gating_exceptions_aware
lp_clock_gating_exclude
lp_clock_gating_exclude_signal
lp_clock_gating_extract_common_enable
lp_clock_gating_gated_clock_gates
lp_clock_gating_gated_flops
lp_clock_gating_hierarchical
lp_clock_gating_infer_enable
lp_clock_gating_is_flop_rc_gated
lp_clock_gating_is_flop_user_gated
lp_clock_gating_is_leaf_clock_gate
lp_clock_gating_max_flops
lp_clock_gating_method
lp_clock_gating_min_flops
lp_clock_gating_module
lp_clock_gating_prefix
lp_clock_gating_stage
lp_clock_gating_style
lp_clock_gating_test_signal
lp_clock_tree_buffers
lp_clock_tree_leaf_max_fanout
lp_computed_probability
lp_computed_toggle_rate
lp_default_toggle_percentage
March 2025 1621 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
lp_display_negative_internal_power
lp_dynamic_analysis_scope
lp_get_state_dependent_lkg_pow
lp_insert_clock_gating
lp_internal_power
lp_leakage_power
lp_net_power
lp_power_unit
lp_probability_type
lp_pso_aware_estimation
lp_pso_aware_tcf
lp_system_asserted_probability
lp_system_asserted_probability
lp_toggle_rate_type
lp_toggle_rate_unit
lp_x_transition_probability_count
lp_x_transition_toggle_count
lp_z_transition_probability_count
lp_z_transition_toggle_count
M
macro_isolation_rules
macro_model
macro_models
macro_power_domains
map_clock_tree
map_drc_first
map_latch_allow_async_decomp
map_prefer_non_inverted_clock_line
map_respect_rtl_clk_phase
map_to_master_slave_lssd
map_to_multiple_output_gates
map_to_mux
mark_async_pin_using_timing_arcs
mark_inconsistent_cells_as_dont_use
mark_macro_as_power_switch_cell
mark_retention_pin_ideal
mark_valid_lp_cell_as_usable
max_cap_cost
max_cap_cost
max_cpus_per_server
max_fanout
March 2025 1622 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
max_fanout_cost
max_print
max_trans_cost
max_transition
memory_usage
merge_combinational_hier_instance
merge_combinational_hier_instances
merge_non_scan_to_scan_flops
mesg_severity_downgrade
messages
metric_advanced_url_endpoint
metric_capture_3d_hotspots
metric_capture_depth
metric_capture_design_image
metric_capture_design_image_blockages
metric_capture_design_image_blockages_threshold
metric_capture_design_image_power_intent
metric_capture_design_image_route_drc
metric_capture_max_drc_markers
metric_capture_min_count
metric_capture_overwrite
metric_capture_pba_tns_histogram
metric_capture_per_view
metric_capture_reg2reg_metrics
metric_capture_timing_analysis_mode
metric_capture_timing_path_groups
metric_capture_timing_paths
metric_capture_tns_histogram
metric_capture_tns_histogram_buckets
metric_capture_tns_histogram_max_slack
metric_capture_tns_histogram_paths
metric_capture_vth_metrics
metric_capture_vth_per_power_domain
metric_category_default
metric_current_run_id
metric_enable
metric_summary_metrics
min_cap_cost
min_fanout_cost
min_pulse_width
min_timing_arcs
min_trans_cost
March 2025 1623 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
minimize_uniquify
mode_name
module
modules
mtdcl_traverse_by_level
multibit_allow_async_phase_map
multibit_allow_sr_head_flop_merge
multibit_allow_unused_bits
multibit_area_power_scoring
multibit_auto_exclude_registers_with_exceptions
multibit_aware_seq_mapping
multibit_aware_seq_mapping_higher_priority
multibit_cells_from_different_busses
multibit_combo_name_concat_string
multibit_debug
multibit_invert_clock_phase
multibit_mapping_effort_level
multibit_predefined_allow_unused_bits
multibit_prefix_string
multibit_preserve_inferred_instances
multibit_preserved_net_check
multibit_seqs_instance_naming_style
multibit_seqs_members_naming_style
multibit_seqs_name_concat_string
multibit_short_prefix_string
multibit_split_string
multibit_unused_input_value
N
name
net_area
nets
nominal_conditions
non_dft_timing_mode_name
num_insts
num_local_hpins
num_nets
num_pg_nets
num_phys_insts
O
oa_def_file
March 2025 1624 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
obj_type
obj_types
obsolete
obsolete_state
obstruction_routing_layer
ocv_mode
one_pass_formal_verification
opconds
operating_conditions
operator
opt_allow_floating_outputs
opt_high_effort_cells
opt_leakage_to_dynamic_ratio
opt_spatial_common_db
opt_spatial_early_clock
opt_spatial_effort
opt_spatial_merge_flops
opt_spatial_useful_skew
opt_tns
optimize_constant_0_flops
optimize_constant_0_seq
optimize_constant_1_flops
optimize_constant_1_seq
optimize_constant_across_preserved
optimize_constant_feedback_seqs
optimize_constant_latches
optimize_merge_flops
optimize_merge_latches
optimize_merge_seq
optimize_seq_x_to
optimize_yield
override_library_max_drc
P
param_association
parameters
parent
parse_lib_moments_table
part_power_intent_file
partition_based_synthesis
path
pbs_db_directory
March 2025 1625 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
pbs_gen_summary
pbs_iopt_summary
pbs_load_lib_in_group_of
pbs_map_summary
pcells
peak_memory
percent_control_tolerance_for_map
permutable_group
pg_hnets
pg_nets
pg_ports
phys_annotate_ndr_nets
phys_assume_met_fill
phys_checkout_innovus_license
phys_density_based_balancing_max_area_ratio
phys_density_based_balancing_min_area_ratio
phys_extra_vias_length_factor
phys_fix_multi_height_cells
phys_flow_effort
phys_ignore_nets
phys_ignore_special_nets
phys_insts
phys_pre_place_iopt
phys_premorph_density
phys_read_script_large_file_source
phys_refresh_power_intent_1801
phys_scan_def_file
phys_skip_and_copy_special_nets
phys_socv
phys_summary_table_print_negative_tns
phys_update_preannotation_script
physical_aware_multibit_mapping
physical_cell_area
physical_force_predict_floorplan
physical_memory_usage
pi_disable_aon_buffering
pi_parser_error_on_missing_objects
pi_parser_honor_avoided_cells
pi_read_enable_exhaustive_search
pi_relax_map_iso_cell_checks
pi_relax_map_ls_cell_checks
pias_aon_enable_mode_analysis
March 2025 1626 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
pin
pin_association
pins
pinstances
place_status
platform_wordsize
pmbist_enable_multiple_views
pmbist_ffn_cell
pmbist_ffsync_cell
pmbist_full_async_reset
pmbist_instruction_set
pmbist_map2mux_cell
pmbist_unresolved
pnets
port_busses
ports
power_domain
power_domains
power_dynamic
power_engine
power_internal
power_leakage
power_library
power_model
power_models
power_modes
power_scope
power_scopes
power_switching
power_total
pqos_ignore_msv
pqos_ignore_scan_chains
pqos_placement_effort
pre_elab_script
predict_floorplan_allow_core_reshape
predict_floorplan_allow_illegal_macro
predict_floorplan_constraints
predict_floorplan_enable_cpg
predict_floorplan_enable_during_generic
predict_floorplan_invs_post_resize_script
predict_floorplan_keep_fences
predict_floorplan_keep_fixed_macros
March 2025 1627 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
predict_floorplan_script
predict_floorplan_skip_propagate_activity
predict_floorplan_use_innovus
preferred_comp
preferred_impl
preserve
preserve_combinational_loop_ports_nets
preserve_power_domain_boundary
preserve_sdc_annotated_comb_insts
preserve_techelts
print_count
print_error_info
print_ports_nets_preserved_for_cb
priority
program_major_version
program_name
program_short_name
program_version
prompt_print_cwd
propagate_constant_from_timing_model
protected
proto_feasible_target
proto_feasible_target_adjust_slack_pct
proto_feasible_target_threshold
proto_feasible_target_threshold_clock_pct
proto_hdl
Q
qos_report_power
qrc_tech_file
R
rc_corners
read_def_fuzzy_name_match
read_def_keep_net_property
read_def_libcell_mismatch_error
read_qrc_tech_file_rc_corner
real_runtime
regions
reload_when_for_macro_cell
remove_assigns
repeater_rules
March 2025 1628 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
report_as_datapath
report_clock_from_different_views
report_library_message_summary
report_logic_levels_histogram_fixed_depth
report_ndr_min_layer_count
report_tcl_command_error
reset_icg_violation
restore_history_file
retime
retime_async_reset
retime_effort_level
retime_hard_region
retime_move_mux_loop_with_reg
retime_optimize_reset
retime_original_registers
retime_period_percentage
retime_reg_naming_suffix
retime_ssw_sync_enable
retime_verification_flow
retiming_clocks
route_early_global_horizontal_supply_scale_factor
route_early_global_num_tracks_per_clock_wire
route_early_global_secondary_pg
route_early_global_vertical_supply_scale_factor
route_rules
route_types
rows
S
safety_dcls_isolate_clock
safety_dcls_isolate_groups
safety_dcls_isolate_halo_type
safety_dcls_isolate_inputs
safety_dcls_isolate_is_group_input_cell
safety_dcls_isolate_is_group_output_cell
safety_dcls_isolate_is_halo
safety_dcls_isolate_outputs
safety_dcls_isolate_pin
safety_dcls_isolate_reset
safety_dcls_isolate_scan_enable
safety_dcls_isolate_signal_type
safety_dcls_isolate_type
March 2025 1629 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
safety_dcls_isolate_use_halo
safety_dcls_route_types
safety_failure_mode
safety_flow_enable
safety_mechanism
safety_mechanism_type
safety_midas_enable
safety_parity_bit_cells
safety_parity_endpoint
safety_parity_error_signal_endpoint
safety_parity_group_size_max
safety_parity_group_size_min
safety_ser_cells
safety_ser_type
safety_tmr_clones
safety_tmr_custom_voter_cell
safety_tmr_error_signal_endpoint
safety_tmr_isolate_clock
safety_tmr_isolate_reset
safety_tmr_isolate_scan_enable
safety_tmr_parent
safety_tmr_spacing
safety_tmr_spacing_x
safety_tmr_spacing_y
safety_tmr_voters
safety_tmr_well_tap_cells
safety_tmr_well_tap_left_padding
safety_tmr_well_tap_right_padding
save_history_file
scale_factor_group_path_weights
scale_of_cap_per_unit_length
scale_of_res_per_unit_length
scan_chains
screen_max_print
screen_print_count
script_begin
script_end
script_search_path
sdc_filter_match_more_slashes
sdc_flat_view_default
sdc_match_more_slashes
sdp_files
March 2025 1630 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
sdp_groups
sdp_type
secondary_domain
selected
selected_impl
seq_reason_deleted
set_db_verbose
setup
severity
show_report_options
show_wns_in_log
shrink_factor
signed
sim_model
sites
skip_default_lib_check
skip_in_write_def
skip_ungroup_on_applied_constraint
skip_ungroup_with_exception
slack
slots
small_blocked_box_count
socv_derate
socv_library
source_of_via_resistance
source_suspend_on_error
source_verbose
source_verbose_info
source_verbose_proc
spatial_path_group_effort_level
specialnets
speed_grade
speed_up_read_socv
speedup_library_establishment
st_launch_wait_time
startup_license
state
state_ignore_cdn_exception_buff
state_retention_rule
state_retention_rules
stdout_log
stop_at_iopt_state
March 2025 1631 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
styles
sub_arch
super_thread_batch_command
super_thread_debug_directory
super_thread_debug_jobs
super_thread_equivalent_licenses
super_thread_kill_command
super_thread_rsh_command
super_thread_servers
super_thread_shell_command
super_thread_status_command
support_3Dtable_power_arc
support_aae_lib_path_change
support_appending_libs
support_combo_clock
support_internal_pg_pins
support_master_slave_flop
support_multi_seq_elements
support_multi_seq_scan_latch
support_serial_scanin_multibit_cell
support_tlatch_group
support_ui_units
suppress_syntech_messages
syn_generic_effort
syn_global_effort
syn_map_effort
syn_opt_effort
sync_enable_pins
synthesis_off_command
synthesis_on_command
synthesis_skip_pd_timing_derate
T
target_library
tcl_partial_cmd_argument_matching
tcl_return_display_length_limit
technology
test_enable_icg_violation
tim_ignore_data_check_for_non_endpoint_pins
time_recovery_arcs
timing_analysis_clock_propagation_mode
timing_analysis_clock_source_paths
March 2025 1632 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
timing_analysis_socv
timing_analysis_type
timing_conditions
timing_defer_mmmc_obj_updates
timing_disable_internal_inout_net_arcs
timing_disable_library_data_to_data_checks
timing_disable_non_sequential_checks
timing_enable_get_ports_for_current_instance
timing_enable_sr_latch_preset_clear_arcs
timing_library_lookup_drv_per_frequency
timing_model_reason
timing_no_path_segmentation
timing_nsigma_multiplier
timing_path
timing_propagate_latch_data_uncertainty
timing_report_default_formatting
timing_report_enable_common_header
timing_report_endpoint_fields
timing_report_exception_data
timing_report_fields
timing_report_load_unit
timing_report_path_type
timing_report_unconstrained
timing_socv_view_based_nsigma_multiplier_mode
timing_spatial_derate_chip_size
tinfo_include_load
tinfo_tstamp_file
tns_critical_range
total_area
trace_retime
track_count
track_patterns
transition_type
treat_net_as_analog
treat_non_seq_arc_cell_as_unusable
trigger_post_time_info
truncate
turbo_lib_loading
type
U
ui_precision
March 2025 1633 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
ui_precision_capacitance
ui_precision_derating
ui_precision_power
ui_precision_sensitivities
ui_precision_timing
ui_respects_preserve
ui_units_capacitance
ui_units_capacitance_reporting
ui_units_timing
ui_units_timing_reporting
unbound_oper_pin
ungroup
ungroup_ok
ungroup_separator
uniquify_naming_style
uniquify_rename_all
unmap_scan_flops
unresolved
unusable_reason
update_sv_wrapper_post_elab
usable_flop
usable_latch
use_area_from_lef
use_base_cell_set
use_cells
use_compatibility_based_grouping
use_default_related_pg_pin_for_aon
use_main_cell_output_function_for_test_cell
use_max_cap_lut
use_multi_clks_latency_uncertainty_optimize
use_multi_clks_latency_uncertainty_report
use_multibit_cells
use_multibit_combo_cells
use_multibit_iso_cells
use_multibit_seq_and_tristate_cells
use_nextstate_type_only_to_assign_sync_ctrls
use_only_on_power_critical_nets
use_power_ground_pin_from_lef
use_scan_seqs_for_non_dft
use_tiehilo_for_const
user_mean_derate
user_mean_derate
March 2025 1634 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
user_speed_grade
user_sub_arch
utilization
utilization_threshold
V
verification_directory
verification_directory_naming_style
via_resistance
vias
voltage
W
wccd_threshold_percentage
wcdc_clock_dom_comb_propagation
wcdc_synchronizer_type
wclp_lib_statetable
win_fp_inst_threshold
wireload
wireload_mode
wireload_selection
wlec_add_noblack_box_retime_subdesign
wlec_analyze_abort
wlec_analyze_setup
wlec_auto_analyze
wlec_black_box_ilm_modules
wlec_compare_threads
wlec_composite_compare
wlec_dft_constraint_file
wlec_gzip_fv_json
wlec_hier_append_string
wlec_hier_comp_threshold
wlec_hier_compare_string
wlec_hier_prepend_string
wlec_lib_statetable
wlec_low_power_analysis
wlec_multithread_license_list
wlec_no_dft_constraints
wlec_parallel_threads
wlec_post_add_notranslate_modules
wlec_run_hier_check_noneq
wlec_set_cdn_synth_root
March 2025 1635 Product Version 23.1
Genus Attribute Reference
Alphabetical List of Attributes--innovus.timing
wlec_uniquify
wlec_use_lec_model
wlec_use_smart_lec
wlec_verbose
write_db_auto_save_user_globals
write_db_use_relative_filepath
write_mmmc_forking_enabled
write_sdc_use_libset_name_set_dont_use
write_sv_port_wrapper
write_verification_files
write_vlog_bit_blast_bus_connections
write_vlog_bit_blast_constants
write_vlog_bit_blast_mapped_ports
write_vlog_bit_blast_tech_cell
write_vlog_convert_onebit_vector_to_scalar
write_vlog_declare_wires
write_vlog_empty_module_for_black_box
write_vlog_empty_module_for_logic_abstract
write_vlog_empty_module_for_subdesign
write_vlog_generic_gate_define
write_vlog_line_wrap_limit
write_vlog_no_negative_index
write_vlog_port_association_style
write_vlog_preserve_net_name
write_vlog_simplify_constant
write_vlog_skip_ilm_modules
write_vlog_skip_subdesign
write_vlog_top_module_first
write_vlog_unconnected_port_style
write_vlog_wor_wand
X
xedebug_executable
xm_protect_version
March 2025 1636 Product Version 23.1
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