Chapter 2 Assembly Language Programming

Instruction Formats (Opcodes, Mnemonics and Operands)

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. Each instruction has two parts: one is task to be performed, called the operation code
(opcode) and second is the data to be operated on, called the operand. The operand or data can be
specified in various ways. It may include 8-bit or 16-bit data, an internal register, a memory
location, or 8-bit or 16-bit address. In some instructions, the operand is implicit.

Every instruction in 8085 is represented by an 8-bit binary value. A microprocessor executes

instruction given by the user. Instruction should be in a language known to the microprocessor.
But Microprocessor understands the language of 0’s and 1’s. This language is called Machine
Language. We write 8085 program in assembly language which microprocessor cannot
understand so, a program known as Assembler is used to convert an assembly language.
Instruction formats are divided into three types:

 One-byte instructions: A 1-byte instruction includes the opcode and the operand in the
same byte. For example MOV C, A and ADD B.

 Two-byte instructions: In a 2-byte instruction, the first byte specifies the operation code
an second byte specifies the operand. For example MVI A,08H.

 Three-byte instructions: In a 3-byte instruction, the first byte specifies the opcode and the
following the two bytes specify the 16-bit address. Note that the second byte is the low-
order address and the third byte is the higher-order address. For example JMP 2000H,
LDA D000H.

8085 Instruction Sets

The complete set of instructions which a particular computer can interpret and execute is known
as Instruction Set. The program is written using the instructions from this instruction set and the
computer fetches and executes these instructions.
These instructions can be classified into the following five functional categories:

  Data transfer (copy) Instructions

  Arithmetic Instructions
  Logical Instructions
  Branching Instructions
 Machine-control Instructions

Data Transfer Instructions: This instruction copy the contents of the source register into the
destination register. For example:

I. MOV Rd, Rs  e.g., MOV C, A where C is the destination register and A is source
Register. In the below example, Rs and Rd are all general purpose registers such as A, B,
C, D, E, H, L. The contents of the source register do not change.
Before Execution After Execution

A=08 Flag Register A=08 Flag Register

B C=00 B C=08
D E D E
H L H L
SP SP
PC PC

II. MVI R, data  e.g., MVI A, 05H where 05 is the immediate data and A is the destination
register. Here, the immediate data 05H is copied to A register.

A=00 Flag Register A=05 Flag Register

B C B C
D E D E
H L H L
SP SP
PC PC
III. MOV M, Rs  e.g., MOV M, C where C is the source register and M is the memory
pointer which is HL pair. The HL pair contains the memory address whose data is 00H
(assume). C register content is copied to HL pair content.
Before Execution After Execution

A Flag Register A Flag Register

B C=08 B C=08
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFFH FFFFH

C000H 00 C000H 08

0000H 0000H

IV. MOV Rd, M  MOV C, M where C is the destination register and M is the memory
pointer which is HL pair. This case is quite reverse of the last case.
Before Execution After Execution

A Flag Register A Flag Register

B C=00 B C=08
D E D E
H=C0 L=00 H=C0 L=00
SP SP
PC PC

[C000H]
V. MVI M,data  MVI M, 10H where M is the memory pointer which is HL pair. This
instruction moves immediate data to memory. Now, by taking the address from the HL
pair, the immediate data written to this memory location.

Before execution After execution

A Flag Register A Flag Register

B C B C
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFF FFFF

C000 00 C000 10

0000 0000

Here the memory contents are changed.

VI. LXI Rp, data  LXI H 3000H where 3000H is the 16-bit data and H stands for HL pair.
This instruction loads register pair with the 16-bit data. Finally we can see that H contains
30H and L contains 00H.

Before execution After execution

A Flag Register A Flag Register

B C B C
D E D E
H(05) L(00) H(30) L(00)
SP SP
PC PC
VII. LDA address  LDA D000H where D000H is the address. This instruction loads the
accumulator direct from memory location D000H.
Before execution After execution

A(50) Flag Register A(20) Flag Register

B C B C
D E D E
H L H L
SP SP
PC PC

FFFF FFFF

D000 20 D000 20

0000 0000

VIII. STA address  STA D001H where D001H is the address. This instruction stores the
accumulator direct to memory location D001H.
Before execution After execution

A(50) Flag Register A(50) Flag Register

B C B C
D E D E
H L H L
SP SP
PC PC

FFFF FFFF

D001 20 D001 50

0000 0000
Arithmetic Instructions: This group of instructions performs arithmetic
operations such as addition, subtraction, increment and decrement.

I. ADD Rs  e.g., ADD B where A is the destination register and B is source Register. In
the above example, Rs is all general purpose registers such as A, B, C, D, E, H, L. The
contents of the source register do not change. A (98)  A (47) +B (51), The register A
value is added with register B value and the result goes to A register.

Before Execution After Execution

A=47 S Z AC P CY A=98 1 0 0 0 0
B=51 C B=51 C
D E D E
H L H L
SP SP
PC PC

II. ADD M  e.g., ADD M where M is the memory pointer which is HL pair. The HL pair
contains the memory address whose data is 20H (assume). A register value 10 is added
with [HL] and the results can be seen in the accumulator.
Before Execution After Execution

A=10 S Z AC P CY A=30 0 0 00 01 0 0
B C B C
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFFH FFFFH

C000H 20 C000H 20

0000H 0000H
III. ADC R  ADC B where B is the source register. Here the register B value is added with
Accumulator and carry flag CY.

Before Execution After Execution

A=3F S Z AC P CY A=60 0 0 01 0 1 0 0
B=20 C B=20 C
D E D E
H L H L
SP SP
PC PC

IV. ADC M  ADC M where M is the memory pointer which is HL pair. This instruction
adds memory content with Accumulator and Carry flag CY. The final result goes to the
accumulator.
Before execution After execution

A=10 S Z AC P CY A=31 0 0 0 0 0 00 0
B C B C
D E D E
H(C0) L(02) H(C0) L(02)
SP SP
PC PC

FFFF FFFF

C002 20 C002 20

0000 0000
V. ADI data  ADI B7H where B7H is the 8-bit data. This data is added with Accumulator
and the result goes to A register. This comes under immediate addressing mode.

Before execution After execution

A=59 S Z AC P CY A=10 0 0 010 0 0 1

B C B C
D E D E
H L H L
SP SP
PC PC

VI. ACI Data  ACI 20H where 20H is the immediate data. This is added with accumulator
and carry flag CY. The final result goes to accumulator.
Before execution After execution

A=C0 S Z AC P CY A=E0 1 0 0 0 0 0 0 0
B C B C
D E D E
H L H L
SP SP
PC PC

VII. DAD Rp  DAD B where B is Register pair BC. This BC pair is added with HL pair
value and final results goes to HL register.
Before execution After execution

A S Z AC P CY A 0 0 00 0 00 0
B=20 C=35 B=20 C=35
D E D E
H=80 L=45 H=A0 L=7A
SP SP
PC PC
VIII. SUB R  SUB B where B is the source register. This instruction subtracts the contents of
register B from the contents of accumulator and the result is placed in accumulator. The
contents of B are not altered. All fags are modified to reflect the result. The subtraction is
performed by using 2’s complement method. If carry flag CY is set the result is negative
and is in 2’s complement form. If CY is reset, the result is positive and is in normal form.
Before execution After execution

A=37H S Z AC P CY A=F7H 1 0 0 0 0 00 1
B=40H C B=40H C
D E D E
H L H L
SP SP
PC PC
In the example above, no carry is generated so CY=0. The microprocessor complements
the carry which means CY=1 which represents that the result is negative and is in 2’s
complement form.

IX. SUB M  SUB M where M is the memory pointer. This instruction subtracts the
memory location contents from accumulator.

Before execution After execution

A=50 S Z AC P CY A=30 0 00 0 0 10 0
B C B C
D E D E
H(C2) L(00) H(C2) L(00)
SP SP
PC PC

FFFF FFFF

C200 20 C200 20
C001 C201

0000 0000
X. SBB R  SBB B where B is the Source Register. This instruction subtracts register B
and borrow flag from accumulator.

Before execution After execution

A=37 S Z AC P CY A=F7 1 0 00 0 0 0 1
B=3F C B=3F C
D E D E
H L H L
SP SP
PC PC

XI. SBB M  SBB M where M is the memory pointer. This instruction subtracts memory
contents and borrow flag from accumulator.
Before execution After execution

A=20H S Z AC P CY A=D0 1 0 00 0 00 1
B C B C
D E D E
H=C2 L=00 H=C2 L=00
SP SP
PC PC

FFFF FFFF

C200 4F C200 4F

0000 0000
XII. SUI Data  SUI 50 where 50H is the immediate data. This instruction subtracts
immediate data from accumulator.

Before execution After execution

A=20H S Z AC P CY A=D0 1 0 0 0 000 1

B C B C
D E D E
H L H L
SP SP
PC PC

XIII. SBI Data  SBI 4F where 4F is immediate data. This instruction subtracts immediate
data and borrow flag from accumulator.

Before execution After execution

A=20H S Z AC P CY A=D0 1 0 00 00 0 1
B C B C
D E D E
H L H L
SP SP
PC PC

XIV. Decimal Adjust Accumulator (DAA):

i. If the value of the low order 4-bits D3-0 in the accumulator is greater than 9 or if AC
flag is set, the instruction adds 6 to the low order 4-bits of accumulator.
ii. If the value of the higher order 4-bits D7-4 in the accumulator is greater than 9 or if
carry flag is set, the instruction adds 6 to the higher order 4-bits of accumulator.

If we want to add two BCD numbers 12 and 39 and want result in BCD form.

MVI A, 12
ADI 39
DAA
When DAA is executed, it checks lower D0-D3 is greater than 9 or AC flag is set. Here the result
addition is 4B in hexadecimal where B is greater than 9 so 6 is added to the lower order 4-bits.
However, nothing is added to the higher D4-7 bits. So, the final result 51.

XV. INR R/DCR R  INR B/DCR B where B is source register. This instruction
increments/decrements the register value by 1. The below example is for increment.

Before execution After execution

A S Z AC P CY A 0 0 01 0 1 0 0
B=2F C B=30 C
D E D E
H L H L
SP SP
PC PC

XVI. INR M/DCR M where M is the memory pointer. This instruction increment/decrement
memory contents by one. The below example is for increment.

Before execution After execution

A S Z AC P CY A 0 0 0 0 01 0 0
B C B C
D E D E
H=C2 L=00 H=C2 L=00
SP SP
PC PC

C200 05 C200 06
XVII. INX Rp/DCX Rp  INX B/DCX B where BC is the register pair Rp. This instruction
increments/decrements the register pair value by 1. The below example is for increment.

Before execution After execution

A S Z AC P CY A 0 0 0 101 0 0
B=02 C=FF B=03 C=00
D E D E
H L H L
SP SP
PC PC
Logical Instructions: This group of instructions performs logical operations such
as and, or, xor etc. with the contents of accumulator.

I. ANA R  e.g., ANA B where A is the destination register and B is source Register. In
the below example, Rs is all general purpose registers such as A, B, C, D, E, H, L. The
contents of the source register do not change. A (02)  A (56) and B (82), The register A
value is anded with register B value and the result goes to A register.

Before Execution After Execution

A=56 S Z AC P CY A=02 0 0 01 0 0 0 0
B=82 C B=82 C
D E D E
H L H L
SP SP
PC PC

II. ANA M  e.g., ANA M where M is the memory pointer which is HL pair. The HL pair
contains the memory address whose data is F2H (assume). A register value 10 is added
with [HL] and the results can be seen in the accumulator.
Before Execution After Execution

A=4A S Z AC P CY A=42 0 0 0 1 0 10 0
B C B C
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFFH FFFFH

C000H F2 C000H F2

0000H 0000H
III. ANI Data  ANI 0FH where A is the destination register. This instruction logically
AND the immediate data with accumulator.

Before Execution After Execution

A=F7 S Z AC P CY A=07 0 0 01 0 0 0 0
B C B C
D E D E
H L H L
SP SP
PC PC

IV. ORA R  e.g., ORA B where A is the destination register and B is source Register. In
the below example, Rs is all general purpose registers such as A, B, C, D, E, H, L. The
contents of the source register do not change. A (B7)  A (A2) or B (B5), The register A
value is anded with register B value and the result goes to A register.

Before Execution After Execution

A=A2 S Z AC P CY A=B7 1 0 0 1 0 1 0 0
B=B5 C B=B5 C
D E D E
H L H L
SP SP
PC PC

V. ORA M ORA M where M is the memory pointer which is HL pair. This instruction
does logical OR with memory content.

Before execution After execution

A=AA S Z AC P CY A=FF 1 0 0 0 0 10 0
B C B C
D E D E
H(C0) L(02) H(C0) L(02)
SP SP
PC PC
FFFF FFFF

C002 55 C002 55

0000 0000

VI. ORI data  ORI 20H where 20H is the 8-bit data. This instruction does logically OR to
the immediate data with accumulator.

Before execution After execution

A=55 S Z AC P CY A=75 0 0 00 0 00 0
B C B C
D E D E
H L H L
SP SP
PC PC

VII. XRA R  XRA B where A is the destination register and B is the source register. This
instruction does Exclusive-OR operation with accumulator.

Before execution After execution

A=77 S Z AC P CY A=71 0 0 0 0 0 10 0
B=06 C B=06 C
D E D E
H L H L
SP SP
PC PC
VIII. XRA M  XRA M where M is the memory pointer which is HL pair. This instruction
does Exclusive-OR with memory content.

Before execution After execution

A=A5 S Z AC P CY A=F5 1 0 00 0 1 0 0
B C B C
D E D E
H(C2) L(00) H(C2) L(00)
SP SP
PC PC

FFFF FFFF

C200 50 C200 50
C001 C201

0000 0000

IX. XRI data  XRI 2FH where 2FH is the 8-bit data. This instruction does Exclusive-OR of
immediate data with accumulator.

Before execution After execution

A=75 S Z AC P CY A=5A 0 0 00 0 1 0 0
B C B C
D E D E
H L H L
SP SP
PC PC
X. CMA  CMA where A is the Source Register. This instruction complements the
accumulator value and the result is placed in the accumulator.

Before execution After execution

A=AA S Z AC P CY A=55 0 0 00 0 0 0 0
B C B C
D E D E
H L H L
SP SP
PC PC

XI. CMC: This instruction complements the carry flag. If carry flag is set, the instruction will
reset it and carry flag is reset, the instruction will set it. Only the carry flag is
complemented. No other flags are modified.

XII. STC: This instruction sets the carry flag. It does not consider previous carry flag status.
Only sets the carry flag. Only the carry flag is set and no other flags are changed.

XIII. CMP R  CMP B where Accumulator value A is compared with B register value. The
operation of comparing is performed by subtracting register from accumulator. The
contents of register or accumulator are not changed.
The result of comparison by setting flags as follows:
If accumulator > register B: CY is set and Zero Flag is Reset.
If accumulator < register B: Zero Flag is set
If accumulator = register B: CY is set.

Before execution After execution

A=20H S Z AC P CY A=20H 0 0 0 0 0 0 0 0
B=10H C B=10H C
D E D E
H L H L
SP SP
PC PC
XIV. CMP M: This instruction compares the memory content with the accumulator. The
address of the memory location is given by HL register pair. The operation is performed
in same way as CMP R instruction. Contents of accumulator and contents of memory
location are not changed.

XV. CPI Data: This instruction compares the immediate data with the accumulator similar to
that of CMP R and the result is indicated by Z and CY flags. The accumulator contents
are not altered.

XVI. RLC: RLC refers to Rotate Accumulator Left. This instruction rotates the content of
accumulator left by 1-bit which implies it shifts the bits left by single position. D0 will be
transferred to D1 and D2 to D3 and so on. The D7 result is transferred to CY flag and Do.
This can be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example: MVI A, 1F

RLC

Before Execution

CY

0 0 0 1 1 1 1 1
After Execution

0 0 1 1 1 1 1 0

XVII. RRC: RRC refers to Rotate Accumulator Right. This instruction rotates the content of
accumulator right by 1-bit which implies it shifts the bits right by single position. D7 will
be transferred to D6 and D6 to D5 and so on. The D0 result is transferred to CY flag and
D7. This can be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example:

MVI A, 1C
RRC

Before Execution

CY

0 0 0 1 1 1 0 0
After Execution

0 0 0 0 1 1 1 0

XVIII. RAL: RAL refers to Rotate Accumulator Left through Carry. This instruction rotates the
content of accumulator left by 1-bit. D0 will be transferred to D1 and D1 to D2 and so on.
The D7 result is transferred to CY flag and CY flag result is transferred to D0. This can
be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example:

MVI A, 1E
RAL

Before Execution

CY=1

0 0 0 1 1 1 1 0

After Execution

0 0 1 1 1 1 0 1
XIX. RAR: RAR refers to Rotate Accumulator Right through Carry. This instruction rotates the
content of accumulator right by 1-bit. D7 will be transferred to D6 and D6 to D5 and so
on. The D0 result is transferred to CY flag and CY flag result is transferred to D7. This
can be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example:

MVI A, 0E
RAR

Before Execution

CY=1

0 0 0 0 1 1 1 0

After Execution

1 0 0 0 0 1 1 1