Computer Architecture

Building a Modern Computer From First Principles

www.nand2tetris.org

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 1
Von Neumann machine (circa 1940)

CPU
Input
device
Memory Arithmetic Logic
Unit (ALU)

(data
+ Registers
instructions)
Output
Control device

Stored
program
concept!

John Von Neumann (and others) ... made it possible Andy Grove (and others) ... made it small and fast.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 2
Processing logic: the instruction cycle

CPU
Input
device
Memory Arithmetic Logic
Unit (ALU)

(data
+ Registers
instructions)
Output
Control device

Executing the current instruction involves one or more of

the following micro-tasks:
Fetch the next instruction
Decode the instruction
Read source operands
Perform ALU operation
Store the result

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 3
The Hack computer
A 16-bit Von Neumann platform
The instruction memory and the data memory are physically separate
Screen: 512 columns by 256 rows, black and white
Keyboard: standard
Designed to execute programs written in the Hack machine language
Can be easily built from the chip-set that we built so far in the course

Main parts of the Hack computer:

Instruction memory (ROM)
Memory (RAM):
• Data memory
• Screen (memory map)
• Keyboard (memory map)
CPU
Computer (the logic that holds everything together).

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 4
Memory: conceptual / programmer’s view

Memory

Data

Screen
memory
map
Screen
Keyboard map

Keyboard

Using the memory:

To record or recall values (e.g. variables, objects, arrays), use the first 16K words of
the memory
To write to the screen (or read the screen), use the next 8K words of the memory
To read which key is currently pressed, use the next word of the memory.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 5
Memory: physical implementation
load The Memory chip is essentially a
Memory package that integrates the three chip-
parts RAM16K, Screen, and Keyboard
0 into a single, contiguous address space.
in
This packaging effects the
RAM16K
16 programmer’s view of the memory, as
(16K mem. chip) out well as the necessary I/O side-effects.

16383 16

address 16384 Screen

(8K mem. chip)
15
24575 Screen
Keyboard
24576 (one register)

Keyboard

Access logic:
Access to any address from 0 to 16,383 results in accessing the RAM16K chip-part
Access to any address from 16,384 to 24,575 results in accessing the Screen chip-part
Access to address 24,576 results in accessing the keyboard chip-part
Access to any other address is invalid.

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 6
CPU

from
data memory inM
16 outM
16
to data
writeM

CPU
from memory
instruction instruction 1
memory 16 addressM
15
pc to instruction
reset memory
a Hack machine language 15
instruction like M=D+M, 1

stated as a 16-bit value

CPU internal components (invisible in this chip diagram): ALU and 3 registers: A, D, PC

CPU fetch logic:

Recall that:
1. the instruction may include a jump directive (expressed as non-zero jump bits)
2. the ALU emits two control bits, indicating if the ALU output is zero or less than zero
If reset==0: the CPU uses this information (the jump bits and the ALU control bits) as follows:
If there should be a jump, the PC is set to the value of A; else, PC is set to PC+1
If reset==1: the PC is set to 0. (restarting the computer)

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 7
The C-instruction revisited

dest = comp; jump comp dest jump

binary: 1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 8
CPU implementation dest = comp; jump comp dest jump

binary: 1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
Chip diagram:
Includes most of the
ALU output
CPU’s execution logic
The CPU’s control logic is
hinted: each circled “c” C
C C

represents one or more

control bits, taken from D
D
the instruction C C
decode
outM
The “decode”

ALU
C
bar does not A

Mux
A
represent a instruction A/M
C

chip, but

Mux
rather indicates M
that the inM
C writeM
instruction bits
A
are decoded addressM
somehow. C
reset

A
PC pc

Cycle: Execute logic: Fetch logic: Resetting the computer:

Execute Decode If there should be a jump, Set reset to 1,
set PC to A then set it to 0.
Fetch Execute
else set PC to PC+1
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 9
Perspective: from here to a “real” computer

Pipelining

Caching

More I/O units

Special-purpose processors (I/O, graphics, communications, …)

Multi-core / parallelism; GPUs

Efficiency

Energy consumption considerations

And more ...

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 10
Perspective: some issues we haven’t discussed (among many)

CISC / RISC (hardware / software trade-off)

Hardware diversity: desktop, laptop, mobile, game machines, …

General-purpose vs. embedded computers

Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 5: Computer Architecture slide 11