MT7621 ProgrammingGuide Preliminary Platform
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sanshian666MT7621 ProgrammingGuide Preliminary Platform
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t.c EN
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MT7621
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PROGRAMMING
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GUIDE
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[email protected],time=2015-12-30 10:58:32,ip=119.139.225.28,doctitle=MT7621_ProgrammingGuide_Preliminary_Platform.pdf,company=B-LINK_WCN
MT7621 PROGRAMMING GUIDE
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MT7621 Overview
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The MT7621 SoC includes a high performance 880 MHz MIPS1004Kc CPU core and high speed
ON
USB3.0/PCIe/SDXC interfaces, which is designed to enable a multitude of high performance, cost-effective IEEE
802.11n/ac applications with a MediaTek (Ralink) WiFi client card.
n U TI
Functional Block Diagram
EJTAG 16-Bit DDR2/DDR3 To CPU
t.c EN
INTC interrupts
MIPS 1004Kc DRAM Timer
32/32 KB I/D- Controller
SPI SPI
Cache per Core OCP_IF
(880 MHz) OCP Bridge Arbiter NFI NAND
.ne ID
UARTLx3 UART
PBUS
RBUS GPIO
GPIO
/LED
I2C I2C
ink NF
PBUS
USB 3.0/2.0 PCIe 1.1 Crypto Switch GDMA/ I2S I2S
SDXC
PHY PHY Engine (5GE) HSDMA
PCM x4 PCM
5-Port EPHY RGMII SPDIF SPDIF
SD Host PCIe x 3
RJ45 x5 TMII/MII x1
b-l CO
Figure 1-1 MT7621 Block Diagram
There are several masters (MIPS 1004KEc, USB, PCI Express, SDXC, FE) in the MT7621 SoC on a high
18 TEK
performance, low latency Rbus, (Ralink Bus). In addition, the MT7621 SoC supports lower speed peripherals
such as UART Lite, GPIO, NFI and SPI via a low speed peripheral bus (Pbus). The DDR2/DDR3 controller is the
only bus slave on the Rbus. It includes an Advanced Memory Scheduler to arbitrate the requests from bus
masters, enhancing the performance of memory access intensive tasks.
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MT7621 PROGRAMMING GUIDE
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Table of Contents
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MT7621 OVERVIEW 2
FUNCTIONAL BLOCK DIAGRAM 2
TABLE OF CONTENTS 3
n U TI
1. MIPS 1004KC PROCESSOR 5
1.1 FEATURES 5
1.2 MEMORY MAP SUMMARY 7
1.3 INTERUPT TABLE SUMMARY 9
t.c EN
2. REGISTERS 11
2.1 NOMENCLATURE 11
2.2 SYSTEM CONTROL 12
.ne ID
2.2.1 FEATURES 12
2.2.2 BLOCK DIAGRAM 12
2.2.3 REGISTERS 13
2.3 TIMER 41
ink NF
2.3.1 FEATURES 41
2.3.2 BLOCK DIAGRAM 42
2.3.3 REGISTERS 43
2.4 SYSTEM TICK COUNTER 48
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2.4.1 REGISTERS 48
2.5 UART LITE 50
2.5.1 FEATURES 50
2.5.2 REGISTERS 51
2.6 PROGRAMMABLE I/O 65
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2.6.1 FEATURES 65
2.6.2 BLOCK DIAGRAM 65
2.6.3 GPIO PIN MAPPING 65
2.6.4 REGISTERS 67
2
2.7 I C CONTROLLER 79
2.7.1 FEATURES 79
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2.7.2 LIST OF REGISTERS 80
RD A
2.8 NAND FLASH INTERFACE 87
2.8.1 FEATURES 87
R DI
2.8.2 REGISTERS 88
2.8.3 PROGRAMMING GUIDE 106
2.9 NFI ECC CONTROLLER 115
FO ME
2.9.1 FEATURES 115
2.9.2 REGISTERS 116
2.9.3 PROGRAMMING GUIDE 130
2.10 PCM CONTROLLER 134
2.10.1 FEATURES 134
2.10.2 BLOCK DIAGRAM 134
2.10.3 LIST OF REGISTERS 136
2.10.4 PCM CONFIGURATION 152
2.11 GENERIC DMA CONTROLLER 154
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MT7621 PROGRAMMING GUIDE
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2.11.1 FEATURES 154
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2.11.2 BLOCK DIAGRAM 154
ON
2.11.3 PERIPHERAL CHANNEL CONNECTION 155
2.11.4 REGISTERS 156
2.12 SPI CONTROLLER 202
n U TI
2.12.1 FEATURES 202
2.12.2 BLOCK DIAGRAM 202
2.12.3 REGISTERS 203
2.13 I2S CONTROLLER 213
t.c EN
2.13.1 FEATURES 213
2.13.2 BLOCK DIAGRAM 213
2.13.3 REGISTERS 215
2.14 SPDIF TX 220
.ne ID
2.14.1 REGISTERS 221
2.15 MEMORY CONTROLLER 235
2.15.1 FEATURES 235
ink NF
2.15.2 REGISTERS 236
2.16 RBUS MATRIX AND QOS ARBITER 319
2.16.1 FEATURES 319
2.16.2 BLOCK DIAGRAM 319
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2.16.3 REGISTERS OF QOS CONTROL 320
2.16.4 REGISTERS OF RBUS MATRIX 325
2.17 EXTERNAL MC ARBITER 329
2.17.1 REGISTERS 330
2.18 ANALOG MACRO CONTROL 333
2.18.1 REGISTERS 334
18 TEK
3. LIST 346
4. REVISION HISTORY 349
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MT7621 PROGRAMMING GUIDE
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1. MIPS 1004Kc Processor
ON
1.1 Features
8-9-stage pipeline
32-bit Address Paths
n U TI
64-bit Data Paths to Caches
MIPS32 Enhanced Architecture (Release 2) Features
– Standardized Instruction Set Architecture
– Vectored interrupts and support for an external interrupt controller
t.c EN
– Programmable exception vector base
– Atomic interrupt enable/disable
– Bit field manipulation instructions
MIPS16e Application Specific Extension
– 16 bit encodings of 32-bit instructions to improve code density
.ne ID
– Special PC-relative instructions for efficient loading of addresses and constants
– Data type conversion instructions (ZEB, SEB, ZEH, SEH)
– Compact jumps (JRC, JALRC)
– Stack frame set-up and tear down “macro” instructions (SAVE and RESTORE)
ink NF
MIPS MT Application Specific Extension (ASE)
– Support for 2 Virtual Processing Elements (VPEs) per CORE
– One Thread Context (TC) per VPE
Programmable L1 Cache Sizes
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– Individually configurable instruction and data caches
– 32KB I/D cache
– 4-way set associative
– Up to 9 non-blocking loads
– Data cache supports coherent and non-coherent Write-back with write-allocation
– 32-byte cache line size, doubleword sectored - suitable for standard single-port SRAM
–
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Cache line locking support
– Non-blocking prefetches
– Duplicate tag array in D-cache allows coherence requests to access the cache in parallel with normal
load/store traffic
Standard Memory Management Unit
– 32 dual-entry MIPS32-style JTLB per VPE with variable page sizes
– JTLBs are sharable under software control
@
– 4-5 entry instruction TLB
RD A
– 8-entry data TLB
OCP Bus Interface Unit (BIU)
R DI
– 32b address and 64b data
– Supports bursts of 4x64b
– 8 entry write buffer - handles eviction data, intervention response, uncached, and uncached
accelerated store data
FO ME
– Simple Byte enable mode allows easier bridging to other bus standards
– Extensions for management of front side L2 cache
– Intervention port supports memory coherency for use in a 1004K Coherent Processing System
Multiply-Divide Unit
– Maximum issue rate of one 32x32 multiply per clock
– Early-in divide control. Minimum 11, maximum 34 clock latency on divide
Power Control
– No minimum frequency
– Support for software-controlled clock divider
– Support for extensive use of fine-grain clock gating
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MT7621 PROGRAMMING GUIDE
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EJTAG Debug Support
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– Start, stop, and single stepping control
–
ON
Software breakpoints via the SDBBP instruction
– Optional hardware breakpoints on virtual addresses; 0, 2, or 4 instruction and 0,1, or 2 data
breakpoints per VPE
SOC-it L2 Cache Controller
n U TI
– 7-stage pipeline. (Optional 8th stage for pipelined memory arrays.)
– 32-bit address paths, 256-bit internal data paths
– 8-way set associativity
– Cache size: 256KB
t.c EN
– Line Size: 32 bytes (4 doublewords)
.ne ID
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18 TEK
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1004K CPU Block Diagram
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MT7621 PROGRAMMING GUIDE
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1.2 Memory Map Summary
ON
Start End Size Description
0 1BFFFFFF 448M DRAM Direct Map
n U TI
1C000000 1DFFFFFF 32M <<Reserved>>
1E000000 1E0000FF 256 SYSCTL
1E000100 1E0001FF 256 TIMER
t.c EN
1E000200 1E0002FF 256 INTCTL
1E000300 1E0003FF 256 Flash Controller (NOR/SRAM/SDRAM)
1E000400 1E0004FF 256 Rbus Matrix CTRL
1E000500 1E0005FF 256 MIPS CNT
1E000600 1E0006FF 256 GPIO
.ne ID
1E000700 1E0007FF 256 S/PDIF
1E000800 1E0008FF 256 DMA_CFG_ARB
1E000900 1E0009FF 256 I2C
ink NF
1E000A00 1E000AFF 256 I2S
1E000B00 1E000BFF 256 SPI CSR
1E000C00 1E000CFF 256 UARTLITE 1
1E000D00 1E000DFF 256 UARTLITE 2
b-l CO
1E000E00 1E000EFF 256 UARTLITE 3
1E000F00 1E000FFF 256 ANACTL
1E001000 1E0017FF 2K <<Reserved>>
1E001800 1E001FFF 2K <<Reserved>>
1E002000 1E0027FF 2K PCM (up to 16 channel)
18 TEK
1E002800 1E002FFF 2K Generic DMA (up to 64 channel)
1E003000 1E0037FF 2K NAND Controller *(actually 1K in Module)
1E003800 1E003FFF 2K NAND_ECC Controller *(actually 3K in module)
1E004000 1E004FFF 4K Crypto Engine
1E005000 1E005FFF 4K MEM_CTRL (DDRII/DDRIII)
1E006000 1E006FFF 4K EXT_MC_ARB
@
1E007000 1E007FFF 4K HS DMA
RD A
1E008000 1E00FFFF 32K <<Reserved>>
1E010000 1E0FFFFF 960K <<Reserved>>
R DI
1E100000 1E10DFFF 56K Frame Engine (FE SRAM: 0x1E108000~0x1E10DFFF)
1E10E000 1E10FFFF 8K PCIe SRAM
1E110000 1E117FFF 32K Ethernet GMAC
FO ME
1E118000 1E11FFFF 32K ROM
1E120000 1E12FFFF 64K <<Reserved>>
1E130000 1E137FFF 32K SDXC
1E138000 1E13FFFF 32K <<Reserved>>
1E140000 1E17FFFF 256K PCI Express
1E180000 1E1BFFFF 256K <<Reserved>>
1E1C0000 1E1FFFFF 256K USB Host (U2+U3)
1E200000 1E23FFFF 256K <<Reserved>>
1E240000 1E24FFFF 64K <<Reserved>>
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MT7621 PROGRAMMING GUIDE
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1E250000 1E7FFFFF 5824K <<Reserved>>
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1E800000 1EBFFFFF 4M PCIE Direct Access for iNIC
ON
1EC00000 1FBBFFFF 16128K <<Reserved>>
1FBC0000 1FBDFFFF 128 CM_GIC
1FBE0000 1FBEFFFF 64K <<Reserved>>
n U TI
1FBF0000 1FBF7FFF 32K CM_CPC
1FBF8000 1FBFFFFF 32K CM_GCR
1FC00000 1FFFFFFF 4M ROM/SPI FLASH Direct Access
t.c EN
20000000 23FFFFFF 64M DRAM Re-Map
24000000 5FFFFFFF 960M <<Reserved>>
60000000 6FFFFFFF 256M PCIE Direct Access
70000000 7FFFFFFF 256M <<Reserved>>
.ne ID
ink NF
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18 TEK
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MT7621 PROGRAMMING GUIDE
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1.3 Interupt Table Summary
ON
MIPS1004Kc
n U TI
GIC Pin5 GIC
All the system
GIC
(Local) Pin4 GIC
(Local)
interrupts are
GIC
(Local) Pin3 GIC
(Local)
n GIC GIC
(Local) Pin2 (Local)
connected to VPE0
t.c EN
here. (Shared) (Local) Pin1
(GIC INT0~63)
Pin0
SI_FDCInt, SI_PCInt, SI_TimerInt, SI_SWInt[1:0]
.ne ID
ink NF MT7621 Interrupt architecture
b-l CO
18 TEK
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MT7621 PROGRAMMING GUIDE
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ON
n U TI
t.c EN
.ne ID
ink NF
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18 TEK
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RD A
PS: the empty part means reserved.
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MT7621 PROGRAMMING GUIDE
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2. Registers
ON
2.1 Nomenclature
The following nomenclature is used for register types:
n U TI
RO Read Only
WO Write Only
RW Read or Write
RC Read Clear
t.c EN
W1C Write One Clear
- Reserved bit
X Undefined binary value
.ne ID
ink NF
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18 TEK
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MT7621 PROGRAMMING GUIDE
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2.2 System Control
ON
2.2.1 Features
Provides read-only chip revision registers
Provides a window to access boot-strapping signals
n U TI
Supports memory remapping configurations
Supports software reset to each platform building block
Provides registers to determine GPIO and other peripheral pin muxing schemes
t.c EN
Provides some power-on-reset only test registers for software programmers
Combines miscellaneous registers (such as clock skew control, status register, memo registers, etc)
2.2.2 Block Diagram
.ne ID
System Control Block
Memory Remapping
CPU Rbus Wrapper
ink NF
Boot Strapping Signals
GPIO Pin Muxing Scheme
Pin Muxing Block
System Control
Registers Per Block S/W Reset
Platform Blocks
b-l CO
Cache Hit/Miss Strobes
Miscellaneous Registers
PCIe, PCM, ...
To/From MIPS
PalmBus Interface
18 TEK
Figure 2-1 System Control Block Diagram
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MT7621 PROGRAMMING GUIDE
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SE AL
2.2.3 Registers
ON
SYSCTL Changes LOG
Revision Date Author Change Log
0.1 2012/7/11 James Hu Initialization
n U TI
Module name: SYSCTL Base address: (+1E000000h)
t.c EN
Address Name Widt Register Function
h
1E000000 CHIPID0_3 32 CHIP ID ASCII Character 0-3
.ne ID
1E000004 CHIPID4_7 32 CHIP ID ASCII Character 4-7
1E00000C CHIP_REV_ID 32 Chip Revision Identification
1E000010 SYSCFG 32 System Configuration Register
1E000014 SYSCFG1 32 System Configuration Register 1
ink NF
1E000018 TESTSTAT 32 Firmware Test Status
1E00001C TESTSTAT2 32 Firmware Test Status 2
1E000020 BOOT_SRAM_BA 32 Boot from SRAM base Address
SE
b-l CO
1E000024 BOOT_RELEASE 32 Release CPU's reset to let CPU boot in boot from SRAM mode
1E00002C CLKCFG0 32 Clock Configuration Register 0
1E000030 CLKCFG1 32 Clock Configuration Register 1
1E000034 RSTCTL 32 Reset Control Register
1E000038 RSTSTAT 32 Reset Status Register
18 TEK
1E00003C MISR_GOLDEN 32 ROM BIST MISR Golden Value
1E000040 MISR_RESULT 32 ROM BIST MISR Result Value
1E000044 CUR_CLK_STS 32 Current clock status
1E000048 PAD_UART1_GPI 32 PAD configuration of UART1 and GPIO0 groups
O0_CFG
1E00004C PAD_UART3_I2C_ 32 PAD configuration of UART3 and I2C groups
@
CFG
RD A
1E000050 PAD_UART2_JTA 32 PAD configuration of UART2 and JTAG groups
G_CFG
1E000054 PAD_PERST_WDT 32 PAD configuration of PICe RST and WDT RST groups
R DI
_CFG
1E000058 PAD_RGMII2_MDI 32 PAD configuration of RGMII2 and MDIO RST groups
O_CFG
1E00005C PAD_SDXC_SPI_C 32 PAD configuration of SDXC and SPI RST groups
FO ME
FG
1E000060 GPIO_MODE 32 GPIO purpose selection
1E000068 MEMO1 32 Memory1
1E00006C MEMO2 32 Memory2
1E000070 PAD_BOPT_ESWI 32 PAD configuration of Bonding OPT and ESW INT groups
NT_CFG
1E000074 PAD_RGMII1_CFG 32 PAD configuration of RGMII1 group
1E000078 CPE_ROSC_SEL0 32
1E00007C CPE_ROSC_SEL1 32
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MT7621 PROGRAMMING GUIDE
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1E000080 CPU_CPE_CNT0 32 CPU CPE counter 0
SE AL
1E000084 CPU_CPE_CNT1 32 CPU CPE counter 1
ON
1E000088 CPU_CFG 32 CPU configuration
1E00008C CPU_MEM_CFG 32 CPU memory delay, power down and sleep control
1E000090 FMTR_CFG0 32 Frequency meter configuration 0
n U TI
1E000094 FMTR_CNT_MAX 32 Frequency meter count maximum
1E000098 FMTR_CNT_MIN 32 Frequency meter count minimum
1E00009C FMTR_CNT_VAL 32 Frequency meter counter value
t.c EN
1E000000 CHIPID0_3 CHIP ID ASCII Character 0-3 3637544
D
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CHIP_ID3 CHIP_ID2
Type RO RO
Reset 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name CHIP_ID1 CHIP_ID0
Type RO RO
Reset 0 1 0 1 0 1 0 0 0 1 0 0 1 1 0 1
Bit(s) Name Description
b-l CO
31:24 CHIP_ID3 ASCII CHIP Name Identification Character 3
23:16 CHIP_ID2 ASCII CHIP Name Identification Character 2
15:8 CHIP_ID1 ASCII CHIP Name Identification Character 1
7:0 CHIP_ID0 ASCII CHIP Name Identification Character 0
18 TEK
1E000004 CHIPID4_7 CHIP ID ASCII Character 4-7 2020313
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CHIP_ID7 CHIP_ID6
Type RO RO
@
Reset 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
RD A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CHIP_ID5 CHIP_ID4
Type RO RO
R DI
Reset 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0
Bit(s) Name Description
31:24 CHIP_ID7 ASCII CHIP Name Identification Character 3
FO ME
23:16 CHIP_ID6 ASCII CHIP Name Identification Character 2
15:8 CHIP_ID5 ASCII CHIP Name Identification Character 1
7:0 CHIP_ID4 ASCII CHIP Name Identification Character 0
1E00000C CHIP_REV_ID Chip Revision Identification 0002010
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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MT7621 PROGRAMMING GUIDE
L Y
Name DU
PK
SE AL
MM
G_I
Y_I
ON
D
D
Type RO RO
Reset 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name VER_ID ECO_ID
Type RO RO
Reset 0 0 0 1 0 0 0 1
t.c EN
Bit(s) Name Description
17 DUMMY_ID DUMMY ID
1: Reserved
0: Reserved
16 PKG_ID Package ID
.ne ID
1: A
0: N
11:8 VER_ID Chip Version ID
3:0 ECO_ID Chip ECO ID
ink NF
1E000010 SYSCFG System Configuration Register 0000000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TEST_CODE BS_SHADOW[9:4]
Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DR
OC DR
18 TEK
AM
XTAL_MODE_SE P_R AM
BS_SHADOW[3:0] _FR CHIP_MODE
L ATI _TY
OM
O PE
_EE
Type RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
31:24 TEST_CODE Default value is from bootstrap and can be modified by software.
RD A
21:12 BS_SHADOW BS shadow register for last boot-up value
Displays a backup copy of the last bootup value
R DI
9 DRAM_FROM_EE DRAM configuration source
1: Auto detection
0: from EEPROM
8:6 XTAL_MODE_SEL XTAL mode selection
FO ME
0: 20 MHz, Self Oscillation mode
1: 20 MHz, Single end input
2: 20 MHz, differential input
3: 40 MHz, Self Oscillation mode
4: 40 MHz, Single end input
5: 40 MHz, differential input
6: 25 MHz, Self Oscillation mode
7: 25 MHz, Single end input
5 OCP_RATIO 0: 1/3
1: 1/4
4 DRAM_TYPE DDR type
1: DDR2
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MT7621 PROGRAMMING GUIDE
L Y
0: DDR3
SE AL
3:0 CHIP_MODE A vector to set chip function/test/debug modes in non-test/debug operation.
ON
For more information see the Bootstrapping Pins Description in the datasheet for this
chip.
n U TI
1E000014 SYSCFG1 System Configuration Register 1 0000C10
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI
CP
U_
.ne ID
E_R
GE2_MOD GE1_MOD CT
C_
E E RL_
MO
UTI
DE
F
Type RW RW RW RW
ink NF
Reset 1 1 0 0 1 0
Bit(s) Name Description
15:14 GE2_MODE Gigabit Port #2 Mode
b-l CO
Sets the interface mode on Gigabit port 2
3: RJ-45 Mode
2: Reverse MII Mode (10/100 Mbps)
1: MII Mode (10/100 Mbps)
0: RGMII Mode (10/100/1000 Mbps)
13:12 GE1_MODE Gigabit Port #1 Mode
Sets the interface mode on Gigabit port 1.
18 TEK
0: RGMII Mode (10/100/1000 Mbps)
1: MII Mode (10/100 Mbps)
2: Reverse MII Mode (10/100 Mbps)
31: Reserved
8 PCIE_RC_MODE PCIe Mode
1: Root Complex mode
0: End Point mode
@
4 CPU_CTRL_UTIF CPU control and monitor UTIF interface enable
RD A
1: Enable
0: Disable
R DI
1E000018 TESTSTAT Firmware Test Status 0000000
0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TESTSTAT[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TESTSTAT[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 TESTSTAT Firmware Test Status register
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MT7621 PROGRAMMING GUIDE
L Y
NOTE: This register is reset only by a power-on reset.
SE AL
ON
1E00001C TESTSTAT2 Firmware Test Status 2 0000000
0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TESTSTAT2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TESTSTAT2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:0 TESTSTAT2 Firmware Test Status Register 2
NOTE: This register is reset only by a power-on reset.
ink NF
1E000020 BOOT_SRAM Boot from SRAM base Address 1E18000
_BASE 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name BOOTSRAMBASE[31:16]
Type RW
Reset 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BOOTSRAMBASE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 BOOTSRAMBASE Boot from SRAM base address (Test mode only)
Addr_tuned =
bootsram[31:0] | oc_maddr[15:0]
@
RD A
1E000024 BOOT_RELEA Release CPU's reset to let CPU boot in boot from 0000000
SE SRAM mode 0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BO
OT_
RE
LE
AS
E
Type RW
Reset 0
Bit(s) Name Description
PGMT7621_V.1.0_130607 Page 17 of 349
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MT7621 PROGRAMMING GUIDE
L Y
0 BOOT_RELEASE Release CPU's command to access DRAM or CR.
SE AL
1: Release CPU command
0: Block CPU command
ON
1E000028 RESERVED_C Reserved CR1 0000000
n U TI
R 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED_CR1[31:16]
t.c EN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RESERVED_CR1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
ink NF
1E00002C CLKCFG0 Clock Configuration Register 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name RE
MP
PCI FCL
LL_
CPU_CLK_ E_C K_F
OSC_1US_DIV CF REFCLK_FDIV
SEL LK_ FR
G_
SEL AC[
SEL
4:4]
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PE
RI_
TRGMII_C
REFCLK_FFRAC[3:0] REFCLK0_RATE CL
LK_SEL
K_S
EL
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0
@
RD A
Bit(s) Name Description
31:30 CPU_CLK_SEL CPU clock selection.
R DI
CPU PLL is programmable.
3: XTAL clock
2: XTAL clock
1: CPU PLL
FO ME
0: 500MHz
29:24 OSC_1US_DIV Oscillator 1 usec Divider
Sets the maximum for the reference clock counter for either a 20 MHz or 40 MHz
external XTAL input. The count increments each 1usec (indicating 1 MHz), up to the
maximum, before resetting to zero. This counts the frequency of an external XTAL.
This count is used to output a 32 KHz frequency to the REFCLK0 pin.
0: Automatically generates a 1 usec system tick regardless of whether XTAL frequency
is 20 MHz or 40 MHz.
39: Default value for an external 40 MHz XTAL.
19: Default value for an external 20 MHz XTAL.
Others: Manual mode for tick generation.
23 MPLL_CFG_SEL MEMPLL parameter configuration selection
PGMT7621_V.1.0_130607 Page 18 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: from CR configuration
0: follow XTAL frequncy boot strapping
SE AL
22:18 REFCLK_FDIV Internal Clock Frequency Divider
ON
The frequency divider used to generate the Fraction-N clock frequency.
Valid values range from 1 to 31.
Fraction-N clock frequency = (INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
17 PCIE_CLK_SEL PCIe clock selection.
n U TI
1: from GPLL 125MHz
0: from PCIe PHY
16:12 REFCLK_FFRAC Internal Clock Fraction-N Frequency
A parameter used in conjunction with INT_CLK_FDIV to generate the Fraction-N clock
t.c EN
frequency.
Valid values range from 0 to 31.
Fraction-N clock Frequency = (INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
11:9 REFCLK0_RATE Output clock rate of reference Clock 0
7: CPU clock/8
.ne ID
6: Reserved
5: Internal Fraction-N_CLK/2
4: Internal Fraction-N_CLK/4
3: Reserved
2: 25 MHz
ink NF
1: 12.5 MHz
0: Xtal clock(20/25/40 MHz by boot strap)
6:5 TRGMII_CLK_SEL TRGMII Tx clock selection
2: APLL
1: DDR PLL to DRAMC
b-l CO
0: 250MHz
4 PERI_CLK_SEL Peripheral Clock Source Select
1: XTAL input
0: 50 MHz from EPLL
18 TEK
1E000030 CLKCFG1 Clock Configuration Register 1 67BFEF
E0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CR
SH PCI PCI PCI ET UA UA UA
YPT SPI I2S I2C
XC_ E2_ E1_ E0_ H_ RT3 RT2 RT1
O_ _CL _CL _CL
CL CL CL CL CL _CL _CL _CL
CL K_E K_E K_E
@
K_E K_E K_E K_E K_E K_E K_E K_E
K_E N N N
RD A
N N N N N N N N
N
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NA GD PC TIM
SP HS
PIO MC INT DIF FE_ DM
ND MA M_ ER_
_CL _CL _CL TX_ CL A_
_CL _CL CL CL
K_E K_E K_E CL K_E CL
FO ME
K_E K_E K_E K_E
N N N K_E N K_E
N N N N
N N
Type RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
30 SHXC_CLK_EN SHXC clock control
1: Clock Enable
0: Clock Disable
29 CRYPTO_CLK_EN AUX system tick counter clock control
1: Clock Enable
PGMT7621_V.1.0_130607 Page 19 of 349
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MT7621 PROGRAMMING GUIDE
L Y
0: Clock Disable
SE AL
26 PCIE2_CLK_EN PCIE2 clock control
ON
1: Clock Enable
0: Clock Disable
25 PCIE1_CLK_EN PCIE1 clock control
1: Clock Enable
0: Clock Disable
n U TI
24 PCIE0_CLK_EN PCIE0 clock control
1: Clock Enable
0: Clock Disable
t.c EN
23 ETH_CLK_EN ETH clock control
1: Clock Enable
0: Clock Disable
21 UART3_CLK_EN UART3 clock control
1: Clock Enable
.ne ID
0: Clock Disable
20 UART2_CLK_EN UART2 clock control
1: Clock Enable
0: Clock Disable
ink NF
19 UART1_CLK_EN UART1 clock control
1: Clock Enable
0: Clock Disable
18 SPI_CLK_EN SPI clock control
1: Clock Enable
b-l CO
0: Clock Disable
17 I2S_CLK_EN I2S clock control
1: Clock Enable
0: Clock Disable
16 I2C_CLK_EN I2C clock control
1: Clock Enable
0: Clock Disable
18 TEK
15 NAND_CLK_EN NAND clock control
1: Clock Enable
0: Clock Disable
14 GDMA_CLK_EN GDMA clock control
1: Clock Enable
0: Clock Disable
@
13 PIO_CLK_EN PIO clock control
RD A
1: Clock Enable
0: Clock Disable
11 PCM_CLK_EN PCM clock control
R DI
1: Clock Enable
0: Clock Disable
10 MC_CLK_EN MC clock control
1: Clock Enable
FO ME
0: Clock Disable
9 INT_CLK_EN INT clock control
1: Clock Enable
0: Clock Disable
8 TIMER_CLK_EN TIMER clock control
1: Clock Enable
0: Clock Disable
7 SPDIFTX_CLK_EN SPDIFTX clock control
1: Clock Enable
0: Clock Disable
6 FE_CLK_EN FE clock control
PGMT7621_V.1.0_130607 Page 20 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: Clock Enable
0: Clock Disable
SE AL
5 HSDMA_CLK_EN HSDMA clock control
ON
1: Clock Enable
0: Clock Disable
n U TI
1E000034 RSTCTL Reset Control Register 0000000
0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name AU
CR
SD X_S PCI PCI PCI ET UA UA UA
PP YPT SPI I2S I2C
XC_ TC E2_ E1_ E0_ H_ RT3 RT2 RT1
E_R O_ _RS _RS _RS
RS K_ RS RS RS RS _RS _RS _RS
ST RS T T T
T RS T T T T T T T
T
.ne ID
T
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SP HS
ink NF
GD PC TIM
NFI PIO MC INT DIF FE_ DM MC SY
MA M_ ER_
_RS _RS _RS _RS TX_ RS A_ M_ S_R
_RS RS RS
T T T T RS T RS RST ST
T T T
T T
Type RW RW RW RW RW RW RW RW RW RW RW
W1
C
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 PPE_RST PPE reset control
1: Reset Assert
0: Reset Deassert
18 TEK
30 SDXC_RST SHXC reset control
1: Reset Assert
0: Reset Deassert
29 CRYPTO_RST Crypto engine reset control
1: Reset Assert
0: Reset Deassert
@
28 AUX_STCK_RST AUX system tick counter clock control
RD A
1: Reset Assert
0: Reset Deassert
26 PCIE2_RST PCIE2 reset control
R DI
1: Reset Assert
0: Reset Deassert
25 PCIE1_RST PCIE1 reset control
1: Reset Assert
FO ME
0: Reset Deassert
24 PCIE0_RST PCIE0 reset control
1: Reset Assert
0: Reset Deassert
23 ETH_RST ETH reset control
1: Reset Assert
0: Reset Deassert
21 UART3_RST UART3 reset control
1: Reset Assert
0: Reset Deassert
20 UART2_RST UART2 reset control
PGMT7621_V.1.0_130607 Page 21 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: Reset Assert
0: Reset Deassert
SE AL
19 UART1_RST UART1 reset control
ON
1: Reset Assert
0: Reset Deassert
18 SPI_RST SPI reset control
n U TI
1: Reset Assert
0: Reset Deassert
17 I2S_RST I2S reset control
1: Reset Assert
0: Reset Deassert
t.c EN
16 I2C_RST I2C reset control
1: Reset Assert
0: Reset Deassert
15 NFI_RST NFI reset control
.ne ID
1: Reset Assert
0: Reset Deassert
14 GDMA_RST GDMA reset control
1: Reset Assert
0: Reset Deassert
ink NF
13 PIO_RST PIO reset control
1: Reset Assert
0: Reset Deassert
11 PCM_RST PCM reset control
b-l CO
1: Reset Assert
0: Reset Deassert
10 MC_RST MC reset control
1: Reset Assert
0: Reset Deassert
9 INT_RST INT reset control
1: Reset Assert
18 TEK
0: Reset Deassert
8 TIMER_RST TIMER reset control
1: Reset Assert
0: Reset Deassert
7 SPDIFTX_RST SPDIFTX reset control
1: Reset Assert
0: Reset Deassert
@
RD A
6 FE_RST FE reset control
1: Reset Assert
0: Reset Deassert
R DI
5 HSDMA_RST HSDMA reset control
1: Reset Assert
0: Reset Deassert
2 MCM_RST MCM(MT7530) reset control
FO ME
1: Reset Assert
0: Reset Deassert
0 SYS_RST Whole System Reset Control
1: Whole System Reset
0: NA
1E000038 RSTSTAT Reset Status Register C003000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PGMT7621_V.1.0_130607 Page 22 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Name WD
WD
SE AL
T2S
T2R
YS
ON
ST WDTRSTPD
RS
O_
T_E
EN
N
Type RW RW RW
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SW WD
SYS RS
RST T
t.c EN
Type W1 W1
C C
Reset 0 0
Bit(s) Name Description
.ne ID
31 WDT2SYSRST_EN WDT reset apply to System Reset
Enables watchdog timeout to trigger a system reset.
1: Enable
0: Disable
ink NF
30 WDT2RSTO_EN WDT reset apply to watch dog reset pin out.
1: Enable
0: Disable
29:16 WDTRSTPD Watchdog Reset Output Low Period
Controls the WDT reset output low period. For example:
b-l CO
If the pin share mode was set correctly and WDT2RSTO_EN=1,
When WDTRSTPD= 0, you can see duration of 1 usec low on the WDT reset output
pin.
When WDTRSTPD= 3, you can see duration of 4 usec low on the WDT reset output
pin.
(unit: 1 usec)
2 SWSYSRST Software System Reset
18 TEK
Indicates when software has reset the chip by writing to the RSTSYS bit in RSTCTL.
NOTE: This register is reset only by a power on reset.
0: Has no effect.
1: Clears this bit.
1 WDRST Watchdog Reset
Indicates when the watchdog timer has reset the chip.
NOTE: This register is reset only by power-on reset.
0: Has no effect.
@
1: Clears this bit.
RD A
R DI
1E00003C MISR_GOLDE ROM BIST MISR Golden Value 0000000
N 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name MISR_GOLDEN[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MISR_GOLDEN[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 MISR_GOLDEN ROM BIST golden value
PGMT7621_V.1.0_130607 Page 23 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E000040 MISR_RESUL ROM BIST MISR Result Value 0000000
ON
T 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MISR_RESULT[31:16]
n U TI
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MISR_RESULT[15:0]
Type RO
t.c EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 MISR_RESULT ROM BIST result
1E000044
S
.ne ID
CUR_CLK_ST Current clock status 00030A0
1
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SA
ME
CUR_OCP_RATIO
_FR
EQ
b-l CO
Type RO RO
Reset 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CUR_CPU_FDIV CUR_CPU_FFRAC
Type RO RO
Reset 0 1 0 1 0 0 0 0 0 1
18 TEK
Bit(s) Name Description
20 SAME_FREQ SYS_CLK and DRAM_clk are same frequency.
18:16 CUR_OCP_RATIO Current CPU_OCP_RATIO(SYS:CPU)
4: 1:4
3: 1:3
12:8 CUR_CPU_FDIV Current divider number of CPU frequency
@
4:0 CUR_CPU_FFRAC Current fraction number of CPU frequency.
RD A
R DI
1E000048 PAD_UART1_ PAD configuration of UART1 and GPIO0 groups 0A180A1
GPIO0_CFG 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name UA UA
UA
UA
UART1_R UART1_E4 RT1
UART1_TDSEL RT1 RT1 RT1
DSEL _E2 _S
_PU _PD _SR
MT
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPI
GPI GPI GPI
GPIO0_RD GPIO0_E4 O0_
GPIO0_TDSEL O0_ O0_ O0_
SEL _E2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
PGMT7621_V.1.0_130607 Page 24 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 1 0 1 0 0 1 1 0 0 0
SE AL
ON
Bit(s) Name Description
29:28 UART1_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
n U TI
3: For 1.8V
0: For 3.3V
27:24 UART1_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
t.c EN
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
21:20 UART1_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
.ne ID
1: 4mA
0: 2mA
19 UART1_PU 75K pull-up resistor control.
1: Enable
ink NF
0: Disable
18 UART1_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 UART1_SMT RX input buffer schmit trigger hysteresis control enable.
b-l CO
1: Enable
0: Disable
16 UART1_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
13:12 GPIO0_RDSEL RX duty select
18 TEK
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
11:8 GPIO0_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
@
0: For 1.8V
RD A
5:4 GPIO0_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
R DI
1: 4mA
0: 2mA
3 GPIO0_PU 75K pull-up resistor control.
1: Enable
FO ME
0: Disable
2 GPIO0_PD 75K pull-down resistor control.
1: Enable
0: Disable
1 GPIO0_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
0 GPIO0_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
PGMT7621_V.1.0_130607 Page 25 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E00004C PAD_UART3_I PAD configuration of UART3 and I2C groups 0A140A1
2C_CFG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name UA UA
UA
UA
UART3_R UART3_E4 RT3
UART3_TDSEL RT3 RT3 RT3
DSEL _E2 _S
_PU _PD _SR
MT
Type RW RW RW RW RW RW RW
t.c EN
Reset 0 0 1 0 1 0 0 1 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I2C_RDSE I2C I2C
I2C
I2C
I2C_TDSEL I2C_E4_E2 _S
L _PU _PD _SR
MT
Type RW RW RW RW RW RW RW
.ne ID
Reset 0 0 1 0 1 0 0 1 0 0 0 0
Bit(s) Name Description
ink NF
29:28 UART3_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 UART3_TDSEL TX duty select
b-l CO
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
21:20 UART3_E4_E2 TX Driving Strength Control.
3: 8mA
18 TEK
2: 6mA
1: 4mA
0: 2mA
19 UART3_PU 75K pull-up resistor control.
1: Enable
0: Disable
18 UART3_PD 75K pull-down resistor control.
1: Enable
@
0: Disable
RD A
17 UART3_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
R DI
0: Disable
16 UART3_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
FO ME
13:12 I2C_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
11:8 I2C_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
5:4 I2C_E4_E2 TX Driving Strength Control.
3: 8mA
PGMT7621_V.1.0_130607 Page 26 of 349
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MT7621 PROGRAMMING GUIDE
L Y
2: 6mA
1: 4mA
SE AL
0: 2mA
ON
3 I2C_PU 75K pull-up resistor control.
1: Enable
0: Disable
2 I2C_PD 75K pull-down resistor control.
n U TI
1: Enable
0: Disable
1 I2C_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
t.c EN
0: Disable
0 I2C_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
1E000050
.ne ID
PAD_UART2_
JTAG_CFG
PAD configuration of UART2 and JTAG groups 0A140A1
4
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name JTA
JTA JTA JTA
JTAG_RD JTAG_E4_ G_
JTAG_TDSEL G_ G_ G_
SEL E2 SM
PU PD SR
T
b-l CO
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name UA UA
UA
UA
UART2_R UART2_E4 RT2
UART2_TDSEL RT2 RT2 RT2
DSEL _E2 _S
_PU _PD _SR
MT
18 TEK
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 0 1 0 0
Bit(s) Name Description
29:28 JTAG_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
@
3: For 1.8V
RD A
0: For 3.3V
27:24 JTAG_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
R DI
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
21:20 JTAG_E4_E2 TX Driving Strength Control.
FO ME
3: 8mA
2: 6mA
1: 4mA
0: 2mA
19 JTAG_PU 75K pull-up resistor control.
1: Enable
0: Disable
18 JTAG_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 JTAG_SMT RX input buffer schmit trigger hysteresis control enable.
PGMT7621_V.1.0_130607 Page 27 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: Enable
0: Disable
SE AL
16 JTAG_SR Output Slew Rate Control.
ON
1: Slower slew.
0: No slew rate controlled.
13:12 UART2_RDSEL RX duty select
n U TI
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
11:8 UART2_TDSEL TX duty select
t.c EN
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
5:4 UART2_E4_E2 TX Driving Strength Control.
.ne ID
3: 8mA
2: 6mA
1: 4mA
0: 2mA
3 UART2_PU 75K pull-up resistor control.
ink NF
1: Enable
0: Disable
2 UART2_PD 75K pull-down resistor control.
1: Enable
0: Disable
b-l CO
1 UART2_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
0 UART2_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
18 TEK
1E000054 PAD_PERST_ PAD configuration of PICe RST and WDT RST groups 0A180A1
WDT_CFG 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PE PE PE PE
@
PERST_R PERST_E4 RS RS RS RS
RD A
PERST_TDSEL
DSEL _E2 T_P T_P T_S T_S
U D MT R
Type RW RW RW RW RW RW RW
R DI
Reset 0 0 1 0 1 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WDT_RDS WDT_E4_E
WD WD WD WD
WDT_TDSEL T_P T_P T_S T_S
EL 2
FO ME
U D MT R
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 1 0 0 0
Bit(s) Name Description
29:28 PERST_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 PERST_TDSEL TX duty select
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MT7621 PROGRAMMING GUIDE
L Y
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
SE AL
10: For3.3V
ON
0: For 1.8V
21:20 PERST_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
n U TI
1: 4mA
0: 2mA
19 PERST_PU 75K pull-up resistor control.
1: Enable
t.c EN
0: Disable
18 PERST_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 PERST_SMT RX input buffer schmit trigger hysteresis control enable.
.ne ID
1: Enable
0: Disable
16 PERST_SR Output Slew Rate Control.
1: Slower slew.
ink NF
0: No slew rate controlled.
13:12 WDT_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
b-l CO
11:8 WDT_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
5:4 WDT_E4_E2 TX Driving Strength Control.
18 TEK
3: 8mA
2: 6mA
1: 4mA
0: 2mA
3 WDT_PU 75K pull-up resistor control.
1: Enable
0: Disable
@
2 WDT_PD 75K pull-down resistor control.
RD A
1: Enable
0: Disable
1 WDT_SMT RX input buffer schmit trigger hysteresis control enable.
R DI
1: Enable
0: Disable
0 WDT_SR Output Slew Rate Control.
1: Slower slew.
FO ME
0: No slew rate controlled.
1E000058 PAD_RGMII2_ PAD configuration of RGMII2 and MDIO RST groups 0A210A2
MDIO_CFG 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
RG RG RG
RGMII2_R RGMII2_E4 MII2
RGMII2_TDSEL MII2 MII2 MII2
DSEL _E2 _S
_PU _PD _SR
MT
PGMT7621_V.1.0_130607 Page 29 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Type RW RW RW RW RW RW RW
Reset
SE AL
0 0 1 0 1 0 1 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Name MDI MDI
MDI
MDI
MDIO_RDS MDIO_E4_ O_
MDIO_TDSEL O_ O_ O_
EL E2 SM
PU PD SR
T
n U TI
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 1 0 0 0 0 1
Bit(s) Name Description
t.c EN
29:28 RGMII2_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
.ne ID
27:24 RGMII2_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
ink NF
21:20 RGMII2_E4_E2 TX Driving Strength Control. (CID)
3: 16mA
2: 12mA
1: 8mA
0: 4mA
b-l CO
19 RGMII2_PU 75K pull-up resistor control.
1: Enable
0: Disable
18 RGMII2_PD 75K pull-down resistor control.
1: Enable
0: Disable
18 TEK
17 RGMII2_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
16 RGMII2_SR Output Slew Rate Control. (CID)
1: Slower slew.
0: No slew rate controlled.
13:12 MDIO_RDSEL RX duty select
@
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RD A
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
R DI
11:8 MDIO_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
FO ME
5:4 MDIO_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
1: 4mA
0: 2mA
3 MDIO_PU 75K pull-up resistor control.
1: Enable
0: Disable
2 MDIO_PD 75K pull-down resistor control.
1: Enable
0: Disable
PGMT7621_V.1.0_130607 Page 30 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1 MDIO_SMT RX input buffer schmit trigger hysteresis control enable.
SE AL
1: Enable
0: Disable
ON
0 MDIO_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
n U TI
1E00005C PAD_SDXC_S PAD configuration of SDXC and SPI RST groups 0A210A1
t.c EN
PI_CFG 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SD SD
SD
SD
SDXC_RD SDXC_E4_ XC_
SDXC_TDSEL XC_ XC_ XC_
SEL E2 SM
PU PD SR
T
.ne ID
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 1 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPI
SPI_RDSE SPI SPI SPI
ink NF
SPI_TDSEL SPI_E4_E2 _S
L _PU _PD _SR
MT
Type RW RW RW RW RW RW RW
Reset 0 0 1 0 1 0 0 1 1 0 0 0
b-l CO
Bit(s) Name Description
29:28 SDXC_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
27:24 SDXC_TDSEL TX duty select
18 TEK
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
21:20 SDXC_E4_E2 TX Driving Strength Control.
3: 8mA
2: 6mA
@
1: 4mA
0: 2mA
RD A
19 SDXC_PU 75K pull-up resistor control.
1: Enable
R DI
0: Disable
18 SDXC_PD 75K pull-down resistor control.
1: Enable
0: Disable
FO ME
17 SDXC_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
16 SDXC_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
13:12 SPI_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
PGMT7621_V.1.0_130607 Page 31 of 349
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MT7621 PROGRAMMING GUIDE
L Y
11:8 SPI_TDSEL TX duty select
SE AL
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
ON
10: For3.3V
0: For 1.8V
5:4 SPI_E4_E2 TX Driving Strength Control.
3: 8mA
n U TI
2: 6mA
1: 4mA
0: 2mA
3 SPI_PU 75K pull-up resistor control.
t.c EN
1: Enable
0: Disable
2 SPI_PD 75K pull-down resistor control.
1: Enable
0: Disable
.ne ID
1 SPI_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
0 SPI_SR Output Slew Rate Control.
ink NF
1: Slower slew.
0: No slew rate controlled.
b-l CO
1E000060 GPIO_MODE GPIO purpose selection 0004D42
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ES
WIN
SDXC_MO
T_ SPI_MODE
DE
MO
18 TEK
DE
Type RW RW RW
Reset 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG UA
JTA I2C
MII2 MII1 RT1
MDIO_MO PERST_M WDT_MOD G_ UART2_M UART3_M _M
_M _M _M
DE ODE E MO ODE ODE OD
OD OD OD
@
DE E
E E E
RD A
Type RW RW RW RW RW RW RW RW RW RW
Reset 1 1 0 1 0 1 0 0 0 0 1 0 1 1 0
R DI
Bit(s) Name Description
20 ESWINT_MODE Ether switch interrupt GPIO mode
1: GPIO
FO ME
0: Ether switch interrupt
19:18 SDXC_MODE SDXC GPIO mode
3: NAND
2: NAND
1: GPIO
0: SDXC
17:16 SPI_MODE SPI GPIO mode
3: NAND
2: NAND
1: GPIO
0: SPI
15 RGMII2_MODE RGMII2 GPIO mode
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MT7621 PROGRAMMING GUIDE
L Y
1: GPIO
0: RGMII2
SE AL
14 RGMII1_MODE RGMII1 GPIO mode
ON
1: GPIO
0: RGMII1
13:12 MDIO_MODE MDC/MDIO GPIO mode
n U TI
3: GPIO
2: GPIO
1: GPIO
0: MDIO
11:10 PERST_MODE PCIe reset GPIO mode
t.c EN
3: Reference clock
2: Reference clock
1: GPIO
0: PCIe reset
9:8 WDT_MODE Watch dog timeout GPIO mode
.ne ID
3: Reference clock
2: Reference clock
1: GPIO
0: Watch dog
7 JTAG_MODE JTAG GPIO mode
ink NF
1: GPIO
0: JTAG
6:5 UART2_MODE UART2 GPIO mode
3: GPIO
2: PCM
b-l CO
1: GPIO
0: UART2
4:3 UART3_MODE UART3 GPIO mode
3: SPDIF
2: I2S
1: GPIO
0: UART3
18 TEK
2 I2C_MODE I2C GPIO mode
1: GPIO
0: I2C
1 UART1_MODE UART1 GPIO mode
1: GPIO
0: UART1
@
RD A
1E000068 MEMO1 Memory1 0000000
R DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MEMO1[31:16]
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 MEMO1 Memory1
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MT7621 PROGRAMMING GUIDE
L Y
1E00006C MEMO2 Memory2 0000000
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MEMO2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MEMO2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 MEMO2 Memory2
.ne ID
1E000070 PAD_BOPT_E PAD configuration of Bonding OPT and ESW INT 0A000A0
SWINT_CFG groups 0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BO
BO BO BO
BOPT_RD BOPT_E4_ PT_
BOPT_TDSEL PT_ PT_ PT_
SEL E2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
b-l CO
Reset 0 0 1 0 1 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ES ES
ES
ES
ESW_RDS ESW_E4_E W_
ESW_TDSEL W_ W_ W_
EL 2 SM
PU PD SR
T
Type RW RW RW RW RW RW RW
18 TEK
Reset 0 0 1 0 1 0 0 0 0 0 0 0
Bit(s) Name Description
29:28 BOPT_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
@
0: For 3.3V
RD A
27:24 BOPT_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
R DI
10: For3.3V
0: For 1.8V
21:20 BOPT_E4_E2 TX Driving Strength Control.
3: 8mA
FO ME
2: 6mA
1: 4mA
0: 2mA
19 BOPT_PU 75K pull-up resistor control.
1: Enable
0: Disable
18 BOPT_PD 75K pull-down resistor control.
1: Enable
0: Disable
17 BOPT_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
PGMT7621_V.1.0_130607 Page 34 of 349
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MT7621 PROGRAMMING GUIDE
L Y
0: Disable
SE AL
16 BOPT_SR Output Slew Rate Control.
ON
1: Slower slew.
0: No slew rate controlled.
13:12 ESW_RDSEL RX duty select
RDSEL[0]: Level shifter duty high when asserted (high pulse width adjustment)
n U TI
RDSEL[1]: Level shifter duty low when asserted (low pulse width adjustment)
3: For 1.8V
0: For 3.3V
11:8 ESW_TDSEL TX duty select
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
t.c EN
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
10: For3.3V
0: For 1.8V
5:4 ESW_E4_E2 TX Driving Strength Control.
3: 8mA
.ne ID
2: 6mA
1: 4mA
0: 2mA
3 ESW_PU 75K pull-up resistor control.
ink NF
1: Enable
0: Disable
2 ESW_PD 75K pull-down resistor control.
1: Enable
0: Disable
b-l CO
1 ESW_SMT RX input buffer schmit trigger hysteresis control enable.
1: Enable
0: Disable
0 ESW_SR Output Slew Rate Control.
1: Slower slew.
0: No slew rate controlled.
18 TEK
1E000074 PAD_RGMII1_ PAD configuration of RGMII1 group 0000000
CFG 5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RGMII1_RDSEL RGMII1_TDSEL
Type RW RW
@
Reset
RD A
0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RMI RG
R DI
MII1
RGMII1_DRVP RGMII1_DRVN RGMII1_RTT I1_ MII1
_PD
PD _SR
B
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1
FO ME
Bit(s) Name Description
25:20 RGMII1_RDSEL RX duty select
RDSEL[1:0]: Input buffer duty high when asserted (high pulse width adjustment)
RDSEL[3:2]: Input buffer duty low when asserted(low pulse width adjustment)
RDSEL4: Level shifter duty high when asserted (high pulse width adjustment)
RDSEL5: Level shifter duty low when asserted (low pulse width adjustment)
DDR3:
RDSEL[5:0]=[000000]
DDR2:
RDSEL[5:0]=[000001]
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MT7621 PROGRAMMING GUIDE
L Y
19:16 RGMII1_TDSEL TX duty select
SE AL
TDSEL[1:0]: Output level shifter duty high when asserted (high pulse width adjustment)
TDSEL[3:2]: Output level shifter duty low when asserted(low pulse width adjustment)
ON
15:12 RGMII1_DRVP GDDR3/DDR2 Pull-Up Driving Strength Control.
00000: weakest. 11111: strongest.
Default(Typical):
GDDR3/POD18:DRVP[3:0]=[0100] (90 Ohm)
n U TI
DDR2/SSTL18: DRVP[3:0]=[1110] (40 Ohm)
DDR3/SSTL15: DRVP[3:0]=[1111] (40 Ohm)
3: Strongest.
0: Weakest.
t.c EN
11:8 RGMII1_DRVN GDDR3/DDR2 Pull-Down Driving Strength Control.
00000: weakest. 11111: strongest.
Default(Typical):
GDDR3/POD18:DRVN[3:0]=[1110] (40 Ohm)
DDR2/SSTL18: DRVN[3:0]=[1110] (40 Ohm)
DDR3/SSTL15: DRVN[3:0]=[1111] (40 Ohm)
.ne ID
3: Strongest.
0: Weakest.
6:4 RGMII1_RTT GDDR3(POD18)/DDR2(SSTL18) On-Die-Termination.
*Suggest to turn-off RTT[2:0] when not in read mode for power saving.
ink NF
GDDR3(POD18)
1.Comply to JESD8-19(POD18) for ODT pull-up 60/120/240 ohm requirement
2.Comply to GDDR3-SDRAM requirement
DDR2(SSTL18)
Follow JESD79-2B EMRS(1) Programming for Address Field [A6,A2]
b-l CO
Supported all range [A6,A2] ODT setting.
GDDR3 mode:
RTT[2:0]=[110], GDDR3 ODT pull-up 60ohm (or [100])
RTT[2:0]=[001], GDDR3 ODT pull-up 120ohm
RTT[2:0]=[010], GDDR3 ODT pull-up 240ohm
18 TEK
DDR2 mode:
RTT[2:0]=[000], ODT disable,Default for DDR/LVTTL mode.
RTT[2:0]=[001], DDR2 ODT 75ohm
RTT[2:0]=[010], DDR2 ODT 150ohm
RTT[2:0]=[011], DDR2 ODT 50ohm
DDR3 mode:
RTT[2:0]=[000], ODT disable,Default for DDR/LVTTL mode.
@
RTT[2:0]=[001], DDR2 ODT 60ohm
RD A
RTT[2:0]=[010], DDR2 ODT 120ohm
RTT[2:0]=[100], DDR2 ODT 40ohm
2 RGMII1_PDB 75K pull-down resistor control. Low activiate.
R DI
GDDR3/DDR2/DDR1 mode, PDB=1 to disable 75K pull-down resistors.
1: Disable
0: Enable
1 RMII1_PD GDDR3/DDR2/DDR input buffer Power Down mode.High asserted. PD=1, O=0.
FO ME
At LVTTL mode, set IE=0,PD=1
At GDDR3/DDR2/DDR1 power down mode, set IE=0, PD=1
1: Enable
0: Disable
0 RGMII1_SR Output Slew Rate Control. High asserted.
1: Slower slew.
0: No slew rate controlled.
1E000078 CPE_ROSC_S 0000000
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MT7621 PROGRAMMING GUIDE
L Y
EL0 0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name CPE_ROSC_SEL0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name CPE_ROSC_SEL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 CPE_ROSC_SEL0 CPE ROSC cell selection bit 31 ~ 0
.ne ID
1E00007C CPE_ROSC_S 0000000
EL1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CPE_ROSC_SEL1[31:16]
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CPE_ROSC_SEL1[15:0]
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CPE_ROSC_SEL1 CPE ROSC cell selection bit 63 ~ 32
18 TEK
1E000080 CPU_CPE_CN CPU CPE counter 0 0000000
T0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CPU_DFD_CNT0[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name CPU_DFD_CNT0[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:0 CPU_DFD_CNT0 CPU DFD counter value bit 31 ~ 0
FO ME
1E000084 CPU_CPE_CN CPU CPE counter 1 0000000
T1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CPU_DFD_CNT1
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MT7621 PROGRAMMING GUIDE
L Y
Type RO
Reset
SE AL
0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
7:0 CPU_DFD_CNT1 CPU DFD counter value bit 39 ~ 32
n U TI
1E000088 CPU_CFG CPU configuration 55AA002
1
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MBIST_BKGND
Type RW
Reset 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.ne ID
Name RG
SI_
_R
IT_ SY
CM_DFT_T W_
TOI NC
ARGET SW
TU TX_
_TG
ink NF
EN
R
Type RW RW RW RW
Reset 1 0 0 0 1
Bit(s) Name Description
b-l CO
31:16 MBIST_BKGND CPU MBISTA background pattern
5:4 CM_DFT_TARGET CM default target
2: IOCU
0: Memory
2 RG_RW_SW_TGR SW trigger DFD counter to start
1: Enable
18 TEK
0: Disable
1 IT_TOITU CM arbitraction
1: DRAM access priority - favor CPU cores, but RRB between two cores
0: DRAM access priority - CPU core and IOCU master port RRB
0 SI_SYNCTX_EN Bus support OCP SYNC command or not
1: Enable
0: Disable
@
RD A
1E00008C CPU_MEM_CF CPU memory delay, power down and sleep control 0000000
R DI
G A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CP
FO ME
E_R
CPE_ROS
OS CPE_ROSC_OUT
C_SEL2
C_E
N
Type RW RW RO
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CP
CP
U_
U_
RA CPU_L2_D CPU_L1_D
RA
M_ EL_SEL EL_SEL
M_
SLE
PD
EP
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MT7621 PROGRAMMING GUIDE
L Y
Type RW RW RW RW
Reset
SE AL
0 0 1 0 1 0
ON
Bit(s) Name Description
31 CPE_ROSC_EN CPE ROSC enable
1: Enable
n U TI
0: Disable
30:29 CPE_ROSC_SEL2 CPE ROSC cell selection bit 65 ~ 64
27:24 CPE_ROSC_OUT CPE ROSC output
15 CPU_RAM_PD CPU RAM power down enable
t.c EN
1: Enable
0: Disable
14 CPU_RAM_SLEEP CPU RAM sleep enable
1: Enable
0: Disable
.ne ID
3:2 CPU_L2_DEL_SEL CPU L2 cache RAM delay selection
1:0 CPU_L1_DEL_SEL CPU L1 cache RAM delay selection
ink NF
1E000090 FMTR_CFG0 Frequency meter configuration 0 0000000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name FMTR_CNT_LMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FM
FM
TR_
FMTR_CK TR_
FMTR_CK_SEL CN
_DIV RS
18 TEK
T_E
T
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:16 FMTR_CNT_LMT Freq. meter counter limitation
@
15:12 FMTR_CK_SEL Freq. meter DUT clock selection
RD A
10: CPLL monitor clock
9: DDRPLL4 monitor clock
8: DDRPLL3 monitor clock
R DI
7: DDRPLL2 monitor clock
6: DDRPLL1 monitor clock
5: PCIe1 clock
4: PCIe clock
3: CPU clock
FO ME
2: GMPLL clock
1: APLL clock
0: XTAL clock
9:8 FMTR_CK_DIV Freq. meter clock divider selection
3: divided by 40
2: divided by 40
1: divided by 10
0: no divided
4 FMTR_RST Reset freq. meter
1: Reset
0: Not reset
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MT7621 PROGRAMMING GUIDE
L Y
0 FMTR_CNT_EN Freq. meter counter enable
SE AL
1: Enable
0: Disable
ON
1E000094 FMTR_CNT_M Frequency meter count maximum 0000000
n U TI
AX 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FMTR_CNT_MAX[31:16]
t.c EN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FMTR_CNT_MAX[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 FMTR_CNT_MAX Freq. meter counter maximum value
ink NF
1E000098 FMTR_CNT_M Frequency meter count minimum 0000000
IN 0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FMTR_CNT_MAX[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FMTR_CNT_MAX[15:0]
Type RW
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 FMTR_CNT_MAX Freq. meter counter minimum value
@
RD A
1E00009C FMTR_CNT_V Frequency meter counter value 0000000
AL 0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FMTR_CNT_VAL[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name FMTR_CNT_VAL[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 FMTR_CNT_VAL Freq. meter counter final value
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.3 Timer
ON
2.3.1 Features
Independent 1usec tick pre-scale for each timer.
Independent interrupts for each timer.
n U TI
Two general-purpose timers and a watchdog timer. Watchdog timer resets system on time-out.
Timer Modes
Periodic
t.c EN
In periodic mode, the timer counts down to zero from the limited value. An interrupt is generated when
the count is zero. After reaching zero, the limited value is reloaded into the timer and the timer counts
down again. A limited value of zero disables the timer.
Timeout
.ne ID
In timeout mode, the timer counts down to zero from the limited value. An interrupt is generated when
the count is zero. In this mode, the ENABLE bit is reset when the timer reaches zero, stopping the
counter.
Watchdog
ink NF
In watchdog mode, the timer counts down to zero from the limited value. If the load value is not reloaded
or the timer is not disabled before the count is zero, the chip will be reset. When this occurs, every
register in the chip is reset except the watchdog reset status bit WDRST in the RSTSTAT register in the
b-l CO
system control block; it remains set to alert firmware of the timeout event when it re-executes its
bootstrap.
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.3.2 Block Diagram
ON
Timer 0
Limited Value Prescale
n U TI
Counter Mode Control
Timer 0 Interrupt
t.c EN
Timer 1 Interrupt
Watchdog Timer (Timer 1)
Interrupt
Control
Limited Value Prescale
.ne ID
Counter Mode Control
Timer 2
ink NF
Watchdog Timeout
Limited Value Prescale
APBus Signals
Counter Mode Control
b-l CO
Figure 2-2 Timer Block Diagram
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.3.3 Registers
ON
Address Name Widt Register Function
h
n U TI
1E000100 TGLB_REG 32 RISC Global Control Register
1E000110 T0CTL_REG 32 RISC Timer 0 Control Register
1E000114 T0LMT_REG 32 RISC Timer 0 Limit Register
t.c EN
1E000118 T0_REG 32 RISC Timer 0 Register
1E000120 WDTCTL_REG 32 Watch Dog Timer Control Register
1E000124 WDTLMT_REG 32 Watch Dog Timer Limit Register
1E000128 WDT_REG 32 Watch Dog Timer Register
1E000130 T1CTL_REG 32 RISC Timer 1 Control Register
.ne ID
1E000134 T1LMT_REG 32 RISC Timer 1 Limit Register
1E000138 T1_REG 32 RISC Timer 1 Register
ink NF
1E000100 TGLB_REG RISC Global Control Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name RESV1[20:5]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WD WD
T1R T0R T1I T0I
RESV1[4:0] TR RESV0 TIN
ST ST NT NT
ST T
18 TEK
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:11 RESV1 Reserved
10 T1RST Timer 1 reset
@
1: to reset timer 1 to T1LMT value
RD A
9 WDTRST Watch dog timer reset
1: to reset watch dog timer to WDTLMT value
8 T0RST Timer 0 reset
R DI
1: to reset timer 0 to T0LMT value
7:3 RESV0 Reserved
2 T1INT Timer 1 interrupt status
FO ME
1 WDTINT Watch dog timer interrupt status
0 T0INT Timer 0 interrupt status
1E000110 T0CTL_REG RISC Timer 0 Control Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name T0PRES
Type RW
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0E T0A
ON
RESV2 RESV1 RESV0
N L
Type RW RW RW RW DC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:16 T0PRES Timer 0 count down tick pre-scale. Unit is 1u second.
15:8 RESV2 Reserved
t.c EN
7 T0EN Timer 0 count down enable
6:5 RESV1 Reserved
4 T0AL Timer 0 auto load enable
1: Enable
0: Disable
.ne ID
3:0 RESV0 Reserved
ink NF
1E000114 T0LMT_REG RISC Timer 0 Limit Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type
b-l CO
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0LMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 T0LMT Timer 0 Limit.
When T0AL is set to 1, T0LMT will be loaded into timer 0 when timer 0 is enabled or
when count down to 0.
@
RD A
1E000118 T0_REG RISC Timer 0 Register 0000000
0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV0 Reserved
15:0 T0 RISC down-count timer 0
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MT7621 PROGRAMMING GUIDE
L Y
1E000120 WDTCTL_RE Watch Dog Timer Control Register 0000000
SE AL
G 0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WDTPRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WD
WD
RESV2 TE RESV1 RESV0
TAL
N
t.c EN
Type RW RW RW RW DC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 WDTPRES Watch dog timer count down tick pre-scale. Unit is 1u second.
.ne ID
15:8 RESV2 Reserved
7 WDTEN Watch dog timer count down enable
6:5 RESV1 Reserved
ink NF
4 WDTAL Watch dog timer auto load enable
1: Enable
0: Disable
3:0 RESV0 Reserved
b-l CO
1E000124 WDTLMT_RE Watch Dog Timer Limit Register 0000000
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
18 TEK
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WDTLMT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
RD A
31:16 RESV0 Reserved
15:0 WDTLMT Watch dog timer Limit.
When WDTAL is set to 1, WDTLMT will be loaded into watch dog timer when watch
R DI
dog timer is enabled or when count down to 0.
FO ME
1E000128 WDT_REG Watch Dog Timer Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WDT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
31:16 RESV0 Reserved
ON
15:0 WDT watch dog timer.
n U TI
1E000130 T1CTL_REG RISC Timer 1 Control Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name T1PRES
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T1E T1A
RESV2 RESV1 RESV0
N L
.ne ID
Type RW RW RW RW DC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
31:16 T1PRES Timer 1 count down tick pre-scale. Unit is 1u second.
15:8 RESV2 Reserved
7 T1EN Timer 1 count down enable
6:5 RESV1 Reserved
b-l CO
4 T1AL Timer 1 auto load enable
3:0 RESV0 Reserved
1E000134 T1LMT_REG RISC Timer 1 Limit Register 0000000
18 TEK
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T1LMT
@
Type RW
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R DI
31:16 RESV0 Reserved
15:0 T1LMT Timer 1 Limit.
When T1AL is set to 1, T1LMT will be loaded into timer 1 when timer 1 is enabled or
when count down to 0.
FO ME
1E000138 T1_REG RISC Timer 1 Register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Name T1
SE AL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31:16 RESV0 Reserved
n U TI
15:0 T1 RISC down-count timer 1
t.c EN
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.4 System Tick Counter
ON
2.4.1 Registers
n U TI
Address Name Width Register Function
1E000500 STCK_CNT_CFG 32 MIPS Configuration
1E000504 CMP_CNT 32 MIPS Compare
Sets the cutoff point for the free run counter (MIPS counter). If the free run
t.c EN
counter equals the compare counter, then the timer circuit generates an interrupt.
The interrupt remains active until the compare counter is written again.
1E000508 CNT 32 MIPS Counter
The MIPS counter (free run counter) increases by 1 every 20 us (50 KHz). The
counter continues to count until it reaches the value loaded into CMP_CNT.
1E000500
.ne ID
STCK_CNT_CFG MIPS Configuration 00000000
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV[29:14]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name RESV[13:0]
EXT_ST CNT_E
K_EN N
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:2 RESV
1 EXT_STK_EN External System Tick Enable - Selects the system tick source.
0: Use the MIPS internal timer interrupts.
1: Use the external timer interrupt from an external MIPS counter.
0 CNT_EN Counter Enable - Enable the free run counter (MIPS counter).
0: Disable
1: Enable
@
RD A
1E000504 CMP_CNT MIPS Compare 00000000
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMP_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 RESV
15:0 CMP_CNT Compare Count
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E000508 CNT MIPS Counter 00000000
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESV
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:16 RESV
15:0 CNT MIPS Counter
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.5 UART Lite
ON
2.5.1 Features
2-pin UART
16550-compatible register set, except for Divisor Latch register
n U TI
5-8 data bits
1-2 stop bits (1 or 2 stop bits are supported with 5 data bits)
Even, odd, stick or no parity
t.c EN
All standard baud rates up to 345600 b/s
16-byte receive buffer
16-byte transmit buffer
Receive buffer threshold interrupt
Transmit buffer threshold interrupt
.ne ID
False start bit detection in asynchronous mode
Internal diagnostic capabilities
Break simulation
ink NF
Loop-back control for communications link fault isolation
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.5.2 Registers
n = 1; for uart1 only.
ON
UARTn+0000h RX Buffer Register UARTn_RBR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name RBR[7:0]
Type RO
RBR RX Buffer Register. Read-only register. The received data can be read by accessing this register.
t.c EN
Modified when LCR[7] = 0.
UARTn+0000h TX Holding Register UARTn_THR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.ne ID
Name THR[7:0]
Type WO
THR TX Holding Register. Write-only register. The data to be transmitted is written to this register, and
ink NF
then sent to the PC via serial communication.
Modified when LCR[7] = 0.
UARTn+0004h Interrupt Enable Register UARTn_IER
b-l CO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CTSI RTSI XOFFI X EDSSI ELSI ETBEI ERBFI
Type R/W
Reset 0
IER By storing a ‘1’ to a specific bit position, the interrupt associated with that bit is enabled. Otherwise,
18 TEK
the interrupt is disabled.
IER[3:0] are modified when LCR[7] = 0.
IER[7:4] are modified when LCR[7] = 0 & EFR[4] = 1.
CTSI Masks an interrupt that is generated when a rising edge is detected on the CTS modem control line.
Note: This interrupt is only enabled when hardware flow control is enabled.
@
0 Unmask an interrupt that is generated when a rising edge is detected on the CTS modem control
RD A
line.
1 Mask an interrupt that is generated when a rising edge is detected on the CTS modem control line.
R DI
RTSI Masks an interrupt that is generated when a rising edge is detected on the RTS modem control line.
Note: This interrupt is only enabled when hardware flow control is enabled.
0 Unmask an interrupt that is generated when a rising edge is detected on the RTS modem control
FO ME
line.
1 Mask an interrupt that is generated when a rising edge is detected on the RTS modem control line.
XOFFI Masks an interrupt that is generated when an XOFF character is received.
Note: This interrupt is only enabled when software flow control is enabled.
0 Unmask an interrupt that is generated when an XOFF character is received.
1 Mask an interrupt that is generated when an XOFF character is received.
EDSSI When set ("1"), an interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
0 No interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
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MT7621 PROGRAMMING GUIDE
L Y
1 An interrupt is generated if DDCD, TERI, DDSR or DCTS (MSR[4:1]) becomes set.
SE AL
ELSI When set ("1"), an interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
ON
0 No interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
1 An interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes set.
ETBEI When set ("1"), an interrupt is generated if the TX Holding Register is empty or the contents of the TX
n U TI
FIFO
have been reduced to its Trigger Level.
0 No interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have
t.c EN
been reduced to its Trigger Level.
1 An interrupt is generated if the TX Holding Register is empty or the contents of the TX FIFO have
been reduced to its Trigger Level
ERBFI When set ("1"), an interrupt is generated if the RX Buffer contains data.
.ne ID
0 No interrupt is generated if the RX Buffer contains data.
1 An interrupt is generated if the RX Buffer contains data.
ink NF
UARTn+0008h Interrupt Identification Register UARTn_IIR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIFOE ID4 ID3 ID2 ID1 ID0 NINT
Type RO
Reset 0 0 0 0 0 0 0 1
b-l CO
IIR Identify if there are pending interrupts; ID4 and ID3 are presented only when EFR[4] = 1.
The following table gives the IIR[5:0] codes associated with the possible interrupts:
IIR[5:0] Priority Interrupt Source
Level
18 TEK
000001 - No interrupt pending
000110 1 Line Status Interrupt BI, FE, PE or OE set in LSR
000100 2 RX Data Received RX Data received or RX Trigger Level reached.
001100 2 RX Data Timeout Timeout on character in RX FIFO.
000010 3 TX Holding Register TX Holding Register empty or TX FIFO Trigger Level
@
Empty reached.
RD A
000000 4 Modem Status change DDCD, TERI, DDSR or DCTS set in MSR
010000 5 Software Flow Control XOFF Character received
R DI
100000 6 Hardware Flow Control CTS or RTS Rising Edge
Table 1 The IIR[5:0] codes associated with the possible interrupts
FO ME
Line Status Interrupt: A RX Line Status Interrupt (IIR[5:0`] == 000110b) is generated if ELSI (IER[2]) is set and
any of BI, FE, PE or OE (LSR[4:1]) becomes set. The interrupt is cleared by reading the Line Status Register.
RX Data Received Interrupt: A RX Received interrupt (IER[5:0] == 000100b) is generated if EFRBI (IER[0]) is set
and either RX Data is placed in the RX Buffer Register or the RX Trigger Level is reached. The interrupt is
cleared by reading the RX Buffer Register or the RX FIFO (if enabled).
RX Data Timeout Interrupt:
When virtual FIFO mode is disabled, RX Data Timeout Interrupt is generated if all of the following apply:
1. FIFO contains at least one character;
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L Y
2. The most recent character was received longer than four character periods ago (including all start, parity
SE AL
and stop bits);
ON
3. The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register, or on a CPU read from the
n U TI
RX FIFO.
The RX Data Timeout Interrupt is enabled by setting EFRBI (IER[0]) to 1, and is cleared by reading RX FIFO.
When virtual FIFO mode is enabled, RX Data Timeout Interrupt is generated if all of the following apply:
1. FIFO is empty;
t.c EN
2. The most recent character was received longer than four character periods ago (including all start, parity
and stop bits);
.ne ID
3. The most recent CPU read of the FIFO was longer than four character periods ago.
The timeout timer is restarted on receipt of a new byte from the RX Shift Register.
RX Holding Register Empty Interrupt: A TX Holding Register Empty Interrupt (IIR[5:0] = 000010b) is generated if
ink NF
ETRBI (IER[1]) is set and either the TX Holding Register or, if FIFOs are enabled, the TX FIFO becomes empty.
The interrupt is cleared by writing to the TX Holding Register or TX FIFO if FIFO enabled.
Modem Status Change Interrupt: A Modem Status Change Interrupt (IIR[5:0] = 000000b) is generated if EDSSI
(IER[3]) is set and either DDCD, TERI, DDSR or DCTS (MSR[3:0]) becomes set. The interrupt is cleared by
reading the Modem Status Register.
b-l CO
Software Flow Control Interrupt: A Software Flow Control Interrupt (IIR[5:0] = 010000b) is generated if
Software Flow Control is enabled and XOFFI (IER[5]) becomes set, indicating that an XOFF character has been
received. The interrupt is cleared by reading the Interrupt Identification Register.
Hardware Flow Control Interrupt: A Hardware Flow Control Interrupt (IER[5:0] = 100000b) is generated if
Hardware Flow Control is enabled and either RTSI (IER[6]) or CTSI (IER[7]) becomes set indicating that a
18 TEK
rising edge has been detected on either the RTS/CTS Modem Control line. The interrupt is cleared by reading
the Interrupt Identification Register.
UARTn+0008h FIFO Control Register UARTn_FCR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RFTL1 RFTL0 TFTL1 TFTL0 DMA1 CLRT CLRR FIFOE
@
Type WO
RD A
FCR FCR is used to control the trigger levels of the FIFOs, or flush the FIFOs.
R DI
FCR[7:6] is modified when LCR != BFh
FCR[5:4] is modified when LCR != BFh & EFR[4] = 1
FCR[4:0] is modified when LCR != BFh
FO ME
FCR[7:6] RX FIFO trigger threshold
0 1
1 6
2 12
3 RXTRIG
FCR[5:4] TX FIFO trigger threshold
0 1
1 4
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MT7621 PROGRAMMING GUIDE
L Y
2 8
SE AL
3 14 (FIFOSIZE - 2)
ON
DMA1 This bit determines the DMA mode, which the TXRDY and RXRDY pins support. TXRDY and
RXRDY act to support single-byte transfers between the UART and memory (DMA mode 0) or
multiple byte transfers (DMA mode1). Note that this bit has no effect unless the FIFOE bit is set as
n U TI
well
0 The device operates in DMA Mode 0.
1 The device operates in DMA Mode 1.
t.c EN
TXRDY – mode0: Goes active (low) when the TX FIFO or the TX Holding Register is empty.
Becomes inactive when a byte is written to the Transmit channel.
TXRDY – mode1: Goes active (low) when there are no characters in the TX FIFO. Becomes inactive
when the TX FIFO is full.
.ne ID
RXRDY – mode0: Becomes active (low) when at least one character is in the RX FIFO or the RX
Buffer Register is full. Becomes inactive when there are no more characters in the RX FIFO or
RX Buffer register.
ink NF
RXRDY – mode1: Becomes active (low) when the RX FIFO Trigger Level is reached or an RX FIFO
Character Timeout occurs. Goes inactive when the RX FIFO is empty.
CLRT Clear Transmit FIFO. This bit is self-clearing.
0 Leave TX FIFO intact.
b-l CO
1 Clear all the bytes in the TX FIFO.
CLRR Clear Receive FIFO. This bit is self-clearing.
0 Leave RX FIFO intact.
1 Clear all the bytes in the RX FIFO.
FIFOE FIFO Enabled. This bit must be set to 1 for any of the other bits in the registers to have any effect.
18 TEK
0 Disable both the RX and TX FIFOs.
1 Enable both the RX and TX FIFOs.
UARTn+000Ch Line Control Register UARTn_LCR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name DLAB SB SP EPS PEN STB WLS1 WLS0
RD A
Type R/W
Reset 0 0 0 0 0 0 0 0
R DI
LCR Line Control Register. Determines characteristics of serial communication signals.
Modified when LCR[7] = 0.
DLAB Divisor Latch Access Bit.
FO ME
0 The RX and TX Registers are read/written at Address 0 and the IER register is read/written at
Address 4.
1 The Divisor Latch LS is read/written at Address 0 and the Divisor Latch MS is read/written at
Address 4.
SB Set Break
0 No effect
1 SOUT signal is forced into the “0” state.
SP Stick Parity
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MT7621 PROGRAMMING GUIDE
L Y
0 No effect.
SE AL
1 The Parity bit is forced into a defined state, depending on the states of EPS and PEN:
ON
If EPS=1 & PEN=1, the Parity bit is set and checked = 0.
If EPS=0 & PEN=1, the Parity bit is set and checked = 1.
EPS Even Parity Select
n U TI
0 When EPS=0, an odd number of ones is sent and checked.
1 When EPS=1, an even number of ones is sent and checked.
PEN Parity Enable
t.c EN
0 The Parity is neither transmitted nor checked.
1 The Parity is transmitted and checked.
STB Number of STOP bits
0 One STOP bit is always added.
.ne ID
1 Two STOP bits are added after each character is sent; unless the character length is 5 when 1 STOP
bit is added.
WLS1, 0 Word Length Select.
ink NF
0 5 bits
1 6 bits
2 7 bits
3 8 bits
b-l CO
UARTn+0010h Modem Control Register UARTn_MCR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XOFF
DCM_
Name STATU X OUT2 OUT1 RTS DTR
EN
S
18 TEK
Type R/W
Reset 0 0 0 0 0 0 0
MCR Modem Control Register. Control interface signals of the UART.
MCR[4:0] are modified when LCR[7] = 0,
MCR[7:6] are modified when LCR[7] = 0 & EFR[4] = 1.
@
XOFF Status This is a read-only bit.
RD A
0 When an XON character is received.
1 When an XOFF character is received.
R DI
DCM_EN UART DCM function enable bit
0 UART DCM is disabled.
1 UART DCM is enabled.
FO ME
OUT2 Controls the state of the output NOUT2, even in loop mode.
0 NOUT2=1.
1 NOUT2=0.
OUT1 Controls the state of the output NOUT1, even in loop mode.
0 NOUT1=1.
1 NOUT1=0.
RTS Controls the state of the output NRTS, even in loop mode.
0 NRTS=1.
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MT7621 PROGRAMMING GUIDE
L Y
1 NRTS=0.
SE AL
DTR Control the state of the output NDTR, even in loop mode.
ON
0 NDTR=1.
1 NDTR=0.
n U TI
UARTn+0014h Line Status Register UARTn_LSR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
Name TEMT THRE BI FE PE OE DR
RR
t.c EN
Type R/W
Reset 0 1 1 0 0 0 0 0
LSR Line Status Register.
Modified when LCR[7] = 0.
.ne ID
FIFOERR RX FIFO Error Indicator.
0 No PE, FE, BI set in the RX FIFO.
1 Set to 1 when there is at least one PE, FE or BI in the RX FIFO.
ink NF
TEMT TX Holding Register (or TX FIFO) and the TX Shift Register are empty.
0 Empty conditions below are not met.
1 If FIFOs are enabled, the bit is set whenever the TX FIFO and the TX Shift Register are empty. If
b-l CO
FIFOs are disabled, the bit is set whenever TX Holding Register and TX Shift Register are empty.
THRE Indicates if there is room for TX Holding Register or TX FIFO is reduced to its Trigger Level.
0 Reset whenever the contents of the TX FIFO are more than its Trigger Level (FIFOs are
enabled), or whenever TX Holding Register is not empty(FIFOs are disabled).
1 Set whenever the contents of the TX FIFO are reduced to its Trigger Level (FIFOs are enabled), or
18 TEK
whenever TX Holding Register is empty and ready to accept new data (FIFOs are disabled).
BI Break Interrupt.
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set whenever the SIN is held in the 0 state for more than one
transmission time (START bit + DATA bits + PARITY + STOP bits).
If the FIFOs are enabled, this error is associated with a corresponding character in the FIFO and is
@
RD A
flagged when this byte is at the top of the FIFO. When a break occurs, only one zero character is
loaded into the FIFO: the next character transfer is enabled when SIN goes into the marking state
R DI
and receives the next valid start bit.
FE Framing Error.
0 Reset by the CPU reading this register
FO ME
1 If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP bit. If the
FIFOs are enabled, the state of this bit is revealed when the byte it refers to is the next to be read.
PE Parity Error
0 Reset by the CPU reading this register
1 If the FIFOs are disabled, this bit is set if the received data did not have a valid parity bit. If the
FIFOs are enabled, the state of this bit is revealed when the referred byte is the next to be read.
OE Overrun Error.
0 Reset by the CPU reading this register.
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L Y
1 If the FIFOs are disabled, this bit is set if the RX Buffer was not read by the CPU before new data
SE AL
from the RX Shift Register overwrote the previous contents.
ON
If the FIFOs are enabled, an overrun error occurs when the RX FIFO is full and the RX Shift
Register becomes full. OE is set as soon as this happens. The character in the Shift Register is
then overwritten, but not transferred to the FIFO.
n U TI
DR Data Ready.
0 Cleared by the CPU reading the RX Buffer or by reading all the FIFO bytes.
1 Set by the RX Buffer becoming full or by a byte being transferred into the FIFO.
t.c EN
UARTn+0018h Modem Status Register UARTn_MSR
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DCD RI DSR CTS DDCD TERI DDSR DCTS
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset Input Input Input Input 0 0 0 0
ink NF
Note: After a reset, D4-D7 are inputs. A modem status interrupt can be cleared by writing ‘0’ or set by writing
‘1’ to this register. D0-D3 can be written to.
Modified when LCR[7] = 0.
MSR Modem Status Register
b-l CO
DCD Data Carry Detect.
When Loop = "0", this value is the complement of the NDCD input signal.
When Loop = "1", this value is equal to the OUT2 bit in the Modem Control Register.
RI Ring Indicator.
When Loop = "0", this value is the complement of the NRI input signal.
18 TEK
When Loop = "1", this value is equal to the OUT1 bit in the Modem Control Register.
DSR Data Set Ready
When Loop = "0", this value is the complement of the NDSR input signal.
When Loop = "1", this value is equal to the DTR bit in the Modem Control Register.
CTS Clear To Send.
@
When Loop = "0", this value is the complement of the NCTS input signal.
RD A
When Loop = "1", this value is equal to the RTS bit in the Modem Control Register.
DDCD Delta Data Carry Detect.
R DI
0 The state of DCD has not changed since the Modem Status Register was last read
1 Set if the state of DCD has changed since the Modem Status Register was last read.
TERI Trailing Edge Ring Indicator
FO ME
0 The NRI input does not change since this register was last read.
1 Set if the NRI input changes from “0” to “1” since this register was last read.
DDSR Delta Data Set Ready
0 Cleared if the state of DSR has not changed since this register was last read.
1 Set if the state of DSR has changed since this register was last read.
DCTS Delta Clear To Send
0 Cleared if the state of CTS has not changed since this register was last read.
1 Set if the state of CTS has changed since this register was last read.
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L Y
UARTn+001Ch Scratch Register UARTn_SCR
SE AL
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SCR[7:0]
Type R/W
n U TI
A general purpose read/write register. After reset, its value is un-defined.
Modified when LCR[7] = 0.
UARTn+0000h Divisor Latch (LS) UARTn_DLL
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLL[7:0]
Type R/W
Reset 1
.ne ID
UARTn+0004h Divisor Latch (MS) UARTn_DLM
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name DLL[7:0]
Type R/W
Reset 0
Note: DLL & DLM can only be updated if DLAB is set (“1”).. Note too that division by 1 generates a BAUD signal
b-l CO
that is constantly high.
Modified when LCR[7] = 1.
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13, 26 MHz and
52 MHz. The effective clock enable generated is 16 x the required baud rate.
BAUD 13MHz 26MHz 52MHz
110 7386 14773 29545
18 TEK
300 2708 5417 10833
1200 677 1354 2708
2400 338 677 1354
4800 169 339 677
9600 85 169 339
@
RD A
19200 42 85 169
38400 21 42 85
R DI
57600 14 28 56
115200 6 14 28
Table 2 Divisor needed to generate a given baud rate
FO ME
UARTn+0008h Enhanced Feature Register UARTn_EFR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTO AUTO ENABLE
Name D5 SW FLOW CONT[3:0]
CTS RTS -E
Type R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
*NOTE: Only when LCR=BF’h
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MT7621 PROGRAMMING GUIDE
L Y
Auto CTS Enables hardware transmission flow control
SE AL
0 Disabled.
ON
1 Enabled.
Auto RTS Enables hardware reception flow control
0 Disabled.
n U TI
1 Enabled.
Enable-E Enable enhancement features.
0 Disabled.
t.c EN
1 Enabled.
CONT[3:0] Software flow control bits.
00xx No TX Flow Control
10xx Transmit XON1/XOFF1 as flow control bytes
.ne ID
01xx Transmit XON2/XOFF2 as flow control bytes
11xx Transmit XON1 & XON2 and XOFF1 & XOFF2 as flow control words
xx00 No RX Flow Control
ink NF
xx10 Receive XON1/XOFF1 as flow control bytes
xx01 Receive XON2/XOFF2 as flow control bytes
xx11 Receive XON1 & XON2 and XOFF1 & XOFF2 as flow control words
b-l CO
UARTn+0010h XON1 UARTn_XON1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XON1[7:0]
Type R/W
Reset 0
18 TEK
UARTn+0014h XON2 UARTn_XON2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XON2[7:0]
Type R/W
@
Reset 0
RD A
UARTn+0018h XOFF1 UARTn_XOFF1
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF1[7:0]
Type R/W
FO ME
Reset 0
UARTn+001Ch XOFF2 UARTn_XOFF2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF2[7:0]
Type R/W
Reset 0
*Note: XON1, XON2, XOFF1, XOFF2 are valid only when LCR=BFh.
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L Y
SE AL
ON
UARTn+0024h HIGH SPEED UART UARTn_HIGHSPEED
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPEED [1:0]
Type R/W
n U TI
Reset 0
SPEED UART sample counter base
t.c EN
0 based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLH, DLL}
1 based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLH, DLL}
2 based on 4*baud_pulse, baud_rate = system clock frequency/4/{DLH, DLL}
3 based on sampe_count * baud_pulse, baud_rate = system clock frequency / sampe_count
.ne ID
When HIGHSPEED=3, the value (A * B) means ({DLM, DLL} * SAMPLE_COUNT).
When the Baudrate is more than 115200, it will be more accurate if we set HIGHSPEED=3.
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 13M Hz based on
different HIGHSPEED value.
ink NF
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 7386 14773 29545 7386 * 16
300 2708 7386 14773 2708 * 16
b-l CO
1200 677 2708 7386 677 * 16
2400 338 677 2708 338 * 16
4800 169 338 677 169 * 16
9600 85 169 338 85 * 16
18 TEK
19200 42 85 169 9 * 75
38400 21 42 85 13 * 26
57600 14 21 42 8 * 28
115200 7 14 21 4 * 28
230400 * 7 14 2 * 28
@
RD A
460800 * * 7 1 * 28
921600 * * * 1 * 14
R DI
Table 3 Divisor needed to generate a given baud rate from 13MHz based on different HIGHSPEED value
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 26 MHz based on
FO ME
different HIGHSPEED value.
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 14773 29545 59091 7386 * 32
300 5417 14773 29545 2708 * 32
1200 1354 5417 14773 677 * 32
2400 677 1354 5417 338 * 32
4800 339 677 1354 169 * 32
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L Y
9600 169 339 667 85 * 32
SE AL
19200 85 169 339 18 * 75
ON
38400 42 85 169 26 * 26
57600 28 42 85 16 * 28
n U TI
115200 14 28 42 8 * 28
230400 7 14 28 4 * 28
460800 * 7 14 2 * 28
t.c EN
921600 * * 7 1 * 28
Table 4 Divisor needed to generate a given baud rate from 26 MHz based on different HIGHSPEED value
.ne ID
The table below shows the divisor needed to generate a given baud rate from CLK inputs of 52MHz based on
different HIGHSPEED value.
BAUD HIGHSPEED = 0 HIGHSPEED = 1 HIGHSPEED = 2 HIGHSPEED = 3
110 29545 59091 118182 14773 * 32
ink NF
300 10833 29545 59091 5417 * 32
1200 2708 10833 29545 1354 * 32
2400 1354 2708 10833 667 * 32
b-l CO
4800 677 1354 2708 339 * 32
9600 339 677 1354 169 * 32
19200 169 339 677 36 * 75
38400 85 169 339 52 * 26
18 TEK
57600 56 85 169 32 * 28
115200 28 56 85 16 * 28
230400 14 28 56 8 * 28
460800 7 14 28 4 * 28
@
921600 * 7 14 2 * 28
RD A
Table 5 Divisor needed to generate a given baud rate from 52 MHz based on different HIGHSPEED value
R DI
UARTn+0028h SAMPLE_COUNT UARTn_SAMPLE_COUNT
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLECOUNT [7:0]
Type R/W
Reset 0
When HIGHSPEED=3, the sample_count is the threshold value for UART sample counter (sample_num).
Count from 0 to sample_count.
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L Y
UARTn+002Ch SAMPLE_POINT UARTn_SAMPLE_POINT
SE AL
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLEPOINT [7:0]
Type R/W
Reset Ffh
n U TI
When HIGHSPEED=3, UART gets the input data when sample_count=sample_num.
e.g. system clock = 13MHz, 921600 = 13000000 / 14
t.c EN
sample_count = 14 and sample point = 7 (sample the central point to decrease the inaccuracy)
The SAMPLE_POINT is usually (SAMPLE_COUNT/2).
UARTn+0034h Rate Fix Address UARTn_RATEFIX_AD
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTE_FIX
Type R/W
ink NF
Reset 0
rate_fix When you set "rate_fix"(34H[0]), you can transmit and receive data only if
the input f16m_en is enable.
b-l CO
UARTn+003Ch Guard time added register UARTn_GUARD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUARD_EN GUARD_CNT[3:0]
18 TEK
Type R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
GUARD_CNT Guard interval count value. Guard interval = (1/(system clock / div_step / div )) *
GUARD_CNT.
GUARD_EN Guard interval add enable signal.
@
0 No guard interval added.
RD A
1 Add guard interval after stop bit.
R DI
UARTn+0040h Escape character register UARTn_ESCAPE_DAT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ESCAPE_DAT[7:0]
Type WO
FO ME
Reset FFh
ESCAPE_DAT Escape character added before software flow control data and escape character, i.e. if tx data is
xon (31h), with esc_en =1, uart transmits data as esc + CEh (~xon).
UARTn+0044h Escape enable register UARTn_ESCAPE_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ESC_EN
Type R/W
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L Y
Reset 0
SE AL
ESC_EN Add escape character in transmitter and remove escape character in receiver by UART.
ON
0 Do not deal with the escape character.
1 Add escape character in transmitter and remove escape character in receiver.
n U TI
UARTn+0048h Sleep enable register UARTn_SLEEP_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SELLP_EN
t.c EN
Type R/W
Reset 0
SLEEP_EN For sleep mode issue
0 Do not deal with sleep mode indicate signal
.ne ID
1 To activate hardware flow control or software control according to software initial setting when
chip enters sleep mode. Releasing hardware flow when chip wakes up; but for software control,
uart sends xon when awaken and when FIFO does not reach threshold level.
ink NF
UARTn+004Ch Virtual FIFO enable register UARTn_VFIFO_EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VFIFO_EN
b-l CO
Type R/W
Reset 0
VFIFO_EN Virtual FIFO mechanism enable signal.
0 Disable VFIFO mode.
1 Enable VFIFO mode. When virtual mode is enabled, the flow control is based on the DMA
18 TEK
threshold, and generates a timeout interrupt for DMA.
UARTn+0050h Rx Trigger Address UARTn_RXTRI_AD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTRIG[3:0]
Type R/W
@
Reset 0
RD A
RXTRIG When {rtm,rtl}=2’b11, The Rx FIFO threshold will be Rxtrig.
R DI
UARTn+0054h Fractional Divider LSB Address UARTn_FRACDIV_L
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name FRACDIV_L
Type R/W
Reset 0 0 0 0 0 0 0 0
FRACDIV_L Add sampling count (+1) from state data7 to state data0, in order to contribute fractional
divisor.
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MT7621 PROGRAMMING GUIDE
L Y
UARTn+0058h Fractional Divider MSB Address UARTn_FRACDIV_M
SE AL
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FRACDIV_M
Type R/W
Reset 0 0
n U TI
FRACDIV_M Add sampling count in state stop and state parity, in order to contribute fractional divisor.
FRACDIV_L / FRACDIV_L Add one sampling period to each symbol, in order to increase the baud rate
t.c EN
accuracy.
bit_extend register = FRACDIV_L[7:0]
.ne ID
FRACDIV_M[1:0]
ink NF
Start d0 d1 d2 d3 d4 d5 d6 d7 Parity Stop
n n + L[0] n + L[1] n + L[2] n + L[3] n + L[4] n + L[5] n + L[6] n + L[7] n + M[0] n + M[1]
b-l CO
m
18 TEK
UARTn+005Ch FIFO Control Register UARTn_FCR_RD
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RFTL1 RFTL0 TFTL1 TFTL0 DMA1 FIFOE
Type RO RO
Read out UARTn_FCR register.
@
RD A
UARTn+0060h TX Active Enable Address UARTn_TX_ACTIVE_EN
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PU_EN TX_OE_EN
Type R/W R/W
FO ME
Reset 0 0
TX_OE_EN Enable UART_TX_OE switching function. TX_OE is to control UART_TX output enable.
TX_PU_EN Enable UART_TX_PU switching function. TX_PU is to control UART_TX pull up enable.
PGMT7621_V.1.0_130607 Page 64 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.6 Programmable I/O
ON
2.6.1 Features
Parameterized numbers of independent inputs, outputs, and inouts
Independent polarity controls for each pin
n U TI
Independently masked edge detect interrupt on any input transition
2.6.2 Block Diagram
t.c EN
gpio_top cfg_ctrl[95:0] gpio_oe[95:0]
x96
gpio_reg cfg_data[95:0] gpio_control gpio_out[95:0]
.ne ID
PBus signals
Configuration
gpio_in[95:0]
ink NF
Registers
gpio_interrupt
gpio_int I/O PAD
b-l CO
Figure 2-3 Programmable I/O Block Diagram
2.6.3 GPIO pin mapping
PAD Name Function 0 Function 1 Function 2 Function 3 strap pmux_group GPIO
18 TEK
PAD_GPIO0 gpio (I/O) 0 gpio_psel[0] 0
PAD_RXD1 rxd1 (I) gpio (I/O) 1
uartl_psel[0]
PAD_TXD1 txd1 (O) gpio (I/O) 1 2
PAD_I2C_SD i2c_sd (I/O) gpio (I/O) 3
i2c_psel[0]
PAD_I2C_SCLK i2c_sclk (I/O) gpio (I/O) 4
@
PAD_RTS3_N rts3_n (O) gpio (I/O) i2s_sdo (O) spdif_tx (O) 2 5
RD A
PAD_CTS3_N cts3_n (I) gpio (I/O) i2s_clk (I/O) gpio (I/O) 6
uart3_psel[1:0]
PAD_TXD3 txd3 (O) gpio (I/O) i2s_ws (I/O) gpio (I/O) 7
R DI
PAD_RXD3 rxd3 (I) gpio (I/O) i2s_sdi (I) gpio (I/O) 8
PAD_RTS2_N rts2_n (O) gpio (I/O) pcm_dtx (I/O) gpio (I/O) 3 9
PAD_CTS2_N cts2_n (I) gpio (I/O) pcm_drx (I) gpio (I/O) 10
uart2_psel[1:0]
FO ME
PAD_TXD2 txd2 (O) gpio (I/O) pcm_clk (O) spdif_tx (O) 4 11
PAD_RXD2 rxd2 (I) gpio (I/O) pcm_fs (I/O) gpio (I/O) 12
PAD_JTDO jtdo (I/O) gpio (I/O) 13
PAD_JTDI jtdi (I) gpio (I/O) 14
PAD_JTMS jtms (I) gpio (I/O) jtag_psel[0] 15
PAD_JTCLK jtclk (I) gpio (I/O) 16
PAD_JTRST_N jtrst_n (I) gpio (I/O) 17
PAD_WDT_RST_N wdt_rst_n (I/O) gpio (I/O) ref_clk0_out (O) wdt_psel[1:0] 18
PAD_PERST_N perst_n (O) gpio (I/O) ref_clk0_out (O) 5 perst_psel[1:0] 19
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MT7621 PROGRAMMING GUIDE
L Y
PAD_MDIO mdio (I/O) gpio (I/O) gpio (I/O) 20
mdio_psel[1:0]
SE AL
PAD_MDC mdc (O) gpio (I/O) ref_clk0_out (O) 6 21
ON
PAD_G1_TXD0 g1_txd[0] (I/O) gpio (I/O) 49
PAD_G1_TXD1 g1_txd[1] (I/O) gpio (I/O) 50
PAD_G1_TXD2 g1_txd[2] (I/O) gpio (I/O) 51
n U TI
PAD_G1_TXD3 g1_txd[3] (I/O) gpio (I/O) 52
PAD_G1_TXEN g1_txen (I/O) gpio (I/O) 53
PAD_G1_TXC g1_txc (I/O) gpio (I/O) 54
t.c EN
rgmii1_psel[0]
PAD_G1_RXD0 g1_rxd[0] (I/O) gpio (I/O) 55
PAD_G1_RXD1 g1_rxd[1] (I/O) gpio (I/O) 56
PAD_G1_RXD2 g1_rxd[2] (I/O) gpio (I/O) 57
PAD_G1_RXD3 g1_rxd[3] (I/O) gpio (I/O) 58
.ne ID
PAD_G1_RXDV g1_rxdv (I/O) gpio (I/O) 59
PAD_G1_RXC g1_rxc (I/O) gpio (I/O) 60
PAD_G2_TXD0 g2_txd[0] (I/O) gpio (I/O) 22
ink NF
PAD_G2_TXD1 g2_txd[1] (I/O) gpio (I/O) 23
PAD_G2_TXD2 g2_txd[2] (I/O) gpio (I/O) 24
PAD_G2_TXD3 g2_txd[3] (I/O) gpio (I/O) 25
PAD_G2_TXEN 26
b-l CO
g2_txen (I/O) gpio (I/O)
PAD_G2_TXC g2_txc (I/O) gpio (I/O) 27
rgmii2_psel[0]
PAD_G2_RXD0 g2_rxd[0] (I/O) gpio (I/O) 28
PAD_G2_RXD1 g2_rxd[1] (I/O) gpio (I/O) 29
PAD_G2_RXD2 g2_rxd[2] (I/O) gpio (I/O) 30
18 TEK
PAD_G2_RXD3 g2_rxd[3] (I/O) gpio (I/O) 31
PAD_G2_RXDV g2_rxdv (I/O) gpio (I/O) 32
PAD_G2_RXC g2_rxc (I/O) gpio (I/O) 33
PAD_SPI_CS0_N spi_cs0 (I/O) gpio (I/O) nd_cs_n (O) 7 34
PAD_SPI_CS1_N spi_cs1 (I/O) gpio (I/O) nd_we_n (O) 8 35
PAD_SPI_SCLK spi_clk (I/O) 36
@
gpio (I/O) nd_re_n (O) 9
RD A
PAD_SPI_MISO spi_miso (I/O) gpio (I/O) nd_d[4] (I/O) spi_psel[1:0] 37
PAD_SPI_MOSI spi_mosi (I/O) gpio (I/O) nd_d[5] (I/O) 38
R DI
PAD_SPI_WP_N spi_wp (I/O) gpio (I/O) nd_d[6] (I/O) 39
PAD_SPI_HOLD_N spi_hold (I/O) gpio (I/O) nd_d[7] (I/O) 40
PAD_SD_WP sd_wp (I) gpio (I/O) nd_wp (O) 41
FO ME
PAD_SD_CLK sd_clk (I/O) gpio (I/O) nd_rb_n (I) 42
PAD_SD_CD sd_cd (I) gpio (I/O) nd_cle (O) 43
PAD_SD_CMD sd_cmd (I/O) gpio (I/O) nd_ale (O) 44
sd_psel[1:0]
PAD_SD_D0 sd_data[0] (I/O) gpio (I/O) nd_d[0] (I/O) 45
PAD_SD_D1 sd_data[1] (I/O) gpio (I/O) nd_d[1] (I/O) 46
PAD_SD_D2 sd_data[2] (I/O) gpio (I/O) nd_d[2] (I/O) 47
PAD_SD_D3 sd_data[3] (I/O) gpio (I/O) nd_d[3] (I/O) 48
PAD_ESW_INT esw_int(I) gpio (I/O) esw_psel[0] 61
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.6.4 Registers
ON
Module name: GPIO Base address: (+1E000600h)
Address Name Width Register Function
n U TI
1E000600 GPIO_CTRL_0 32 GPIO0 to GPIO31 direction control register
These direction control registers are used to select the data direction of the GPIO
pin.
The value driven onto the GPIO pins, are controlled by the GPIO_POL_x, and
t.c EN
GPIO_DATA_x registers.
1E000604 GPIO_CTRL_1 32 GPIO32 to GPIO63 direction control register
These direction control registers are used to select the data direction of the GPIO
pin.
The value driven onto the GPIO pins, are controlled by the GPIO_POL_x, and
GPIO_DATA_x registers.
.ne ID
1E000608 GPIO_CTRL_2 32 GPIO64 to GPIO95 direction control register
These direction control registers are used to select the data direction of the GPIO
pin.
The value driven onto the GPIO pins, are controlled by the GPIO_POL_x, and
ink NF
GPIO_DATA_x registers.
1E000610 GPIO_POL_0 32 GPIO0 to GPIO31 polarity control register
These polarity control registers are used to control the polarity of the data is
driven on or read from the GPIO pin.
1E000614 GPIO_POL_1 32 GPIO32 to GPIO63 polarity control register
b-l CO
These polarity control registers are used to control the polarity of the data is
driven on or read from the GPIO pin.
1E000618 GPIO_POL_2 32 GPIO64 to GPIO95 polarity control register
These polarity control registers are used to control the polarity of the data is
driven on or read from the GPIO pin.
1E000620 GPIO_DATA_0 32 GPIO0 to GPIO31 data register
18 TEK
These data registers store current GPIO data value for GPIO input mode, or output
driven value for GPIO output mode.
Bit position stand for correspondent GPIO pin.
1E000624 GPIO_DATA_1 32 GPIO32 to GPIO63 data register
These data registers store current GPIO data value for GPIO input mode, or output
driven value for GPIO output mode.
Bit position stand for correspondent GPIO pin.
@
1E000628 GPIO_DATA_2 32 GPIO64 to GPIO95 data register
RD A
These data registers store current GPIO data value for GPIO input mode, or output
driven value for GPIO output mode.
Bit position stand for correspondent GPIO pin.
R DI
1E000630 GPIO_DSET_0 32 GPIO0 to GPIO31 data set register
These data set registers are used to set bits in the GPIO_DATA_x registers.
1E000634 GPIO_DSET_1 32 GPIO32 to GPIO63 data set register
These data set registers are used to set bits in the GPIO_DATA_x registers.
FO ME
1E000638 GPIO_DSET_2 32 GPIO64 to GPIO95 data set register
These data set registers are used to set bits in the GPIO_DATA_x registers.
1E000640 GPIO_DCLR_0 32 GPIO0 to GPIO31 data clear register
These data set registers are used to clear bits in the GPIO_DATA_x registers.
1E000644 GPIO_DCLR_1 32 GPIO32 to GPIO63 data clear register
These data set registers are used to clear bits in the GPIO_DATA_x registers.
1E000648 GPIO_DCLR_2 32 GPIO64 to GPIO95 data clear register
These data set registers are used to clear bits in the GPIO_DATA_x registers.
1E000650 GINT_REDGE_0 32 GPIO0 to GPIO31 rising edge interrupt enable register
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MT7621 PROGRAMMING GUIDE
L Y
These registers are used to enable the condition of rising edge triggered interrupt.
SE AL
1E000654 GINT_REDGE_1 32 GPIO32 to GPIO63 rising edge interrupt enable register
ON
These registers are used to enable the condition of rising edge triggered interrupt.
1E000658 GINT_REDGE_2 32 GPIO64 to GPIO95 rising edge interrupt enable register
These registers are used to enable the condition of rising edge triggered interrupt.
1E000660 GINT_FEDGE_0 32 GPIO0 to GPIO31 falling edge interrupt enable register
n U TI
These registers are used to enable the condition of falling edge triggered interrupt.
1E000664 GINT_FEDGE_1 32 GPIO32 to GPIO63 falling edge interrupt enable register
These registers are used to enable the condition for falling edge triggered
interrupt.
t.c EN
1E000668 GINT_FEDGE_2 32 GPIO64 to GPIO95 falling edge interrupt enable register
These registers are used to enable the condition of falling edge triggered interrupt.
1E000670 GINT_HLVL_0 32 GPIO0 to GPIO31 high level interrupt enable register
These registers are used to enable the condition of high level triggered interrupt.
.ne ID
The bit in this register and the corresponded bit in GINT_LLVL_0 cannot be set to 1
at the same time.
1E000674 GINT_HLVL_1 32 GPIO32 to GPIO63 high level interrupt enable register
These registers are used to enable the condition of high level triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_1 cannot be set to 1
ink NF
at the same time.
1E000678 GINT_HLVL_2 32 GPIO64 to GPIO95 high level interrupt enable register
These registers are used to enable the condition of high level triggered interrupt.
The bit in this register and the corresponded bit in GINT_LLVL_2 cannot be set to 1
at the same time.
b-l CO
1E000680 GINT_LLVL_0 32 GPIO0 to GPIO31 low level interrupt enable register
These registers are used to enable the condition of low level triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_0 cannot be set to 1
at the same time.
1E000684 GINT_LLVL_1 32 GPIO32 to GPIO63 low level interrupt enable register
These registers are used to enable the condition of low level triggered interrupt.
18 TEK
The bit in this register and the corresponded bit in GINT_HLVL_1 cannot be set to 1
at the same time.
1E000688 GINT_LLVL_2 32 GPIO64 to GPIO95 low level interrupt enable register
These registers are used to enable the condition of low level triggered interrupt.
The bit in this register and the corresponded bit in GINT_HLVL_2 cannot be set to 1
at the same time.
1E000690 GINT_STAT_0 32 GPIO0 to GPIO31 interrupt status register
@
These registers are used to record the GPIO current interrupt status.
RD A
1E000694 GINT_STAT_1 32 GPIO32 to GPIO63 interrupt status register
These registers are used to record the GPIO current interrupt status.
R DI
1E000698 GINT_STAT_2 32 GPIO64 to GPIO95 interrupt status register
These registers are used to record the GPIO current interrupt status.
1E0006A0 GINT_EDGE_0 32 GPIO0 to GPIO31 edge status register
These registers are used to record the GPIO current interrupt's edge status.
FO ME
These registers are useful only in edge triggered interrupt.
1E0006A4 GINT_EDGE_1 32 GPIO32 to GPIO63 edge status register
These registers are used to record the GPIO current interrupt's edge status.
These registers are useful only in edge triggered interrupt.
1E0006A8 GINT_EDGE_2 32 GPIO64 to GPIO95 edge status register
These registers are used to record the GPIO current interrupt's edge status.
These registers are useful only in edge triggered interrupt.
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E000600 GPIO_CTRL_0 GPIO0 to GPIO31 direction control register 00000000
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOCTRL0[31:16]
Type RW
Reset
n U TI
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOCTRL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 GPIOCTRL0 GPIO Pin Direction
0: GPIO input mode
.ne ID
1: GPIO output mode
1E000604 GPIO_CTRL_1 GPIO32 to GPIO63 direction control register 00000000
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOCTRL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name GPIOCTRL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIOCTRL1 GPIO Pin Direction
0: GPIO input mode
1: GPIO output mode
18 TEK
1E000608 GPIO_CTRL_2 GPIO64 to GPIO95 direction control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOCTRL2[31:16]
Type RW
@
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOCTRL2[15:0]
Type RW
R DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
31:0 GPIOCTRL2 GPIO Pin Direction
0: GPIO input mode
1: GPIO output mode
1E000610 GPIO_POL_0 GPIO0 to GPIO31 polarity control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Name GPIOPOL0[15:0]
Type
SE AL
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31:0 GPIOPOL0 GPIO Data Polarity
n U TI
0: Data is non-inverted
1: Data is inverted
t.c EN
1E000614 GPIO_POL_1 GPIO32 to GPIO63 polarity control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOPOL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:0 GPIOPOL1 GPIO Data Polarity
0: Data is non-inverted
1: Data is inverted
b-l CO
1E000618 GPIO_POL_2 GPIO64 to GPIO95 polarity control register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIOPOL2[31:16]
Type RW
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIOPOL2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit(s) Name Description
RD A
31:0 GPIOPOL2 GPIO Data Polarity
0: Data is non-inverted
1: Data is inverted
R DI
1E000620 GPIO_DATA_0 GPIO0 to GPIO31 data register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name GPIODATA0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODATA0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODATA0 GPIO Data
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E000624 GPIO_DATA_1 GPIO32 to GPIO63 data register 00000000
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODATA1[31:16]
Type RW
Reset
n U TI
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODATA1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 GPIODATA1 GPIO Data
.ne ID
1E000628 GPIO_DATA_2 GPIO64 to GPIO95 data register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODATA2[31:16]
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODATA2[15:0]
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODATA2 GPIO Data
18 TEK
1E000630 GPIO_DSET_0 GPIO0 to GPIO31 data set register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODSET0[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET0[15:0]
@
Type WO
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:0 GPIODSET0 GPIO Data Set
1: Set the GPIO_DATA_0 register
0: No effect
FO ME
1E000634 GPIO_DSET_1 GPIO32 to GPIO63 data set register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODSET1[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET1[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31:0 GPIODSET1 GPIO Data Set
1: Set the GPIO_DATA_1 register
0: No effect
n U TI
1E000638 GPIO_DSET_2 GPIO64 to GPIO95 data set register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name GPIODSET2[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODSET2[15:0]
Type WO
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
31:0 GPIODSET2 GPIO Data Set
1: Set the GPIO_DATA_2 register
0: No effect
b-l CO
1E000640 GPIO_DCLR_0 GPIO0 to GPIO31 data clear register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR0[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODCLR0[15:0]
18 TEK
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODCLR0 GPIO Data Clear
1: Clear the GPIO_DATA_0 register
@
0: No effect
RD A
1E000644 GPIO_DCLR_1 GPIO32 to GPIO63 data clear register 00000000
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GPIODCLR1[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GPIODCLR1[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GPIODCLR1 GPIO Data Clear
1: Clear the GPIO_DATA_1 register
0: No effect
PGMT7621_V.1.0_130607 Page 72 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1E000648 GPIO_DCLR_2 GPIO64 to GPIO95 data clear register 00000000
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name GPIODCLR2[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name GPIODCLR2[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 GPIODCLR2 GPIO Data Clear
1: Clear the GPIO_DATA_2 register
0: No effect
.ne ID
1E000650 GINT_REDGE_0 GPIO0 to GPIO31 rising edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ink NF
Name GINTREDGE0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTREDGE0[15:0]
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTREDGE0 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
18 TEK
0: Disable rising edge triggered
1E000654 GINT_REDGE_1 GPIO32 to GPIO63 rising edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTREDGE1[31:16]
Type RW
@
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTREDGE1[15:0]
Type RW
R DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
31:0 GINTREDGE1 GPIO Rising Edge Interrupt Enable
1: Enable rising edge triggered
0: Disable rising edge triggered
1E000658 GINT_REDGE_2 GPIO64 to GPIO95 rising edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTREDGE2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGMT7621_V.1.0_130607 Page 73 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Name GINTREDGE2[15:0]
Type
SE AL
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31:0 GINTREDGE2 GPIO Rising Edge Interrupt Enable
n U TI
1: Enable rising edge triggered
0: Disable rising edge triggered
t.c EN
1E000660 GINT_FEDGE_0 GPIO0 to GPIO31 falling edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTFEDGE0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:0 GINTFEDGE0 GPIO Falling Edge Interrupt Enable
1: Enable falling edge triggered
0: Disable falling edge triggered
b-l CO
1E000664 GINT_FEDGE_1 GPIO32 to GPIO63 falling edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTFEDGE1[31:16]
Type RW
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit(s) Name Description
RD A
31:0 GINTFEDGE1 GPIO Falling Edge Interrupt Enable
1: Enable falling edge triggered
0: Disable falling edge triggered
R DI
1E000668 GINT_FEDGE_2 GPIO64 to GPIO95 falling edge interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name GINTFEDGE2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTFEDGE2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTFEDGE2 GPIO Falling Edge Interrupt Enable
PGMT7621_V.1.0_130607 Page 74 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: Enable falling edge triggered
0: Disable falling edge triggered
SE AL
ON
1E000670 GINT_HLVL_0 GPIO0 to GPIO31 high level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name GINTHLVL0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL0[15:0]
t.c EN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:0 GINTHLVL0 GPIO High Level Interrupt Enable
1: Enable high level triggered
0: Disable high level triggered
ink NF
1E000674 GINT_HLVL_1 GPIO32 to GPIO63 high level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTHLVL1[31:16]
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 GINTHLVL1 GPIO High Level Interrupt Enable
1: Enable high level triggered
0: Disable high level triggered
1E000678 GINT_HLVL_2 GPIO64 to GPIO95 high level interrupt enable register 00000000
@
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD A
Name GINTHLVL2[31:16]
Type RW
Reset
R DI
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTHLVL2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31:0 GINTHLVL2 GPIO High Level Interrupt Enable
1: Enable high level triggered
0: Disable high level triggered
1E000680 GINT_LLVL_0 GPIO0 to GPIO31 low level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTLLVL0[31:16]
PGMT7621_V.1.0_130607 Page 75 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Name GINTLLVL0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:0 GINTLLVL0 GPIO Low Level Interrupt Enable
1: Enable low level triggered
t.c EN
0: Disable low level triggered
1E000684 GINT_LLVL_1 GPIO32 to GPIO63 low level interrupt enable register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.ne ID
Name GINTLLVL1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name GINTLLVL1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
31:0 GINTLLVL1 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
1E000688 GINT_LLVL_2 GPIO64 to GPIO95 low level interrupt enable register 00000000
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTLLVL2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTLLVL2[15:0]
Type RW
@
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit(s) Name Description
R DI
31:0 GINTLLVL2 GPIO Low Level Interrupt Enable
1: Enable low level triggered
0: Disable low level triggered
FO ME
1E000690 GINT_STAT_0 GPIO0 to GPIO31 interrupt status register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTSTAT0[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT0[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
31:0 GINTSTAT0 GPIO Interrupt Status
ON
1: Interrupt is detected
0: Interrupt is not detected
n U TI
1E000694 GINT_STAT_1 GPIO32 to GPIO63 interrupt status register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTSTAT1[31:16]
Type W1C
t.c EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT1[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 GINTSTAT1 GPIO Interrupt Status
1: Interrupt is detected
ink NF
0: Interrupt is not detected
1E000698 GINT_STAT_2 GPIO64 to GPIO95 interrupt status register 00000000
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTSTAT2[31:16]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTSTAT2[15:0]
Type W1C
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTSTAT2 GPIO Interrupt Status
1: Interrupt is detected
0: Interrupt is not detected
@
1E0006A0 GINT_EDGE_0 GPIO0 to GPIO31 edge status register 00000000
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTEDGE0[31:16]
R DI
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE0[15:0]
Type W1C
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 GINTEDGE0 GPIO Interrupt Edge Status
1: Rising edge
0: Falling edge
1E0006A4 GINT_EDGE_1 GPIO32 to GPIO63 edge status register 00000000
PGMT7621_V.1.0_130607 Page 77 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SE AL
Name GINTEDGE1[31:16]
Type W1C
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE1[15:0]
Type W1C
n U TI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
t.c EN
31:0 GINTEDGE1 GPIO Interrupt Edge Status
1: Rising edge
0: Falling edge
.ne ID
1E0006A8 GINT_EDGE_2 GPIO64 to GPIO95 edge status register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GINTEDGE2[31:16]
Type W1C
ink NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GINTEDGE2[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
31:0 GINTEDGE2 GPIO Interrupt Edge Status
1: Rising edge
0: Falling edge
18 TEK
@
RD A
R DI
FO ME
PGMT7621_V.1.0_130607 Page 78 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2
2.7 I C Controller
ON
2.7.1 Features
2
Programmable I C bus clock rate
2
Supports the Synchronous Inter-Integrated Circuits (I C) serial protocol
n U TI
Bi-directional data transfer
Programmable address width up to 8 bits
Sequential byte read or write capability
t.c EN
Device address and data address can be transmitted for device, page and address selection
Supports Standard mode and Fast mode
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
PGMT7621_V.1.0_130607 Page 79 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.7.2 List of Registers
ON
Address Name Widt Register Function
h
n U TI
1E000908 SM0CFG0 32 SERIAL INTERFACE MASTER 0 CONFIG 0 REGISTER
1E000910 SM0DOUT 32 SERIAL INTERFACE MASTER 0 DATAOUT REGISTER
1E000914 SM0DIN 32 SERIAL INTERFACE MASTER 0 DATAIN REGISTER
t.c EN
1E000918 SM0ST 32 SERIAL INTERFACE MASTER 0 STATUS REGISTER
1E00091C SM0AUTO 32 SERIAL INTERFACE MASTER 0 AUTO-MODE REGISTER
1E000920 SM0CFG1 32 SERIAL INTERFACE MASTER 0 CONFIG 1 REGISTER
1E000928 SM0CFG2 32 SERIAL INTERFACE MASTER 0 CONFIG 2 REGISTER
1E000940 SM0CTL0 32 Serial interface master 0 control 0 register
.ne ID
1E000944 SM0CTL1 32 Serial interface master 0 control 1 register
1E000950 SM0D0 32 Serial interface master 0 data 0 register
1E000954 SM0D1 32 Serial interface master 0 data 1 register
ink NF
1E00095C PINTEN 32 Peripheral interrupt enable register
1E000960 PINTST 32 Peripheral interrupt status register
1E000964 PINTCL 32 Peripheral interrupt clear register
b-l CO
1E000908 SM0CFG0 SERIAL INTERFACE MASTER 0 CONFIG 0 REGISTER 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[24:9]
18 TEK
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[8:0] SM0_DEVADDR
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
RD A
31:7 RSV0 Reserved
6:0 SM0_DEVADDR Device address for transmission
R DI
1E000910 SM0DOUT SERIAL INTERFACE MASTER 0 DATAOUT 0000000
REGISTER 0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[7:0] SM0_DATAOUT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
31:8 RSV0 Reserved
SE AL
7:0 SM0_DATAOUT Data out register for auto mode
ON
1E000914 SM0DIN SERIAL INTERFACE MASTER 0 DATAIN REGISTER 0000000
n U TI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
Type RO
t.c EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[7:0] SM0_DATAIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:8 RSV0 Reserved
7:0 SM0_DATAIN Data in register for auto mode
ink NF
1E000918 SM0ST SERIAL INTERFACE MASTER 0 STATUS REGISTER 0000000
2
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[28:13]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
SM
18 TEK
0_
0_R SM
WD
DA 0_B
RSV0[12:0] AT
TA_ US
A_E
RD Y
MP
Y
TY
Type RO RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
@
RD A
Bit(s) Name Description
31:3 RSV0 Reserved
R DI
2 SM0_RDATA_RDY I2C read data is ready
1 SM0_WDATA_EMPTY I2C data output register is empty
0 SM0_BUSY State machine is busy
FO ME
1E00091C SM0AUTO SERIAL INTERFACE MASTER 0 AUTO-MODE 0000000
REGISTER 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
RSV0[14:0]
0_S
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MT7621 PROGRAMMING GUIDE
L Y
TA
SE AL
RT_
RW
ON
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
31:1 RSV0 Reserved
0 SM0_START_RW Written with 1 to start a read transaction, and 0 to start a write transaction. This
bit is only valid at auto mode.
t.c EN
1E000920 SM0CFG1 SERIAL INTERFACE MASTER 0 CONFIG 1 REGISTER 0000000
0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[25:10]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name RSV0[9:0] SM0_BYTECNT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
31:6 RSV0 Reserved
5:0 SM0_BYTECNT The value + 1 indicateds the number of data bytes for sequential reads/writes.
(word address is included in data bytes)
18 TEK
1E000928 SM0CFG2 SERIAL INTERFACE MASTER 0 CONFIG 2 REGISTER 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
RD A
Name SM
0_I
S_A
RSV0[14:0] UT
R DI
OM
OD
E
Type RO RW
Reset
FO ME
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:1 RSV0 Reserved
0 SM0_IS_AUTOMODE Set 1 to configure auto mode
1E000940 SM0CTL0 Serial interface master 0 control 0 register 0000034
C
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MT7621 PROGRAMMING GUIDE
L Y
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SE AL
Name SM
0_O RS SM0_VSY
ON
SM0_CLK_DIV
DR V0 NC_MODE
AIN
Type RW RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
SM
SM SM SM
0_ SM 0_S 0_S 0_S
0_C SM
RS WAI 0_D CL_ DA CL_
SM0_DEG_CNT S_S 0_E
V1 T_L EG ST _ST ST
t.c EN
TAT N
EV _EN AT AT RE
US
EL E E CH
Type RW RO RW RW RO RO RO RW RW
Reset 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0
.ne ID
Bit(s) Name Description
31 SM0_ODRAIN Open-drain output configuration
0: When SIF output is logic 1, the output is pulled high by outer devices. SIF output is
open-drained.
ink NF
1: When SIF output is logic 1, the output is pulled high by SIF master 0.
30 RSV0 Reserved
29:28 SM0_VSYNC_MODE Restrict SIF master 0 trigger within VSYNC pulse
00: Disable
01: Allow triggered in VSYNC pulse
b-l CO
10: Allow triggered at VSYNC rising edge
27:16 SM0_CLK_DIV SIF master 0 clock divide value
This is used to set the divider to generate expected SCL.
15:8 SM0_DEG_CNT SIF master 0 de-glitch value
This is used to set the de-glitch number of SDA and SCL input.
7 RSV1 Reserved
18 TEK
6 SM0_WAIT_LEVEL SIF master 0 wait level configuration
0: output L when SIF master 0 is in WAIT state
1: output H when SIF master 0 is in WAIT state
5 SM0_DEG_EN SIF master 0 de-glitch enable bit
0: Disable SIF master de-glitch.
1: Enable SIF master de-glitch.
4 SM0_CS_STATUS Clock stretching status
@
0: no clock stretching
RD A
1: clock stretching
3 SM0_SCL_STATE SCL value on the bus
R DI
2 SM0_SDA_STATE SDA value on the bus
1 SM0_EN SIF master 0 enable bit
0: Disable SIF master 0.
1: Enable SIF master 0.
FO ME
0 SM0_SCL_STRECH Clock stretching enable
0: Not allow slaves hold SCL
1: Allow slaves hold SCL
1E000944 SM0CTL1 Serial interface master 0 control 1 register 0000008
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV3 SM0_ACK
Type RO RO
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
ON
RS
RSV2 SM0_PGLEN SM0_MODE RSV0 0_T
V1
RI
Type RO RW RO RW RO RW
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:24 RSV3 Reserved
t.c EN
23:16 SM0_ACK Acknowledge bits
ACK[7:0] is acknowledge of 8 bytes of data
15:11 RSV2 Reserved
10:8 SM0_PGLEN Page length
Page length of sequential read/write. The maximum is 8 bytes. Set 0 as 1 byte.
.ne ID
7 RSV1 Reserved
6:4 SM0_MODE SIF master mode
001: Start
010: Write data
ink NF
011: Stop
100: Read data with no ack for final byte
101: Read data with ack
3:1 RSV0 Reserved
0 SM0_TRI Trigger serial interface
b-l CO
0: Read back as serial interface is idle.
1: Set 1 to trigger this serial interface. Read back as serial interface is busy.
1E000950 SM0D0 Serial interface master 0 data 0 register FFFFFF
FF
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SM0_DATA3 SM0_DATA2
Type RW RW
Reset x x x x x x x x x x x x x x x x
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM0_DATA1 SM0_DATA0
Type RW RW
@
Reset x x x x x x x x x x x x x x x x
RD A
Bit(s) Name Description
R DI
31:24 SM0_DATA3 Serial interface data byte 3
23:16 SM0_DATA2 Serial interface data byte 2
15:8 SM0_DATA1 Serial interface data byte 1
FO ME
7:0 SM0_DATA0 Serial interface data byte 0
1E000954 SM0D1 Serial interface master 0 data 1 register FFFFFF
FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SM0_DATA7 SM0_DATA6
Type RW RW
Reset x x x x x x x x x x x x x x x x
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Name SM0_DATA5 SM0_DATA4
SE AL
Type RW RW
Reset x x x x x x x x x x x x x x x x
ON
Bit(s) Name Description
31:24 SM0_DATA7 Serial interface data byte 7
n U TI
23:16 SM0_DATA6 Serial interface data byte 6
15:8 SM0_DATA5 Serial interface data byte 5
7:0 SM0_DATA4 Serial interface data byte 4
t.c EN
1E00095C PINTEN Peripheral interrupt enable register 0000000
0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name SM
0_I
RSV0[14:0]
NT_
EN
Type RO RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:1 RSV0 Reserved
0 SM0_INT_EN Serial interface master 0 interrupt enable
18 TEK
1E000960 PINTST Peripheral interrupt status register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[30:15]
Type RO
@
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
0_I
R DI
RSV0[14:0]
NT_
ST
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31:1 RSV0 Reserved
0 SM0_INT_ST Serial interface master 0 interrupt status
1E000964 PINTCL Peripheral interrupt clear register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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MT7621 PROGRAMMING GUIDE
L Y
Name RSV0[30:15]
SE AL
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SM
0_I
RSV0[14:0]
NT_
n U TI
CL
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:1 RSV0 Reserved
0 SM0_INT_CL Serial interface master 0 interrupt clear
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.8 NAND Flash Interface
ON
2.8.1 Features
ECC (BCH code) acceleration capable of 4/6/8 error correction. (with ECC engine)
n U TI
Programmable page size and spare size
Programmable FDM data size and protected FDM data size.
t.c EN
Word/byte access through APB bus.
DMA for massive data transfer.
Latch sensitive interrupt to indicate ready state for read, program, erase operation.
.ne ID
Programmable wait states, command/address setup and hold time, read enable hold time, and
write enable recovery time.
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.8.2 Registers
ON
Address Name Width Register Function
1E003000 NFI_CNFG 16 NFI Configuration
n U TI
The register controls the NFI functions.
For all enable fields, Setting to be logic-1 represents enabled, while 0 represents
disabled.
1E003004 NFI_PAGEFMT 16 NFI Page Format Control Register
t.c EN
This register manages the page format of the device. It includes the bus width
selection, the page size, the associated address format, and the spare format.
1E003008 NFI_CON 16 NFI Operation Control Register
This is recommended to reset the state machine, data FIFO and flush the data
FIFO before starting a new command
.ne ID
1E00300C NFI_ACCCON 32 NAND Flash Access Timing Control register
This is the timing access control register for the NAND FLASH interface. In order
to accommodate operations for different system clock frequency ranges from
13MHz to 61.44MHz, wait states and setup/hold time margin can be configured
in this register.
ink NF
1E003010 NFI_INTR_EN 16 NFI Interrupt Enable Register
This register controls the activity for the interrupt sources. These enable should
be turned on only while SW expects the corresponding interrupt will occur.
1E003014 NFI_INTR 16 NFI Interrupt Status Register
b-l CO
The register indicates the status of all the interrupt sources. Read this register will
clear all interrupts.
1E003020 NFI_CMD 16 NFI Command register
This is the command input register. The user should write this register to issue a
command. Please refer to device datasheet for the command set. Before write
the command, please check out the settings for register NFI_CON.
1E003030 NFI_ADDRNOB 16 NFI Address Length Register
18 TEK
This register represents the number of bytes corresponding to current command.
The each valid number of bytes ranges from 0 to 4. The address format depends
on what device to be used and what commands to be applied. The NFI core is
made transparent to those different situations except that the user has to define
the number of bytes.
The user should write the target address to the address register NFI_COLADDR
and NFI_ROWADDR before programming this register.
1E003034 NFI_COLADDR 32
@
NFI Column Address Register
RD A
This defines the 4 bytes of the column address field to be applied to the device.
Since the device bus width is 1 byte, the NFI core arranges the order of address
data to be least significant byte first. The user should put the first address byte in
the field ADDR0, the second byte in the field ADDR1, and so on.
R DI
1E003038 NFI_ROWADDR 32 NFI Row Address Register
This defines the 4 bytes of the row address field to be applied to the device. Since
the device bus width is 1 byte, the NFI core arranges the order of address data to
be least significant byte first. The user should put the first address byte in the
FO ME
field ADDR0, the second byte in the field ADDR1, and so on.
1E003040 NFI_STRDATA 16 NFI Data Transfer Start Trigger Register
This register controls the activity for the interrupt sources.
1E003044 NFI_CNRNB 16 NFI Check NAND Ready/Busy Register
This register controls the activity for the interrupt sources.
1E003050 NFI_DATAW 32 NFI Write Data Buffer
This is the write port of the data FIFO. It supports word access. The least
significant byte DW0 is to be programmed to the device first, then DW1, and so
on.
1E003054 NFI_DATAR 32 NFI Read Data Buffer
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MT7621 PROGRAMMING GUIDE
L Y
This is the read port of the data FIFO. It supports word access. The least
significant byte DR0 is the first byte read from the device, then DR1, and so on.
SE AL
1E003058 NFI_PIO_DIRDY 16 PIO_mode Data Ready Register
ON
This register indicates the data is ready for input
1E003060 NFI_STA 32 NFI Status
This register represents the NFI core control status including command mode,
n U TI
address mode, data program and read mode. The user should poll this register for
the end of those operations.
1E003064 NFI_FIFOSTA 16 NFI FIFO Status
The register represents the status of the data FIFO. The FIFO top and bottom
t.c EN
pointer of read & write will be reset when issue "command" to NAND Flash
1E003068 NFI_LOCKSTA 16 NFI Lock Status
This register represents the lock status for each lock range.
If any access_lockxx happens, the nfi core will automatic issue a reset (0xFF)
command to NAND device.
.ne ID
1E003070 NFI_ADDRCNTR 16 NFI Page Address Counter Register
The register represents the current read/write address with respect to initial
address input. It counts in unit of byte. In page read and page program operation,
the address should be the same as that in the state machine in the target device.
1E003080 NFI_STRADDR 32 NFI AHB Start Address Register
ink NF
The register represents the start address for DMA to access EMI. These memory
from the start address is used to put read data from NAND or write data to NAND
in DMA mode
1E003084 NFI_BYTELEN 16 NFI DMA Byte Length Register
The register represents the current transfer length for DMA to access EMI.
b-l CO
1E003090 NFI_CSEL 16 NFI device select register
The register is used to select the target device. It decides which CEB pin to be
functional. This is useful while using the high-density device.
1E003094 NFI_IOCON 16 NFI IO Control register
Data bus pull down when no use.
32
18 TEK
1E0030A0 NFI_FDM0L NFI Least FDM Data for Sector 0 Register
This register represents the Least FDM data for the sector 0. Since the device bus
width is 1 byte, the NFI core arranges the order of address data to be least
significant byte first. The user should put the first address byte in the field
FDM0_0, the second byte in the field FDM0_1, and so on. It will be reset to 0xFF
when issue NFI_Reset.
1E0030A4 NFI_FDM0M 32 NFI Most FDM Data for Sector 0 Register
This register represents the Most FDM data for the sector 0. Since the device bus
@
width is 1 byte, the NFI core arranges the order of address data to be least
RD A
significant byte first. The user should put the first address byte in the field
1E003100 NFI_LOCK 16 NFI Lock Enable Register
R DI
This register enable the lock function of NFI .
These setting can only be set once after reset chip.
1E003104 NFI_LOCKCON 32 NFI Lock Control Register
This register control the lock function of NFI .
These setting can only be set once after reset chip.
FO ME
1E003108 NFI_LOCKANOB 16 NFI Address Format for Lock Register
This register represents the number of bytes corresponding to erase and program
command. The each valid number of bytes ranges from 0 to 4. The address
format depends on what device to be used and what commands to be applied.
The NFI core will force these setting during some command operation(8X or 6X).
These setting can only be set once after reset chip.
1E003110 NFI_LOCK00ADD 32 NFI Row Start Address for Lock Set00 Register
This defines the 4 bytes of the row start address field to be locked range for the
device.
These setting can only be set once after reset chip.
1E003114 NFI_LOCK00FMT 32 NFI Row Address Format for Lock Set00 Register
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MT7621 PROGRAMMING GUIDE
L Y
This defines the 4 bytes format of the row address field to be locked range for the
device.
SE AL
These setting can only be set once after reset chip.
ON
The MSB unused range must be set to 0 for LOCKxxFMT.
1E003190 NFI_FIFODATA0 32 NFI FIFO Content Data 0
This register represents the content data 0 of fifo.
1E003194 NFI_FIFODATA1 32 NFI FIFO Content Data 1
n U TI
This register represents the content data 1 of fifo.
1E003198 NFI_FIFODATA2 32 NFI FIFO Content Data 2
This register represents the content data 2 of fifo.
t.c EN
1E00319C NFI_FIFODATA3 32 NFI FIFO Content Data 3
This register represents the content data 3 of fifo.
1E003200 NFI_MCON 16 NFI LCD Monitor Control Register
1E003204 NFI_TOTALCNT 32 NFI LCD Monitor Total Cycle Count
.ne ID
1E003208 NFI_RQCNT 32 NFI LCD Monitor Request Cycle Count
1E00320C NFI_ACCNT 32 NFI LCD Monitor Access Cycle Count
1E003210 NFI_MASTERSTA 16 NFI Master Status
The four indicator represents MASTER status in the BUS access. There are three
ink NF
channels for AHB master. The MSB(Bit 2) to LSB(bit0) repesent ECC, Auto-
Correction and NFI channel respectively. Each bit represents the channel is active
or inactive. 0 is inactive, 1 is active. After NFI reset, the NFI_MASTERSTA should
be checked to guarantee the master is stopped.
For example:
b-l CO
MAS_XX[0] The NFI channel is in the XX status.
MAS_XX[1] The Auto-Correction channel is in the XX status.
MAS_XX[2] The ECC channel is in the XX status.
1E003000 NFI_CNFG NFI Configuration 0000
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne OP_MODE AUT HW BYT DM REA DM
O_F _EC E_R A_B D_ A_M
MT_ C_E W URS MO ODE
EN N T_E DE
N
Type R/W R/W R/W R/W R/W R/W R/W
Reset
@
0 0 0 0 0 0 0 0 0
RD A
Bit(s) Name Description
14:12 OP_MODE The field control the operating process flow of FSM for NFI.
R DI
000b: Idle state.
001b: Read Process. Recommend for basic read operation.
010b: Single Read Process. Recommend for read id and read status.
011b: Program Process. Recommend for basic program operation.
FO ME
100b: Erase Process. Recommend for basic erase operation.
101b: Reset Process. Recommend for basic reset operation.
110b: Custom Process. Recommend for all advance operation.
Others: Reserved
9 AUTO_FMT_EN Automatic HW ECC encode or decode enable.
If enabled, the ECC parity from HW ECC engine and FDM data from Register are written
automatically to the spare area. If disable, the spare data all comes from PIO register, like
DATAR, DATAW, (PIO Mode) or the memory(DMA Mode) as main area data.
8 HW_ECC_EN This field is used to enable encoding or decoding operation of HW ECC engine. If the bit is
enabled, the data is transferring to ECC engine for encoding and decoding. The ECC Engine
should be configured as nfi encoding mode, otherwise the NFI will hang.
6 BYTE_RW Enable byte access. The valid bytes read from NFI_DATAR and NFI_DATAW is only DR0 and
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MT7621 PROGRAMMING GUIDE
L Y
DW0 if BYTE_RW is enabled.
SE AL
2 DMA_BURST_EN
ON
1 READ_MODE This field is used to control the activity of read or write transfer.
0: write operation of DMA or PIO.
1: read operation of DMA or PIO.
0 DMA_MODE This field is used to control the Operation mode.
n U TI
0: PIO mode. All data (include read or write) move by MCU through APB access.
1: DMA mode. All data (include read or write) move by HW automation through AHB bus.
t.c EN
1E003004 NFI_PAGEFMT NFI Page Format Control Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FDM_ECC_NUM FDM_NUM SPARE_SIZE DBY PAGE_SIZE
TE_E
.ne ID
N
Type R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
15:12 FDM_ECC_NUM The number of each FDM data for HW ECC protection. The valid number of bytes ranges are
from 0 to 8.
11:8 FDM_NUM The FDM data number for each spare area. The valid number of bytes are from 0 to 8.
5:4 SPARE_SIZE
b-l CO
3 DBYTE_EN 16 bits I/O bus interface enable.
1:0 PAGE_SIZE Page Size. The field specifies the size of one page for the device. Some most widely used
page size are supported.
0: The page size is 512 bytes (including 512 bytes data area and (spare_size*1) bytes spare
area).
1: The page size is 2k bytes (including 2048 bytes data area and (spare_size*4) bytes spare
area).
18 TEK
2: The page size is 4k bytes (including 4096 bytes data area and (spare_size*8) bytes spare
area).
3: Reserved.
1E003008 NFI_CON NFI Operation Control Register 0000
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Mne SEC_NUM BW BRD NOB SRD NFI_ FIFO
R RST _FL
USH
R DI
Type R/W R/W R/W W/R WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
15:12 SEC_NUM The field represents the sector number to be retrieved from the device or DMA Master. The
valid number ranges from 1 to 8.
9 BWR Burst write mode. Setting to be logic-1 enables the data burst write operation.
8 BRD Burst read mode. Setting this field to be logic-1 enables the data read operation. The NFI
core will issue read cycles to retrieve data from the device when the data FIFO is not full or
the device is not in the busy state. The NFI core supports consecutive page reading.
7:5 NOB The field represents the number of bytes to be retrieved from the device in single mode, and
the number of bytes per APB transaction in both single and burst mode. If device is 16-bit IO,
the read bytes number will double
0: Read 8 bytes from the device. (16 byte for 16-bit IO)
1: Read 1 byte from the device. (2 byte for 16-bit IO)
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L Y
2: Read 2 bytes from the device. (4 byte for 16-bit IO)
3: Read 3 bytes from the device. (6 byte for 16-bit IO)
SE AL
4: Read 4 bytes from the device. (8 byte for 16-bit IO)
ON
5: Read 5 byte from the device. (10 byte for 16-bit IO)
6: Read 6 bytes from the device. (12 byte for 16-bit IO)
7: Read 7 bytes from the device. (14 byte for 16-bit IO)
4 SRD Setting to be logic-1 initializes the one-shot data read operation. It's mainly used for read ID
n U TI
and read status command, which requires no more than 4 read cycles to retrieve data from
the device. It used when FIFO is empty or after reset nficore
1 NFI_RST Reset the state machine, data FIFO (0x0000) and FDM data (0xffff)
0 FIFO_FLUSH Flush the data FIFO.
t.c EN
1E00300C NFI_ACCCON NAND Flash Access Timing Control register NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.ne ID
Mne POECS PRECS C2R
Type R/W R/W R/W
Reset F F F F 0F 0F 0F 0F 0F 0F 3F 3F 3F 3F 3F 3F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Mne W2R WH WST RLT
Type R/W R/W R/W R/W
Reset F F F F F F F F F F F F F F F F
Bit(s) Name Description
b-l CO
31:28 POECS The field represents the minimum required time for CS post-pulling down after the access to
device.
Minimum required time = PRECS[1:0] + PRECS[2]*8 + PRECS[3]*64 (T)
27:22 PRECS The field represents the minimum required time for CS pre-pulling down before any access to
device.
Minimum required time = PRECS[1:0] + PRECS[3:2]*8 + PRECS[5:4]*128 (T)
18 TEK
21:16 C2R The field represents the minimum required time from NCEB low to NREB low. It's in unit of
2T.
Minimum required time = C2R[5:0]*2 + 1 (T)
15:12 W2R The field represents the minimum required time from NWEB high to NREB low. It's in unit of
2T. So the actual time ranges from 0T to 30T in step of 2T.
Minimum required time = W2R[3:0]*2 + 1 (T)
11:8 WH Write-enable hold-time.
@
The field specifies the hold time of NALE, NCLE, NCEB signals relative to the rising edge of
RD A
NWEB. This field is associated with WST to expand the write cycle time, and is associated with
RLT to expand the read cycle time.
7:4 WST Write Wait State
R DI
The field specifies the wait states to be inserted to meet the requirement of the pulse width of
the NWEB signal.
00b: No wait state.
01b: 1T wait state.
10b: 2T wait state.
FO ME
11b: 3T wait state.
3:0 RLT Read Latency Time
The field specifies how many wait states to be inserted to meet the requirement of the read
access time for the device.
00b: No wait state.
01b: 1T wait state.
10b: 2T wait state.
11b: 3T wait state.
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L Y
1E003010 NFI_INTR_EN NFI Interrupt Enable Register 0000
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Mne AHB ACC BUS ERA RESE WR_ RD_
_DO ESS_ Y_R SE_ T_D DON DON
NE_ LOC ETU DON ONE E_E E_E
EN K_E RN_ E_E _EN N N
n U TI
N EN N
Type R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
6 AHB_DONE_EN The done interrupt enable for DMA mode.
5 ACCESS_LOCK_EN
4 BUSY_RETURN_EN The busy return interrupt enable.
.ne ID
3 ERASE_DONE_EN The erase completion interrupt enable.
2 RESET_DONE_EN The reset completion interrupt enable.
1 WR_DONE_EN The single page write completion interrupt enable.
0 RD_DONE_EN The single page read completion interrupt enable.
ink NF
1E003014 NFI_INTR NFI Interrupt Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Mne AHB ACC BUS ERA RESE WR_ RD_
_DO ESS_ Y_R SE_ T_D DON DON
NE LOC ETU DON ONE E E
K RN E
Type RC RC RC RC RC RC RC
Reset 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
6 AHB_DONE Indicates that the AHB operation is completed.
5 ACCESS_LOCK
4 BUSY_RETURN Indicates that the device state returns from busy by inspecting the R/B# pin.
3 ERASE_DONE Indicates that the erase operation is completed.
2 RESET_DONE Indicates that the reset operation is completed.
@
RD A
1 WR_DONE Indicates that the write operation is completed.
0 RD_DONE Indicates that the single page read operation is completed.
R DI
1E003020 NFI_CMD NFI Command register 0000
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne CMD
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7:0 CMD Command word.
1E003030 NFI_ADDRNOB NFI Address Length Register 0000
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L Y
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE AL
Mne ROW_ADDR_NOB COL_ADDR_NOB
Type R/W R/W
ON
Reset 0 0 0 0 0 0
Bit(s) Name Description
n U TI
6:4 ROW_ADDR_NOB Number of bytes for the row address
2:0 COL_ADDR_NOB Number of bytes for the column address
t.c EN
1E003034 NFI_COLADDR NFI Column Address Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne COL_ADDR3 COL_ADDR2
Type R/W R/W
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne COL_ADDR1 COL_ADDR0
Type R/W R/W
Reset
ink NF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 COL_ADDR3 The 3-th column address byte.
23:16 COL_ADDR2 The 2-th column address byte.
b-l CO
15:8 COL_ADDR1 The 1-th column address byte.
7:0 COL_ADDR0 The 0-th column address byte.
1E003038 NFI_ROWADDR NFI Row Address Register 00000000
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ROW_ADDR3 ROW_ADDR2
Type R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ROW_ADDR1 ROW_ADDR0
Type R/W R/W
@
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit(s) Name Description
R DI
31:24 ROW_ADDR3 The 3-th row address byte.
23:16 ROW_ADDR2 The 2-th row address byte.
15:8 ROW_ADDR1 The 1-th row address byte.
7:0 ROW_ADDR0 The 0-th row address byte.
FO ME
1E003040 NFI_STRDATA NFI Data Transfer Start Trigger Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne STR
_DA
TA
Type WO
Reset 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
0 STR_DATA This signal triggers the data transfer for read or write. It only takes effect as custom
ON
operation mode
n U TI
1E003044 NFI_CNRNB NFI Check NAND Ready/Busy Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne CB2R_TIME STR
_CN
t.c EN
RNB
Type R/W WO
Reset 0 0 0 0 0
Bit(s) Name Description
.ne ID
7:4 CB2R_TIME This time-out registers for polling the NAND busy/ready signal. The unit is 16T clock cycles.
The clock rate is 61.44MHz in normal mode. It will be slow down after enable HW DCM
mode.
0 STR_CNRNB This signal triggers NFI to poll the status the NAND busy/ready signal after CB2R_TIME*16
cycles. This function is used to avoid the fail function of "BUSY2READY" status or
ink NF
"BUSY_RETURN" interrupt when NAND is operating at very low frequency( <7MHz ). If NAND
is operating in lower frequency, the sampling for the event, NAND busy/ready signal from
low to high, may be failed and NFI will be hanged in busy state. This signal is a time-out
register to check the NAND status. The results will be report to "BUSY2READY" status and
"BUSY_RETURN" interrupt.
b-l CO
1E003050 NFI_DATAW NFI Write Data Buffer 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DW3 DW2
Type WO WO
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DW1 DW0
Type WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
RD A
31:24 DW3 Write data byte 3.
23:16 DW2 Write data byte 2.
15:8 DW1 Write data byte 1.
R DI
7:0 DW0 Write data byte 0.
FO ME
1E003054 NFI_DATAR NFI Read Data Buffer 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DR3 DR2
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DR1 DR0
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
31:24 DR3 Read data byte 3.
ON
23:16 DR2 Read data byte 2.
15:8 DR1 Read data byte 1.
7:0 DR0 Read data byte 0.
n U TI
1E003058 NFI_PIO_DIRDY PIO_mode Data Ready Register 0000
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PIO_
DI_R
DY
Type RO
Reset 0
.ne ID
Bit(s) Name Description
0 PIO_DI_RDY indicates the PIO mode is ready for read data in read mode and ready for write data in write
mode.
ink NF
0: NFI_DATAR and NFI_DATAW should not be read or write (not ready).
1: NFI is ready for reading data in ready mode and writing data in write mode.
b-l CO
1E003060 NFI_STA NFI Status 00001000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne NAND_FSM NFI_FSM
Type RO RO
Reset 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Mne REA BUS BUS ACC DAT DAT ADD CM
D_E Y2R Y ESS_ AW AR R D
MPT EAD LOC
Y Y K
Type RO RO RO RO RO RO RO RO
Reset 1 0 0 0 0 0 0 0
Bit(s) Name Description
@
RD A
28:24 NAND_FSM The field represents the state of NAND interface FSM.
000000b: IDLE. idle.
111000b: PRE_CS. Pre CS state.
R DI
001001b: CMD_WRST. command write set up
001010b: CMD_WR. Command write enable.
001011b: CMD_WRHD. Command write hold.
001000b: CMD_WRRDY
010001b: ADDR_WRST. Address write set up
FO ME
010010b: ADDR_WR. Address write enable
010011b: ADDR_WRHD. Address write hold
010000b: ADDR_WRRDY.
011000b: CA2DEXT. Command address write extension.
100001b: DATA_RDST. Data read set up.
100010b: DATA_RD. Data read enable.
100011b: DATA_RDHD. Data read hold.
110001b: DATA_WRST. Data write set up.
110010b: DATA_WR. Data write enable.
110011b: DATA_WRHD. Data write hold.
Others: Reserved
19:16 NFI_FSM The field represents the state of NFI internal FSM.
0000b: idle.
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MT7621 PROGRAMMING GUIDE
L Y
0001b: reset. Reset command to ready
0010b: read busy.
SE AL
0011b: read data.
ON
0100b: program busy
0101b: program data. Input data command to program command
1000b: erase busy. Erase command to ready
1001b: erase data. Erase command 1 to erase command 2
1111b: custom mode
n U TI
1110b: custom mode for data access
Others: Reserved
12 READ_EMPTY Empty page indication during read operation, include all data, FDM and parity for all sectors
9 BUSY2READY It's read-only. This signal indicates NAND from busy to ready state and it will be reset after
t.c EN
nfi_reset or write command/address.
8 BUSY Synchronized busy signal from the NAND flash. It's read-only. This signal is sampled from NFI
4 ACCESS_LOCK The access range is locked for erase or program .
3 DATAW The NFI core is in data write mode.
.ne ID
2 DATAR The NFI core is in data read mode.
1 ADDR The NFI core is in address mode.
0 CMD The NFI core is in command mode.
ink NF
1E003064 NFI_FIFOSTA NFI FIFO Status 4040
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne
b-l CO
WR WR WR_REMAIN RD_ RD_ RD_REMAIN
_FU _EM FULL EMP
LL PTY TY
Type RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 1 0 0 0 0 0
Bit(s) Name Description
18 TEK
15 WR_FULL Data FIFO full in burst write mode.
14 WR_EMPTY Data FIFO empty in burst write mode.
12:8 WR_REMAIN Data FIFO remaining byte number in burst write mode.
7 RD_FULL Data FIFO full in burst read mode.
6 RD_EMPTY Data FIFO empty in burst read mode.
4:0 RD_REMAIN Data FIFO remaining byte number in burst read mode.
@
RD A
1E003068 NFI_LOCKSTA NFI Lock Status 0000
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC ACC
ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_ ESS_
LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
FO ME
K15 K14 K13 K12 K11 K10 K09 K08 K07 K06 K05 K04 K03 K02 K01 K00
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15 ACCESS_LOCK15 The access command violates the locking range 15
14 ACCESS_LOCK14 The access command violates the locking range 14
13 ACCESS_LOCK13 The access command violates the locking range 13
12 ACCESS_LOCK12 The access command violates the locking range 12
11 ACCESS_LOCK11 The access command violates the locking range 11
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MT7621 PROGRAMMING GUIDE
L Y
10 ACCESS_LOCK10 The access command violates the locking range 10
SE AL
9 ACCESS_LOCK09 The access command violates the locking range 9
ON
8 ACCESS_LOCK08 The access command violates the locking range 8
7 ACCESS_LOCK07 The access command violates the locking range 7
6 ACCESS_LOCK06 The access command violates the locking range 6
n U TI
5 ACCESS_LOCK05 The access command violates the locking range 5
4 ACCESS_LOCK04 The access command violates the locking range 4
3 ACCESS_LOCK03 The access command violates the locking range 3
2 ACCESS_LOCK02 The access command violates the locking range 2
t.c EN
1 ACCESS_LOCK01 The access command violates the locking range 1
0 ACCESS_LOCK00 The access command violates the locking range 0
.ne ID
1E003070 NFI_ADDRCNTR NFI Page Address Counter Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne SEC_CNTR SEC_ADDR
ink NF
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:12 SEC_CNTR The sector count.
b-l CO
9:0 SEC_ADDR The address count of 512 main data and spare data for each sector.
1E003080 NFI_STRADDR NFI AHB Start Address Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
18 TEK
Mne STR_ADDR[31:16]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne STR_ADDR[15:0]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
RD A
Bit(s) Name Description
31:0 STR_ADDR The start address of EMI for both read or write in DMA mode.
R DI
If start address of any sector data is not 4-byte aligned, the transfer will be automatically split
into byte and word transaction by NFI DMA. Non 4-byte aligned data will be transferred in
single-byte transaction. Non 16-byte aligned data will be transferred in single-word
transaction. 16-byte aligned data will be transferred by 4 word incrementing bust if the
NFI_CNFG->DMA_BURST_EN is enabled.
FO ME
1E003084 NFI_BYTELEN NFI DMA Byte Length Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne BUS_SEC_CNTR BUS_SEC_ADDR
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
15:12 BUS_SEC_CNTR The sector count.
SE AL
9:0 BUS_SEC_ADDR The address count of 512 main data and spare data for each sector.
ON
1E003090 NFI_CSEL NFI device select register 0000
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne CSEL
Type R/W
Reset 0
t.c EN
Bit(s) Name Description
0 CSEL Chip select. The value defaults to 0.
0: Device 1 is selected.
1: Device 2 is selected.
1E003094
.ne ID
NFI_IOCON NFI IO Control register 0006
ink NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne BRSTN L2N L2N NLD
W R _PD
Type R/W R/W R/W R/W
Reset 0 0 0 0 1 1 0
b-l CO
Bit(s) Name Description
7:4 BRSTN Maximum Burst Number for NAND read and writes. The unit is number of byte (8bits I/O) or
double byte (16bits I/O)
2 L2NW Enable 1T latency for the arbitration from LCD to NAND write operation, this is used to
prevent bus contention between chip, NAND flash and LCD device.
18 TEK
1 L2NR Enable 1T latency for the arbitration from LCD to NAND read operation, this is used to
prevent bus contention between chip, NAND flash and LCD device.
0 NLD_PD data bus pull down when no use.
0: disable.
1: enable.
@
RD A
1E0030A0 NFI_FDM0L NFI Least FDM Data for Sector 0 Register NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Mne FDM0_3 FDM0_2
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FDM0_1 FDM0_0
FO ME
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Bit(s) Name Description
31:24 FDM0_3 The 3-th FDM byte data for sector 0.
23:16 FDM0_2 The 2-th FDM byte data for sector 0.
15:8 FDM0_1 The 1-th FDM byte data for sector 0.
7:0 FDM0_0 The 0-th FDM byte data for sector 0.
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E0030A4 NFI_FDM0M NFI Most FDM Data for Sector 0 Register NA
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FDM0_7 FDM0_6
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FDM0_5 FDM0_4
Type R/W R/W
Reset ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
t.c EN
Bit(s) Name Description
31:24 FDM0_7 The 3-th FDM byte data for sector 0.
23:16 FDM0_6 The 2-th FDM byte data for sector 0.
.ne ID
15:8 FDM0_5 The 1-th FDM byte data for sector 0.
7:0 FDM0_4
ink NF The 0-th FDM byte data for sector 0.
1E003100 NFI_LOCK NFI Lock Enable Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne LOC
K_O
b-l CO
N
Type R/W
1
Reset 0
Bit(s) Name Description
18 TEK
0 LOCK_ON Enable the lock checking process for any lock set.
0: Disable lock checking process.
1: Enable lock checking process.
1E003104 NFI_LOCKCON NFI Lock Control Register 00000000
@
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD A
Mne LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
K15 K15 K14 K14 K13 K13 K12 K12 K11 K11 K10 K10 K09 K09 K08 K08
_CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN
R DI
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC
FO ME
K07 K07 K06 K06 K05 K05 K04 K04 K03 K03 K02 K02 K01 K01 K00 K00
_CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN _CS _EN
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 LOCK15_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 15 for CS0.
1: Lock range check of set 15 for CS1.
30 LOCK15_EN Enable the lock checking process of lock set 15. Before it takes effect, the LOCK_ON must be
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MT7621 PROGRAMMING GUIDE
L Y
turned on.
SE AL
0: Disable Lock Range check for set 15.
1: Enable Lock Range check for set 15.
ON
29 LOCK14_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 14 for CS0.
1: Lock range check of set 14 for CS1.
28 LOCK14_EN Enable the lock checking process of lock set 14. Before it takes effect, the LOCK_ON must be
n U TI
turned on.
0: Disable Lock Range check for set 14.
1: Enable Lock Range check for set 14.
27 LOCK13_CS Indicate the lock checking process of lock set.n for CS0 or CS1
t.c EN
0: Lock range check of set 13 for CS0.
1: Lock range check of set 13 for CS1.
26 LOCK13_EN Enable the lock checking process of lock set 13. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 13.
.ne ID
1: Enable Lock Range check for set 13.
25 LOCK12_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 12 for CS0.
1: Lock range check of set 12 for CS1.
ink NF
24 LOCK12_EN Enable the lock checking process of lock set 12. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 12.
1: Enable Lock Range check for set 12.
23 LOCK11_CS Indicate the lock checking process of lock set.n for CS0 or CS1
b-l CO
0: Lock range check of set 11 for CS0.
1: Lock range check of set 11 for CS1.
22 LOCK11_EN Enable the lock checking process of lock set 11. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 11.
1: Enable Lock Range check for set 11.
21 LOCK10_CS Indicate the lock checking process of lock set.n for CS0 or CS1
18 TEK
0: Lock range check of set 10 for CS0.
1: Lock range check of set 10 for CS1.
20 LOCK10_EN Enable the lock checking process of lock set 10. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 10.
1: Enable Lock Range check for set 10.
19 LOCK09_CS Indicate the lock checking process of lock set.n for CS0 or CS1
@
RD A
0: Lock range check of set 9 for CS0.
1: Lock range check of set 9 for CS1.
18 LOCK09_EN Enable the lock checking process of lock set 9. Before it takes effect, the LOCK_ON must be
R DI
turned on.
0: Disable Lock Range check for set 9.
1: Enable Lock Range check for set 9.
17 LOCK08_CS Indicate the lock checking process of lock set.n for CS0 or CS1
FO ME
0: Lock range check of set 8 for CS0.
1: Lock range check of set 8 for CS1.
16 LOCK08_EN Enable the lock checking process of lock set 8. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 8.
1: Enable Lock Range check for set 8.
15 LOCK07_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 7 for CS0.
1: Lock range check of set 7 for CS1.
14 LOCK07_EN Enable the lock checking process of lock set 7. Before it takes effect, the LOCK_ON must be
turned on.
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MT7621 PROGRAMMING GUIDE
L Y
0: Disable Lock Range check for set 7.
1: Enable Lock Range check for set 7.
SE AL
13 LOCK06_CS Indicate the lock checking process of lock set.n for CS0 or CS1
ON
0: Lock range check of set 6 for CS0.
1: Lock range check of set 6 for CS1.
12 LOCK06_EN Enable the lock checking process of lock set 6. Before it takes effect, the LOCK_ON must be
turned on.
n U TI
0: Disable Lock Range check for set 6.
1: Enable Lock Range check for set 6.
11 LOCK05_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 5 for CS0.
t.c EN
1: Lock range check of set 5 for CS1.
10 LOCK05_EN Enable the lock checking process of lock set 5. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 5.
1: Enable Lock Range check for set 5.
.ne ID
9 LOCK04_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 4 for CS0.
1: Lock range check of set 4 for CS1.
8 LOCK04_EN Enable the lock checking process of lock set 4. Before it takes effect, the LOCK_ON must be
ink NF
turned on.
0: Disable Lock Range check for set 4.
1: Enable Lock Range check for set 4.
7 LOCK03_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 3 for CS0.
b-l CO
1: Lock range check of set 3 for CS1.
6 LOCK03_EN Enable the lock checking process of lock set 3. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 3.
1: Enable Lock Range check for set 3.
5 LOCK02_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 2 for CS0.
18 TEK
1: Lock range check of set 2 for CS1.
4 LOCK02_EN Enable the lock checking process of lock set 2. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 2.
1: Enable Lock Range check for set 2.
3 LOCK01_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 1 for CS0.
@
1: Lock range check of set 1 for CS1.
RD A
2 LOCK01_EN Enable the lock checking process of lock set 1. Before it takes effect, the LOCK_ON must be
turned on.
R DI
0: Disable Lock Range check for set 1.
1: Enable Lock Range check for set 1.
1 LOCK00_CS Indicate the lock checking process of lock set.n for CS0 or CS1
0: Lock range check of set 0 for CS0.
1: Lock range check of set 0 for CS1.
FO ME
0 LOCK00_EN Enable the lock checking process of lock set 0. Before it takes effect, the LOCK_ON must be
turned on.
0: Disable Lock Range check for set 0.
1: Enable Lock Range check for set 0.
1E003108 NFI_LOCKANOB NFI Address Format for Lock Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PROG_RADD_NOB PROG_CADD_NOB ERASE_RADD_NOB ERASE_CADD_NOB
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MT7621 PROGRAMMING GUIDE
L Y
Type R/W1 R/W1 R/W1 R/W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
ON
Bit(s) Name Description
14:12 PROG_RADD_NOB Number of bytes for the row address for program operation (command is 8'h8X)
10:8 PROG_CADD_NOB Number of bytes for the column address for program operation (command is 8'h8X)
n U TI
6:4 ERASE_RADD_NOB Number of bytes for the row address for erase operation (command is 8'h6X)
2:0 ERASE_CADD_NOB Number of bytes for the column address for erase operation (command is 8'h6X)
t.c EN
1E003110 NFI_LOCK00ADD NFI Row Start Address for Lock Set00 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne LOCK00_ROW3 LOCK00_ROW2
Type
.ne ID
R/W1 R/W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne LOCK00_ROW1 LOCK00_ROW0
Type R/W1 R/W1
ink NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 LOCK00_ROW3 The 3-th row start address byte to be locked for lock set 0.
b-l CO
23:16 LOCK00_ROW2 The 2-th row start address byte to be locked for lock set 0.
15:8 LOCK00_ROW1 The 1-th row start address byte to be locked for lock set 0.
7:0 LOCK00_ROW0 The 0-th row start address byte to be locked for lock set 0.
18 TEK
1E003114 NFI_LOCK00FMT NFI Row Address Format for Lock Set00 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne LOCK00_FMT3 LOCK00_FMT2
Type R/W1 R/W1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne LOCK00_FMT1 LOCK00_FMT0
@
Type R/W1 R/W1
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R DI
31:24 LOCK00_FMT3 The 3-th row address format byte to be locked for lock set 0.
23:16 LOCK00_FMT2 The 2-th row address format byte to be locked for lock set 0.
15:8 LOCK00_FMT1 The 1-th row address format byte to be locked for lock set 0.
FO ME
7:0 LOCK00_FMT0 The 0-th row address format byte to be locked for lock set 0.
1E003190 NFI_FIFODATA0 NFI FIFO Content Data 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FIFO_DATA0[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA0[15:0]
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MT7621 PROGRAMMING GUIDE
L Y
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
ON
Bit(s) Name Description
31:0 FIFO_DATA0
n U TI
1E003194 NFI_FIFODATA1 NFI FIFO Content Data 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Mne FIFO_DATA1[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA1[15:0]
.ne ID
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
31:0 FIFO_DATA1
1E003198 NFI_FIFODATA2 NFI FIFO Content Data 2 00000000
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FIFO_DATA2[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA2[15:0]
Type RO
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 FIFO_DATA2
@
RD A
1E00319C NFI_FIFODATA3 NFI FIFO Content Data 3 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
R DI
FIFO_DATA3[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FIFO_DATA3[15:0]
FO ME
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 FIFO_DATA3
1E003200 NFI_MCON NFI LCD Monitor Control Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Mne BMC BMS
SE AL
LR TR
Type WO R/W
ON
Reset 0 0
Bit(s) Name Description
n U TI
1 BMCLR Clear NFI-LCD bandwidth monitor register counter
0 BMSTR Enable NFI-LCD bandwidth monitor
0: disable.
1: enable.
t.c EN
1E003204 NFI_TOTALCNT NFI LCD Monitor Total Cycle Count 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.ne ID
Mne NFI_TOTALCNT[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_TOTALCNT[15:0]
ink NF
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
31:0 NFI_TOTALCNT The total clock cycle count during enabling NFI-LCD bandwidth monitor
1E003208 NFI_RQCNT NFI LCD Monitor Request Cycle Count 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
18 TEK
Mne NFI_RQCNT[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_RQCNT[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit(s) Name Description
RD A
31:0 NFI_RQCNT The request clock cycle count during enabling NFI-LCD bandwidth monitor
R DI
1E00320C NFI_ACCNT NFI LCD Monitor Access Cycle Count 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Mne NFI_ACCNT[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_ACCNT[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 NFI_ACCNT The access clock cycle count during enabling NFI-LCD bandwidth monitor
PGMT7621_V.1.0_130607 Page 105 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E003210 NFI_MASTERSTA NFI Master Status 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne MAS_ADDR MAS_RD MAS_WR MAS_RDDLY
n U TI
Type RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
t.c EN
11:9 MAS_ADDR MAS_is in the Address phase of AHB protocol. In this phase, Bus gots the address data from
Master.
000b: There is no MAS in the Address phase of AHB protocol.
001b: NFI is in the Address pahse of AHB protocol.
010b: Auto-Correction is in the Address pahse of AHB protocol.
100b: ECC is in the Address pahse of AHB protocol.
.ne ID
8:6 MAS_RD MAS_is in the Read DATA phase of AHB protocol. In this phase, Bus returns the read data.
5:3 MAS_WR MAS_is in the Write DATA phase of AHB protocol. In this phase, Bus receives the write data.
2:0 MAS_RDDLY MAS is in the Read DATA delay phase of AHB protocol. In this phase, NFI and ECC got the
read back data
ink NF
2.8.3 Programming Guide
b-l CO
This section lists the program sequences for the NAND flash operations.
NAND Device Reset
Programming Sequence Memo
*NFI_INTR_EN = 0x4; // enable reset complete interrupt
*NFI_CMD = 0xff; Reset command
*NFI_CNRNB = 0xf1
18 TEK
Wait for reset complete interrupt
NFI reset ( General )
Programming Sequence Memo
The NFI reset to reset all register and force NFI master be early
*NFI_CON = 0x3
@
terminated
RD A
while ( *NFI_MASTERSTA != 0 ) ; Wait for master finish the last transaction
The second NFI reset is to ensure any status register affected
*NFI_CON = 0x3
by NFI master is reset to normal status
R DI
Read ID
Programming Sequence Memo
FO ME
NFI Configuration
*NFI_CON = 0x3; //Reset NFI before any command. (NFI_state back to IDLE)
*NFI_CNFG = 0x2042; //Single word PIO read. (set 0x2000 for single byte PIO read).
Write Command and Address to NAND Device
(NFI_state from IDLE state jump to READDATA state)
*NFI_CMD = 0x90;
(Issue command when SW write this APB address)
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
*NFI_ADDRNOB = addres_byte_num; //column and row number of bytes.
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MT7621 PROGRAMMING GUIDE
L Y
(Issue address when the SW write this APB address).
SE AL
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
ON
Trigger the start to read register and NFI start to read status or ID from NAND Device
//set number of read command of single read.
*NFI_CON = 0x0090 If this is x8 NF device, this means read 4*(byte) data.
If this is x16 NF device, this means read 4 * (2byte) data.
n U TI
Read Data from NFI by using PIO Mode
for (int i = 0 ; i < number of byte ; i++ ) { //PIO mode to read out read id.
while (*NFI_PIO_RDY == 0); //if the pio_rdy is not 1, keep polling.
t.c EN
pio_rdy = *NFI_PIO_RDY; //if the pio_rdy is equal to 1, data is available for read out.
read_id[i] = *NFI_DATAR; //The read out data from NFI_DATAR can be byte or word
} //It depends on the setting of BYTE_RW in NFI_CNFG
.ne ID
Read Status
Programming Sequence Memo
Configuration
ink NF
*NFI_CON = 0x3; //Reset NFI before any command. (NFI_state back to IDLE)
*NFI_CNFG = 0x2042; //Single word PIO read. (set 0x2000 for single byte PIO read).
Write Command to NAND Device
(NFI_state from IDLE state jump to READDATA state)
*NFI_CMD = 0x70;
(Issue command when SW write this APB address)
b-l CO
Start to read status or ID from NAND Device
//set number of read command of single read.
*NFI_CON = 0x0090 If this is x8 NF device, this means read 4*(byte) data.
If this is x16 NF device, this means read 4 * (2byte) data.
Read Data by using PIO Mode
18 TEK
for (int i = 0 ; i < number of byte ; i++ ) { //PIO mode to read out read id.
while (*NFI_PIO_RDY == 0); //if the pio_rdy is not 1, keep polling.
pio_rdy = *NFI_PIO_RDY; //if the pio_rdy is equal to 1, data is available for read out.
read_status[i] = *NFI_DATAR; //The read out data from NFI_DATAR can be byte or word
} //It depends on the setting of BYTE_RW in NFI_CNFG
@
Block Erase
RD A
Programming Sequence Memo
Configuration
R DI
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
*NFI_INTR_EN = 0x8 ; //Enable erase complete interrupt
//erase operation. (NFI_state from IDLE state jump to
*NFI_CNFG = 0x4000;
FO ME
ERASEDATA state)
Write Command and Address to NAND Device
// erase first command.
*NFI_CMD = 0x60;
(Issue command when SW write this APB address)
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
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MT7621 PROGRAMMING GUIDE
L Y
//erase second command. (NFI state from ERASEDATA state
*NFI_CMD = 0xD0;
SE AL
jump to ERASEBUSY state)
ON
*NFI_CNRNB = 0xf1
nd
After 2 Command 0xD0, Waiting for Erase Done Interrupt
//After Nand flash from busy to ready will issue the IRQ.
Wait for interrupt ……
(NFI_state back to IDLE)
n U TI
Page Program ( Using DMA Mode )
Configure Memo
t.c EN
ECC Engine Configuration
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en) {
(reference NFIECC Functional spec)
while ( *NFIECC_ENCIDLE == 0 ); //Polling IDLE signal until Encoder is available.
.ne ID
//Configure Encoder parameter in NFI mode.
//The setting must be referred to NFIECC document
*NFIECC_ENCCNFG = 0x10400010; //The encode size depends on the FDMECC setting
//0x10400010 means ENC_MS = 520 (512+8), the setting is
ink NF
used for hwecc_en = 1, FDM_ECC_NUM = 8
*NFIECC_DECCON = 0x0 ; //make sure Decoder is close.
*NFIECC_ENCCON = 0x1 ; //enable Encoder.
}
b-l CO
NFI Configuration
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
if ( custom_mode ) {
18 TEK
*NFI_CNFG = (0x6001 | auto_fmt_en
| hw_ecc_en | nfi_dma_burst )
} else {
*NFI_CNFG = (0x3001 | auto_fmt_en
//Setting NFI configuration according your usage.
| hw_ecc_en | nfi_dma_burst )
}
@
*NFI_CON = 0x4000; //Set the length of Burst write
RD A
if (auto_fmt_en) {
*NFI_FDMxx = FDM_value //set FDM value
R DI
}
Write Command and Address to NAND Device
// write first command.
*NFI_CMD = 0x80; (Issue command when SW write this APB address)
FO ME
NFI_state from IDLE state jumps to PROGDATA state.
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
*NFI_STRADDR = 0x1000_0000 //Write Data start address
Setting Interrupt,
*NFI_INTR_EN = 0x0042; //Set ahb_done and wr_done interrupt. Ahb_done interrupt
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MT7621 PROGRAMMING GUIDE
L Y
must be set after setting the length of burst write in NFI_CON
SE AL
and before burst write strobe.
ON
Trigger the BWR register and NFI start to write the data into NAND device
*NFI_CON = *NFI_CON | 0x0200; //Set Burst write strobe.
if ( custom_mode ) *NFI_STRDATA = 1; //strobe to transfer data
n U TI
//After Nand flash finishing transferring data from ahb bus into
wait for ahb done interrupt
NFI FIFO, AHB_DONE interrupt will be issued
//polling when nf_tsf_num is not equal to expted transfer data
while (*NFI_ADDRCNTR != expected_nfi_tsf_num); number. This action is to guarantee all the data in NFI FIFO has
t.c EN
been written into NAND device.
// write second command.
*NFI_CMD = 0x10; (Issue command when SW write this APB address)
NFI_state from PROGDATA jumps to PROGBUSY.
.ne ID
*NFI_CNRNB = 0xf1
//After Nand flash from busy to ready will issue ready_return
Waiting for wr_done interrupt IRQ, also the write_done IRQ.
NFI state from PROGBUSY jumps to IDLE.
ink NF
Page Program ( Using PIO Mode )
Configure Memo
ECC Engine Configuration
b-l CO
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en) {
(reference NFIECC Functional spec)
while ( *NFIECC_ENCIDLE == 0 ); //Polling IDLE signal until Encoder is available.
//Configure Encoder parameter in NFI mode.
*NFIECC_ENCCNFG = 0x10400010; //The setting must be referred to NFIECC document
//The encode size depends on the FDMECC setting
18 TEK
*NFIECC_DECCON = 0x0 ; //make sure Decoder is close.
*NFIECC_ENCCON = 0x1 ; //enable Encoder.
}
NFI Configuration
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
@
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
RD A
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
if ( custom_mode ) {
*NFI_CNFG = (0x6000 | auto_fmt_en
R DI
| hw_ecc_en )
} else {
*NFI_CNFG = (0x3000 | auto_fmt_en
//Setting NFI configuration according your usage.
FO ME
| hw_ecc_en )
}
*NFI_CON = 0x4000; //Set the length of Burst write
if ( custom_mode ) *NFI_STRDATA = 1; //strobe to transfer data
if (auto_fmt_en) {
*NFI_FDMxx = FDM_value //set FDM value
}
Write Command and Address to NAND Device
*NFI_CMD = 0x80; // write first command.
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MT7621 PROGRAMMING GUIDE
L Y
(Issue command when SW write this APB address)
SE AL
NFI_state from IDLE state jumps to PROGDATA state.
ON
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
n U TI
while ( *NFI_STA & 0xF != 0 ) ; //wait for writing the address to NAND
*NFI_STRADDR = 0x1000_0000 //Write Data start address
Setting Interrupt,
t.c EN
//Set ahb_done and wr_done interrupt. Ahb_done interrupt
*NFI_INTR_EN = 0x0042; must be set after setting the length of burst write in NFI_CON
and before burst write strobe.
Trigger the BWR register and NFI start to write the data into NAND device
.ne ID
*NFI_CON = *NFI_CON | 0x0200; //Set Burst write strobe.
Read Data by using PIO Mode
//PIO mode.
// if (~autofmt_en ) transfer size = sec_num*(512+spare_size)
ink NF
// if ( autofmt_en ) transfer size = sec_num*(512+(spare_size-
for ( int i = 0; i < sec_num *(512+spare_size) ; i++ ) {
fdm_num) )
// The parity data in spare area must be read from NFIECC
register by MCU in PIO mode.
b-l CO
while (*NFI_PIO_RDY ==0x0 ) //if the pio_rdy is not 1, keep polling.
pio_rdy = *NFI_PIO_RDY;
*NFI_DATAW = nfi_data[i]; //if the pio_rdy is equal to 1, data is available for write in.
}
nd
Check end condition and write 2 command to NAND device
18 TEK
//polling when nf_tsf_num is not equal to expted transfer data
while (*NFI_ADDRCNTR != expected_nfi_tsf_num); number. This action is to guarantee all the data in NFI FIFO has
been written into NAND device.
// write second command.
*NFI_CMD = 0x10; (Issue command when SW write this APB address)
NFI_state from PROGDATA jumps to PROGBUSY.
@
*NFI_CNRNB = 0xf1
RD A
//After Nand flash from busy to ready will issue ready_return
Waiting for wr_done interrupt IRQ, also the write_done IRQ.
NFI state from PROGBUSY jumps to IDLE.
R DI
Page Read (DMA Mode)
Configure Memo
FO ME
ECC Engine Configuration
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en) {
(reference NFIECC Functional spec)
dec_idle = *NFIECC_DECIDLE ; //Polling IDLE signal until Decoder is available.
while (dec_idle==0) ;
dec_idle = *NFIECC_DECIDLE ;
*NFIECC_DECCNFG = 0x90743010; //Configure Decoder parameter in NFI mode.
*NFIECC_ENCCON = 0x0 ; //make sure Encoder is close.
*NFIECC_DECCON = 0x1 ; //enable Decoder.
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MT7621 PROGRAMMING GUIDE
L Y
}
SE AL
NFI Configuration
ON
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
n U TI
if ( custom_mode ) {
*NFI_CNFG= (0x3003 | auto_fmt_en | hw_ecc_en |
nfi_dma_burst )
} else {
t.c EN
*NFI_CNFG= (0x1003 | auto_fmt_en | hw_ecc_en |
//Setting NFI configuration according your usage.
nfi_dma_burst )
}
*NFI_INTR_EN = 0x0010; //Set busy_return interrupt
.ne ID
*NFI_STRADDR = 0x1000_0000 //Read Data start address
*NFI_CON = 0x4000; //Set length of Burst read
Write Command and Address to NAND Device
// read first command.
ink NF
*NFI_CMD = 0x00; (Issue command when SW write this APB address)
NFI_state from IDLE state jumps to READBUSY state.
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
b-l CO
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
(Issue address when the SW write this APB address).
while (*NFI_STA &0xf !== 0) ; //polling when programming state is not equal to 0.
// read second command.
*NFI_CMD = 0x30;
(Issue command when SW write this APB address)
*NFI_CNRNB = 0xf1
18 TEK
//After Nand flash from busy to ready will issue ready_return
Wait for ready_return interrupt IRQ.
NFI state from READBUSY jumps to READDATA.
Trigger the BWR register and NFI start to write the data into NAND device
*NFI_CON = *NFI_CON | 0x0100; //Set Burst read strobe.
@
wait for ahb_done interrupt //After Nand flash from busy to ready will issue the IRQ.
RD A
//Polling bytelen; nf_tsf_num should be equal to expected
nfi_tsf_num = *NFI_BYTELEN;
transfer data number.
R DI
//polling when nf_tsf_num is not equal to expted transfer data
while (nfi_tsf_num !== expected_nfi_tsf_num)
number.
nfi_tsf_num = *NFI_BYTELEN;
//read AHB_done IRQ and read_done IRQ. nfi_irq_sta should
nfi_irq_sta = *NFI_INTR;
FO ME
be 0x41;
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en)
(reference NFIECC Functional spec)
dec_done = *NFIECC_DECDONE ; //Polling ECC Decoder Done signal.
while (dec_done !==0xf) ; //Because the sec_num is 4; according to sec_num;
dec_done = *NFIECC_DECDONE;
endif
Page Read (PIO Mode)
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L Y
Configure Memo
SE AL
ECC Engine Configuration
ON
//if hw_ecc_en is needed, set ECC configuration.
if (hw_ecc_en) {
(reference NFIECC Functional spec)
dec_idle = *NFIECC_DECIDLE ; //Polling IDLE signal until Decoder is available.
n U TI
while (dec_idle==0) ;
dec_idle = *NFIECC_DECIDLE ;
*NFIECC_DECCNFG = 0x90743010; //Configure Decoder parameter in NFI mode.
*NFIECC_ENCCON = 0x0 ; //make sure Encoder is close.
t.c EN
*NFIECC_DECCON = 0x1 ; //enable Decoder.
}
NFI Configuration
*NFI_CON = 0x3; //Reset NFI before any command. (NFI state back to IDLE)
.ne ID
*NFI_PAGEFMT = 0x8800; //Set device format according to NF device and fdm number.
*NFI_ACCCON = 0x41_0112; //Set device access control according to NF device.
if ( custom_mode ) {
*NFI_CNFG= (0x6003 | auto_fmt_en | hw_ecc_en |
ink NF
nfi_dma_burst )
} else {
*NFI_CNFG= (0x1003 | auto_fmt_en | hw_ecc_en |
//Setting NFI configuration according your usage.
nfi_dma_burst )
b-l CO
}
*NFI_INTR_EN = 0x0010; //Set busy_return interrupt
*NFI_STRADDR = 0x1000_0000 //Read Data start address
*NFI_CON = 0x4000; //Set length of Burst read
Write Command and Address to NAND Device
18 TEK
// read first command.
*NFI_CMD = 0x00; (Issue command when SW write this APB address)
NFI_state from IDLE state jumps to READBUSY state.
*NFI_COLADDR = col_addr ; //column address
*NFI_ROWADDR = row_addr ; //row address
//column and row number of bytes.
*NFI_ADDRNOB = addres_byte_num;
@
(Issue address when the SW write this APB address).
RD A
while (*NFI_STA &0xf !== 0) ; //polling when programming state is not equal to 0.
// read second command.
*NFI_CMD = 0x30;
R DI
(Issue command when SW write this APB address)
*NFI_CNRNB = 0xf1
//After Nand flash from busy to ready will issue ready_return
Wait for ready_return interrupt IRQ.
FO ME
NFI state from READBUSY jumps to READDATA.
Trigger the BWR register and NFI start to write the data into NAND device
*NFI_CON = *NFI_CON | 0x0100; //Set Burst read strobe.
for ( int i = 1 ; i < sec_num*(512+fdm_size) ; i++ ){ //PIO mode.
pio_rdy = *NFI_PIO_RDY; //poling pio_ready register.
while (pio_rdy==0x0) //if the pio_rdy is not 1, keep polling.
pio_rdy = *NFI_PIO_RDY;
*NFI_DATAR = nfi_data[i]; //if the pio_rdy is equal to 1, data is available for write in.
}
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L Y
//After NFI has read out all data from Nand Flash then issue
while (nfi_irq_b==0x1);
SE AL
read_done IRQ.
ON
nfi_irq_sta = *NFI_INTR; //read read_done IRQ. nfi_irq_sta should be 0x01;
//Polling bytelen; nf_tsf_num should be equal to expected
nfi_tsf_num = *NFI_BYTELEN;
transfer data number. (make sure the FDM data is all read out)
//polling when nf_tsf_num is not equal to expted transfer data
n U TI
while (nfi_tsf_num !== expected_nfi_tsf_num)
number.
nfi_tsf_num = *NFI_BYTELEN;
dec_done = *NFIECC_DECDONE ; //Polling ECC Decoder Done signal.
t.c EN
while (dec_done !==0xf) ; //Because the sec_num is 4; according to sec_num;
dec_done = *NFIECC_DECDONE;
endif
.ne ID
Two block erase ( Pseudo-Code )
Configure Memo
Set Interrupt Reg (0x10) //Set busy to ready interrupt
Write command to NAND (0x60)
ink NF
Write address to NAND ( First block address )
Write command to NAND (0x60)
Write address to NAND ( Second block address )
Write Command to NAND (0xd0)
b-l CO
Waiting for Interrupt …
Multiplane Page Program ( Pseudo-Code )
Configure Memo
This reference pseudo code is for TOSHIBA NAND device
st
Write 1 Page to NAND Device
18 TEK
Write command to NAND (0x80)
st
Write address to NAND (The 1 address) Ex: NFI_ROWADDR = 0x100
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
custom_mode enabled
Set Interrupt Reg (0x10) //Set busy to ready interrupt
@
Write_command(0x11)
RD A
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
Wait for B2R interrupt
R DI
nd
Write 2 Page to NAND Device
Reset NFI
Write command to NAND (0x80)
FO ME
nd
Write address to NAND ( The 2 address ) Ex: NFI_ROWADDR = 0x20100
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
custom_mode enabled
Set Interrupt Reg (0x10) //Set busy to ready interrupt
Write_command(0x11)
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
Wait for B2R interrupt
rd
Write 3 Page to NAND Device
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MT7621 PROGRAMMING GUIDE
L Y
Reset NFI
SE AL
Write command to NAND (0x80)
ON
rd
Write address to NAND ( The 3 address ) Ex: NFI_ROWADDR = 0x101
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
custom_mode enabled
Set Interrupt Reg (0x10) //Set busy to ready interrupt
n U TI
Write_command(0x11)
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
t.c EN
Wait for B2R interrupt
th
Write 4 Page to NAND Device
Reset NFI
Write command to NAND (0x80)
th
.ne ID
Write address to NAND ( The 4 address ) Ex: NFI_ROWADDR = 0x20101
//Please refer to the reference code of page program with
Program A page of data by using Custom Mode
custom_mode enabled
Set Interrupt Reg (0x10) //Set busy to ready interrupt
ink NF
Write_command(0x11)
// Set hardware time-out for detecting the busy to ready of
Set NFI CNRNB for waiting B2R Event
NAND Flash event
Wait for B2R interrupt
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.9 NFI ECC Controller
ON
2.9.1 Features
ECC (BCH code) acceleration is capable of 4 bits correction in one full or shorten ECC coded block
size which is less than 8192 (<8192bits)
n U TI
Support data input in 8 bits in NFI mode and 32 bits in DMA / PIO mode and works in 122.88MHz.
Support encoder and decoder work separately in DMA and PIO mode and automatic error
t.c EN
correction.
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
2.9.2 Registers
SE AL
ON
Address Name Width Register Function
1E003800 NFIECC_ENCCON 16 NFIECC Encoder Control Register
This register is for Encoder control.
n U TI
1E003804 NFIECC_ENCCNFG 32 NFIECC Configure Register
This register is for NFIECC encoder configuration.
1E003808 NFIECC_ENCDIADDR 32 NFIECC Encoder DI Memory Address Register
t.c EN
The register indicates the data start address of input data to the Encoder AHB
mode.
1E00380C NFIECC_ENCIDLE 16 NFIECC Encoder Idle Status Register
This register is for NFIECC Encoder idle status.
1E003810 NFIECC_ENCPAR0 32 NFIECC Parity0 Register
.ne ID
The register indicates the highest order of parity bits
1E003814 NFIECC_ENCPAR1 32 NFIECC Parity1 Register
The register indicates the parity bits
32
ink NF
1E003818 NFIECC_ENCPAR2 NFIECC Parity2 Register
The register indicates the parity bits
1E00381C NFIECC_ENCPAR3 32 NFIECC Parity3 Register
The register indicates the parity bits
1E003820 NFIECC_ENCPAR4 32 NFIECC Parity4 Register
b-l CO
The register indicates the parity bits
1E003824 NFIECC_ENCSTA 32 NFIECC Encoder Status Register
This register is for NFIECC Encoder status for SW polling.
1E003828 NFIECC_ENCIRQEN 16 NFIECC Encoder IRQ enable Register
This register is for software programmer to enable NFIECC IRQ signals (ignore in
NFI mode)
18 TEK
1E00382C NFIECC_ENCIRQSTA 16 NFIECC Encoder IRQ status Register
This register is for software programmer tracking NFIECC IRQ status. (ignore in
NFI mode)
1E003880 NFIECC_PIO_DIRDY 16 NFIECC PIO Data Ready Register
This register indicates the data is ready for input
1E003884 NFIECC_PIO_DI 32 NFIECC PIO Data Register
@
The register indicates PIO mode data input by MCU
RD A
1E003900 NFIECC_DECCON 16 NFIECC Decoder Control Register
This register is for Decoder control.
R DI
1E003904 NFIECC_DECCNFG 32 NFIECC Decoder Configure Register
This register is for NFIECC configuration.
1E003908 NFIECC_DECDIADDR 32 NFIECC Decoder DI Memory Address Register
The register indicates the data start address of input data to the Decoder AHB
FO ME
mode.
1E00390C NFIECC_DECIDLE 16 NFIECC Decoder Idle Status Register
This register indicates the Decoder Idle status.
1E003910 NFIECC_DECFER 16 NFIECC Decoder Found Error Status Register
This register is for NFIECC Decoder status.
1E003914 NFIECC_DECENUM 32 NFIECC Decode Error Number Register
The register indicates the error number of the coded block.
1E003918 NFIECC_DECDONE 16 NFIECC Decoder Error Status Register
This register is for NFIECC Decoder done status.
1E00391C NFIECC_DECEL0 32 NFIECC Decoder Error location0 Register
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MT7621 PROGRAMMING GUIDE
L Y
The register indicates the error location of the decoding result
SE AL
1E003920 NFIECC_DECEL1 32 NFIECC Decoder Error Location1 Register
ON
The register indicates the error location of the decoding result.
1E003924 NFIECC_DECEL2 32 NFIECC Decoder Error Location2 Register
The register indicates the error location of the decoding result.
1E003928 NFIECC_DECEL3 32 NFIECC Decoder Error Location3 Register
n U TI
The register indicates the error location of the decoding result.
1E00392C NFIECC_DECEL4 32 NFIECC Decoder Error Location4 Register
The register indicates the error location of the decoding result.
t.c EN
1E003930 NFIECC_DECEL5 32 NFIECC Decoder Error Location5 Register
The register indicates the error location of the decoding result.
1E003934 NFIECC_DECIRQEN 16 NFIECC Decoder IRQ enable Register
This register is for software programmer to enable NFIECC IRQ signals (ignore in
NFI mode)
.ne ID
1E003938 NFIECC_DECIRQSTA 16 NFIECC Decoder IRQ status Register
This register is for software programmer tracking NFIECC IRQ status. (ignore in
NFI mode)
1E00393C NFIECC_FDMADDR 32 NFIECC FDM Register Address
ink NF
The register indicates the address of FDM data in NFI module.
1E003940 NFIECC_DECFSM 32 NFIECC Decoder FSM
The register indicates the finite state machine status of decoder.
1E003944 NFIECC_SYNSTA 32 NFIECC Syndrome Status Register
b-l CO
This register is for NFIECC Syndrom status.
1E003948 NFIECC_NFIDIDECNFI 32 NFIECC NFI input dataNFI input data Register
DI This register is for checking NFI input data.
1E00394C NFIECC_SYN0 32 NFIECC Syndrom Register
The register indicates the error location of the decoding result.
18 TEK
1E003800 NFIECC_ENCCO NFIECC Encoder Control Register 0000
N
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC
_EN
@
Type R/W
RD A
Reset 0
Bit(s) Name Description
R DI
0 ENC_EN indicates the enable in NFI mode and start to work in AHB mode. In AHB mode, parity bits is
remained in the PAR0~PAR4 register field until the ENC_EN is deasserted to 0.
0: means disable the Encode block.
1: means enable the Encode block. In AHB mode, the Encoder starts to fetch data when the
FO ME
register changes from 0 to 1. In NFI mode, the register enables the Encode block, and then the
Encoder module waits start signal and data from NFI.
1E003804 NFIECC_ENCCNF NFIECC Configure Register 00000000
G
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_MS
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE AL
Mne ENC ENC_MODE ENC_TNUM
_BU
ON
RST
_EN
Type R/W R/W R/W
R/W
n U TI
Reset 0 0 0 0 0 0
Bit(s) Name Description
28:16 ENC_MS indicates the total bit size of message block including main data and control(FDM) data in the
t.c EN
NFI mode. The spare_ECC_num parameter in old version has been merged into the message
block_size parameter. If the block_size is equal to zero, the NFIECC do nothing.
The acceptable coded block size, which includes data and parity bits size, is 1~8191bits.
Different ENC_TNUM results in different parity bits, and also results in different maximum
message block size.
.ne ID
8 ENC_BURST_EN indicates the burst enalbe.
0: means DMA mode uses single read.
1: means DMA mode uses burst read.
5:4 ENC_MODE indicates the data source from access through AHB bus or from NFI.
00b: means source data from access through Bus. (DMA mode)
ink NF
01b: means source data from NFI module. (NFI mode)
10b: means source data is written by MCU. (PIO mode)
11b: reserved mode.
2:0 ENC_TNUM indicates the correct capability in one block size. (Remove)
0: means the NFIECC is capable of correct 4 bits in one block size.
b-l CO
1: means the NFIECC is capable of correct 6 bits in one block size.
2: means the NFIECC is capable of correct 8 bits in one block size.
3: means the NFIECC is capable of correct 10 bits in one block size.
4: means the NFIECC is capable of correct 12 bits in one block size.
18 TEK
1E003808 NFIECC_ENCDIA NFIECC Encoder DI Memory Address Register 00000000
DDR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_DIADDR[29:14]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Mne ENC_DIADDR[13:0]
RD A
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:2 ENC_DIADDR indicates the memory address of input data to Encoder block in AHB mode. (4-Byte align)
FO ME
1E00380C NFIECC_ENCIDLE NFIECC Encoder Idle Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC
_IDL
E
Type R
Reset 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
0 ENC_IDLE indicates the Encode block in idle state and ready for new message block.
SE AL
0: means the Encode block is under working.
1: means the Encode block is in Idle state and available for new message block.
ON
1E003810 NFIECC_ENCPAR NFIECC Parity0 Register 00000000
n U TI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR0[31:16]
t.c EN
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR0[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 ENC_PAR0 indicates the highest order of output parity bits and the bit 0 is the highest order of parity
bit. The PAR0~PAR4 register is remain the last message block parity bits until ENC_EN is
ink NF
deasserted. The parity bits should append after main data by order of {PAR0[31:0],
PAR1[31:0], PAR2[31:0], PAR3[31:0], PAR4[31:4], 4'b0}, The redundant bit of parity bit will
be padded by 0.
b-l CO
1E003814 NFIECC_ENCPAR NFIECC Parity1 Register 00000000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR1[31:16]
Type R
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR1[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
31:0 ENC_PAR1 indicates the parity bits and the bit 0 is the highest order of parity bit.
RD A
R DI
1E003818 NFIECC_ENCPAR NFIECC Parity2 Register 00000000
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Mne ENC_PAR2[31:16]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR2[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 ENC_PAR2 indicates the parity bits and the bit 0 is the highest order of parity bit.
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E00381C NFIECC_ENCPAR NFIECC Parity3 Register 00000000
ON
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR3[31:16]
Type
n U TI
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR3[15:0]
Type R
t.c EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 ENC_PAR3 indicates the parity bits and the bit 0 is the highest order of parity bit.
1E003820
4
.ne ID
NFIECC_ENCPAR NFIECC Parity4 Register 00000000
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ENC_PAR4[27:16]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC_PAR4[15:0]
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:0 ENC_PAR4 indicates the parity bits and the 31 is the highest order of parity bit.
18 TEK
1E003824 NFIECC_ENCSTA NFIECC Encoder Status Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne COUNT_MS
@
Type R
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne COUNT_PS ENC_FSM
R DI
Type R R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
29:16 COUNT_MS indicates the remaining un-processing message bits.
15:7 COUNT_PS indicates the parity bits that have not read out from NFI.
5:0 ENC_FSM indicates encoder finite state machine state
6'd0: IDLE
6'd1: WAITIN
6'd2: BUSY
6'd4: PAROUT
1E003828 NFIECC_ENCIRQ NFIECC Encoder IRQ enable Register 0000
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MT7621 PROGRAMMING GUIDE
L Y
EN
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Mne ENC
_IR
QEN
Type R/W
Reset 0
n U TI
Bit(s) Name Description
0 ENC_IRQEN Encoder IRQ mask: triggered when Encoder operation is completed.
t.c EN
0: Disable
1: Enable
.ne ID
1E00382C NFIECC_ENCIRQ NFIECC Encoder IRQ status Register 0000
STA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ENC
ink NF
_IR
QST
A
Type RC
Reset 0
b-l CO
Bit(s) Name Description
0 ENC_IRQSTA indicates interrupt status for Encoder processing.
0: No interrupt is generated.
1: An interrupt is pending and waiting for service. Active when Encoder processing is done.
18 TEK
1E003880 NFIECC_PIO_DIR NFIECC PIO Data Ready Register 0000
DY
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PIO_
DI_R
DY
@
Type R
RD A
Reset 0
R DI
Bit(s) Name Description
0 PIO_DI_RDY indicates the PIO mode (Encoder/Decoder) is ready for input data.
0: ECC is busy. During busy state, NFIECC_PIO_DI should not be over-write.
1: ECC is ready for input data. In PIO mode, write next PIO_DI when pio_di_rdy is equal to 1.
FO ME
1E003884 NFIECC_PIO_DI NFIECC PIO Data Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne PIO_DI[31:16]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne PIO_DI[15:0]
Type R/W
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
ON
Bit(s) Name Description
31:0 PIO_DI indicates the PIO mode data input.
n U TI
1E003900 NFIECC_DECCO NFIECC Decoder Control Register 0000
N
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Mne DEC
_EN
Type R/W
Reset 0
.ne ID
Bit(s) Name Description
0 DEC_EN indicates the enable in NFI mode and start to work in AHB mode. In AHB mode, the decode-
status FER and error number registers and error location registers will be reset to 0 when
DEC_EN is deasserted.
ink NF
0: means disable the Decode block.
1: means enable the Decode block. In AHB mode, the Decoder starts to fetch data when the
register changes from 0 to 1. In NFI mode, the register enables the Decode block, and then the
Decoder module waits start signal and data from NFI.
b-l CO
1E003904 NFIECC_DECCNF NFIECC Decoder Configure Register 00003000
G
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC DEC_CS
_EM
18 TEK
PTY
_EN
Type R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_CON DEC DEC_MODE DEC_TNUM
_BU
RST
@
_EN
RD A
Type R/W R/W R/W R/W
R/W
Reset 1 1 0 0 0 0 0 0
R DI
Bit(s) Name Description
31 DEC_EMPTY_EN indicates the Decoder automatically detects the empty source data and by pass the auto-
correction block (data are all equal to 1). (ignore in AHB_mode)
FO ME
0: means disenable the detection of empty source data.
1: means enable the detection of empty source data.
28:16 DEC_CS indicates the total bit size of coded block including protected data and parity bits. The
acceptable coded block size is 1~8191bits. If the coded block size is equal to zero, the
decoder does nothing. The detail figure shows in Figure 2.
13:12 DEC_CON indicates the bypass configuration in decoding processor.
0: is reserved
1: means only active syndrome calculator for error detecting purpose. ECC reports DONE and
FER status after syndrome calculator is done.
2: means error-correction module is bypassed for being aware of error location purpose. ECC
reports DONE, FER, EL and ERRNUM status after Chien search is done.
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L Y
3: means the ECC processor decoded data and auto-correction error data. The data address is
signaled by DEC_DIADDR register in AHB mode and NFI_DIADDR in NFI mode. ECC reports
SE AL
DONE, FER, EL and ERRNUM status after error-correction is done.
ON
8 DEC_BURST_EN indicates the burst enalbe.
0: means DMA mode uses single read.
1: means DMA mode uses burst read.
5:4 DEC_MODE indicates the data source from access AHB bus or from NFI.
n U TI
00b: means source data from access through Bus. (DMA mode)
01b: means source data from NFI module. (NFI mode)
10b: means source data is written by MCU. (PIO mode)
11b: Reserved mode.
t.c EN
2:0 DEC_TNUM indicates the correct capability in one block size.
0: means the Decoder is capable of correct 4 bits in one block size.
1: means the Decoder is capable of correct 6 bits in one block size.
2: means the Decoder is capable of correct 8 bits in one block size.
3: means the NFIECC is capable of correct 10 bits in one block size.
4: means the NFIECC is capable of correct 12 bits in one block size.
1E003908
.ne ID
NFIECC_DECDIA NFIECC Decoder DI Memory Address Register 00000000
ink NF
DDR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_DIADDR[29:14]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_DIADDR[13:0]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:2 DEC_DIADDR indicates the memory address of input data to the Decoder block in AHB mode. (4-Byte
align).
1E00390C NFIECC_DECIDLE NFIECC Decoder Idle Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Mne DEC
RD A
_IDL
E
Type R
R DI
Reset 0
Bit(s) Name Description
FO ME
0 DEC_IDLE indicates the Decode block is in idle state and ready for new coded block.
0: means the Decode block is under working.
1: means the Decode block is in idle state and available for new coded block.
1E003910 NFIECC_DECFER NFIECC Decoder Found Error Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FER FER FER FER FER FER2 FER FER
7 6 5 4 3 1 0
Type R R R R R R R R
Reset 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
7 FER7 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
n U TI
6 FER6 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
t.c EN
1: means there is(are) error(s) detected in the coded block.
5 FER5 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
.ne ID
1: means there is(are) error(s) detected in the coded block.
4 FER4 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
ink NF
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
3 FER3 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
b-l CO
1: means there is(are) error(s) detected in the coded block.
2 FER2 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
18 TEK
1 FER1 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
0: means there is no error detected in the coded block.
1: means there is(are) error(s) detected in the coded block.
0 FER0 indicates the error found or not in the coded block. The FER numbered by NFI sector number
in NFI mode, otherwise, in AHB mode, always use the FER0. The signal reset when DEC_EN is
deasserted in both NFI and AHB mode.
@
0: means there is no error detected in the coded block.
RD A
1: means there is(are) error(s) detected in the coded block.
R DI
1E003914 NFIECC_DECENU NFIECC Decode Error Number Register 00000000
M
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne ERRNUM7 ERRNUM6 ERRNUM5 ERRNUM4
Type R R R R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne ERRNUM3 ERRNUM2 ERRNUM1 ERRNUM0
Type R R R R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:28 ERRNUM7 indicates the error numbers of coded block in one start signal. 4'hf means the error is
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MT7621 PROGRAMMING GUIDE
L Y
uncorrectable.
SE AL
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
ON
27:24 ERRNUM6 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
n U TI
23:20 ERRNUM5 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
t.c EN
19:16 ERRNUM4 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
15:12 ERRNUM3 indicates the error numbers of coded block in one start signal. 4'hf means the error is
.ne ID
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
11:8 ERRNUM2 indicates the error numbers of coded block in one start signal. 4'hf means the error is
ink NF
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
7:4 ERRNUM1 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
b-l CO
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
3:0 ERRNUM0 indicates the error numbers of coded block in one start signal. 4'hf means the error is
uncorrectable.
But ECC only can partially detect uncorrectable error. If the error number exceeds the error
capability, ECC only can partially detect the situation.
18 TEK
1E003918 NFIECC_DECDO NFIECC Decoder Error Status Register 0000
NE
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DON DON DON DON DON DON DON DON
E7 E6 E5 E4 E3 E2 E1 E0
@
Type R R R R R R R R
RD A
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
R DI
7 DONE7 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
FO ME
in the Table 7.
6 DONE6 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
5 DONE5 indicates the Decoding procedure is done.
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
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MT7621 PROGRAMMING GUIDE
L Y
4 DONE4 indicates the Decoding procedure is done.
SE AL
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
ON
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
3 DONE3 indicates the Decoding procedure is done.
0: means the Decode block is under working.
n U TI
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
2 DONE2 indicates the Decoding procedure is done.
t.c EN
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
1 DONE1 indicates the Decoding procedure is done.
.ne ID
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
0 DONE0 indicates the Decoding procedure is done.
ink NF
0: means the Decode block is under working.
1: means the Decode block is finished. For different DEC_CON and EMPTY_EN in
NFIECC_DECCNFG register, decoder done has different meaning. Detail of the definitions show
in the Table 7.
b-l CO
1E00391C NFIECC_DECEL0 NFIECC Decoder Error location0 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL10
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL01
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
28:16 DEC_EL10 indicates the error location 1 of the decoding result.
RD A
12:0 DEC_EL01 indicates the error location 0 of the decoding result. The EL remains until the DEC_EN is
deasserted to 0 in both AHB and NFI mode. When the error number is less than 12, error
location registers will be filled from DEC_EL0, and the redundant register fields remain 0.
R DI
1E003920 NFIECC_DECEL1 NFIECC Decoder Error Location1 Register 00000000
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL3
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL2
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 DEC_EL3 indicates the error location 3 of the decoding result.
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MT7621 PROGRAMMING GUIDE
L Y
12:0 DEC_EL2 indicates the error location 2 of the decoding result.
SE AL
ON
1E003924 NFIECC_DECEL2 NFIECC Decoder Error Location2 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Mne DEC_EL5
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Mne DEC_EL4
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
28:16 DEC_EL5 indicates the error location 5 of the decoding result.
12:0 DEC_EL4
ink NF indicates the error location 4 of the decoding result.
1E003928 NFIECC_DECEL3 NFIECC Decoder Error Location3 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL7
Type R
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL6
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
28:16 DEC_EL7 indicates the error location 7 of the decoding result.
12:0 DEC_EL6 indicates the error location 6 of the decoding result.
1E00392C NFIECC_DECEL4 NFIECC Decoder Error Location4 Register 00000000
@
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD A
Mne DEC_EL9
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_EL8
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
28:16 DEC_EL9 indicates the error location 9 of the decoding result.
12:0 DEC_EL8 indicates the error location 8 of the decoding result.
1E003930 NFIECC_DECEL5 NFIECC Decoder Error Location5 Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_EL11
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L Y
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Mne DEC_EL10
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
28:16 DEC_EL11 indicates the error location 11 of the decoding result.
12:0 DEC_EL10 indicates the error location 10 of the decoding result.
t.c EN
1E003934 NFIECC_DECIRQ NFIECC Decoder IRQ enable Register 0000
EN
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC
_IR
QEN
Type R/W
ink NF
Reset 0
Bit(s) Name Description
0 DEC_IRQEN Decoder IRQ mask: triggered when Decoder operation is completed.
b-l CO
0: Disable
1: Enable
1E003938 NFIECC_DECIRQ NFIECC Decoder IRQ status Register 0000
STA
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC
_IR
QST
A
Type RC
Reset 0
@
RD A
Bit(s) Name Description
0 DEC_IRQSTA indicates Interrupt status for Decoder processing.
R DI
0: No interrupt is generated.
1: An interrupt is pending and waiting for service. Active when Decoder processing is done.
FO ME
1E00393C NFIECC_FDMAD NFIECC FDM Register Address 00000000
DR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne FDM_ADDR[31:16]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne FDM_ADDR[15:0]
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31:0 FDM_ADDR indicates the APB register address of FDM data in NFI module.
n U TI
1E003940 NFIECC_DECFSM NFIECC Decoder FSM 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne AUTOC_FSM CHIEN_FSM
Type R/W R
t.c EN
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne BMA_FSM SYN_FSM
Type R/W R
Reset 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
28:24 AUTOC_FSM indicates the status of auto-correction stage.
5'd0: IDLE
ink NF
5'd1: READ
5'd2: WRITE
5'd4: DONE
20:16 CHIEN_FSM indicates the status of Chien search stage.
5'd0: IDLE
b-l CO
5'd1: BUSY
5'd2: DONE
12:8 BMA_FSM indicates the status of BMA stage.
5'd0: IDLE
5'd1: BUSY
5'd2: DONE
5:0 SYN_FSM indicates the status of syndrome stage.
18 TEK
6'd0: IDLE
6'd1: WAITIN
6'd2: BUSY
6'd4: DONE
@
1E003944 NFIECC_SYNSTA NFIECC Syndrome Status Register NA
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne SYN_SNUM DIBW NFI_SEC_NUMNFI_S
EC_NUM
R DI
Type 0 R RR
Reset R R R 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_ SYN_COUNT_CS
FO ME
STR
_SET
Type R R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:29 SYN_SNUM indicates the sector number recorded by syndrome.
25:20 DIBW indicates input bandwidth.
18:16 NFI_SEC_NUMNFI_SEC_N indicates the sector number from NFI.
UM
15 NFI_STR_SET indicates the NFI_STR signal from NFI.
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L Y
13:0 SYN_COUNT_CS indicates the remaining un-processing coded block bits.
SE AL
ON
1E003948 NFIECC_NFIDIDE NFIECC NFI input dataNFI input data Register NA
CNFIDI
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne NFI_DINFI_DI[31:16]
Type 0
Reset RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne NFI_DINFI_DI[15:0]
Type 0
Reset RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR
.ne ID
Bit(s) Name Description
31:0 NFI_DINFI_DI
ink NF indicates the latest 4 byte input data from nfi.
1E00394C NFIECC_SYN0 NFIECC Syndrom Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne DEC_SYN3
Type R
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne DEC_SYN1
Type R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
28:16 DEC_SYN3 informs the syndrome 3 from syndrome calculator.
12:0 DEC_SYN1 informs the syndrome 1 from syndrome calculator.
@
2.9.3 Programming Guide
RD A
This section lists the program sequences for ECC operations.
R DI
Encoding in NFI mode
Caution: Before NFI address phase enable and configure ECC.
Configure Memo
FO ME
*NFIECC_ENCCNFG = 0x10400010; //configure Encoder parameter in NFI mode.
*NFIECC_ENCCON = 0x1 ; //enable Encoder.
while (NFI_STR==0x1) ; //NFI_STR is happened in NFI address phase. NFI_STR is from NFI.
0 = *NFIECC_ENCIDLE ; //It indicates the start is triggered and Encoder is in busy state.
//Wait all message data from NFI. After all data has input IDLE will be
while (*NFIECC_ENCIDLE==0x1) ;
asserted.
parity = {*NFIECC_PAR0,*NFIECC_PAR1,
*NFIECC_PAR2, *NFIECC_PAR3, //If parity is necessary, Read out parity from APB register after IDLE=1.
*NFIECC_PAR4}
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Encoding in DMA mode
ON
Configure Memo
while (*NFIECC_ENCIDLE==1) ; //polling IDLE signal until Encoder is available.
*NFIECC_ENCCNFG = 0x10400010; //configure Encoder parameter in NFI mode.
*NFIECC_ENCIRQEN = 0x1; //If IRQ is required when Encoder is done.
n U TI
*NFIECC_ENCDIADDR= 0x10000000; //Configure Data start address.
*NFIECC_ENCCON = 0x1 ; //Encoder starts fetching data from ENCDIADDR.
0 = *NFIECC_ENCIDLE ; //It indicates the start is triggered and Encoder is in busy state.
t.c EN
while (*NFIECC_ENCIDLE==0x1) ; //After all data has fetched and encoded, IDLE will be asserted.
parity = {*NFIECC_PAR0,*NFIECC_PAR1,
// Read out parity from APB register after IDLE=1 and must append parity
*NFIECC_PAR2, *NFIECC_PAR3,
bits behind the original data for decoding.
*NFIECC_PAR4}
.ne ID
Encoding in PIO mode
Configure Memo
ink NF
while (*NFIECC_ENCIDLE==1) ; //polling IDLE signal until Encoder is available.
*NFIECC_ENCCNFG = 0x10400010; //configure Encoder parameter in NFI mode.
*NFIECC_ENCIRQEN = 0x1; //If IRQ is required when Encoder is done.
*NFIECC_ENCCON = 0x1 ; //Encoder starts.
b-l CO
while (*NFIECC_PIO_DIRDY==0x1) { //Wait the NFIECC_PIO_DIRDY is active then
*NFIECC_PIO_DI = DATA[i]; i++ } //Input data 32bit by 32bit input NFIECC_PIO_DI APB register.
//After all data has been written in PIO_DI and encoder has been done, IDLE
while (*NFIECC_ENCIDLE==0x1) ;
will be asserted.
parity = {*NFIECC_PAR0,*NFIECC_PAR1,
// Read out parity from APB register after IDLE=1 and must append parity
*NFIECC_PAR2, *NFIECC_PAR3,
18 TEK
bits behind the original data for decoding.
*NFIECC_PAR4}
Decoding in NFI mode
Caution: Before NFI address phase enable and configure ECC.
Caution: When NFI AUTO_FMT_EN=0, ECC will correct all errors (include parity bits) found in Chien search.
@
RD A
Be careful of those FDM data that was not protected by ECC. Those data would not be realized by ECC
module and might be polluted by ECC module.
Caution: ECC correct limitation is error_limit = error_correct_capability. If the error number(data error
R DI
number + parity error number) is bigger than the error_limit, ECC might decode error.
Configure Memo
*NFIECC_DECCNFG = 0x90743010; //configure Decoder parameter in NFI mode.
FO ME
//configure FDM0 APB address in NFI mode into FDMADDR.
*NFIECC_FDMADDR = 0x800320A0;
(NFI_BASE_ADDR+FDM0_OFFSET_ADDR)
*NFIECC_DECCON = 0x1 ; //enable Decoder.
for i = 1:8 // 8 is equal to NFI read sector number.
while (NFI_STR==0x1) ; //NFI_STR is happened in NFI address phase. NFI_STR is from NFI.
0 = *NFIECC_DECIDLE ; //It indicates the start is triggered and Decoder is in busy state.
//Wait all message data from NFI. After all data has input IDLE will be
while (*NFIECC_DECIDLE==0x1) ;
asserted and FER will be reported.
end for
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L Y
while (*NFIECC_DECDONE==0xff) //Decoder and correction processor is done.
SE AL
Additional Usage for detecting error number or uncorrectable error (execute after Done)
ON
while (*NFIECC_DECFSM==0x0) //All Hardware is done
ERR_SEC = *NFIECC_FER //Read Error status
for i = 0 : (SEC_NUM-1)
if (ERR_SEC[i] == 1) //If the sector has error
n U TI
ERR_NUM = *NFIECC_DECENUM //Read Error number
end if
//Read Error Location to check if location exceeds coded data size. If error
t.c EN
for i = 0 : (ERR_NUM-1)
location exceeds coded data size, it is an uncorrected decoding sector.
ErrorLocation[i] = *NFIECC_EL0+2i;
end for
end for
.ne ID
*NFIECC_DECCON = 0x0 //Disable Decoder.
Decoding in DMA mode
Configure Memo
ink NF
while (*NFIECC_DECIDLE==1) ; //polling IDLE signal until Decoder is available.
*NFIECC_DECCNFG = 0x90743010; //configure Decoder parameter in NFI mode.
*NFIECC_DECIRQEN = 0x1; //If IRQ is required when Encoder is done.
*NFIECC_DECDIADDR= 0x10000000; //Configure Data start address.
b-l CO
*NFIECC_DECCON = 0x1 ; //Decoder starts to fetch data from DECDIADDR.
0 = *NFIECC_DECIDLE ; //It indicates the start is triggered and Decoder is in busy state.
while (*NFIECC_DECDONE==0x1) //Decoder and correction processor is done.
Additional Usage for detecting error number or uncorrectable error (execute after Done)
while (*NFIECC_DECFSM==0x0) //All Hardware is done
ERR_SEC = *NFIECC_FER //Read Error status
18 TEK
for i = 0 : (SEC_NUM-1) //In DMA mode only support SEC_NUM=1
if (ERR_SEC[i] == 1) //If the sector has error
ERR_NUM = *NFIECC_DECENUM //Read Error number
end if
//Read Error Location to check if location exceeds coded data size. If error
for i = 0 : (ERR_NUM-1)
location exceeds coded data size, it is an uncorrected decoding sector.
@
RD A
ErrorLocation[i] = *NFIECC_EL0+2i;
end for
end for
R DI
*NFIECC_DECCON = 0x0 //Disable Decoder.
Decoding in PIO mode
FO ME
Configure Memo
while (*NFIECC_DECIDLE==1) ; //polling IDLE signal until Decoder is available.
*NFIECC_DECCNFG = 0x90743010; //configure Decoder parameter in NFI mode.
*NFIECC_DECIRQEN = 0x1; //If IRQ is required when Encoder is done.
*NFIECC_DECCON = 0x1 ; //Decoder starts.
while (*NFIECC_PIO_DIRDY==0x1) { //Wait the NFIECC_PIO_DIRDY is active then
*NFIECC_PIO_DI = DATA[i]; i++ } //Input data 32bit by 32bit input NFIECC_PIO_DI APB register.
while (*NFIECC_DECDONE==0x1) //Decoder and correction processor is done.
Additional Usage for detecting error number or uncorrectable error (execute after Done)
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L Y
while (*NFIECC_DECFSM==0x0) //All Hardware is done
SE AL
ERR_SEC = *NFIECC_FER //Read Error status
ON
for i = 0 : (SEC_NUM-1) //In PIO mode only support SEC_NUM=1
if (ERR_SEC[i] == 1) //If the sector has error
ERR_NUM = *NFIECC_DECENUM //Read Error number
end if
n U TI
//Read Error Location to check if location exceeds coded data size. If error
for i = 0 : (ERR_NUM-1)
location exceeds coded data size, it is an uncorrected decoding sector.
ErrorLocation[i] = *NFIECC_EL0+2i;
t.c EN
end for
end for
*NFIECC_DECCON = 0x0 //Disable Decoder.
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.10 PCM Controller
ON
2.10.1 Features
Two clock sources are reserved for PCM circuit. (From internal clock generator, INT_PCM_CLK and
EXT_PCM_CLK)
n U TI
PCM module can drive a clock out (with fraction-N dividor) to an external codec.
Up to 4 channels PCM are available. 4 to 128 slots are configurable.
Each channel supports a-law (8-bit)/u-law (8-bit)/raw-PCM (8-bit and 16-bit) transfer.
Hardware converter of a-law<->raw-16 and u-law <-> raw-16 are implemented in design.
t.c EN
Support long (8 cycle)/short (1 cycle)/configurable (intervals are configurable, use to emulate I S
2
interface) FSYNC.
DATA & FSYNC can be driven and sampled by either rising/falling of clock.
Last bit of DTX can be configured as tri-stated on falling edge.
.ne ID
Beginning of each slot is configurable by 10-bit registers on each channel.
32-byte FIFO are available for each channel
PCM interface can emulate I2S interface (only 16-bit data-width supported ).
ink NF
MSB/LSB order is configurable.
Supports both a-law/u-law (8-bits) linear PCM(16-bit) and linear PCM(16-bit) a-law/u-law (8-bit)
2.10.2 Block Diagram
PCM Module
b-l CO
APBBUS
PCM Control
APBBUS LTF
Status Register
18 TEK
RFIFO TFIFO RFIFO TFIFO
(32 bytes) (32 bytes) (32 bytes) (32 bytes)
@
RD A
DRAM CH1 CH0
GDMA LTF
R DI
a/ulaw a/ulaw
SYS clock domain
FO ME
PCM clock domain
PCM IF/I2S IF
Figure 2-4 PCM Controller Block Diagram
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MT7621 PROGRAMMING GUIDE
L Y
Two clock domains are partitioned in this design. PCM converter (u-law < = > raw-16-bit and A-law < = > raw
SE AL
16-bit) are implemented in PCM. The threshold of FIFO is configurable. When the threshold is reached, PCM (a)
ON
triggers the DMA interface to notify external DMA engine to transfer data, and (b) triggers an interrupt to the
host.
The interrupt sources include:
The threshold is reached.
n U TI
FIFO is under-run or over-run.
A fault is detected at the DMA interface.
The A-law and u-law converter is implemented based on the ITU-G.711 A-law and u-law table. In this design,
t.c EN
both A-law/u-law(8-bit) linear PCM (16-bit) and linear PCM (16-bit) A-law/u-law (8-bit) are supported.
The data-flow from codec to PCM-controller (Rx-flow) is shown as below:
The PCM controller latches the data from DRX at the indicated time slot and then writes it to FIFO. If FIFO
is full, the data is lost.
.ne ID
When the Rx-FIFO reaches the threshold, two actions may be taken:
When DMA_ENA=1, DMA_REQ is asserted to request a burst transfer. It rechecks the FIFO threshold
after DMA_END is asserted by GDMA. (GDMA should be configured before channel is enabled.)
Assert the interrupt source to notify the host. The host can check RFIFO_AVAIL information then get
ink NF
back the data from FIFO.
The data flow from the PCM controller to codec (Tx-flow) is shown below. After GDMA is configured, software
should configure and enable the PCM channel. The empty FIFO should behave as follows.
b-l CO
When DMA_ENA=1, DMA_REQ is triggered to request a burst transfer. It then re-checks the FIFO
threshold after DMA_END is asserted by GDMA (a burst is completed).
The Interrupt source is asserted to notify HOST. HOST writes the data to Tx-FIFO. After that, HOST
rechecks TFIFO_EMPTY information, and then writes more data if available.
18 TEK
NOTE: When DMA_ENA=1, the burst size of GDMA should be less than the threshold value.
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.10.3 List of Registers
ON
PCM Changes LOG
Revision Date Author Change Log
0.1 2012/10/8 Paddy Wu Initialization
n U TI
Module name: PCM Base address: (+1E002000h)
t.c EN
Address Name Widt Register Function
h
1E002000 GLB_CFG 32 Global Config
1E002004 PCM_CFG 32 PCM configuration
.ne ID
1E002008 INT_STATUS 32 Interrupt status
1E00200C INT_EN 32 Interrupt enable
1E002010 CHA0_FF_STATU 32 Channel A0(represents channel 0) FIFO status
S
ink NF
1E002014 CHB0_FF_STATU 32 Channel B0(represents channel 1) FIFO status
S
1E002020 CHA0_CFG 32 Channel A0(represents channel 0) Config
1E002024 CHB0_CFG 32 Channel B0(represents channel 1) Config
b-l CO
1E002030 FSYNC_CFG 32 FSYNC config
1E002034 CHA0_CFG2 32 Channel A0(represents channel 0) Config
1E002038 CHB0_CFG2 32 Channel B0(represents channel 1) Config
1E002040 IP_INFO 32 IP version info
1E002044 RSV_REG16 32 SPARE REG 16 bits
18 TEK
1E002050 DIVCOMP_CFG 32 Dividor Compensation part config
1E002054 DIVINT_CFG 32 Dividor Integer part config
1E002060 DIGDELAY_CFG 32 Digital delay config
1E002080 CH0_FIFO 32 Channel 0 FIFO access point
1E002084 CH1_FIFO 32 Channel 1 FIFO access point
1E002088 CH2_FIFO 32 Channel 2 FIFO access point
@
1E00208C CH3_FIFO 32 Channel 3 FIFO access point
RD A
1E002110 CHA0_FF_STATU 32 Channel A1(represents channel 3) FIFO status
S
R DI
1E002114 CHB1_FF_STATU 32 Channel B1(represents channel 4) FIFO status
S
1E002120 CHA1_CFG 32 Channel A1(represents channel 3) Config
1E002124 CHB1_CFG 32 Channel B1(represents channel 1) Config
FO ME
1E002134 CHA1_CFG2 32 Channel A1(represents channel 3) Config
1E002138 CHB1_CFG2 32 Channel B1(represents channel 4) Config
1E002000 GLB_CFG Global Config 0044000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PC DM LB EXT
RSV0 RFF_THRES
RS
TFF_THRES
M_ A_E K_E _LB V1
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MT7621 PROGRAMMING GUIDE
L Y
EN N N K_E
SE AL
N
Type RW RW RW RW RO RW RO RW
ON
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV2 CH_EN
Type RO RW
n U TI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 PCM_EN PCM Enable
t.c EN
When disabled, all FSM of PCM are cleared to their default value.
0: disable
1: enable
30 DMA_EN DMA Enable
0: Disable the DMA interface, transfer data using software.
.ne ID
1: Enable the DMA interface, transfer data using DMA.
0: disable
1: enable
29 LBK_EN loopback enable, loopback path is shown as (Asyn-TXFIFO ->DTX -> DRX->Asyn-
ink NF
RXFIFO)
0: disable
1: enable
28 EXT_LBK_EN loopback enable, loopback path is shown as (Ext-Codec->DRX->DTX->Ext-
Codec)
0: disable
b-l CO
1: enable
27:23 RSV0 Reserved
22:20 RFF_THRES RXFIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO. The threshold
should be >2 and <6.
When data in FIFO is under the threshold, the following interrupts and GDMA are
18 TEK
triggered.
CH0T_THRES, CH0R_THRES, CH1T_THRES, CH1R_THRES
(unit: word)
19 RSV1 Reserved
18:16 TFF_THRES TXFIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO.
It should be >2 and <6.
When data in FIFO is over the threshold, an interrupt and DMA are triggered.
@
(unit: word)
RD A
15:4 RSV2 Reserved
3:0 CH_EN Channels 3 to 0 Tx and Rx Enable
R DI
0: disable
1: enable
FO ME
1E002004 PCM_CFG PCM configuration 0300000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL EXT LO FSY
DT
RS KO _FS NG NC
RSV1 X_T RSV2[20:13]
V0 UT_ YN _SY _P
RI
EN C NC OL
Type RO RW RO RW RW RW RW RO
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Name RSV2[12:0] SLOT_MODE
SE AL
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31 RSV0 Reserved
n U TI
30 CLKOUT_EN PCM Clock Out Enable
0: A PCM clock is provided from the external Codec/OSC.
1: A PCM clock is provided from the internal dividor.
NOTE: Normally, the register should be asserted to 1. Also, it should be asserted after
t.c EN
configuring the divider and enabling the divider clock.
0: EXT_CLK
1: INT_DIV
29:28 RSV1 Reserved
27 EXT_FSYNC FSYNC is provided externally
.ne ID
0: FSYNC is generated by internal circuit.
1: FSYNC is provided externally
26 LONG_SYNC FSYNC Mode
0: Short FSYNC
1: Long FSYNC
ink NF
25 FSYNC_POL FSYNC Polarity
0: FSYNC is low active
1: FSYNC is high active
24 DTX_TRI DTX Tri-State
b-l CO
Tristates DTX when the clock signal on the last bit is has a falling edge.
0: Non- tristate DTX
1: Tristate DTX
23:3 RSV2 Reserved
2:0 SLOT_MODE Sets the number of slots in each PCM frame.
0: 4 slots, PCM clock out/in should be 256 KHz.
1: 8 slots, PCM clock out/in should be 512 KHz.
18 TEK
2: 16 slots, PCM clock out/in should be 1.024 MHz.
3: 32 slots, PCM clock out/in should be 2.048 MHz.
4: 64 slots, PCM clock out/in should be 4.096 MHz.
5:128 slots, PCM clock out/in should be 8.192 MHz.
Other: Reserved.
NOTE: When using the external clock, the frequency clock should be equal to
PCM_clock out. Otherwise, the PCM_CLKin should be 8.192 MHz.
0: _4_SLOT
1: _8_SLOT
@
2: _16_SLOT
RD A
3: _32_SLOT
4: _64_SLOT
5: _128_SLOT
R DI
1E002008 INT_STATUS Interrupt status 0000000
FO ME
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
CH CH CH
CH CH CH
CH
T_D R_ R_ R_
T_O T_U T_T R_T
RSV0[7:0] MA DM OV UN
VR NR HR HR
_FA A_F RU RU
UN UN ES ES
ULT AU N N
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MT7621 PROGRAMMING GUIDE
L Y
LT
SE AL
Type RO
W1 W1 W1 W1 W1 W1 W1 W1
C C C C C C C C
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
31:8 RSV0 Reserved
7 CHT_DMA_FAULT Channel Tx DMA Fault Interrupt, Asserts when a fault has been detected in a CH-
Tx DMA signal.
6 CHT_OVRUN Channel Tx FIFO Overrun Interrupt, Asserts when the CH-Tx FIFO is overrun.
t.c EN
5 CHT_UNRUN Channel Tx FIFO Underrun Interrupt, Asserts when the CH-Tx FIFO is underrun.
4 CHT_THRES Channel Tx Threshold Interrupt, Asserts when the CH-Tx FIFO is lower than the
defined threshold.
3 CHR_DMA_FAULT Channel Rx DMA Fault Interrupt, Asserts when a fault is detected in a CH-Rx
DMA signal.
.ne ID
2 CHR_OVRUN Channel Rx Overrun Interrupt, Asserts when the CH-Rx FIFO is overrun.
1 CHR_UNRUN Channel Rx Underrun Interrupt, Asserts when the CH-Rx FIFO is underrun.
0 CHR_THRES Channel Rx Threshold Interrupt, Asserts when the CH-Rx FIFO is lower than the
defined threshold.
ink NF
1E00200C INT_EN Interrupt enable 0000000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[23:8]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name INT INT INT INT INT INT INT INT
18 TEK
RSV0[7:0] 7_E 6_E 5_E 4_E 3_E 2_E 1_E 0_E
N N N N N N N N
Type RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:8 RSV0 Reserved
@
7 INT7_EN INT_STATUS[7] Enable,Enables the Channel Tx DMA Fault Interrupt. This
RD A
interrupt asserts when a fault has been detected in a CH-Tx DMA signal.
6 INT6_EN INT_STATUS[6] Enable,Enables the Channel Tx FIFO Overrun Interrupt. This
interrupt asserts when the CH-Tx FIFO is overrun.
R DI
5 INT5_EN INT_STATUS[5] Enable,Enables the Channel Tx FIFO Underrun Interrupt. This
interrupt asserts when the CH-Tx FIFO is underrun.
4 INT4_EN INT_STATUS[4] Enable,Enables the Channel Tx Threshold Interrupt. This
interrupt when the CH-Tx FIFO is lower than the defined threshold.
FO ME
3 INT3_EN INT_STATUS[3] Enable,Enables the Channel Rx DMA Fault Interrupt. This
interrupt when a fault is detected in a CH-Rx DMA signal.
2 INT2_EN INT_STATUS[2] Enable,Enables the Channel Rx Overrun Interrupt. This interrupt
when the CH-Rx FIFO is overrun.
1 INT1_EN INT_STATUS[1] Enable,Enables the Channel Rx Underrun Interrupt. This
interrupt when the CH-Rx FIFO is under-run.
0 INT0_EN INT_STATUS[0] Enable,Enables the Channel Rx Threshold Interrupt. This
interrupt asserts when the CH-Rx FIFO is lower than the defined threshold.
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MT7621 PROGRAMMING GUIDE
L Y
1E002010 CHA0_FF_ST Channel A0(represents channel 0) FIFO status 0010000
SE AL
ATUS 8
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH CH
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
n U TI
RSV0 OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
Type W1 W1 W1 W1 W1 W1 W1 W1
RO
t.c EN
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
.ne ID
Bit(s) Name Description
31:24 RSV0 Reserved
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A0
ink NF
Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel A0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel A0 Tx FIFO is underrun.
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO is lower
b-l CO
than the defined threshold.
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A0
Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel A0 Rx FIFO is overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel A0 Rx FIFO is underrun.
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO is lower
18 TEK
than the defined threshold.
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel A0 RXFIFO Available Space Count,Counts the available space for reads
in channel A0 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel A0 TXFIFO Available Space Count,Counts the available space for writes
in channel A0 TXFIFO.(unit: word)
@
RD A
1E002014 CHB0_FF_ST Channel B0(represents channel 1) FIFO status 0010000
R DI
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH CH
CH CH CH CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
FO ME
DM DM
RSV0 OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
Type W1 W1 W1 W1 W1 W1 W1 W1
RO
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
31:24 RSV0 Reserved
ON
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B0
Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel B0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel B0 Tx FIFO is underrun.
n U TI
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel B0 FIFO is lower
than the defined threshold.
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B0
Rx DMA signal.
t.c EN
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel B0 Rx FIFO is overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel B0 Rx FIFO is underrun.
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel B0 FIFO is lower
than the defined threshold.
.ne ID
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel B0 RXFIFO Available Space Count,Counts the available space for reads
in channel B0 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel B0 TXFIFO Available Space Count,Counts the available space for writes
ink NF
in channel B0 TXFIFO.(unit: word)
1E002020 CHA0_CFG Channel A0(represents channel 0) Config 0000000
b-l CO
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
@
Sets the conversion method for the hardware converter to compress raw data.
RD A
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
R DI
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
FO ME
compressed format)
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
16-bit format)
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
9:0 TS_START Timeslot starting location
(unit: clock cycles)
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E002024 CHB0_CFG Channel B0(represents channel 1) Config 0000000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
.ne ID
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
ink NF
011: Reserved
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
b-l CO
compressed format)
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
16-bit format)
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
5: EN_R2ULW
18 TEK
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
9:0 TS_START Timeslot starting location
(unit: clock cycles)
@
RD A
1E002030 FSYNC_CFG FSYNC config 2800000
0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CF PO PO
PO PO
G_F S_C S_D
S_C S_D
SY AP_ RV_ RSV0 RSV1[11:6]
AP_ RV_
NC FSY FSY
FO ME
DT DT
_EN NC NC
Type RW RW RW RW RW RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] FSYNC_INTV
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 CFG_FSYNC_EN Enables configurable FSYNC.
30 POS_CAP_DT Positive Edge Capture Data, Sets the PCM controller to capture data on the
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MT7621 PROGRAMMING GUIDE
L Y
negative or positive edge of the PCM clock. NOTE: This configuration should be
0 if DTX_TRI=1.
SE AL
29 POS_DRV_DT Positive Edge Drive Data, Sets the PCM controller to drive data on the negative or
ON
positive edge of the PCM clock.
28 POS_CAP_FSYNC Positive Edge Capture FSYNC, Sets the PCM controller to capture FSYNC on the
positive or negative edge of the PCM clock.
n U TI
27 POS_DRV_FSYNC Positive Edge Driver FSYNC, Sets the PCM controller to drive FSYNC on the
negative or positive edge of the PCM clock.
26:22 RSV0 Reserved
21:10 RSV1 Reserved
t.c EN
9:0 FSYNC_INTV Interval when FSYNC may be configured.
(unit: clock cycles)
.ne ID
1E002034 CHA0_CFG2 Channel A0(represents channel 0) Config 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
ink NF
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH CH
_RX _TX CH
RS
b-l CO
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel A0 Rx FIFO Clear
0: Normal operation
1: Clear this bit
2 CH_TXFF_CLR Channel A0 Tx FIFO Clear
0: Normal operation
1: Clear this bit
@
1 RSV1 Reserved
RD A
0 CH_LSB Enable CH A0 Tx in LSB order.
R DI
1E002038 CHB0_CFG2 Channel B0(represents channel 1) Config 0000000
0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH CH
_RX _TX CH
RS
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel B0 Rx FIFO Clear
0: Normal operation
1: Clear this bit
n U TI
2 CH_TXFF_CLR Channel B0 Tx FIFO Clear
0: Normal operation
1: Clear this bit
1 RSV1 Reserved
t.c EN
0 CH_LSB Enable CH B0 Tx in LSB order.
1E002040 IP_INFO IP version info 0000040
.ne ID
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0
ink NF
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MAX_CH VER
Type RO RO
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
b-l CO
Bit(s) Name Description
31:16 RSV0 Reserved
15:8 MAX_CH Maximum channel number.
7:0 VER Version of this PCM Controller
18 TEK
1E002044 RSV_REG16 SPARE REG 16 bits 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0
@
Type RO
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPARE_REG
R DI
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
31:16 RSV0 Reserved
15:0 SPARE_REG Spare register for future use
1E002050 DIVCOMP_CF Dividor Compensation part config 0000000
G 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL
RSV0[22:8]
K_E
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MT7621 PROGRAMMING GUIDE
L Y
N
SE AL
Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV0[7:0] DIVCOMP
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31 CLK_EN Clock Enable
t.c EN
Enables setting of the PCM interface clock based on DIVCOMP and DIVINT
parameters.
30:8 RSV0 Reserved
7:0 DIVCOMP A parameter in an equation which determines FREQOUT. See DIVINT.
.ne ID
1E002054 DIVINT_CFG Dividor Integer part config 0000000
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[21:6]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name RSV0[5:0] DIVINT
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:10 RSV0 Reserved
18 TEK
9:0 DIVINT A parameter in an equation which determines FREQOUT.
Formula:
FREQOUT = 1/(FREQIN*2*(DIVINT+DIVCOMP /(2^8)))
FREQIN is always fixed to 40 MHz.
1E002060 DIGDELAY_C Digital delay config 0000000
@
RD A
FG 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX CH CH CH CH
R DI
TX
D_ EN_ EN EN EN
D_
CL CL N_ P_ RS PD_
RSV0 GL RSV1 RSV2
R_ R_ GL GL V3 GL
T_S
GL GL T_S T_S T_S
T
T T T T T
FO ME
Type RW RW RO RW RO RW RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX CH
D_ EN_
DIG DIG
RSV4 TXD_DLYVAL RSV5 CHEN_DLYVAL
DL DL
Y_E Y_E
N N
Type RW RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
31 TXD_CLR_GLT TXD Clear Glitch Flag
ON
Clears the glitch detected flag for TXD.
0: No effect.
1: Clear the flag.
30 CHEN_CLR_GLT Channel Enable (CHEN) Clear Glitch Flag
n U TI
Clears the glitch detected flag for CHEN.
0: No effect .
1: Clear the flag.
29:27 RSV0 Reserved
t.c EN
26 TXD_GLT_ST TXD Glitch Status
Indicates if a glitch is detected in a TXD signal. It can be cleared by bit[31].
0: Not detected.
1: Detected
25:23 RSV1 Reserved
.ne ID
22 CHENN_GLT_ST CHEN Negative Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30] (negedge
sample).
0: Not detected.
1: Detected
ink NF
21:19 RSV2 Reserved
18 CHENP_GLT_ST CHEN Positive Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30] (posedge
sample).
0: Not detected.
b-l CO
1: Detected
17 RSV3 Reserved
16 CHENPD_GLT_ST CHEN Positive Delay Glitch Status
Indicates if a glitch is detected in a CHEN signal. It can be cleared by bit[30] (posedge
sample, delay 1 cycle).
0: Not detected.
18 TEK
1: Detected
15 TXD_DIGDLY_EN TXD Digital Delay Enable
Enables digital delay path.
0: Disable
1: Enable
14:13 RSV4 Reserved
12:8 TXD_DLYVAL Delay Count Value
@
The description is the same as the CHEN_DLYVAL field in this register.
RD A
CHEN Digital Delay Enable, Enables the digital delay path.
0: Disable
1: Enable
R DI
7 CHEN_DIGDLY_EN CHEN Digital Delay Enable
Enables the digital delay path.
0: Disable
1: Enable
FO ME
6:5 RSV5 Reserved
4:0 CHEN_DLYVAL Delay Count Value
The delay error =
CLK_PERIOD * (SYNC_DELAY + SYNC_DELTA + (DLYCNT_CFG) + 1)
For example,
DLYCNT_CFG = 4,
(SYNC_DELAY is always fixed to 4)
Final Delay
= CLK_PERIOD * (2 + (-1/0/+1) + (4) + 1)
= CLK_PERIOD * (6/7/8)= CLK_PERIOD * (6 to 8)
= 25 ns to 33.3 ns
NOTE:
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MT7621 PROGRAMMING GUIDE
L Y
Period is 1/240 MHz = 4.1667 ns in MT7620.
SE AL
ON
1E002080 CH0_FIFO Channel 0 FIFO access point 0000000
0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH0_FIFO[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH0_FIFO[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:0 CH0_FIFO
ink NF Channel 0 FIFO access point
1E002084 CH1_FIFO Channel 1 FIFO access point 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH1_FIFO[31:16]
b-l CO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH1_FIFO[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 CH1_FIFO Channel 1 FIFO access point
1E002088 CH2_FIFO Channel 2 FIFO access point 0000000
@
0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH2_FIFO[31:16]
Type RW
R DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH2_FIFO[15:0]
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH2_FIFO Channel 2 FIFO access point
1E00208C CH3_FIFO Channel 3 FIFO access point 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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MT7621 PROGRAMMING GUIDE
L Y
Name CH3_FIFO[31:16]
SE AL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH3_FIFO[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:0 CH3_FIFO Channel 3 FIFO access point
t.c EN
1E002110 CHA0_FF_ST Channel A1(represents channel 3) FIFO status 0010000
ATUS 8
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH
CH CH CH
CH
CH CH CH
TX_ RX_
TX_ TX_ TX_ RX_ RX_ RX_
DM DM
RSV0 OV UN TH OV UN TH
A_F A_F
ink NF
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
Type W1 W1 W1 W1 W1 W1 W1 W1
RO
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit(s) Name Description
31:24 RSV0 Reserved
18 TEK
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A1
Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel A0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel A1 Tx FIFO is underrun.
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel A0 FIFO is lower
than the defined threshold.
@
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel A1
RD A
Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel A1 Rx FIFO is overrun.
R DI
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel A1 Rx FIFO is underrun.
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel A1 FIFO is lower
than the defined threshold.
15:8 RSV1 Reserved
FO ME
7:4 CHRFF_AVCNT Channel A1 RXFIFO Available Space Count,Counts the available space for reads
in channel A1 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel A1 TXFIFO Available Space Count,Counts the available space for writes
in channel A1 TXFIFO.(unit: word)
1E002114 CHB1_FF_ST Channel B1(represents channel 4) FIFO status 0010000
ATUS 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CH CH CH CH CH CH CH CH
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MT7621 PROGRAMMING GUIDE
L Y
TX_ TX_ TX_ TX_ RX_ RX_ RX_ RX_
SE AL
DM OV UN TH DM OV UN TH
A_F RU RU RE A_F RU RU RE
ON
AU N N S AU N N S
LT LT
Type RO
W1 W1 W1 W1 W1 W1 W1 W1
C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1 CHRFF_AVCNT CHTFF_EPCNT
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
t.c EN
Bit(s) Name Description
31:24 RSV0 Reserved
23 CHTX_DMA_FAULT Tx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B1
.ne ID
Tx DMA signal.
22 CHTX_OVRUN Tx Overrun Interrupt,Asserts when the Channel B0 Tx FIFO is overrun.
21 CHTX_UNRUN Tx FIFO Underrun Interrupt,Asserts when the Channel B1 Tx FIFO is underrun.
20 CHTX_THRES Tx FIFO Below Threshold Interrupt,Asserts when the Channel B1 FIFO is lower
ink NF
than the defined threshold.
19 CHRX_DMA_FAULT Rx DMA Fault Detected Interrupt,Asserts when a fault is detected in a Channel B1
Rx DMA signal.
18 CHRX_OVRUN Rx FIFO Overrun Interrupt,Asserts when the Channel B1 Rx FIFO is overrun.
17 CHRX_UNRUN Rx FIFO Underrun Interrupt,Asserts when the Channel B1 Rx FIFO is underrun.
b-l CO
16 CHRX_THRES Rx FIFO Below Threshold Interrupt,Asserts when the Channel B1 FIFO is lower
than the defined threshold.
15:8 RSV1 Reserved
7:4 CHRFF_AVCNT Channel B1 RXFIFO Available Space Count,Counts the available space for reads
in channel B1 RXFIFO.(unit: word)
3:0 CHTFF_EPCNT Channel B1 TXFIFO Available Space Count,Counts the available space for writes
18 TEK
in channel B1 TXFIFO.(unit: word)
1E002120 CHA1_CFG Channel A1(represents channel 3) Config 0000000
1
@
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD A
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
FO ME
Bit(s) Name Description
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw data.
000: Disable HW converter, linear raw data (16-bit)
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
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MT7621 PROGRAMMING GUIDE
L Y
110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
compressed format)
SE AL
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
ON
16-bit format)
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
5: EN_R2ULW
n U TI
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
9:0 TS_START Timeslot starting location
t.c EN
(unit: clock cycles)
1E002124 CHB1_CFG Channel B1(represents channel 1) Config 0000000
.ne ID
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0 CMP_MODE RSV1[16:6]
Type RO RW RO
ink NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RSV1[5:0] TS_START
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
b-l CO
Bit(s) Name Description
31:30 RSV0 Reserved
29:27 CMP_MODE Compression Mode
Sets the conversion method for the hardware converter to compress raw data.
000: Disable HW converter, linear raw data (16-bit)
18 TEK
010: Disable HW converter, linear raw data (8-bit), A-law or u-law (8-bit)
011: Reserved
100: Enable HW converter, raw data(16-bit) ? U-law mode (8-bit) (PCM bus in
compressed format)
101: Enable HW converter, u-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw, 16-
bit format)
110: Enable HW converter, raw data (16-bit) ? A-law mode (8-bit) (PCM bus in
compressed format)
@
111: Enable HW converter, A-law mode (8-bit) ? raw data (16-bit) (PCM bus in raw,
RD A
16-bit format)
0: DIS_CONV16
2: DIS_CONV8
4: EN_ULW2R
R DI
5: EN_R2ULW
6: EN_ALW2R
7: EN_R2ALW
26:10 RSV1 Reserved
FO ME
9:0 TS_START Timeslot starting location
(unit: clock cycles)
1E002134 CHA1_CFG2 Channel A1(represents channel 3) Config 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
Type RO
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH CH
ON
_RX _TX CH
RS
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
n U TI
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
t.c EN
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel A1 Rx FIFO Clear
0: Normal operation
1: Clear this bit
2 CH_TXFF_CLR Channel A1 Tx FIFO Clear
.ne ID
0: Normal operation
1: Clear this bit
1 RSV1 Reserved
0 CH_LSB Enable CH A1 Tx in LSB order.
ink NF
1E002138 CHB1_CFG2 Channel B1(represents channel 4) Config 0000000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RSV0[27:12]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH CH
18 TEK
_RX _TX CH
RS
RSV0[11:0] FF_ FF_ _LS
V1
CL CL B
R R
Type RO RW RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
RD A
31:4 RSV0 Reserved
3 CH_RXFF_CLR Channel B1 Rx FIFO Clear
0: Normal operation
R DI
1: Clear this bit
2 CH_TXFF_CLR Channel B1 Tx FIFO Clear
0: Normal operation
1: Clear this bit
FO ME
1 RSV1 Reserved
0 CH_LSB Enable CH B1 Tx in LSB order.
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.10.4 PCM Configuration
PCM Initialization Flow
ON
1. Set PCM_CFG
2. Set CH0/1_CFG
3. Write PCM data to FIFO CH0/1_FIFO
n U TI
4. Set GLB_CFG to enable the PCM and channel.
5. Set dividor clock
6. Enable clock
7. Monitor FF_STATUS to receive/transmit the other PCM data.
t.c EN
PCM Configuration Examples
Below are some examples of PCM configuration.
.ne ID
Case 1:
CFG_FSYNC Register: CFG_FSYNC_EN = 0 (PS: fsync is always driven at SLOT_CNT=1)
CH0_CFG Register: TS_START=1
ink NF
CH1_CFG Register: TS_START=9
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0
b-l CO
18 TEK
Case 2:
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0, interval=16
@
CH0_CFG Register: TS_START=1
RD A
CH1_CFG Register: TS_START=17
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b1, DRX_TRI=1’b0, SLOT_MODE=3’b0, RAW16-bits
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
Case 3:
CFG_FSYNC Register: CFG_FSYNC_EN = 1, START_LOC=0x1A, interval=2
CH0_CFG Register: TS_START=1 (disable)
n U TI
CH1_CFG Register: TS_START=0x1A
PCM_CFG Register: LONG_FSYNC=1’b0, FSYNC_POL=1’b0 (LOW active), DRX_TRI=1’b0, SLOT_MODE=3’b0,
RAW16-bits
t.c EN
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.11 Generic DMA Controller
ON
2.11.1 Features
Supports 16 DMA channels
Supports 32 bit address.
n U TI
Maximum 65535 byte transfer
Programmable DMA burst size (1, 2, 4, 8, 16 double word burst)
Supports memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral
t.c EN
transfers.
Supports continuous mode.
Supports division of target transfer count into 1 to 256 segments
Support for combining different channels into a chain.
Programmable hardware channel priority.
.ne ID
Interrupts for each channel.
2.11.2 Block Diagram
ink NF
Rbus Interface Rbus Interface
b-l CO
(Master) Rbus Rbus (Master)
Master Master
DMA Engine
DMA
18 TEK
Interface
Arbiter
@
RD A
Interrupt
Interface Ch0 APBbus
R DI
Interrupt Interface
Controller ABbus (Slave)
Mux
Slave
FO ME
Ch"n"
Figure 2-5 Generic DMA Controller Block Diagram
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MT7621 PROGRAMMING GUIDE
L Y
2.11.3 Peripheral Channel Connection
SE AL
Channel number Peripheral
ON
0 Reserved
1 Reserved
2 I2S Controller (TXDMA)
n U TI
3 I2S Controller (RXDMA)
4 PCM Controller (RDMA, channel-0)
t.c EN
5 PCM Controller (RDMA, channel-1)
6 PCM Controller (TDMA, channel-0)
7 PCM Controller (TDMA, channel-1)
8 PCM Controller (RDMA, channel-2)
.ne ID
9 PCM Controller (RDMA, channel-3)
10 PCM Controller (TDMA, channel-2)
11 PCM Controller (TDMA, channel-3)
ink NF
12 SPI Controller (RXDMA)
13 SPI Controller (TXDMA)
8 to 15 Reserved
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.11.4 Registers
ON
GDMA Changes LOG
Revision Date Author Change Log
0.1 2012/10/15 Mark Wang Initialization
n U TI
Module name: GDMA Base address: (+1E002800h)
t.c EN
Address Name Widt Register Function
h
1E002800 GDMA_SA_0 32 Source Address of GDMA Channel 0
1E002804 GDMA_DA_0 32 Destination Address of GDMA Channel 0
.ne ID
1E002808 GDMA_CT0_0 32 Control Register 0 of GDMA Channel 0
1E00280C GDMA_CT1_0 32 Control Register 1 of GDMA Channel 0
1E002810 GDMA_SA_1 32 Source Address of GDMA Channel 1
1E002814 GDMA_DA_1 32 Destination Address of GDMA Channel 1
ink NF
1E002818 GDMA_CT0_1 32 Control Register 0 of GDMA Channel 1
1E00281C GDMA_CT1_1 32 Control Register 1 of GDMA Channel 1
1E002820 GDMA_SA_2 32 Source Address of GDMA Channel 2
1E002824 GDMA_DA_2 32 Destination Address of GDMA Channel 2
b-l CO
1E002828 GDMA_CT0_2 32 Control Register 0 of GDMA Channel 2
1E00282C GDMA_CT1_2 32 Control Register 1 of GDMA Channel 2
1E002830 GDMA_SA_3 32 Source Address of GDMA Channel 3
1E002834 GDMA_DA_3 32 Destination Address of GDMA Channel 3
1E002838 GDMA_CT0_3 32 Control Register 0 of GDMA Channel 3
18 TEK
1E00283C GDMA_CT1_3 32 Control Register 1 of GDMA Channel 3
1E002840 GDMA_SA_4 32 Source Address of GDMA Channel 4
1E002844 GDMA_DA_4 32 Destination Address of GDMA Channel 4
1E002848 GDMA_CT0_4 32 Control Register 0 of GDMA Channel 4
1E00284C GDMA_CT1_4 32 Control Register 1 of GDMA Channel 4
@
1E002850 GDMA_SA_5 32 Source Address of GDMA Channel 5
RD A
1E002854 GDMA_DA_5 32 Destination Address of GDMA Channel 5
1E002858 GDMA_CT0_5 32 Control Register 0 of GDMA Channel 5
R DI
1E00285C GDMA_CT1_5 32 Control Register 1 of GDMA Channel 5
1E002860 GDMA_SA_6 32 Source Address of GDMA Channel 6
1E002864 GDMA_DA_6 32 Destination Address of GDMA Channel 6
32
FO ME
1E002868 GDMA_CT0_6 Control Register 0 of GDMA Channel 6
1E00286C GDMA_CT1_6 32 Control Register 1 of GDMA Channel 6
1E002870 GDMA_SA_7 32 Source Address of GDMA Channel 7
1E002874 GDMA_DA_7 32 Destination Address of GDMA Channel 7
1E002878 GDMA_CT0_7 32 Control Register 0 of GDMA Channel 7
1E00287C GDMA_CT1_7 32 Control Register 1 of GDMA Channel 7
1E002880 GDMA_SA_8 32 Source Address of GDMA Channel 8
1E002884 GDMA_DA_8 32 Destination Address of GDMA Channel 8
1E002888 GDMA_CT0_8 32 Control Register 0 of GDMA Channel 8
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MT7621 PROGRAMMING GUIDE
L Y
1E00288C GDMA_CT1_8 32 Control Register 1 of GDMA Channel 8
SE AL
1E002890 GDMA_SA_9 32 Source Address of GDMA Channel 9
ON
1E002894 GDMA_DA_9 32 Destination Address of GDMA Channel 9
1E002898 GDMA_CT0_9 32 Control Register 0 of GDMA Channel 9
1E00289C GDMA_CT1_9 32 Control Register 1 of GDMA Channel 9
n U TI
1E0028A0 GDMA_SA_10 32 Source Address of GDMA Channel 10
1E0028A4 GDMA_DA_10 32 Destination Address of GDMA Channel 10
1E0028A8 GDMA_CT0_10 32 Control Register 0 of GDMA Channel 10
t.c EN
1E0028AC GDMA_CT1_10 32 Control Register 1 of GDMA Channel 10
1E0028B0 GDMA_SA_11 32 Source Address of GDMA Channel 11
1E0028B4 GDMA_DA_11 32 Destination Address of GDMA Channel 11
1E0028B8 GDMA_CT0_11 32 Control Register 0 of GDMA Channel 11
32
.ne ID
1E0028BC GDMA_CT1_11 Control Register 1 of GDMA Channel 11
1E0028C0 GDMA_SA_12 32 Source Address of GDMA Channel 12
1E0028C4 GDMA_DA_12 32 Destination Address of GDMA Channel 12
1E0028C8 GDMA_CT0_12 32 Control Register 0 of GDMA Channel 12
ink NF
1E0028CC GDMA_CT1_12 32 Control Register 1 of GDMA Channel 12
1E0028D0 GDMA_SA_13 32 Source Address of GDMA Channel 13
1E0028D4 GDMA_DA_13 32 Destination Address of GDMA Channel 13
1E0028D8 GDMA_CT0_13 32 Control Register 0 of GDMA Channel 13
b-l CO
1E0028DC GDMA_CT1_13 32 Control Register 1 of GDMA Channel 13
1E0028E0 GDMA_SA_14 32 Source Address of GDMA Channel 14
1E0028E4 GDMA_DA_14 32 Destination Address of GDMA Channel 14
1E0028E8 GDMA_CT0_14 32 Control Register 0 of GDMA Channel 14
1E0028EC GDMA_CT1_14 32 Control Register 1 of GDMA Channel 14
18 TEK
1E0028F0 GDMA_SA_15 32 Source Address of GDMA Channel 15
1E0028F4 GDMA_DA_15 32 Destination Address of GDMA Channel 15
1E0028F8 GDMA_CT0_15 32 Control Register 0 of GDMA Channel 15
1E0028FC GDMA_CT1_15 32 Control Register 1 of GDMA Channel 15
1E002A00 GDMA_UNMASK_I 32 Unmask Fail Interrupt Status
NTSTS
@
1E002A04 GDMA_DONE_INT 32 Segment Done Interrupt Status
RD A
STS
1E002A20 GDMA_GCT 32 Global Control
R DI
1E002A30 GDMA_PERI_ADD 32 Peripheral Region 0 Starting Address
R_START_0
1E002A34 GDMA_PERI_ADD 32 Peripheral Region 0 End Address
R_END_0
FO ME
1E002A38 GDMA_PERI_ADD 32 Peripheral Region 1 Starting Address
R_START_1
1E002A3C GDMA_PERI_ADD 32 Peripheral Region 1 End Address
R_END_1
1E002A40 GDMA_PERI_ADD 32 Peripheral Region 2 Starting Address
R_START_2
1E002A44 GDMA_PERI_ADD 32 Peripheral Region 2 End Address
R_END_2
1E002A48 GDMA_PERI_ADD 32 Peripheral Region 3 Starting Address
R_START_3
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MT7621 PROGRAMMING GUIDE
L Y
1E002A4C GDMA_PERI_ADD 32 Peripheral Region 3 End Address
SE AL
R_END_3
ON
1E002800 GDMA_SA_0 Source Address of GDMA Channel 0 0000000
n U TI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
t.c EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ink NF
1E002804 GDMA_DA_0 Destination Address of GDMA Channel 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 DEST_ADDR Destination address
@
1E002808 GDMA_CT0_0 Control Register 0 of GDMA Channel 0 0000000
RD A
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
FO ME
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
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MT7621 PROGRAMMING GUIDE
L Y
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
SE AL
7 SOURCE_ADDR_MO Sets the source address mode
ON
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
n U TI
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
t.c EN
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
.ne ID
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
ink NF
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
b-l CO
request is asserted.
0: Hardware mode
1: Software mode
1E00280C GDMA_CT1_0 Control Register 1 of GDMA Channel 0 0000000
18 TEK
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name CH
RD A
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
R DI
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
FO ME
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
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MT7621 PROGRAMMING GUIDE
L Y
32: The source of the transfer is memory (always ready)
SE AL
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
ON
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
n U TI
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
t.c EN
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
.ne ID
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
ink NF
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
b-l CO
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
18 TEK
1E002810 GDMA_SA_1 Source Address of GDMA Channel 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
@
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
R DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
31:0 SOURCE_ADDR Souce address
1E002814 GDMA_DA_1 Destination Address of GDMA Channel 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Name DEST_ADDR[15:0]
SE AL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31:0 DEST_ADDR Destination address
n U TI
1E002818 GDMA_CT0_1 Control Register 0 of GDMA Channel 1 0000000
t.c EN
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
ink NF
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
18 TEK
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
@
1: 2 DWs
RD A
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
R DI
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
FO ME
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E00281C GDMA_CT1_1 Control Register 1 of GDMA Channel 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
.ne ID
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
b-l CO
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
18 TEK
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
@
2: DMA_REQ2
RD A
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
R DI
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
FO ME
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
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MT7621 PROGRAMMING GUIDE
L Y
by HW/SW.
SE AL
0: Channel is not masked
1: Channel is masked
ON
1E002820 GDMA_SA_2 Source Address of GDMA Channel 2 0000000
n U TI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
t.c EN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
ink NF
1E002824 GDMA_DA_2 Destination Address of GDMA Channel 2 0000000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
@
RD A
1E002828 GDMA_CT0_2 Control Register 0 of GDMA Channel 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
SE AL
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
ON
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
n U TI
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
t.c EN
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
.ne ID
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
ink NF
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
b-l CO
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
18 TEK
1E00282C GDMA_CT1_2 Control Register 1 of GDMA Channel 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name CH
_U
CO
CO NM
RE HE CH
R DI
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
FO ME
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
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MT7621 PROGRAMMING GUIDE
L Y
1: DMA_REQ1
2: DMA_REQ2
SE AL
32: The source of the transfer is memory (always ready)
ON
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
n U TI
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
t.c EN
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
.ne ID
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
ink NF
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
b-l CO
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
18 TEK
1E002830 GDMA_SA_3 Source Address of GDMA Channel 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@
Name SOURCE_ADDR[31:16]
RD A
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DI
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
1E002834 GDMA_DA_3 Destination Address of GDMA Channel 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
ON
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
31:0 DEST_ADDR Destination address
t.c EN
1E002838 GDMA_CT0_3 Control Register 0 of GDMA Channel 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
.ne ID
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ink NF
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
b-l CO
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
18 TEK
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
@
5:3 BURST_SIZE Sets the number of double words in each burst transaction
RD A
0: 1 DW
1: 2 DWs
2: 4 DWs
R DI
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
FO ME
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
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MT7621 PROGRAMMING GUIDE
L Y
0: Hardware mode
1: Software mode
SE AL
ON
1E00283C GDMA_CT1_3 Control Register 1 of GDMA Channel 3 0000000
0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset
t.c EN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
.ne ID
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
ink NF
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
b-l CO
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
18 TEK
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
@
0: DMA_REQ0
RD A
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
R DI
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
FO ME
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
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MT7621 PROGRAMMING GUIDE
L Y
1: Enable
SE AL
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
ON
0: Channel is not masked
1: Channel is masked
n U TI
1E002840 GDMA_SA_4 Source Address of GDMA Channel 4 0000000
0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
.ne ID
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
31:0 SOURCE_ADDR Souce address
b-l CO
1E002844 GDMA_DA_4 Destination Address of GDMA Channel 4 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
@
RD A
1E002848 GDMA_CT0_4 Control Register 0 of GDMA Channel 4 0000000
R DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
n U TI
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
t.c EN
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
.ne ID
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
ink NF
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
b-l CO
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
18 TEK
1E00284C GDMA_CT1_4 Control Register 1 of GDMA Channel 4 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
RD A
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DI
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
FO ME
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
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MT7621 PROGRAMMING GUIDE
L Y
21:16 SOURCE_DMA_REQ Selects the source DMA request
SE AL
0: DMA_REQ0
1: DMA_REQ1
ON
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
n U TI
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
t.c EN
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
.ne ID
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
ink NF
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
b-l CO
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
18 TEK
by HW/SW.
0: Channel is not masked
1: Channel is masked
1E002850 GDMA_SA_5 Source Address of GDMA Channel 5 0000000
@
0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
R DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
1E002854 GDMA_DA_5 Destination Address of GDMA Channel 5 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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MT7621 PROGRAMMING GUIDE
L Y
Name DEST_ADDR[31:16]
SE AL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:0 DEST_ADDR Destination address
t.c EN
1E002858 GDMA_CT0_5 Control Register 0 of GDMA Channel 5 0000000
0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
b-l CO
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
@
0: Incremental mode
1: Fix mode
RD A
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
R DI
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
FO ME
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
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MT7621 PROGRAMMING GUIDE
L Y
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
SE AL
0: Hardware mode
ON
1: Software mode
n U TI
1E00285C GDMA_CT1_5 Control Register 1 of GDMA Channel 5 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
.ne ID
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
ink NF
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
18 TEK
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
@
RD A
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
R DI
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
FO ME
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
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MT7621 PROGRAMMING GUIDE
L Y
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
SE AL
0: Disable
1: Enable
ON
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
n U TI
1E002860 GDMA_SA_6 Source Address of GDMA Channel 6 0000000
t.c EN
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
b-l CO
1E002864 GDMA_DA_6 Destination Address of GDMA Channel 6 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
31:0 DEST_ADDR Destination address
RD A
R DI
1E002868 GDMA_CT0_6 Control Register 0 of GDMA Channel 6 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
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MT7621 PROGRAMMING GUIDE
L Y
Type RO RW RW RW RW RW RW
Reset
SE AL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
n U TI
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
t.c EN
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
.ne ID
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
ink NF
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
b-l CO
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
18 TEK
0: Hardware mode
1: Software mode
1E00286C GDMA_CT1_6 Control Register 1 of GDMA Channel 6 0000000
0
@
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
R DI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
FO ME
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
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MT7621 PROGRAMMING GUIDE
L Y
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
SE AL
21:16 SOURCE_DMA_REQ Selects the source DMA request
ON
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
n U TI
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
t.c EN
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
.ne ID
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
ink NF
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
b-l CO
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
18 TEK
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
@
RD A
1E002870 GDMA_SA_7 Source Address of GDMA Channel 7 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
1E002874 GDMA_DA_7 Destination Address of GDMA Channel 7 0000000
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MT7621 PROGRAMMING GUIDE
L Y
0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 DEST_ADDR Destination address
.ne ID
1E002878 GDMA_CT0_7 Control Register 0 of GDMA Channel 7 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ST_ SW
b-l CO
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
@
1: Fix mode
RD A
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
R DI
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
FO ME
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
PGMT7621_V.1.0_130607 Page 176 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: Enable
SE AL
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
ON
request is asserted.
0: Hardware mode
1: Software mode
n U TI
1E00287C GDMA_CT1_7 Control Register 1 of GDMA Channel 7 0000000
0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.ne ID
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
ink NF
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset
b-l CO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
18 TEK
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
@
clear the CH_EN.
RD A
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
R DI
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
FO ME
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
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MT7621 PROGRAMMING GUIDE
L Y
1: Enable
SE AL
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
ON
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
n U TI
0: Channel is not masked
1: Channel is masked
t.c EN
1E002880 GDMA_SA_8 Source Address of GDMA Channel 8 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
.ne ID
SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
b-l CO
1E002884 GDMA_DA_8 Destination Address of GDMA Channel 8 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
18 TEK
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
RD A
Bit(s) Name Description
31:0 DEST_ADDR Destination address
R DI
1E002888 GDMA_CT0_8 Control Register 0 of GDMA Channel 8 0000000
FO ME
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO DE SE
SW
UR ST_ GM
_M
CE_ AD EN CH
CURR_SEGMENT BURST_SIZE OD
AD DR T_D _EN
E_E
DR _M ON
N
_M OD E_I
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MT7621 PROGRAMMING GUIDE
L Y
OD E NT_
SE AL
E EN
Type RO RW RW RW RW RW RW
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
t.c EN
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
.ne ID
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
ink NF
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
b-l CO
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
18 TEK
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
@
1E00288C GDMA_CT1_8 Control Register 1 of GDMA Channel 8 0000000
RD A
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
FO ME
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
SE AL
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
ON
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
n U TI
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
t.c EN
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
.ne ID
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
ink NF
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
b-l CO
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
18 TEK
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
@
RD A
1E002890 GDMA_SA_9 Source Address of GDMA Channel 9 0000000
R DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
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MT7621 PROGRAMMING GUIDE
L Y
1E002894 GDMA_DA_9 Destination Address of GDMA Channel 9 0000000
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 DEST_ADDR Destination address
.ne ID
1E002898 GDMA_CT0_9 Control Register 0 of GDMA Channel 9 0000000
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
b-l CO
SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
18 TEK
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
@
DE
RD A
0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
R DI
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
FO ME
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
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MT7621 PROGRAMMING GUIDE
L Y
bytes transfferred reaches the TARGET_BYTE_CNT
SE AL
0: Disable
1: Enable
ON
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
n U TI
1: Software mode
t.c EN
1E00289C GDMA_CT1_9 Control Register 1 of GDMA Channel 9 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
ink NF
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
b-l CO
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
18 TEK
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
@
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
RD A
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
R DI
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
FO ME
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
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MT7621 PROGRAMMING GUIDE
L Y
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
SE AL
0: Disable
1: Enable
ON
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
n U TI
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
t.c EN
1E0028A0 GDMA_SA_10 Source Address of GDMA Channel 10 0000000
0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
1E0028A4 GDMA_DA_10 Destination Address of GDMA Channel 10 0000000
18 TEK
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
@
Type RW
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R DI
31:0 DEST_ADDR Destination address
FO ME
1E0028A8 GDMA_CT0_1 Control Register 0 of GDMA Channel 10 0000000
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO DE SE SW
UR ST_ GM CH _M
CURR_SEGMENT BURST_SIZE
CE_ AD EN _EN OD
AD DR T_D E_E
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MT7621 PROGRAMMING GUIDE
L Y
DR _M ON N
SE AL
_M OD E_I
OD E NT_
ON
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
t.c EN
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
.ne ID
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
ink NF
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
b-l CO
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
18 TEK
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
@
RD A
1E0028AC GDMA_CT1_1 Control Register 1 of GDMA Channel 10 0000000
0 0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
n U TI
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
t.c EN
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
.ne ID
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
ink NF
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
b-l CO
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
18 TEK
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
@
0: Channel is not masked
RD A
1: Channel is masked
R DI
1E0028B0 GDMA_SA_11 Source Address of GDMA Channel 11 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E0028B4 GDMA_DA_11 Destination Address of GDMA Channel 11 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:0 DEST_ADDR Destination address
ink NF
1E0028B8 GDMA_CT0_1 Control Register 0 of GDMA Channel 11 0000000
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
DE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
18 TEK
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
@
RD A
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
R DI
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
FO ME
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
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MT7621 PROGRAMMING GUIDE
L Y
1: Enable
SE AL
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
ON
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
n U TI
request is asserted.
0: Hardware mode
1: Software mode
t.c EN
1E0028BC GDMA_CT1_1 Control Register 1 of GDMA Channel 11 0000000
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.ne ID
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
b-l CO
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
@
2: DMA_REQ2
RD A
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
R DI
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
FO ME
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
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MT7621 PROGRAMMING GUIDE
L Y
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
SE AL
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
ON
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
n U TI
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
t.c EN
0: Channel is not masked
1: Channel is masked
.ne ID
1E0028C0 GDMA_SA_12 Source Address of GDMA Channel 12 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
18 TEK
1E0028C4 GDMA_DA_12 Destination Address of GDMA Channel 12 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:0 DEST_ADDR Destination address
FO ME
1E0028C8 GDMA_CT0_1 Control Register 0 of GDMA Channel 12 0000000
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO DE SE CH SW
CURR_SEGMENT BURST_SIZE
UR ST_ GM _EN _M
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MT7621 PROGRAMMING GUIDE
L Y
CE_ AD EN OD
SE AL
AD DR T_D E_E
DR _M ON N
ON
_M OD E_I
OD E NT_
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
t.c EN
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
.ne ID
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
ink NF
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
b-l CO
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
18 TEK
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
1: Software mode
@
RD A
R DI
1E0028CC GDMA_CT1_1 Control Register 1 of GDMA Channel 12 0000000
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
FO ME
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
ON
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
n U TI
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
t.c EN
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
.ne ID
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
ink NF
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
b-l CO
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
18 TEK
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
@
by HW/SW.
RD A
0: Channel is not masked
1: Channel is masked
R DI
1E0028D0 GDMA_SA_13 Source Address of GDMA Channel 13 0000000
0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
31:0 SOURCE_ADDR Souce address
SE AL
ON
1E0028D4 GDMA_DA_13 Destination Address of GDMA Channel 13 0000000
0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 DEST_ADDR
ink NF Destination address
1E0028D8 GDMA_CT0_1 Control Register 0 of GDMA Channel 13 0000000
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
b-l CO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO
DE
SE
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
18 TEK
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
RD A
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
R DI
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
FO ME
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
PGMT7621_V.1.0_130607 Page 191 of 349
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MT7621 PROGRAMMING GUIDE
L Y
T_EN segment is done.
SE AL
0: Disable
1: Enable
ON
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
n U TI
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
request is asserted.
0: Hardware mode
t.c EN
1: Software mode
1E0028DC GDMA_CT1_1 Control Register 1 of GDMA Channel 13 0000000
.ne ID
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
ink NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
_U
CO
CO NM
RE HE CH
NT_ AS
b-l CO
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
@
0: DMA_REQ0
RD A
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
R DI
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
FO ME
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
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MT7621 PROGRAMMING GUIDE
L Y
1: Channel 1
n: Channel n
SE AL
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
ON
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
n U TI
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
0: Disable
1: Enable
t.c EN
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
.ne ID
1E0028E0 GDMA_SA_14 Source Address of GDMA Channel 14 0000000
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SOURCE_ADDR Souce address
18 TEK
1E0028E4 GDMA_DA_14 Destination Address of GDMA Channel 14 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEST_ADDR[31:16]
@
Type RW
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
R DI
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
31:0 DEST_ADDR Destination address
1E0028E8 GDMA_CT0_1 Control Register 0 of GDMA Channel 14 0000000
4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE AL
Name SO SE
DE
UR GM
ON
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
n U TI
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
.ne ID
DE 0: Incremental mode
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
ink NF
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
b-l CO
4: 16 DWs
5: Undefined
6: Undefined
7: Undefined
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
0: Disable
18 TEK
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
@
request is asserted.
RD A
0: Hardware mode
1: Software mode
R DI
1E0028EC GDMA_CT1_1 Control Register 1 of GDMA Channel 14 0000000
4 0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CO
CH
CO _U
RE HE CH
NT_ NM
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK AS
RV NT_ AS
DE_ K_F
ED INT K
EN AIL
_EN
_IN
PGMT7621_V.1.0_130607 Page 194 of 349
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MT7621 PROGRAMMING GUIDE
L Y
T_E
SE AL
N
Type RO RW RW RW RW RW RW
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
{(TARGET_BYTE_CNT/2N) + 1}.
21:16 SOURCE_DMA_REQ Selects the source DMA request
t.c EN
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
.ne ID
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
ink NF
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
b-l CO
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
channel itself.
0: Channel 0
1: Channel 1
n: Channel n
18 TEK
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
@
0: Disable
RD A
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
R DI
0: Channel is not masked
1: Channel is masked
FO ME
1E0028F0 GDMA_SA_15 Source Address of GDMA Channel 15 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SOURCE_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SOURCE_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31:0 SOURCE_ADDR Souce address
n U TI
1E0028F4 GDMA_DA_15 Destination Address of GDMA Channel 15 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name DEST_ADDR[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEST_ADDR[15:0]
Type RW
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 DEST_ADDR Destination address
ink NF
1E0028F8 GDMA_CT0_1 Control Register 0 of GDMA Channel 15 0000000
5 0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TARGET_BYTE_CNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SO SE
DE
18 TEK
UR GM
ST_ SW
CE_ EN
AD _M
AD T_D CH
CURR_SEGMENT DR BURST_SIZE OD
DR ON _EN
_M E_E
_M E_I
OD N
OD NT_
E
E EN
Type RO RW RW RW RW RW RW
Reset
@
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit(s) Name Description
31:16 TARGET_BYTE_CNT The number of bytes to be transferred
R DI
15:8 CURR_SEGMENT Indicates the current segment (0 to 255)
7 SOURCE_ADDR_MO Sets the source address mode
DE 0: Incremental mode
FO ME
1: Fix mode
6 DEST_ADDR_MODE Sets the destination address mode
0: Incremental mode
1: Fix mode
5:3 BURST_SIZE Sets the number of double words in each burst transaction
0: 1 DW
1: 2 DWs
2: 4 DWs
3: 8 DWs
4: 16 DWs
5: Undefined
6: Undefined
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L Y
7: Undefined
SE AL
2 SEGMENT_DONE_IN Enable the segment done interrupt. This interrupt asserts after transfer of each
T_EN segment is done.
ON
0: Disable
1: Enable
1 CH_EN If CONT_MODE_EN=0, this bit is de-asserted by hardware after the number of
bytes transfferred reaches the TARGET_BYTE_CNT
n U TI
0: Disable
1: Enable
0 SW_MODE_EN Software mode enable. If software mode enable is set, the data transfer starts
when the CH_EN bit is set. Otherwise, the data transfer starts when the DMA
t.c EN
request is asserted.
0: Hardware mode
1: Software mode
.ne ID
1E0028FC GDMA_CT1_1 Control Register 1 of GDMA Channel 15 0000000
5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ink NF
Name RESERVED NUM_SEGMENT SOURCE_DMA_REQ
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH
b-l CO
_U
CO
CO NM
RE HE CH
NT_ AS
SE RE _M
MO DEST_DMA_REQ NEXT_CH2UNMASK K_F
RV NT_ AS
DE_ AIL
ED INT K
EN _IN
_EN
T_E
N
18 TEK
Type RO RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:22 NUM_SEGMENT the number of segments=2N, where N is the value of this field. Valid values for
this field are N=0 to 8. The segment size=(TARGET_BYTE_CNT/2N). It the
TARGET_BYTE_CNT is not a multiple of 2N, the segment size =
@
{(TARGET_BYTE_CNT/2N) + 1}.
RD A
21:16 SOURCE_DMA_REQ Selects the source DMA request
0: DMA_REQ0
1: DMA_REQ1
R DI
2: DMA_REQ2
32: The source of the transfer is memory (always ready)
14 CONT_MODE_EN If CONT_MODE_EN=1, HW will NOT clear CH_EN after the number of bytes
transferred reachs TARGET_BYTE_CNT. Otherwise, HW will clear CH_EN will
FO ME
clear the CH_EN.
0: Continuous mode is disabled
1: Continuous mode is enabled
13:8 DEST_DMA_REQ Selects the destination DMA request
0: DMA_REQ0
1: DMA_REQ1
2: DMA_REQ2
32: The destination of the transfer is memory (always ready)
7:3 NEXT_CH2UNMASK Selects the channel to clear the CH_MASK bit. When the number of bytes
transferred reaches the TARGET_BYTE_CNT, the hardware will clear the
CH_MASK field of the NEXT_CH2UNMASK channel. If the hardware does not
need to clear CH_MASK field of any channel, this field should be set to the
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MT7621 PROGRAMMING GUIDE
L Y
channel itself.
SE AL
0: Channel 0
1: Channel 1
ON
n: Channel n
2 COHERENT_INT_EN If COHERENT_INT_EN is set, GDMA will issue a dummy read to destination after
the last write to destination to avoid data coherent problem. Note: DO NOT set
this field if the destination is not MEM. (may corrupt data, if destination is a FIFO)
n U TI
0: Disable
1: Enable
1 CH_UNMASK_FAIL_I If this field is set, an interrupt will be assert when HW detect the CH_MASK field
NT_EN of NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
t.c EN
0: Disable
1: Enable
0 CH_MASK When this field is set, the transfer of this channel is gated untill this field is clear
by HW/SW.
0: Channel is not masked
1: Channel is masked
1E002A00
.ne ID
GDMA_UNMA Unmask Fail Interrupt Status 0000000
ink NF
SK_INTSTS 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name UNMASK_FAIL_INTSTS[31:16]
Type W1C
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name UNMASK_FAIL_INTSTS[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:0 UNMASK_FAIL_INTST This field is the bit-map of unmask fail interrupt status of each channel. The
S unmask fail interrupt will assert when HW detect the CH_MASK field of
NEXT_CH2UNMASK channel is 1'b0 while trying to clear it.
1E002A04 GDMA_DONE Segment Done Interrupt Status 0000000
@
_INTSTS 0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEGMENT_DONE_INTSTS[31:16]
R DI
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEGMENT_DONE_INTSTS[15:0]
Type W1C
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 SEGMENT_DONE_IN This field is the bit-map of segment done interrupt status of each channel. The
TSTS segment done interrupt will assert when each segment is transferred completely.
1E002A20 GDMA_GCT Global Control 0000000
E
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Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SE AL
Name RESERVED[26:11]
Type RO
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AR
TOTAL_C B_
RESERVED[10:0] IP_VER
n U TI
H_NUM MO
DE
Type RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
t.c EN
Bit(s) Name Description
4:3 TOTAL_CH_NUM Total channel number supported
0: 8 channels
1: 16 channels
.ne ID
2: 32 channels
3: Undefined
2:1 IP_VER GDMA core version
0 ARB_MODE Arbitration mode selection
ink NF
0: channel 0 has highest priority and others are round-robin
1: All channel are round-robin
b-l CO
1E002A30 GDMA_PERI_ Peripheral Region 0 Starting Address 1C00000
ADDR_START 0
_0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_0[31:16]
Type RW
Reset 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
RD A
0 PERI_ADDR_START_x & < PERI_ADDR_END_x
R DI
1E002A34 GDMA_PERI_ Peripheral Region 0 End Address 2000000
ADDR_END_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name PERI_ADDR_END_0[31:16]
Type RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_END_0 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E002A38 GDMA_PERI_ Peripheral Region 1 Starting Address 1C00000
ADDR_START 0
_1
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_1[31:16]
Type RW
Reset 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
1 PERI_ADDR_START_x & < PERI_ADDR_END_x
ink NF
1E002A3C GDMA_PERI_ Peripheral Region 1 End Address 2000000
ADDR_END_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name PERI_ADDR_END_1[31:16]
Type RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 PERI_ADDR_END_1 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
@
1E002A40 GDMA_PERI_ Peripheral Region 2 Starting Address 6000000
RD A
ADDR_START 0
_2
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_2[31:16]
Type RW
Reset 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
2 PERI_ADDR_START_x & < PERI_ADDR_END_x
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MT7621 PROGRAMMING GUIDE
L Y
1E002A44 GDMA_PERI_ Peripheral Region 2 End Address 7000000
SE AL
ADDR_END_2 0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_END_2[31:16]
Type RW
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 PERI_ADDR_END_2 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
1E002A48
.ne ID
GDMA_PERI_
ADDR_START
Peripheral Region 3 Starting Address 6000000
0
ink NF
_3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_START_3[31:16]
Type RW
Reset
b-l CO
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_START_3[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:0 PERI_ADDR_START_ GDMA request will direct to peripheral bus if the request address >=
3 PERI_ADDR_START_x & < PERI_ADDR_END_x
1E002A4C GDMA_PERI_ Peripheral Region 3 End Address 7000000
ADDR_END_3 0
@
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PERI_ADDR_END_3[31:16]
Type RW
R DI
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PERI_ADDR_END_3[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31:0 PERI_ADDR_END_3 GDMA request will direct to peripheral bus if the request address >=
PERI_ADDR_START_x & < PERI_ADDR_END_x
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.12 SPI Controller
ON
2.12.1 Features
Supports up to 2 SPI master operations
Programmable clock polarity
n U TI
Programmable interface clock rate
Programmable bit ordering
Firmware-controlled SPI enable
t.c EN
Programmable payload (address + data) length
Supports 1/2/4 multi-IO SPI flash memory
Supports command/user mode operation
Supports SPI direct access
Extends the addressable range from 24 bits to 32 bits for memory size larger than 128 Mb.
.ne ID 2.12.2 Block Diagram
ink NF
clock
reset TX_FIFO Clock
SPICLK
from System Generator
b-l CO
Controller
CPU SO/SIO1
18 TEK
CPU Interface SERDES
from PalmBus Interface WP/SIO2
Controller
@
RD A
GDMA RX_FIFO SPI Control
FSM
R DI
Figure 2-6 SPI Controller Block Diagram
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.12.3 Registers
ON
SPI Changes LOG
Revision Date Author Change Log
0.1 2012/8/29 Lancelot Initialization
n U TI
0.2 2012/11/6 Lancelot 1. Remove 0x38 SW_RST 2. Add CS_POLAR at 0x38
0.3 2012/11/23 Lancelot Fix default value
t.c EN
Module name: SPI Base address: (+1E000B00h)
Address Name Widt Register Function
h
.ne ID
1E000B00 SPI_TRANS 32 SPI transaction control/status register
1E000B04 SPI_OP_ADDR 32 SPI opcode/address register
1E000B08 SPI_DIDO_0 32 SPI DI/DO data #0 register
1E000B0C SPI_DIDO_1 32 SPI DI/DO data #1 register
ink NF
1E000B10 SPI_DIDO_2 32 SPI DI/DO data #2 register
1E000B14 SPI_DIDO_3 32 SPI DI/DO data #3 register
1E000B18 SPI_DIDO_4 32 SPI DI/DO data #4 register
1E000B1C SPI_DIDO_5 32 SPI DI/DO data #5 register
b-l CO
1E000B20 SPI_DIDO_6 32 SPI DI/DO data #6 register
1E000B24 SPI_DIDO_7 32 SPI DI/DO data #7 register
1E000B28 SPI_MASTER 32 SPI master mode register
1E000B2C SPI_MORE_BUF 32 SPI more buf control register
1E000B30 SPI_QUEUE_CTL 32 SPI flash queue control register
18 TEK
1E000B34 SPI_STATUS 32 SPI controller status register
1E000B38 SPI_CS_POLAR 32 SPI chip select polarity
1E000B3C SPI_SPACE 32 SPI flash space control register
@
1E000B00 SPI_TRANS SPI transaction control/status register 0016000
RD A
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name spi
_m
spi_addr_s ast
spi_addr_ext Reserved0 Reserved1
ize er_
bus
FO ME
y
Type RW RO RW RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spi
_m
ast
Reserved2 miso_byte_cnt mosi_byte_cnt
er_
star
t
Type RO WO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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L Y
SE AL
Bit(s) Name Description
ON
31:24 spi_addr_ext SPI address extention
Address extenstion for 32-bit SPI address size. Usually this field specifies the first byte
of the address phase to transmit to SPI device when more_buf_mode = 0 and
spi_addr_size = 3. And spi_addr[31:24], spi_addr[23:16], and spi_addr[15:0] are
n U TI
respectively the second, third and fourth byte of the address phase
20:19 spi_addr_size SPI address size.
0: reserved.
1: spi_addr[15:0] of SPI DI data register are valid (16-bit size).
2: spi_addr[23:0] of SPI DI data register are valid (24-bit size).
t.c EN
3: {spi_addr_ext[7:0], spi_addr[23:0]} of SPI DI data register are valid
(32-bit size)
Note: The spi_addr_size is valid only when more_buf_mode = 0.
16 spi_master_busy Transaction busy indication (Read-only). Writes to this bit are ignored.
0: No SPI transaction is ongoing. Software may start a new SPI transaction by writing
.ne ID
to the SPI transaction start bit within this register.
1: An SPI transaction presently is underway. Software must not try to start a new SPI
transaction. Software may not alter the value of any field of the SPI master control
registers.
8 spi_master_start SPI transaction start. Only writes to this field are meaningful, reads always return
ink NF
0.
Writes:
0: No effect
1: Starts SPI transaction.
7:4 miso_byte_cnt SPI MISO (rx) byte count.
b-l CO
Determines the number of bytes received from the SPI device from the SPI
opcode/address register and the SPI DI/DO data #0 register. Values of 0 ~ 8 are valid,
other values are illegal.
Note: The miso_byte_cnt is valid only when more_buf_mode = 0.
3:0 mosi_byte_cnt SPI MOSI (tx) byte count.
Determines the number of bytes transmitted from the SPI opcode/address register and
the SPI DI/DO data #0 register to the SPI device. Values of 1 ~ 8 are valid, other values
18 TEK
are illegal.
Note: The mosi_byte_cnt is valid only when more_buf_mode = 0. The transmitted data
sequence is as follows: spi_opcode, spi_addr (conditional) and d0_byte ~ d3_byte
(conditional).
@
1E000B04 SPI_OP_ADD SPI opcode/address register 0000000
RD A
R 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
R DI
spi_addr[23:8]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name spi_addr[7:0] spi_opcode
FO ME
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:8 spi_addr SPI address. Usually this field specifies the 24-bits address to transmit to the SPI
device when more_buf_mode = 0.
1: (16-bits SPI address size), spi_addr[23:16] is the 1st byte of the address phase and
spi_addr[15:8] is the 2nd byte of the address phase.
2: (24-bits SPI address size), spi_addr[31:24] is the 1st byte of the address phase and
spi_addr[23:16] is the 2nd byte of the address phase and spi_addr[15:8] is the 3rd byte
of the address phase.
3: (32-bits SPI address size), spi_addr[31:24] is the 2nd byte of the address phase and
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MT7621 PROGRAMMING GUIDE
L Y
spi_addr[23:16] is the 3rd byte of the address phase and spi_addr[15:8] is the 4th byte
of the address phase
SE AL
Note: For SPI read transaction and more_buf_mode = 0
ON
Field [15:8] is also used to store the 6-th byte of data read phase.
Field [23:16] is also used to store the 7-th byte of data read phase.
Field [31:24] is also used to store the 8-th byte of data read phase.
7:0 spi_opcode SPI opcode. Usually this field specifies the 8-bits opcode (instruction) to transmit
n U TI
to the SPI device as the first byte of a SPI transaction when more_buf_mode = 0.
Note: For SPI read transaction and more_buf_mode = 0, this byte is also used to store
the 5-th byte of data read phase according to the rx byte count miso_byte_cnt.
t.c EN
1E000B08 SPI_DIDO_0 SPI DI/DO data #0 register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.ne ID
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
ink NF
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
18 TEK
1E000B0C SPI_DIDO_1 SPI DI/DO data #1 register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
FO ME
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B10 SPI_DIDO_2 SPI DI/DO data #2 register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
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MT7621 PROGRAMMING GUIDE
L Y
Type RW RW
Reset
SE AL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
t.c EN
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
.ne ID
1E000B14 SPI_DIDO_3 SPI DI/DO data #3 register 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
ink NF
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
18 TEK
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B18 SPI_DIDO_4 SPI DI/DO data #4 register 0000000
0
@
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD A
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B1C SPI_DIDO_5 SPI DI/DO data #5 register 0000000
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MT7621 PROGRAMMING GUIDE
L Y
0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
1E000B20
.ne ID
SPI_DIDO_6 SPI DI/DO data #6 register 0000000
ink NF
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset
b-l CO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
@
RD A
1E000B24 SPI_DIDO_7 SPI DI/DO data #7 register 0000000
0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name d3_byte d2_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name d1_byte d0_byte
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 d3_byte The 4th data byte of data read/write phase.
23:16 d2_byte The 3th data byte of data read/write phase.
15:8 d1_byte The 2nd data byte of data read/write phase.
7:0 d0_byte The 1st data byte of data read/write phase.
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E000B28 SPI_MASTER SPI master mode register 000D888
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name clk_
rs_slave_sel mo rs_clk_sel
de
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name full spi spi
mor
bidi lsb e_b
_du int_ _st _pr cph cpo serial_mod
cs_dsel_cnt r_m _fir uf_
ple en art_ efet a l e
ode st mo
x sel ch
de
.ne ID
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
31:29 rs_slave_sel select SPI device
0: select SPI device 0 (default is flash)
1: select SPI device 1
...
7: select SPI device 7
b-l CO
28 clk_mode This register is used to specify that period of SCLK HIGH is longer or period of
SCLK LOW is longer when clock divisor(clk_sel) is odd.
0: period of SCLK LOW is longer.
1: period of SCLL HIGH is longer.
27:16 rs_clk_sel Register Space SPI clock frequency select.
0: SPI clock frequency is hclk/2. (50% duty cycle, duty cycle is the ratio of the output
18 TEK
high time to the total cycle time)
1: SPI clock frequency is hclk/3. (33.33% or 66.67% duty cycle)
2: SPI clock frequency is hclk/4. (50% duty cycle)
3: SPI clock frequency is hclk/5. (40% or 60% duty cycle)
4095: SPI clock frequency is hclk/4097.
15:11 cs_dsel_cnt De-select time of SPI chip select is configured to occupy the number of cycles of
AHB clock
10 full_duplex Full duplex or half duplex mode.
@
0: half duplex mode.
RD A
1: full duplex mode.
Full duplex timing diagram
Note: The full_duplex is valid only when more_buf_mode = 1. The transmission is
R DI
always as half duplex when more_buf_mode = 0;
9 int_en Interrupt enable.
0: disable SPI interrupt.
1: enable SPI interrupt.
FO ME
8 spi_start_sel The interval between spi_cs_n and spi_sclk.
0: 3 clk
1: 6 clk
7 spi_prefetch SPI pre-fetch buffer enable
0: disable pre-fetch buffer.
1: enable pre-fetch buffer.
6 bidir_mode Bi-direction mode. In this mode, the SPI uses only one serial data pin for
interface with external devices. The MOSI pin becomes the serial data I/O pin for
the SPI transaction and MISO pin is not used. Bi-direction mode is used for the
application with only 1 bi-direction serial pin for SPI transaction.
0: normal mode (both MOSI and MISO pins are used).
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L Y
1: bi-direction mode (only MOSI pin is used). SPI host controller must operate in half
duplex mode if bidir_mode = 1.
SE AL
Note: The bidir_mode is valid only when more_buf_mode = 1.
ON
5 cpha (CPHA, clock phase). Initial SPI clock phase for SPI transaction.
There are four SPI modes used to latch data. These SPI modes latch data in one of
four ways, and are defined by the logic state combinations of the CLK Polarity (CPOL)
in relation to the CLK Phase (CPHA). The valid logic combinations identify and
n U TI
determine the SPI modes supported by the SPI device.
SPI mode
At CPOL=0 the base value of the clock is zero
t.c EN
For CPHA=0 (mode 0), data is read on the clock's rising edge and data is changed on
a falling edge.
For CPHA=1 (mode 1), data is read on the clock's falling edge and data is changed on
a rising edge.
At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
For CPHA=0 (mode 2), data is read on clock's falling edge and data is changed on a
.ne ID
rising edge.
For CPHA=1 (mode 3), data is read on clock's rising edge and data is changed on a
falling edge.
4 cpol cpol (CPOL, clock polarity). Initial SPI clock polarity for SPI transaction.
ink NF
3 lsb_first 0: MSB(most significant bit) is transferred first for SPI transaction.
1: LSB(least significant bit) is transferred first for SPI transaction.
2 more_buf_mode Select 2 words buffer or 8 words buffer for SPI transaction.
0: SPI transfer data buffer size is only 2 words. In this mode, SPI DI/DO data #0
register and SPI opcode/address register are the data buffer for SPI transaction. And,
b-l CO
SPI master follows mosi_byte_cnt and miso_byte_cnt to complete the transmission and
reception, respectively. This kind of transaction must operate in half duplex mode.
1: SPI transfer data buffer size is 8 words. In this mode, SPI opcode/address register
are the data buffer for SPI transaction and follows cmd_bit_cnt to complete the
transaction. SPI DI/DO data #0~#7 register are the data buffer for SPI transaction and
follows do_bit_cnt and di_bit_cnt to complete the transmission and reception,
respectively. In half duplex mode, transmitted data are loaded from SPI
opcode/address register and SPI DI/DO data #0~#7 registers. And, the received data
18 TEK
will overwrite the SPI DI/DO data #0~#7 registers. In full duplex mode, SPI DI/DO data
#0~#3 registers are used for transmission and SPI DI/DO #4~#7 registers are used for
receipt.
1:0 serial_mode This mode is designed for Winbond SPI flash W25Q80/16/32 and
W25X10/20/40/80/16/32/64 series.
0: standard serial.
1: dual serial.
2: quad serial.
@
3: reserved.
RD A
Note: The serial_mode is valid only when more_buf_mode = 0. The transaction mode is
always as standard serial when more_buf_mode = 1.
R DI
1E000B2C SPI_MORE_B SPI more buf control register 0000000
UF 0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved0 cmd_bit_cnt Reserved1 miso_bit_cnt[8:4]
Type RO RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name miso_bit_cnt[3:0] Reserved2 mosi_bit_cnt
Type RW RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
29:24 cmd_bit_cnt SPI command phase MOSI (tx) bit count. Determines the number of command
SE AL
bits transmitted from the SPI opcode/address register to the SPI device. Values
of 0 ~ 32 are valid, but other values are illegal.
ON
Note: The cmd_bit_cnt is valid only when more_buf_mode = 1 and the SPI
opcode/address register is treated as a command register.
20:12 miso_bit_cnt SPI data phase MISO (rx) bit count. Determines the number of bits received from
the SPI device into the SPI DI/DO data #0~#7 register. Values of 0 ~ 256 are valid,
n U TI
but other values are illegal. Maximum value is 256 for half duplex mode and 128
for full duplex mode. Please note that do_bit_cnt must be equal to di_bit_cnt in
full duplex mode.
Note: The miso_bit_cnt is valid only when more_buf_mode = 1.
t.c EN
8:0 mosi_bit_cnt SPI data phase MOSI (tx) bit count. Determines the number of data bits
transmitted from the SPI DI/DO data #0~#7 register to the SPI device. Values of 0
~ 256 are valid, but other values are illegal. Maximum value is 256 for half duplex
mode and 128 for full duplex mode.
Note: The mosi_bit_cnt is valid only when more_buf_mode = 1.
1E000B30
.ne ID
SPI_QUEUE_
CTL
SPI flash queue control register 00000A4
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name fs_page_sel Reserved0[12:3]
Type RW RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name fs_ Res
fs_addr_si fs_addr_si
Reserved0[2:0] bus fs_di_ph_byc erv fast_spi_sel
ze_r ze
y ed1
Type RO RO RO RW RW RO RW
Reset 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:26 fs_page_sel Flash Space Page Selection.
0: (Page 0 space) 0x0000_0000 - 0x03ff_ffff
1: (Page 1 space) 0x0400_0000 - 0x07ff_ffff
...
63: (Page 63 space) 0xffc0_0000 - 0xffff_ffff
12 fs_busy Transaction busy indication (Read-only) in flash space. Writes to this bit are
ignored.
@
0: No SPI flash space access is ongoing. Software may change the configuration
RD A
related to flash space.
1: SPI flash space access presently is underway. Software may not alter the
configuration related to flash space.
R DI
11:10 fs_addr_size_r Latched fs_addr_size indication from internal spimc logic
9:8 fs_addr_size SPI address. This field specifies the 24-bits/16-bits address to transmit to the SPI
device for SPI Flash Space Read operation only.
0: 25-bit SPI address size
FO ME
1: 16-bit SPI address size Reserved.
2: 24-bit SPI address size (default for 3B SPI flash)
3: 26-bit SPI address size (default for 4B SPI flash)
If the change of the fs_addr_size is needed, the sequence below must be followed.
Otherwise, the new fs_addr_size configuration will not be updated to the internal spimc
logic .
Step 1: Set new fs_addr_size.
Step 2: Transmit mode change command (ex. En4B or Ex4B of
MX25L25635E)
Note: 1. The value fs_addr_size is not valid in Register Space.
2. The Spimc now only supports 3-Byte mode (24 bits) and 4-Byte
mode (25 or 26 bits) switch.
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MT7621 PROGRAMMING GUIDE
L Y
7:4 fs_di_ph_byc Determines the number of data bytes transmitted from the SPI master controller
SE AL
to the SPI device for SPI Flash Space Read operation. This field is similar to
mosi_byte_cnt in STCSR but is used for setting of flash space access control
ON
path.
Note: this field should
(if fs_addr_size_r = 2, 24-bit fs_addr_size)
= 4 (OP + ADDR) if fast_spi_sel = 0 (0x03)
n U TI
= 5 (OP + ADDR + dummy) if fast_spi_sel = 1 (0x0b)
= 5 (OP + ADDR + dummy) if fast_spi_sel = 2 (0x3b)
= 5 (OP + ADDR + M7-0) if fast_spi_sel = 3 (0xbb)
= 5 (OP + ADDR + dummy) if fast_spi_sel = 4 (0x6b)
= 7 (OP + ADDR + M7-0 + dummy) if fast_spi_sel = 5 (0xeb)
t.c EN
= 5 (OP + ADDR + M7-0) if fast_spi_sel = 6 (0xe3)
(if fs_addr_size_r = 0 or 3, 25 or 26-bit fs_addr_size)
= 5 (OP + ADDR) if fast_spi_sel = 0 (0x03)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 1 (0x0b)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 2 (0x3b)
.ne ID
= 6 (OP + ADDR + M7-0) if fast_spi_sel = 3 (0xbb)
= 6 (OP + ADDR + dummy) if fast_spi_sel = 4 (0x6b)
= 8 (OP + ADDR + M7-0 + dummy) if fast_spi_sel = 5 (0xeb)
= 6 (OP + ADDR + M7-0) if fast_spi_sel = 6 (0xe3)
2:0 fast_spi_sel Select SPI flash read instruction for Flash Space
ink NF
0: standard read data instruction (0x03).
1: standard fast read data instruction (0x0b).
2: fast read dual output instruction defined in Winbond W25Qxx series SPI flash
(0x03b).
3: fast read dual I/O instruction defined in Winbond W25Qxx series SPI flash (0xbb).
4: fast read quad output instruction defined in Winbond W25Qxx series SPI flash
b-l CO
(0x6b).
5: fast read quad I/O instruction defined in Winbond W25Qxx series SPI flash (0xeb).
6: burst read quad I/O instruction defined in Winbond W25Qxx series SPI flash (0xe3).
Note: serial_mode and more_buf_mode are don't care for this flash space access
control path.
18 TEK
1E000B34 SPI_STATUS SPI controller status register 0000003
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved0[25:10]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name spi_flash_ spi
Reserved0[9:0] Reserved1
mode _ok
Type RO RO RO RC
R DI
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Bit(s) Name Description
FO ME
5:4 spi_flash_mode 0: no SPI flash.
1: standard SPI flash.
2: specific SPI flash with dual interface capability.
3: specific SPI flash with quad interface capability.
0 spi_ok When SPI transaction complete, SPI master controller will set this bit and assert
SPI interrupt to notify software. Reading this register will clear this bit and de-
assert SPI interrupt.
1E000B38 SPI_CS_POL SPI chip select polarity 0000000
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L Y
AR 0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name Reserved[23:8]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name Reserved[7:0] cs_polar
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
7:0 cs_polar Chip select default polarity
set cs_polar[n]=1'b0 for cs[n] low active (SPI Flash)
set cs_polar[n]=1'b1 for cs[n] high active
.ne ID
1E000B3C SPI_SPACE SPI flash space control register 0000003
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Reserved[16:1]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name Res
erv
fs_slave_sel fs_clk_sel
ed[
0:0]
Type RO RW RW
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
18 TEK
Bit(s) Name Description
14:12 fs_slave_sel (Flash Space Slave Select)
0: select SPI device #0. (default is flash)
1: select SPI device #1.
...
7: select SPI device #7.
11:0 fs_clk_sel Flash Space SPI clock frequency select.
@
0: SPI clock frequency is hclk/2. (50% duty cycle, duty cycle is the ratio of the output
RD A
high time to the total cycle time)
1: SPI clock frequency is hclk/3. (33.33% or 66.67% duty cycle)
2: SPI clock frequency is hclk/4. (50% duty cycle)
3: SPI clock frequency is hclk/5. (40% or 60% duty cycle)
R DI
4095: SPI clock frequency is hclk/4097.
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.13 I2S Controller
ON
2.13.1 Features
I2S transmitter/receiver, which can be configured as master or slave.
Supports 16-bit data, sampling rates of 8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, and 48 kHz
n U TI
Support stereo audio data transfer.
32-byte FIFO are available for data transmission.
Supports GDMA access
t.c EN
Supports 12 Mhz bit clock from external source (when in slave mode)
2.13.2 Block Diagram
2
The I S transmitter block diagram is shown as below.
.ne ID CPU
RBUS
SDRAM
ink NF
RBUS
I2S Design RBUS
b-l CO
CSR
Async interface
SD
Parallel- RBUS
PBUS GDMA
WS to-serial FIFO Control
converter PBUS
SCLK
18 TEK
2
Figure 2-7 I S Transmitter Block Diagram
@
RD A
2
The I S interface consists of two separate cores, a transmitter and a receiver. Both can operate in either master
or slave mode. The transmitter is only shown here in master or slave mode.
R DI
2 2
I S Signal Timing For I S Data Format
FO ME
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L Y
SE AL
ON
n U TI
t.c EN
Figure 2-8 I2S Transmit/Receive
.ne ID
Serial data is transmitted in 2’s complement with the MSB first. The transmitter always sends the MSB of the
next word one clock period after the WS changes. Serial data sent by the transmitter may be synchronized
ink NF
with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the
serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are
some restrictions when transmitting data that is synchronized with the leading edge.
The word select line indicates the channel being transmitted:
b-l CO
WS = 0; channel 1 (left)
WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be symmetrical. In
the slave, this signal is latched on the leading edge of the clock signal. The WS line changes one clock period
before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data
that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear
18 TEK
the input for the next Word.
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.13.3 Registers
ON
Address Name Width Register Function
1E000A00 I2S_CFG 32 I2S Configuration
n U TI
I2S Tx/Rx Configuration Register
1E000A04 INT_STATUS 32 Interrupt Status
I2S Interrupt Status
32
t.c EN
1E000A08 INT_EN Interrupt Enable
I2S Interrupt Enable Control Register
1E000A0C FF_STATUS 32 FIFO Status
I2S Tx/Rx FIFO Status
1E000A10 TX_FIFO_WREG 32 Transmit FIFO Write to Register
.ne ID
Tx Write Data Buffer
1E000A14 RX_FIFO_RREG 32 Receive FIFO Read Register
DRAM PAD CONTROL 3
1E000A18 I2S_CFG1 32 I2S Configuration 1
ink NF
I2S Loopback Test Control Register
1E000A20 DIVCOMP_CFG 32 Integer Part of the Dividor Register 1
Integer Part of the Dividor Register
1E000A28 DIVINT_CFG 32 Integer Part of the Dividor Register 2
b-l CO
Integer Part of the Dividor Register
1E000A00 I2S_CFG I2S Configuration 0001404
0
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SL
BY
DM AV
I2S TE_ TX_ RX_
A_E E_
_EN SW EN EN
N MO
AP
DE
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 1
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name RX_FF_THRES TX_FF_THRES
Type RW RW
Reset 1 0 0 1 0 0
R DI
Bit(s) Name Description
31 I2S_EN I2S Enable
Enables I2S. When disabled, all I2S control registers are cleared to their initial values.
FO ME
0: Disable
1: Enable
30 DMA_EN DMA Enable
Enables DMA access.
0: Disable
1: Enable
28 BYTE_SWAP Swaps the order of data bytes in each 16-bit channel.
0: No data swap
1: Data byte swap
24 TX_EN Transmitter on/off control
0: Disable
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L Y
1: Enable
SE AL
20 RX_EN Receiver on/off control
ON
0: Disable
1: Enable
16 SLAVE_MODE Sets master or slave mode.
0: Master: using internal clock
1: Slave: using external clock
n U TI
14:12 RX_FF_THRES Rx FIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO.
2<RX_FF_THRES<6
(unit: word)
t.c EN
6:4 TX_FF_THRES Tx FIFO Threshold
When the threshold is reached, the host/DMA is notified to fill FIFO.
2<TX_FF_THRES<6
(unit: word)
1E000A04
.ne ID
INT_STATUS Interrupt Status 0000000
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name RX_
RX_ RX_ RX_
TX_
TX_ TX_ TX_
DM DM
OV UN TH OV UN TH
A_F A_F
RU RU RE RU RU RE
AU AU
N N S N N S
LT LT
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
7 RX_DMA_FAULT Rx DMA Fault Detected Interrupt
Asserts when a fault is detected in Rx DMA signals.
6 RX_OVRUN Rx Overrun Interrupt
Asserts when the Rx FIFO is overrun.
@
5 RX_UNRUN Rx Underrun Interrupt
RD A
Asserts when the Rx FIFO is underrun.
4 RX_THRES Rx FIFO Below Threshold Interrupt
Asserts when the Rx FIFO is lower than the defined threshold.
R DI
3 TX_DMA_FAULT Tx DMA Fault Detected Interrupt
Asserts when a fault is detected in Tx DMA signals.
2 TX_OVRUN Tx FIFO Overrun Interrupt
FO ME
Asserts when the Tx FIFO is overrun.
1 TX_UNRUN Tx FIFO Underrun Interrupt
Asserts when the Tx FIFO is underrun.
0 TX_THRES Tx FIFO Below Threshold Interrupt
Asserts when the FIFO is lower than the defined threshold.
1E000A08 INT_EN Interrupt Enable 0000000
0
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MT7621 PROGRAMMING GUIDE
L Y
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SE AL
Name
Type
ON
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_ RX_ RX_ RX_ TX_ TX_ TX_ TX_
INT INT INT INT INT INT INT INT
n U TI
3_E 2_E 1_E 0_E 3_E 2_E 1_E 0_E
N N N N N N N N
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
7 RX_INT3_EN INT_STATUS[7] Enable
Enables the Rx DMA Fault Detected Interrupt. This interrupt asserts when a fault is
detected in Rx DMA signals.
.ne ID
6 RX_INT2_EN INT_STATUS[6] Enable
Enables the Rx Overrun Interrupt. This interrupt asserts when the Rx FIFO is overrun.
5 RX_INT1_EN INT_STATUS[5] Enable
Enables the Rx Underrun Interrupt. This interrupt asserts when the Rx FIFO is
ink NF
underrun.
4 RX_INT0_EN INT_STATUS[4] Enable
Enables the Rx FIFO Below Threshold Interrupt. This interrupt asserts when the Rx
FIFO is lower than the defined threshold.
3 TX_INT3_EN INT_STATUS[3] Enable
b-l CO
Enables the Tx DMA Fault Detected Interrupt. This interrupt asserts when a fault is
detected in Tx DMA signals.
2 TX_INT2_EN INT_STATUS[2] Enable
Enables the Tx FIFO Overrun Interrupt. This interrupt asserts when the Tx FIFO is
overrun.
1 TX_INT1_EN INT_STATUS[1] Enable
18 TEK
Enables the Tx FIFO Underrun Interrupt. This interrupt asserts when the Tx FIFO is
underrun.
0 TX_INT0_EN INT_STATUS[0] Enable
Enables the Tx FIFO Below Threshold Interrupt. This interrupt asserts when the FIFO is
lower than the defined threshold.
@
RD A
1E000A0C FF_STATUS FIFO Status 0000000
8
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name RX_AVCNT TX_EPCNT
Type RO RO
Reset 0 0 0 0 1 0 0 0
Bit(s) Name Description
7:4 RX_AVCNT Rx FIFO Available Space Count
Counts the available space for reads in Rx FIFO.
(unit: word)
3:0 TX_EPCNT Tx FIFO Available Space Count
Counts the available space for writes in Tx FIFO.
PGMT7621_V.1.0_130607 Page 217 of 349
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MT7621 PROGRAMMING GUIDE
L Y
(unit: word)
SE AL
ON
1E000A10 TX_FIFO_WR Transmit FIFO Write to Register 0000000
EG 0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_FIFO_WDATA[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_FIFO_WDATA[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:0 TX_FIFO_WDATA Tx FIFO Write Data Buffer
Buffers data to be written to the Tx FIFO.
ink NF
1E000A14 RX_FIFO_RR Receive FIFO Read Register 0000000
EG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name RX_FIFO_RDATA[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RX_FIFO_RDATA[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 RX_FIFO_RDATA Rx FIFO Read Data Buffer
Buffers data read from the Rx FIFO.
@
RD A
1E000A18 I2S_CFG1 I2S Configuration 1 0000000
0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name EXT
LB
_LB
K_E
K_E
N
N
FO ME
Type RW RW
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
31 LBK_EN Enables loopback mode.
0: Normal mode
1: Loopback mode
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MT7621 PROGRAMMING GUIDE
L Y
ASYNC_TXFIFIO -> Tx -> Rx -> ASYNC_RXFIFIO
SE AL
30 EXT_LBK_EN Enables external loopback.
ON
0: Normal mode
1: Enables external loop back.
External A/D -> Rx -> Tx -> External D/A
n U TI
1E000A20 DIVCOMP_CF Integer Part of the Dividor Register 1 0000000
G 0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL
K_E
N
Type RW
Reset 0
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DIVCOMP
Type RW
Reset 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31 CLK_EN Enables setting of the I2S clock based on DIVCOMP and DIVINT parameters.
0: Disable
1: Enable
b-l CO
8:0 DIVCOMP A parameter in an equation which determines FREQOUT. See DIVINT_CFG.
1E000A28 DIVINT_CFG Integer Part of the Dividor Register 2 0000000
0
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DIVINT
Type RW
@
Reset 0 0 0 0 0 0 0 0 0 0
RD A
Bit(s) Name Description
R DI
9:0 DIVINT Integer Divider
A parameter in an equation which determines FREQOUT:
FREQOUT = FREQIN *(1/2) *
{1 / [DIVINT+DIVCOMP/(512)]}
FREQIN is always fixed to 40 MHz.
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.14 SPDIF TX
ON
n U TI
t.c EN
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
2.14.1 Registers
SE AL
SPDIFTX Changes LOG
ON
Revision Date Author Change Log
1.0 20120825 Jiechao Wei Initial Revision by RegisterMap_v1p4
1.1 20120919 Jiechao Wei Update for final RISC(PBUS) interface
n U TI
1.2 20121009 Jiechao Wei Update default value
1.3 20121216 Jiechao Wei Update for DRAM ping-pong structure
t.c EN
Module name: SPDIFTX Base address: (+1E000700h)
Address Name Widt Register Function
h
.ne ID
1E000700 IEC_CTRL 32 IEC CONTROL REGISTER
1E000704 IEC_BUF0_BS_SB 32 IEC BITSTREAM BUFFER START BLOCK
LK
ink NF
1E000708 IEC_BUF0_BS_EB 32 IEC BITSTREAM BUFFER END BLOCK
LK
1E00070C IEC_BUF0_NSADR 32 IEC NEXT BURST START ADDRESS
1E000710 IEC_BUF0_NEXT_ 32 IEC USER DATA NEXT START ADDRESS
UADR
b-l CO
1E000714 IEC_BUF0_INTR_N 32 IEC INTERRUPT SIZE
SNUM
1E000718 IEC_BUF0_PCPD_ 32 IEC NEXT BURST LENGTH
PACK
1E00071C IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION TRIGGER
G_TRIG
18 TEK
1E000720 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 0
G0
1E000724 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 1
G1
1E000728 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 2
G2
1E00072C IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 3
@
G3
RD A
1E000730 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 4
G4
R DI
1E000734 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 5
G5
1E000738 IEC_BUF0_CH_CF 32 IEC CHANNEL CONFIGURATION 6
G6
FO ME
1E00073C IEC_ACLK_DIV 32 IEC AUDIO MASTER CLOCK DIVIDER
1E000740 IEC_APLL_CFG0 32 IEC AUDIO PLL CONFIGURATION 0
1E000744 IEC_APLL_CFG1 32 IEC AUDIO PLL CONFIGURATION 1
1E000748 IEC_APLL_CFG2 32 IEC AUDIO PLL CONFIGURATION 2
1E00074C IEC_APLL_CFG3 32 IEC AUDIO PLL CONFIGURATION 3
1E000750 IEC_APLL_DEBUG 32 IEC AUDIO PLL DEBUG INFORMATION
1E000754 IEC_BUF1_BS_SB 32 IEC BITSTREAM BUFFER START BLOCK
LK
1E000758 IEC_BUF1_BS_EB 32 IEC BITSTREAM BUFFER END BLOCK
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MT7621 PROGRAMMING GUIDE
L Y
LK
SE AL
1E00075C IEC_BUF1_NSADR 32 IEC NEXT BURST START ADDRESS
ON
1E000760 IEC_BUF1_NEXT_ 32 IEC USER DATA NEXT START ADDRESS
UADR
1E000764 IEC_BUF1_INTR_N 32 IEC INTERRUPT SIZE
SNUM
n U TI
1E000768 IEC_BUF1_PCPD_ 32 IEC NEXT BURST LENGTH
PACK
1E00076C IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION TRIGGER
G_TRIG
t.c EN
1E000770 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 0
G0
1E000774 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 1
G1
1E000778 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 2
.ne ID
G2
1E00077C IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 3
G3
1E000780 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 4
ink NF
G4
1E000784 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 5
G5
1E000788 IEC_BUF1_CH_CF 32 IEC CHANNEL CONFIGURATION 6
G6
b-l CO
1E000700 IEC_CTRL IEC CONTROL REGISTER 0000008
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
18 TEK
Name INT
RA R_E
W_ NA
EN BL
E
Type RW RW
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name
RD A
DB MU
INT MU BY RA UD DA DA
DB UF_ RA TE_
R_S TE_ TE_ W_ AT TA_ TA_
UF_ DIS DOWN_SAMPLE W_ SA
TAT SP SW SW A_E FM SR
SEL AB 24 MP
R DI
US DF AP AP N T C
LE LE
Type W1
RO RW RW RW RW RW RW RW RW RW RW
C
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31 RAW_EN IEC958 raw data enable
0: disable
1: enable
16 INTR_ENABLE IEC958 interrupt enable
0: disable
1: enable
15 INTR_STATUS IEC958 interrupt status
0: No interrupt
1: Interrupting
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MT7621 PROGRAMMING GUIDE
L Y
12 DBUF_SEL IEC958 DRAM ping-pong buffer indicator
SE AL
0: buffer0 is going
1: buffer1 is going
ON
11 DBUF_DISABLE IEC958 DRAM ping-pong buffer disable
0: enable
1: disable
n U TI
10:8 DOWN_SAMPLE IEC958 down sample control
0: no down sample (recommended for MT7621)
1: 2x down sample
3: 4x down sample
t.c EN
7 MUTE_SPDF mute IEC output SPDF signal
0: normal
1: mute output SPDF signal
6 BYTE_SWAP IEC dram word data bytes switch mode
5 RAW_SWAP IEC 24bit raw data bytes switch mode
.ne ID
4 RAW_24 IEC raw data 24bit mode
3 MUTE_SAMPLE mute IEC output sample data
0: normal
1: mute output sample data
ink NF
2 UDATA_EN user data enable
0: all user data are zero
1: load user data from DRAM (IEC_NEXT_UADR)
1 DATA_FMT output data format selection
0: PCM data
b-l CO
1: encoded data
0 DATA_SRC data source selection
0: cooked data (from PCM receiver or transmitter output)
1: raw data (from DRAM 61937 encoded audio data or 60958 plain PCM data)
18 TEK
1E000704 IEC_BUF0_BS IEC BITSTREAM BUFFER START BLOCK 0000000
_SBLK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BS_SBLK[27:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name BS_SBLK[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
27:0 BS_SBLK IEC958 bitstream buffer start block (double word size)
FO ME
1E000708 IEC_BUF0_BS IEC BITSTREAM BUFFER END BLOCK 0000000
_EBLK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BS_EBLK[27:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BS_EBLK[15:0]
Type RW
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
ON
Bit(s) Name Description
27:0 BS_EBLK IEC958 bitstream buffer end block (double word size)
n U TI
1E00070C IEC_BUF0_NS IEC NEXT BURST START ADDRESS 0000000
ADR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name NSADR[29:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NSADR[15:0]
.ne ID
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
29:0 NSADR next start address for next burst raw data (byte size)
1E000710 IEC_BUF0_NE IEC USER DATA NEXT START ADDRESS 0000000
b-l CO
XT_UADR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NUSADR[29:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name NUSADR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
29:0 NUSADR next start address for next user data, LSB 2 bits are ignored and considered zero
(byte size)
@
RD A
1E000714 IEC_BUF0_IN IEC INTERRUPT SIZE 0000000
R DI
TR_NSNUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INTR_SIZE
FO ME
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NSNUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 INTR_SIZE generating interrupt when how many samples remain for this burst
12:0 NSNUM next sample number represented by next burst raw data
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E000718 IEC_BUF0_PC IEC NEXT BURST LENGTH 0000000
ON
PD_PACK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NB_LEN
n U TI
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BURST_INFO
Type RW
t.c EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 NB_LEN number of bits for next burst(Pd package)
.ne ID
15:0 BURST_INFO burst information for IEC(Pc package)
ink NF
1E00071C IEC_BUF0_CH IEC CHANNEL CONFIGURATION TRIGGER 0000000
_CFG_TRIG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH
_CF
CH2_NUM
b-l CO
G_T
RIG
Type RW RW
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
18 TEK
Reset
Bit(s) Name Description
31 CH_CFG_TRIG channel status update trigger, write 1'b1 to trigger and read busy state or not
23:20 CH2_NUM channel 2 (W) channel number
@
RD A
1E000720 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 0 0000000
_CFG0 0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG0_ CLK_ACC
SAM_FREQ CH1_NUM SRC_NUM
RESERVE URACY
Type RW RW RW RW RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CO
CP_ DIG
NS
CATEGORY MODE ADD_INFO RIG ITA
UM
HT L
ER
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:30 CH_CFG0_RESERVE channel status reserve bits
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MT7621 PROGRAMMING GUIDE
L Y
29:28 CLK_ACCURACY clock accuracy
SE AL
27:24 SAM_FREQ sampling frequency
ON
23:20 CH1_NUM channel 1 (B & M) channel number
19:16 SRC_NUM source number
15:8 CATEGORY category code
n U TI
7:6 MODE channel status mode 0
5:3 ADD_INFO additional information
2 CP_RIGHT copyright information
1 DIGITAL digital (bit 1 of channel status)
t.c EN
0: linear PCM samples
1: other purpose
0 CONSUMER bit 0 of channel status
0: consumer use of channel status block
1: professional use of channel status block
1E000724
.ne ID
IEC_BUF0_CH IEC CHANNEL CONFIGURATION 1 0000000
ink NF
_CFG1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG1_RESERVE[21:6]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG1_RESERVE[5:0] CGMS_A ORIGINAL_FS WORD_LEN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:10 CH_CFG1_RESERVE channel status reserve bits
9:8 CGMS_A CGMS-A information
7:4 ORIGINAL_FS original sample frequency
3:0 WORD_LEN word length
@
RD A
1E000728 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 2 0000000
_CFG2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name CH_CFG2_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name CH_CFG2_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH_CFG2_RESERVE channel status reserve bits
1E00072C IEC_BUF0_CH IEC CHANNEL CONFIGURATION 3 0000000
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MT7621 PROGRAMMING GUIDE
L Y
_CFG3 0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name CH_CFG3_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name CH_CFG3_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 CH_CFG3_RESERVE channel status reserve bits
.ne ID
1E000730 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 4 0000000
_CFG4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG4_RESERVE[31:16]
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG4_RESERVE[15:0]
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH_CFG4_RESERVE channel status reserve bits
18 TEK
1E000734 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 5 0000000
_CFG5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG5_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name CH_CFG5_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:0 CH_CFG5_RESERVE channel status reserve bits
FO ME
1E000738 IEC_BUF0_CH IEC CHANNEL CONFIGURATION 6 0000000
_CFG6 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG6_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG6_RESERVE[15:0]
PGMT7621_V.1.0_130607 Page 227 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Type RW
Reset
SE AL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31:0 CH_CFG6_RESERVE channel status reserve bits
n U TI
1E00073C IEC_ACLK_DI IEC AUDIO MASTER CLOCK DIVIDER 0018241
V F
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MAS_DIV
Type RW
Reset 0 0 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.ne ID
Name IEC_DIV BIT_DIV LRC_DIV
Type RW RW RW
Reset 0 1 0 0 1 0 0 1 1 1 1 1
ink NF
Bit(s) Name Description
23:16 MAS_DIV audio master clock divider by audio pll (default 256xfs)
14:12 IEC_DIV audio iec958 clock divider by audio master clock (default 128xfs)
11:8 BIT_DIV audio bit clock divider by audio master clock (default 64xfs)
b-l CO
4:0 LRC_DIV audio lrck divider by audio bit clock (default 1xfs)
1E000740 IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 0 0000000
G0 0
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name APLL_CFG0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_CFG0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
RD A
Bit(s) Name Description
31:0 APLL_CFG0 audio pll configuration register 0 (Need MT7621 update)
R DI
1E000744 IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 1 0000000
FO ME
G1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name APLL_CFG1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_CFG1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
PGMT7621_V.1.0_130607 Page 228 of 349
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MT7621 PROGRAMMING GUIDE
L Y
31:0 APLL_CFG1 audio pll configuration register 1 (Need MT7621 update)
SE AL
ON
1E000748 IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 2 0000000
G2 0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name APLL_CFG2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_CFG2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 APLL_CFG2
ink NF audio pll configuration register 2 (Need MT7621 update)
1E00074C IEC_APLL_CF IEC AUDIO PLL CONFIGURATION 3 0000000
G3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name APLL_CFG3[31:16]
b-l CO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_CFG3[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 APLL_CFG3 audio pll configuration register 3 (Need MT7621 update)
1E000750 IEC_APLL_DE IEC AUDIO PLL DEBUG INFORMATION 0000000
@
BUG 0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
R DI
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name APLL_DEBUG
Type RO
FO ME
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7:0 APLL_DEBUG audio pll debug information (Need MT7621 update)
1E000754 IEC_BUF1_BS IEC BITSTREAM BUFFER START BLOCK 0000000
_SBLK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PGMT7621_V.1.0_130607 Page 229 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Name BS_SBLK[28:16]
SE AL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BS_SBLK[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
28:0 BS_SBLK IEC958 bitstream buffer start block (double word size)
t.c EN
1E000758 IEC_BUF1_BS IEC BITSTREAM BUFFER END BLOCK 0000000
_EBLK 0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BS_EBLK[28:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name BS_EBLK[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
28:0 BS_EBLK IEC958 bitstream buffer end block (double word size)
1E00075C IEC_BUF1_NS IEC NEXT BURST START ADDRESS 0000000
ADR 0
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NSADR[30:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NSADR[15:0]
Type RW
@
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD A
Bit(s) Name Description
R DI
30:0 NSADR next start address for next burst raw data (byte size)
FO ME
1E000760 IEC_BUF1_NE IEC USER DATA NEXT START ADDRESS 0000000
XT_UADR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NUSADR[30:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NUSADR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGMT7621_V.1.0_130607 Page 230 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
30:0 NUSADR next start address for next user data, LSB 2 bits are ignored and considered zero
ON
(byte size)
n U TI
1E000764 IEC_BUF1_IN IEC INTERRUPT SIZE 0000000
TR_NSNUM 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name INTR_SIZE
t.c EN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name NSNUM
Type RW
Reset
.ne ID
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:16 INTR_SIZE generating interrupt when how many samples remain for this burst
ink NF
12:0 NSNUM next sample number represented by next burst raw data
1E000768 IEC_BUF1_PC IEC NEXT BURST LENGTH 0000000
b-l CO
PD_PACK 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name NB_LEN
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name BURST_INFO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 NB_LEN number of bits for next burst(Pd package)
15:0 BURST_INFO burst information for IEC(Pc package)
@
RD A
R DI
1E00076C IEC_BUF1_CH IEC CHANNEL CONFIGURATION TRIGGER 0000000
_CFG_TRIG 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH
FO ME
_CF
CH2_NUM
G_T
RIG
Type RW RW
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
31 CH_CFG_TRIG channel status update trigger, write 1'b1 to trigger and read busy state or not
SE AL
23:20 CH2_NUM channel 2 (W) channel number
ON
1E000770 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 0 0000000
n U TI
_CFG0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG0_ CLK_ACC
SAM_FREQ CH1_NUM SRC_NUM
RESERVE URACY
t.c EN
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CP_ DIG
CO
NS
CATEGORY MODE ADD_INFO RIG ITA
UM
.ne ID
HT L
ER
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:30 CH_CFG0_RESERVE channel status reserve bits
29:28 CLK_ACCURACY clock accuracy
27:24 SAM_FREQ sampling frequency
b-l CO
23:20 CH1_NUM channel 1 (B & M) channel number
19:16 SRC_NUM source number
15:8 CATEGORY category code
7:6 MODE channel status mode 0
5:3 ADD_INFO additional information
2 CP_RIGHT copyright information
18 TEK
1 DIGITAL digital (bit 1 of channel status)
0: linear PCM samples
1: other purpose
0 CONSUMER bit 0 of channel status
0: consumer use of channel status block
1: professional use of channel status block
@
RD A
1E000774 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 1 0000000
R DI
_CFG1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG1_RESERVE[21:6]
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG1_RESERVE[5:0] CGMS_A ORIGINAL_FS WORD_LEN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:10 CH_CFG1_RESERVE channel status reserve bits
9:8 CGMS_A CGMS-A information
7:4 ORIGINAL_FS original sample frequency
PGMT7621_V.1.0_130607 Page 232 of 349
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MT7621 PROGRAMMING GUIDE
L Y
3:0 WORD_LEN word length
SE AL
ON
1E000778 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 2 0000000
_CFG2 0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG2_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG2_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:0 CH_CFG2_RESERVE
ink NF channel status reserve bits
1E00077C IEC_BUF1_CH IEC CHANNEL CONFIGURATION 3 0000000
_CFG3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG3_RESERVE[31:16]
b-l CO
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG3_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:0 CH_CFG3_RESERVE channel status reserve bits
1E000780 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 4 0000000
@
_CFG4 0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG4_RESERVE[31:16]
R DI
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG4_RESERVE[15:0]
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 CH_CFG4_RESERVE channel status reserve bits
1E000784 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 5 0000000
_CFG5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PGMT7621_V.1.0_130607 Page 233 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Name CH_CFG5_RESERVE[31:16]
SE AL
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CH_CFG5_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:0 CH_CFG5_RESERVE channel status reserve bits
t.c EN
1E000788 IEC_BUF1_CH IEC CHANNEL CONFIGURATION 6 0000000
_CFG6 0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CH_CFG6_RESERVE[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name CH_CFG6_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
31:0 CH_CFG6_RESERVE channel status reserve bits
18 TEK
@
RD A
R DI
FO ME
PGMT7621_V.1.0_130607 Page 234 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.15 Memory Controller
ON
2.15.1 Features
1 SDRAM/DDR2 (16 b) chip selection
128 MB (SDRAM)/128 MB (DDR1)/256 MB (DDR2) per chip selection
n U TI
SDRAM transaction overlapping by early active and hidden pre-charge
User SDRAM Init commands
4 banks per SDRAM chip select
t.c EN
SDRAM burst length: 4 (fixed)
DDR2 burst length: 4/8 (programmable)
Wrap-4 transfer
Bank-Raw-Column and Raw-Bank-Column address mapping
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
PGMT7621_V.1.0_130607 Page 235 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.15.2 Registers
ON
Address Name Widt Register Function
h
n U TI
1E005000 ACTIM0 32 DRAM AC TIMING SETTING 0
DRAM AC TIMING SETTING 0
1E005004 CONF1 32 DRAM CONFIGURATION 1
DRAM CONFIGURATION 1
t.c EN
1E005008 CONF2 32 DRAM CONFIGURATION 2
DRAM CONFIGURATION 2
1E00500C PADCTL1 32 DRAM PAD CONTROL 1
DRAM PAD CONTROL 1
.ne ID
1E005010 PADCTL2 32 DRAM PAD CONTROL 2
DRAM PAD CONTROL 2
1E005014 PADCTL3 32 DRAM PAD CONTROL 3
DRAM PAD CONTROL 3
ink NF
1E005018 DELDLY1 32 DQS INPUT DELAY CHAIN SETTING 1
DQS INPUT DELAY CHAIN SETTING 1
1E005020 DIFDLY1 32 DQS INPUT DELAY CHAIN OFFSET SETTING 1
DQS INPUT DELAY CHAIN OFFSET SETTING 1
b-l CO
1E005028 DLLCONF 32 DLL CONFIGURATION
DLL CONFIGURATION
1E00502C TESTMODE 32 TEST MODE CONFIGURATION 1
TEST MODE CONFIGURATION 1
1E00503C TEST2_1 32 TEST AGENT 2 CONFIGURATION 1
TEST AGENT 2 CONFIGURATION 1
18 TEK
1E005040 TEST2_2 32 TEST AGENT 2 CONFIGURATION 2
TEST AGENT 2 CONFIGURATION 2
1E005044 TEST2_3 32 TEST AGENT 2 CONFIGURATION 3
TEST AGENT 2 CONFIGURATION 3
1E005048 TEST2_4 32 TEST AGENT 2 CONFIGURATION 4
TEST AGENT 2 CONFIGURATION 4
@
1E00507C DDR2CTL 32 DDR2 CONTROL REGISTER
RD A
DDR2 CONTROL REGISTER
1E005084 ZQCS 32 ZQCS setting
R DI
ZQCS setting
1E005088 MRS 32 MRS value setting
MRS value setting
1E00508C CLK1DELAY 32 Clock 1 output delay CONTROL
FO ME
Clock 1 output delay CONTROL
1E005090 IOCTL 32 IO CONTROL
IO misc control
1E005094 DQSIEN 32 DQS INPUT RANGE FINE TUNER
DQS INPUT RANGE FINE TUNER
1E0050B8 DRVCTL0 32 PAD DRIVING CONTROL SETTING 0
PAD DRIVING CONTROL SETTING 0
1E0050BC DRVCTL1 32 PAD DRIVING CONTROL SETTING 1
PAD DRIVING CONTROL SETTING 1
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MT7621 PROGRAMMING GUIDE
L Y
1E0050C0 DLLSEL 32 DLL SELECTION SETTING
SE AL
DLL SELECTION SETTING
ON
1E0050CC TDSEL0 32 IO OUTPUT DUTY CONTROL 0
IO OUTPUT DUTY CONTROL 0
1E0050D0 TDSEL1 32 IO OUTPUT DUTY CONTROL 1
IO OUTPUT DUTY CONTROL 1
n U TI
1E0050D8 MCKDLY 32 MEMORY CLOCK DELAY CHAIN SETTING
MEMORY CLOCK DELAY CHAIN SETTING
1E0050DC DQSCTL0 32 DQS INPUT RANGE CONTROL 0
t.c EN
DQS INPUT RANGE CONTROL 0
1E0050E0 DQSCTL1 32 DQS INPUT RANGE CONTROL 1
DQS INPUT RANGE CONTROL 1
1E0050E4 PADCTL4 32 PAD CONTROL 1
PAD CONTROL 4
.ne ID
1E0050E8 PADCTL5 32 PAD CONTROL 2
PAD CONTROL 5
1E0050EC PADCTL6 32 PAD CONTROL 3
ink NF
PAD CONTROL 6
1E0050F0 PHYCTL1 32 DDR PHY CONTROL 1
DDR PHY CONTROL 1
1E0050F4 GDDR3CTL1 32 GDDR3 CONTROL 1
GDDR3 CONTROL 1
b-l CO
1E0050F8 PADCTL7 32 PAD CONTROL 4
PAD CONTROL 7
1E0050FC MISCTL0 32 MISC CONTROL 0
MISC CONTROL 0
1E005100 OCDK 32 OCD CALIBRATION CONTROL
OCD CALIBRATION CONTROL
18 TEK
1E005104 LBWDAT0 32 LOOP BACK DATA 0
LOOP BACK DATA 0
1E005108 LBWDAT1 32 LOOP BACK DATA 1
LOOP BACK DATA 1
1E00510C LBWDAT2 32 LOOP BACK DATA 2
LOOP BACK DATA 2
@
RD A
1E005110 RKCFG 32 RANK CONFIGURATION
RANK CONFIGURATION
1E005114 CKPHDET 32 CLOCK PHASE DETECTION SETTING
R DI
CLOCK PHASE DETECTION SETTING
1E005124 DQSGCTL 32 INPUT DQS GATING CONTROL
INPUT DQS GATING CONTROL
FO ME
1E005130 CLKENCTL 32 DRAM CLOCK ENABLE CONTROL
DRAM CLOCK ENABLE CONTROL
1E005140 DQSGCTL1 32 DQS gating delay control 1
DQS gating delay control 1
1E005144 DQSGCTL2 32 DQS gating delay control 2
DQS gating delay control 2
1E005168 ARBCTL0 32 ARBITRATION CONTROL 0
ARBITRATION CONTROL 0
1E0051A8 CMDDLY0 32 Command Delay CTL0
Command Delay CTL0
PGMT7621_V.1.0_130607 Page 237 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1E0051AC CMDDLY1 32 Command Delay CTL1
SE AL
Command Delay CTL1
ON
1E0051B0 CMDDLY2 32 Command Delay CTL2
Command Delay CTL2
1E0051B4 CMDDLY3 32 Command Delay CTL3
Command Delay CTL3
n U TI
1E0051B8 CMDDLY4 32 Command Delay CTL4
Command Delay CTL4
1E0051BC CMDDLY5 32 Command Delay CTL5
t.c EN
Command Delay CTL5
1E0051C0 DQSCAL0 32 DQS CAL CONTROL 0
DQS CAL CONTROL 0
1E0051D8 DMMonitor 32 Monitor parameter
Monitor parameter
.ne ID
1E0051DC DRAMC_PD_CTRL 32 PD mode parameter
PD mode parameter
1E0051E0 LPDDR2 32 LPDDR2 setting
ink NF
LPDDR2 setting
1E0051E4 SPCMD 32 Special command mode
Special command mode
1E0051E8 ACTIM1 32 DRAM AC TIMING SETTING 1
DRAM AC TIMING SETTING 1
b-l CO
1E0051EC PERFCTL0 32 PERFORMANCE CONTROL 0
PERFORMANCE CONTROL 0
1E0051F0 AC_DERATING 32 AC TIME DERATING CONTROL
AC TIME DERATING CONTROL
1E0051F4 RRRATE_CTL 32 REFRESH RATE CONTROL
REFRESH RATE CONTROL
18 TEK
1E0051F8 WPATCMP_DAT 32 WRITE PATTERN COMPARE SETTING
WRITE PATTERN COMPARE SETTING
1E0051FC WPATCMP_CTL 32 WRITE PATTERN COMPARE CONTROL
WRITE PATTERN COMPARE CONTROL
1E005200 DQODLY1 32 DQ output DELAY1 CHAIN setting
DQ output DELAY1 CHAIN setting
@
RD A
1E005204 DQODLY2 32 DQ output DELAY2 CHAIN setting
DQ output DELAY2 CHAIN setting
1E005208 DQODLY3 32 DQ output DELAY3 CHAIN setting
R DI
DQ output DELAY3 CHAIN setting
1E00520C DQODLY4 32 DQ output DELAY4 CHAIN setting
DQ output DELAY4 CHAIN setting
FO ME
1E005210 DQIDLY1 32 DQ input DELAY1 CHAIN setting
DQ input DELAY1 CHAIN setting
1E005214 DQIDLY2 32 DQ input DELAY2 CHAIN setting
DQ input DELAY2 CHAIN setting
1E005218 DQIDLY3 32 DQ input DELAY3 CHAIN setting
DQ input DELAY3 CHAIN setting
1E00521C DQIDLY4 32 DQ input DELAY4 CHAIN setting
DQ input DELAY4 CHAIN setting
1E005220 DQIDLY5 32 DQ input DELAY5 CHAIN setting
DQ input DELAY5 CHAIN setting
PGMT7621_V.1.0_130607 Page 238 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1E005224 DQIDLY6 32 DQ input DELAY6 CHAIN setting
SE AL
DQ input DELAY6 CHAIN setting
ON
1E005228 DQIDLY7 32 DQ input DELAY7 CHAIN setting
DQ input DELAY7 CHAIN setting
1E00522C DQIDLY8 32 DQ input DELAY8 CHAIN setting
DQ input DELAY8 CHAIN setting
n U TI
1E005280 R2R_page_hit_cou 32 R2R_page_hit_counter
nter R2R_page_hit_counter
1E005284 R2R_page_miss_c 32 R2R_page_miss_counter
t.c EN
ounter R2R_page_miss_counter
1E005288 R2R_interbank_co 32 R2R_interbank_counter
unter R2R_interbank_counter
1E00528C R2W_page_hit_co 32 R2W_page_hit_counter
unter R2W_page_hit_counter
.ne ID
1E005290 R2W_page_miss_ 32 R2W_page_miss_counter
counter R2W_page_miss_counter
1E005294 R2W_interbank_co 32 R2W_interbank_counter
unter
ink NF
R2W_interbank_counter
1E005298 W2R_page_hit_co 32 W2R_page_hit_counter
unter W2R_page_hit_counter
1E00529C W2R_page_miss_ 32 W2R_page_miss_counter
counter W2R_page_miss_counter
b-l CO
1E0052A0 W2R_interbank_co 32 W2R_interbank_counter
unter W2R_interbank_counter
1E0052A4 W2W_page_hit_co 32 W2W_page_hit_counter
unter W2W_page_hit_counter
1E0052A8 W2W_page_miss_ 32 W2W_page_miss_counter
counter W2W_page_miss_counter
18 TEK
1E0052AC W2W_interbank_c 32 W2W_interbank_counter
ounter W2W_interbank_counter
1E0052B0 dramc_idle_count 32 dramc_idle_counter
er dramc_idle_counter
1E0052B4 freerun_26m_coun 32 freerun_26m_counter
ter freerun_26m_counter
@
RD A
1E0052B8 refresh_pop_coun 32 refresh_pop_counter
ter refresh_pop_counter
1E0052BC JMETER_ST 32 Jitter Meter Status
R DI
1E0052C0 DQ_CAL_MAX_0 32 DQ INPUT CALIBRATION per bit 3-0
DQ INPUT CALIBRATION per bit 3-0
1E0052C4 DQ_CAL_MAX_1 32 DQ INPUT CALIBRATION per bit 7-4
FO ME
DQ INPUT CALIBRATION per bit 7-4
1E0052C8 DQ_CAL_MAX_2 32 DQ INPUT CALIBRATION per bit 11-8
DQ INPUT CALIBRATION per bit 11-8
1E0052CC DQ_CAL_MAX_3 32 DQ INPUT CALIBRATION per bit 15-12
DQ INPUT CALIBRATION per bit 15-12
1E0052D0 DQ_CAL_MAX_4 32 DQ INPUT CALIBRATION per bit 19-16
DQ INPUT CALIBRATION per bit 19-16
1E0052D4 DQ_CAL_MAX_5 32 DQ INPUT CALIBRATION per bit 23-20
DQ INPUT CALIBRATION per bit 23-20
1E0052D8 DQ_CAL_MAX_6 32 DQ INPUT CALIBRATION per bit 27-34
PGMT7621_V.1.0_130607 Page 239 of 349
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MT7621 PROGRAMMING GUIDE
L Y
DQ INPUT CALIBRATION per bit 27-24
SE AL
1E0052DC DQ_CAL_MAX_7 32 DQ INPUT CALIBRATION per bit 31-28
ON
DQ INPUT CALIBRATION per bit 31-28
1E0052E0 DQS_CAL_MIN_0 32 DQS INPUT CALIBRATION per bit 3-0
DQS INPUT CALIBRATION per bit 3-0
1E0052E4 DQS_CAL_MIN_1 32 DQS INPUT CALIBRATION per bit 7-4
n U TI
DQS INPUT CALIBRATION per bit 7-4
1E0052E8 DQS_CAL_MIN_2 32 DQS INPUT CALIBRATION per bit 11-8
DQS INPUT CALIBRATION per bit 11-8
t.c EN
1E0052EC DQS_CAL_MIN_3 32 DQS INPUT CALIBRATION per bit 15-12
DQS INPUT CALIBRATION per bit 15-12
1E0052F0 DQS_CAL_MIN_4 32 DQS INPUT CALIBRATION per bit 19-16
DQS INPUT CALIBRATION per bit 19-16
1E0052F4 DQS_CAL_MIN_5 32 DQS INPUT CALIBRATION per bit 23-20
.ne ID
DQS INPUT CALIBRATION per bit 23-20
1E0052F8 DQS_CAL_MIN_6 32 DQS INPUT CALIBRATION per bit 27-34
DQS INPUT CALIBRATION per bit 27-24
ink NF
1E0052FC DQS_CAL_MIN_7 32 DQS INPUT CALIBRATION per bit 31-28
DQS INPUT CALIBRATION per bit 31-28
1E005300 DQS_CAL_MAX_0 32 DQS INPUT CALIBRATION per bit 3-0
DQS INPUT CALIBRATION per bit 3-0
1E005304 DQS_CAL_MAX_1 32 DQS INPUT CALIBRATION per bit 7-4
b-l CO
DQS INPUT CALIBRATION per bit 7-4
1E005308 DQS_CAL_MAX_2 32 DQS INPUT CALIBRATION per bit 11-8
DQS INPUT CALIBRATION per bit 11-8
1E00530C DQS_CAL_MAX_3 32 DQS INPUT CALIBRATION per bit 15-12
DQS INPUT CALIBRATION per bit 15-12
1E005310 DQS_CAL_MAX_4 32 DQS INPUT CALIBRATION per bit 19-16
18 TEK
DQS INPUT CALIBRATION per bit 19-16
1E005314 DQS_CAL_MAX_5 32 DQS INPUT CALIBRATION per bit 23-20
DQS INPUT CALIBRATION per bit 23-20
1E005318 DQS_CAL_MAX_6 32 DQS INPUT CALIBRATION per bit 27-34
DQS INPUT CALIBRATION per bit 27-24
1E00531C DQS_CAL_MAX_7 32 DQS INPUT CALIBRATION per bit 31-28
@
DQS INPUT CALIBRATION per bit 31-28
RD A
1E005350 DQICAL0 32 DQS INPUT CALIBRATION 0
DQS INPUT CALIBRATION 0
R DI
1E005354 DQICAL1 32 DQS INPUT CALIBRATION 1
DQS INPUT CALIBRATION 1
1E005358 DQICAL2 32 DQS INPUT CALIBRATION 2
DQS INPUT CALIBRATION 2
FO ME
1E00535C DQICAL3 32 DQS INPUT CALIBRATION 3
DQS INPUT CALIBRATION 3
1E005370 CMP_ERR 32 CMP ERROR
CMP ERROR
1E005374 DQSIENDLY 32 DQS INPUT GATING DELAY VALUE
DQS INPUT GATING DELAY VALUE
1E00538C STBEN0 32 DQS RING COUNTER 0
DQS RING COUNTER 0
1E005390 STBEN1 32 DQS RING COUNTER 1
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MT7621 PROGRAMMING GUIDE
L Y
DQS RING COUNTER 1
SE AL
1E005394 STBEN2 32 DQS RING COUNTER 2
ON
DQS RING COUNTER 2
1E005398 STBEN3 32 DQS RING COUNTER 3
DQS RING COUNTER 3
1E0053A0 DQSDLY0 32 DQS INPUT DELAY SETTING 0
n U TI
DQS INPUT DELAY SETTING 0
1E0053B8 SPCMDRESP 32 SPECIAL COMMAND RESPONSE
SPECIAL COMMAND RESPONSE
t.c EN
1E0053BC IORGCNT 32 IO RING COUNTER
IO RING COUNTER
1E0053C0 DQSGNWCNT0 32 DQS GATING WINODW COUNTER 0
DQS GATING WINODW COUNTER 0
1E0053C4 DQSGNWCNT1 32 DQS GATING WINODW COUNTER 1
.ne ID
DQS GATING WINODW COUNTER 1
1E0053C8 DQSGNWCNT2 32 DQS GATING WINODW COUNTER 2
DQS GATING WINODW COUNTER 2
ink NF
1E0053CC DQSGNWCNT3 32 DQS GATING WINODW COUNTER 3
DQS GATING WINODW COUNTER 3
1E0053D0 DQSGNWCNT4 32 DQS GATING WINODW COUNTER 4
DQS GATING WINODW COUNTER 4
1E0053D4 DQSGNWCNT5 32 DQS GATING WINODW COUNTER 5
b-l CO
DQS GATING WINODW COUNTER 5
1E0053D8 DQSSAMPLEV 32 DQS SAMPLE VALUE
DQS SAMPLE VALUE
1E0053DC DLLCNT0 32 DLL STATUS 0
DLL STATUS 0
1E0053E8 CKPHCNT 32 CLOCK PHASE DETECTION RESULT
18 TEK
CLOCK PHASE DETECTION RESULT
1E0053FC TESTRPT 32 TEST AGENT STATUS
TEST AGENT STATUS
1E005600 MEMPLL0 32 MEMPLL REGISTER SETTING 0
MEMPLL REGISTER SETTING 0
1E005604 MEMPLL1 32 MEMPLL REGISTER SETTING 1
@
MEMPLL REGISTER SETTING 1
RD A
1E005608 MEMPLL2 32 MEMPLL REGISTER SETTING 2
MEMPLL REGISTER SETTING 2
R DI
1E00560C MEMPLL3 32 MEMPLL REGISTER SETTING 3
MEMPLL REGISTER SETTING 3
1E005610 MEMPLL4 32 MEMPLL REGISTER SETTING 4
MEMPLL REGISTER SETTING 4
FO ME
1E005614 MEMPLL5 32 MEMPLL REGISTER SETTING 5
MEMPLL REGISTER SETTING 5
1E005618 MEMPLL6 32 MEMPLL REGISTER SETTING 6
MEMPLL REGISTER SETTING 6
1E00561C MEMPLL7 32 MEMPLL REGISTER SETTING 7
MEMPLL REGISTER SETTING 7
1E005620 MEMPLL8 32 MEMPLL REGISTER SETTING 8
MEMPLL REGISTER SETTING 8
1E005624 MEMPLL9 32 MEMPLL REGISTER SETTING 9
PGMT7621_V.1.0_130607 Page 241 of 349
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MT7621 PROGRAMMING GUIDE
L Y
MEMPLL REGISTER SETTING 9
SE AL
1E005628 MEMPLL10 32 MEMPLL REGISTER SETTING 10
ON
MEMPLL REGISTER SETTING 10
1E00562C MEMPLL11 32 MEMPLL REGISTER SETTING 11
MEMPLL REGISTER SETTING 11
1E005630 MEMPLL12 32 MEMPLL REGISTER SETTING 12
n U TI
MEMPLL REGISTER SETTING 12
1E005634 MEMPLL13 32 MEMPLL REGISTER SETTING 13
MEMPLL REGISTER SETTING 13
t.c EN
1E005638 MEMPLL14 32 MEMPLL REGISTER SETTING 14
MEMPLL REGISTER SETTING 14
1E005640 MEMPLL_DIVIDER 32 MEMPLL DIVIDER REGISTER CONTROL
MEMPLL DIVIDER REGISTER CONTROL
1E005644 VREF 32 VREF setting
.ne ID
VREF setting
ink NF
1E005000 ACTIM0 DRAM AC TIMING SETTING 0 2256015
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TRCD TRP TFAW TWR
Type RW RW RW RW
b-l CO
Reset 0 0 1 0 0 0 1 0 0 1 0 1 0 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CL2
BL2 CL3 CL2 TWTR TRC TRAS
5
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0
18 TEK
Bit(s) Name Description
31:28 TRCD tRCD Timing setting
tRCD = (1 + TRCD) DRAMC clock cycles
Note:
DRAMC clock = 2 * DRAM clock when FDIV2 (0x7c[0]) = 1
DRAMC clock = 1 * DRAM clock when FDIV2 (0x7c[0]) = 0
@
27:24 TRP tRP Timing setting
RD A
tRP = (1 + TRP) DRAMC clock cycles
23:20 TFAW tFAW Timing setting
tFAW = (8 + TFAW) DRAMC clock cycles
R DI
Note: 0x1e8[1] is added for TFAW[4]
19:16 TWR tWR Timing setting
for LPDDR2/DDR3: write command to precharge command
TWR >= WL + tDQSS + (BL)/2 + tWR
FO ME
for LPDDR1: last data-in to precharge command
tWR = (1 + TWR) DRAMC clock cycles
15 BL2 When FDIV2 (0x7c[0]) = 1, 1 for burst length 4
When FDIV2 (0x7c[0]) = 0, set this to 0
14 CL3 CAS Latency = 3 (FPGA), reserved
13 CL25 CAS Latency = 2.5 (FPGA), reserved
12 CL2 CAS Latency Timing setting for DDR1
CAS Latency = 2
11:8 TWTR tWTR Timing setting
tWTR = (1 + TWTR) DRAMC clock cycles under LPDDR1
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MT7621 PROGRAMMING GUIDE
L Y
(WL + BL/2 + 1 + tWTR) = (3 + TWTR) DRAMC clock cycles under LPDDR2/DDR3
Note that TWTR value must be less or equal to 3 under LPDDR1,
SE AL
and less or equal to 'ha under other memories
ON
7:4 TRC tRC Timing setting
tRC = (8 + TRC) DRAMC clock cycles
Note: 0x1e8[0] is added for TRC[4]
3:0 TRAS tRAS Timing setting
n U TI
tRAS = (8 + TRAS) DRAMC clock cycles
t.c EN
1E005004 CONF1 DRAM CONFIGURATION 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEL DY CL ST STR RD AU
TES
.ne ID
FR NC KDI TCMD RV_ V_E LO TOI
TLP
EF LK S FRZ N OP NIT
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name CK CM PA
DM
FW FR2 64B
EO DH BL4 MATYPE TRRD GDI
2R W ITE
N LD S
N
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
27 TESTLP Infinite self test loop enabling for test agent 1
0: disable loop
1: enable loop
26 SELFREF Self-refresh mode enabling
18 TEK
0: disable
1: eanble self-refresh
25 DYNCLK
24 CLKDIS
22:20 TCMD Test command
TCMD[2]: RAS_
@
TCMD[1]: CAS_
RD A
TCMD[0]: WE_
19 STRV_FRZ
18 STRV_EN
R DI
17 RDLOOP
16 AUTOINIT
15 CKEON CKE function enabling
FO ME
0: disable power down function, CKE will keep high
1: enable power down function, CKE will go down when idle
13 FW2R Fast write to read turnaround time (for DDR-I only)
0: turnaround time is 0T
1: turnaround time is 1T
12 FR2W
11 CMDHLD
10 BL4 When FDIV2 (0x7c[0]) = 0, 1 for DRAM burst length 4, 0 for burst length 8
When FDIV2 (0x7c[0]) = 1, 1 for DRAM burst length 8, 0 is reserved
When FDIV2 (0x7c[0]) = 1, set 0x00[15] = 1 for burst length 4
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MT7621 PROGRAMMING GUIDE
L Y
9:8 MATYPE DRAM column address width
SE AL
00: 8 bits
01: 9 bits
ON
10: 10 bits
11: 11 bits
7:6 TRRD tRRD Timing setting
tRRD = (1 + TRRD) DRAMC clock cycles
n U TI
Note: 0x1e8[3] is added for TRRD[2]
3 PAGDIS Page mode disabling
0: disable page mode, every transaction is page-miss
1: enable page mode, page will keep opening after accessing
t.c EN
0 DM64BITEN DDR:
When FDIV2 (0x7c[0]) = 0, 1 for 64bit DRAM, 0 for 32bit DRAM
When FDIV2 (0x7c[0]) = 1, 1 for 32bit DRAM, 0 for 16bit DRAM
SDR:
0 for 64bit DRAM
.ne ID
1 for 128bit DRAM
1E005008 CONF2 DRAM CONFIGURATION 2
ink NF
0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TES
TES TES
T2 REFTHD
T2R T1
b-l CO
W
Type RW RW RW RW
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name REFCNT
Type RW
Reset 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31 TEST2W Test Agent 2 write enabling
0: Disable write cycle
1: Enable write cycle
30 TEST2R Test Agent 2 read enabling
0: Disable read cycle
@
1: Enable read cycle
RD A
29 TEST1 Test Agent 1 enabling
0: Disable test agent 1
R DI
1: Enable test agent 1
26:24 REFTHD Refresh threshold value for promoting refresh request to high-priority
0 means always high-priority
7:0 REFCNT Refresh period = (REFCNT * 16) DRAMC clock cycles
FO ME
Setting the value according to DRAM spec and DRAMC frequency
1E00500C PADCTL1 DRAM PAD CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CS1DLY CLK0DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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MT7621 PROGRAMMING GUIDE
L Y
Name
SE AL
Type
Reset
ON
Bit(s) Name Description
31:28 CS1DLY CS1 signal output delay
n U TI
The larger value means larger delay, 1 step = 20ps
27:24 CLK0DLY DRAM clock 0 signal output delay
The larger value means larger delay, 1 step = 20ps
t.c EN
1E005010 PADCTL2 DRAM PAD CONTROL 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.ne ID
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name DQM3DLY DQM2DLY DQM1DLY DQM0DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
15:12 DQM3DLY DRAM DQM[3] signal output delay
The larger value means larger delay, 1 step = 20ps
11:8 DQM2DLY DRAM DQM[2] signal output delay
The larger value means larger delay, 1 step = 20ps
7:4 DQM1DLY DRAM DQM[1] signal output delay
The larger value means larger delay, 1 step = 20ps
18 TEK
3:0 DQM0DLY DRAM DQM[0] signal output delay
The larger value means larger delay, 1 step = 20ps
1E005014 PADCTL3 DRAM PAD CONTROL 3 0000000
@
0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
R DI
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3ODLY DQS2ODLY DQS1ODLY DQS0ODLY
Type RW RW RW RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:12 DQS3ODLY DRAM DQS3 signal output delay
The larger value means larger delay, 1 step = 20ps
11:8 DQS2ODLY DRAM DQS2 signal output delay
The larger value means larger delay, 1 step = 20ps
7:4 DQS1ODLY DRAM DQS1 signal output delay
The larger value means larger delay, 1 step = 20ps
3:0 DQS0ODLY DRAM DQS0 signal output delay
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MT7621 PROGRAMMING GUIDE
L Y
The larger value means larger delay, 1 step = 20ps
SE AL
ON
1E005018 DELDLY1 DQS INPUT DELAY CHAIN SETTING 1 0000000
0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEL3DLY DEL2DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEL1DLY DEL0DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
30:24 DEL3DLY DQS3 input delay line setting
Total delay in typical case = (0.03 * DEL3DLY) ns
22:16 DEL2DLY DQS2 input delay line setting
ink NF
Total delay in typical case = (0.03 * DEL2DLY) ns
14:8 DEL1DLY DQS1 input delay line setting
Total delay in typical case = (0.03 * DEL1DLY) ns
6:0 DEL0DLY DQS0 input delay line setting
Total delay in typical case = (0.03 * DEL0DLY) ns
b-l CO
1E005020 DIFDLY1 DQS INPUT DELAY CHAIN OFFSET SETTING 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
18 TEK
Name DIF3DLY DIF2DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DIF1DLY DIF0DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
RD A
Bit(s) Name Description
30:24 DIF3DLY Offset of DQS3 input delay line setting for auto mode
R DI
total delay in typical case = (0.03 * (DIF3DLY + DLLCNT)) ns, Binary-coded
22:16 DIF2DLY Offset of DQS2 input delay line setting for auto mode
total delay in typical case = (0.03 * (DIF2DLY + DLLCNT)) ns, Binary-coded
14:8 DIF1DLY Offset of DQS1 input delay line setting for auto mode
FO ME
total delay in typical case = (0.03 * (DIF1DLY + DLLCNT)) ns, Binary-coded
6:0 DIF0DLY Offset of DQS0 input delay line setting for auto mode
total delay in typical case = (0.03 * (DIF0DLY + DLLCNT)) ns, Binary-coded
1E005028 DLLCONF DLL CONFIGURATION 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DLL MD WC
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MT7621 PROGRAMMING GUIDE
L Y
FRZ QS KS
SE AL
EL2
Type RW RW RW
ON
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
n U TI
Reset
Bit(s) Name Description
30 DLLFRZ Auto-calibration value update when refresh cycle
t.c EN
0: disable
1: enable
28 MDQS Manual mode for DQS input delay setting
0: auto setting DQS input delay by DLL
1: manual setting DQS input delay by register
.ne ID
21 WCKSEL2 Enable MIO_CK_DIV2 clocks input for MACRO_COM1 (data byte 2, 3)
0: disable
1: enable
ink NF
1E00502C TESTMODE TEST MODE CONFIGURATION 1 5500000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TESTM_PAT0
Type RW
Reset 0 1 0 1 0 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
18 TEK
Bit(s) Name Description
31:24 TESTM_PAT0 Test-pattern 0 for test mode
@
1E00503C TEST2_1 TEST AGENT 2 CONFIGURATION 1 0120000
RD A
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name TEST2_PAT0 TEST2_BASE_28to5[23:16]
Type RW RW
Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
FO ME
TEST2_BASE_28to5[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 TEST2_PAT0 Test-pattern 0 for test agent 2
23:0 TEST2_BASE_28to5 Test base address for test agent 2
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MT7621 PROGRAMMING GUIDE
L Y
1E005040 TEST2_2 TEST AGENT 2 CONFIGURATION 2 0001000
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TEST2_PAT1 TEST2_OFF_28to5[23:16]
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TEST2_OFF_28to5[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:24 TEST2_PAT1 Test-pattern 1 for test agent 2
23:0 TEST2_OFF_28to5 Test offset address for test agent 2
1E005044
.ne ID
TEST2_3 TEST AGENT 2 CONFIGURATION 3 0800000
ink NF
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name AD AD
AG
VP VR
DMPGTIM FZD TRFC
RE EFE
IV2
b-l CO
EN N
Type RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ MA DQ TES DQ
MA DQ
PE SU NU DL TA PST SIC
NU SIC
RBI PD DQ YA DQSICALSTP UD WR AL TESTCNT
DLL AL
T MO SU UT PA 2 UP
18 TEK
FRZ EN
DE PD O T D
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 ADVPREEN Advanced precharge function enable
When page is idle for DMPGTIM cycles, the page is closed automatically
@
0: Disable advanced precharge function
RD A
1: Enable advanced precharge function
30 ADVREFEN Advanced refresh function enable
R DI
Used only for DDR3, DDR3 support refresh pull-in function, please refer DDR3 spec for
detail
0: Disable advnaced precharge function
1: Enable advanced precharge function
29:24 DMPGTIM Advanced precharge function timer, use with AVDPREEN
FO ME
unit: DRAMC clock
22 AGFZDIV2 Agent half frequency mode enable
19:16 TRFC tRFC Timing setting
tRFC = (11 + TRFC[7:0]) DRAMC clock cycles
Note: 0x1e8[7:4] is added for TRFC[7:4]
15 PERBIT Per Bit HW calibration
14 DQSUPDMODE 0: Original manual mode for DQS input delay
1: Update manual DQS input delay only while MANUDQSUPD=1 and DLLFRZ
13 MANUDQSUPD On-line manual DQS input delay adjust enabling
0: disable DQS input delay adjust
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MT7621 PROGRAMMING GUIDE
L Y
1: enable DQS input delay adjust, new value will be updated during refresh period
SE AL
12 MANUDLLFRZ Manual freeze DLL counter
ON
0: DLL counter will be updated by hardware
1: DLL counter will be freezed for software reading
11 DQDLYAUTO DQ delay auto-update during calibration
0: No update
1: Update
n U TI
10:8 DQSICALSTP HW calibration step (=DQSICALSTP*2)
7 TESTAUDPAT Select audio pattern as test pattern of test agent2
0: ISI pattern
t.c EN
1: audio pattern
6 PSTWR2
5 DQSICALUPD Update DQS input delay setting to calibrated value
0: disable update
1: enable update
.ne ID
4 DQSICALEN HW calibration enable
0: disable HW calibration
1: enable HW calibration
3:0 TESTCNT Test loop number of test agent2
ink NF
loop number = 2^(TESTCNT)
1E005048 TEST2_4 TEST AGENT 2 CONFIGURATION 4 0000110
b-l CO
D
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TZQCS
Type RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name TES TES TES
TA TA T2D
UD UD TESTAUDINIT ISS TESTAUDINC
MO BITI CR
DE NV AM
Type RW RW RW RW RW
Reset 0 0 1 0 0 0 1 0 0 1 1 0 1
@
Bit(s) Name Description
RD A
31:24 TZQCS tZQCS Timing setting
tZQCS = (2 + TZQCS) DRAMC clock cycles
R DI
15 TESTAUDMODE Audio pattern: write after read enabling
0: read only
1: write after read
14 TESTAUDBITINV Audio pattern bit inversion enabling
FO ME
0: No bit inversion
1: Bit inversion
12:8 TESTAUDINIT Initial bit inverse position for audio pattern
5 TEST2DISSCRAM Test agent bypass scramble function
0: not bypass scramble function
1: bypass scramble function
4:0 TESTAUDINC Bit inverse incremental value for audio pattern
PGMT7621_V.1.0_130607 Page 249 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1E00507C DDR2CTL DDR2 CONTROL REGISTER 0000000
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RO FIX
EO
DT WLAT RO RODT TWODT
DT
E DT
n U TI
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ER WO RO
DD
FDI
t.c EN
TR2W TRTP DATLAT R2E
OT EN EN V2
N
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31 RODTE Read ODT extend 1T mode enable
0: not extend 1T
1: extend 1T
Unit: DRAM clock cycle
ink NF
30:28 WLAT Write latency = WLAT + 1/WAT + 3 when FDIV2 = 0/1
for example, write latency = 5T, set WLAT = 4/2 when FDIV2 = 0/1
Unit: DRAM clock cycle
27 FIXRODT Fix READ cycle ODT signal
b-l CO
Fix the ODT signal value (to control the PAD termination) as always enabled
0: Not fix on ODT
1: Fix on ODT
26:24 RODT Read ODT timing control for DDR2
000: For CL3
001: For CL4 and CL5
010: for CL6 and CL7
18 TEK
23 EODT
22:16 TWODT Write ODT latency enabling for DDR2
111111: for all cases
others: Reserved
15:12 TR2W Read to write interval time = (TR2W[3:0] + 3) DRAMC clock cycles
TR2W values are the same when >= 'h9
10:8 TRTP tRTP = (TRTP + 1) DRAMC clock cycle
@
In LPDDR, tRTP = BL/2. HW design guarantees, no need to set TRTP
RD A
In LPDDR2, tRTP begins (BL/2 - 2) clock cycles after the read command
In DDR3, precharge can be issued after AL + tRTP
R DI
7 EROT Read ODT timing control for DDR2
0: for CL3, CL5, CL7
1: for CL4, CL6
6:4 DATLAT Internal read data timing control
FO ME
The register and 0xE4[4] (DATLAT3)
4'b0101: CL6, CL7 for DDR2
4'b0100: CL4, CL5 for DDR2
4'b0111: CL9, CL10 for GDDR3
4'b1000: CL11, CL12 for GDDR3
3 WOEN Write ODT enabling
0: disable Write ODT
1: enable Write ODT
2 ROEN Read ODT enabling
0: disable Read ODT
1: enable Read ODT
PGMT7621_V.1.0_130607 Page 250 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1 DDR2EN DDR2 enabling
SE AL
0: disable DDR2 function
1: enable DDR2 function
ON
0 FDIV2 Half frequency mode
0: DRAMC clock cycle = DRAM clock cycle
1: DRAMC clock cycle = 2 * DRAM clock cycle
n U TI
1E005084 ZQCS ZQCS setting 0000000
t.c EN
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ZQCSAD ZQCSOP
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
15:8 ZQCSAD
7:0 ZQCSOP
b-l CO
1E005088 MRS MRS value setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OC
18 TEK
DA MRSOP
DJ
Type RW RW
Reset 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MRSBA MRSMA
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
RD A
Bit(s) Name Description
31 OCDADJ
R DI
23:16 MRSOP For LPDDR2 MRW's OP (MRS_OP[7:0])
15:13 MRSBA For non-LPDDR2 MRW bank address
12:0 MRSMA For MRR/MRW address
FO ME
1E00508C CLK1DELAY Clock 1 output delay CONTROL 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OCDPAT CLK1DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIF
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MT7621 PROGRAMMING GUIDE
L Y
OL
SE AL
EN1
Type RW
ON
Reset 0
Bit(s) Name Description
n U TI
31:24 OCDPAT
19:16 CLK1DLY DRAM clock 1 signal output delay
The larger value means larger delay, 1 step = 20ps
1 FIFOLEN1 Read FIFO length in DDRPHY
t.c EN
0: 8-level
1: 4-level
.ne ID
1E005090 IOCTL IO CONTROL 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SIO
ink NF
EN
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
b-l CO
Type
Reset
Bit(s) Name Description
31 SIOEN DQS singal output enable
0: Differentail output
1: Single-end output
18 TEK
1E005094 DQSIEN DQS INPUT RANGE FINE TUNER 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@
Name DQS3IEN DQS2IEN
RD A
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DI
Name DQS1IEN DQS0IEN
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
30:24 DQS3IEN DQS3 gating delay control
DRAMC uses the gated DQS to sample DQ.
To get the right gated DQS, the gating signal need to be adjust to match DRAM, PCB,
and others components. 1 step = 20ps.
22:16 DQS2IEN DQS2 gating delay control
14:8 DQS1IEN DQS1 gating delay control
6:0 DQS0IEN DQS0 gating delay control
PGMT7621_V.1.0_130607 Page 252 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1E0050B8 DRVCTL0 PAD DRIVING CONTROL SETTING 0 AA22AA
SE AL
22
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ DQ
SR SR
DQSDRVP DQSDRVN DSODTP DSODTN
TTB TTB
n U TI
PJ NJ
Type RW RW RW RW RW RW
Reset 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Name DQ
DQ
RTT
DQDRVP DQDRVN RTT DQODTP DQODTN
BN
BPJ
J
Type RW RW RW RW RW RW
Reset 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0
.ne ID
Bit(s) Name Description
31:28 DQSDRVP DQS P driving control, refer IBIST model for driving strength
27:24 DQSDRVN DQS N driving control, refer IBIST model for driving strength
ink NF
23 DQSRTTBPJ DQS PAD RTTBPJ port control
22:20 DSODTP DQSODT P driving control, refer IBIST model for driving strength
19 DQSRTTBNJ DQS PAD RTTBNJ port control
18:16 DSODTN DQSODT N driving control, refer IBIST model for driving strength
b-l CO
15:12 DQDRVP DQ P driving control, refer IBIST model for driving strength
11:8 DQDRVN DQ N driving control, refer IBIST model for driving strength
7 DQRTTBPJ DQ PAD RTTBPJ port control
6:4 DQODTP DQODT P driving control, refer IBIST model for driving strength
3 DQRTTBNJ DQ PAD RTTBNJ port control
18 TEK
2:0 DQODTN DQODT N driving control, refer IBIST model for driving strength
1E0050BC DRVCTL1 PAD DRIVING CONTROL SETTING 1 AA22AA
00
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@
RD A
Name CL CL
KR KR
CLKDRVP CLKDRVN CKODTP CKODTN
TTB TTB
PJ NJ
R DI
Type RW RW RW RW RW RW
Reset 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMDDRVP CMDDRVN
FO ME
Type RW RW
Reset 1 0 1 0 1 0 1 0
Bit(s) Name Description
31:28 CLKDRVP CLK P driving control, refer IBIST model for driving strength
27:24 CLKDRVN CLK N driving control, refer IBIST model for driving strength
23 CLKRTTBPJ CLK PAD RTTBPJ port control
22:20 CKODTP CLK ODT P driving control, refer IBIST model for driving strength
19 CLKRTTBNJ CLK PAD RTTBNJ port control
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MT7621 PROGRAMMING GUIDE
L Y
18:16 CKODTN CLK ODT N driving control, refer IBIST model for driving strength
SE AL
15:12 CMDDRVP CMD P driving control, refer IBIST model for driving strength
ON
11:8 CMDDRVN CMD N driving control, refer IBIST model for driving strength
n U TI
1E0050C0 DLLSEL DLL SELECTION SETTING 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
t.c EN
CM CM
CM CM
DLLCNTS AUTOKMO PD PD
DLL67SEL DLL45SEL DLL23SEL DLL01SEL PE PC
EL DE RV RV
N AL
NE PE
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CM
CM
OD
CMPDRVP CMPDRVN OD CMPODTP CMPODTN
TN
TPE
E
ink NF
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:30 DLL67SEL DLL6 and DLL7 counter selection
b-l CO
29:28 DLL45SEL DLL4 and DLL5 counter selection
27:26 DLL23SEL DLL2 and DLL3 counter selection
25:24 DLL01SEL DLL0 and DLL1 counter selection
23:22 DLLCNTSEL DLL counter selection
Refer the previous bit fields for meaning
18 TEK
21:20 AUTOKMODE OCD/ODT calibration mode selection
00: disable auto calibration
01: DRVP mode
10: DRVN mode
11: ODTP mode
19 CMPEN Compensation counter enabling
0: disable
1: enable
@
RD A
18 CMPCAL Connect to CMP pad CALP
17 CMPDRVNE Connect to CMP pad DRVNE
16 CMPDRVPE Connect to CMP pad DRVPE
R DI
15:12 CMPDRVP Connect to CMP pad DRVP[3:0]
11:8 CMPDRVN Connect to CMP pad DRVN[3:0]
7 CMODTPE CMP PAD ODTPE port
FO ME
6:4 CMPODTP CMP ODT P driving control
3 CMODTNE CMP PAD ODTNE port
2:0 CMPODTN CMP ODT N driving control
1E0050CC TDSEL0 IO OUTPUT DUTY CONTROL 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3TDSEL DQS2TDSEL
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MT7621 PROGRAMMING GUIDE
L Y
Type RW RW
Reset
SE AL
0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Name CMDTDSEL CLKTDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
27:24 DQS3TDSEL DQS3 output duty control
19:16 DQS2TDSEL DQS2 output duty control
t.c EN
11:8 CMDTDSEL Command output duty control
3:0 CLKTDSEL DRAM clock output duty control
.ne ID
1E0050D0 TDSEL1 IO OUTPUT DUTY CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1TDSEL DQS0TDSEL
ink NF
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQB3TDSEL DQB2TDSEL DQB1TDSEL DQB0TDSEL
Type RW RW RW RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 DQS1TDSEL DQS1 output duty control
19:16 DQS0TDSEL DQS0 output duty control
15:12 DQB3TDSEL DQ byte3 output duty control
18 TEK
11:8 DQB2TDSEL DQ byte2 output duty control
7:4 DQB1TDSEL DQ byte1 output duty control
3:0 DQB0TDSEL DQ byte0 output duty control
@
1E0050D8 MCKDLY MEMORY CLOCK DELAY CHAIN SETTING 0000000
RD A
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name _16
OD
BIT
PINMUX TR DISDQIEN
FUL
EN
L
Type RW RW RW RW
FO ME
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIXDQIEN
Type RW
Reset 0 0 0 0
Bit(s) Name Description
31:30 PINMUX PINMUX function
00: DDR3 (PCB4L)/LPDDR2-POP (PCB8L)
01: DDR3 (PCB6L)
10:LPDDR2 (PCB6L)
PGMT7621_V.1.0_130607 Page 255 of 349
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MT7621 PROGRAMMING GUIDE
L Y
11: Reserve
SE AL
28 _16BITFULL DRAM bus is 16-bit and FDIV2 = 0
ON
22 ODTREN Write ODT turn on when reading
0: disable
1: enable
19:16 DISDQIEN Disable DQ input enable
n U TI
0: DQ input enable when necessary
1: DQ input disable
15:12 FIXDQIEN DQ input enable fixed mode
0: DQ input enable when necessary
t.c EN
1: Keep DQ input always on
1E0050DC DQSCTL0 DQS INPUT RANGE CONTROL 0 0000000
.ne ID
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1CTL[11:4]
Type RW
ink NF
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1CTL[3:0] DQS0CTL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
23:12 DQS1CTL DQS1 input range control, 1 hot encoding
Unit: 1/2 DRAM clock cycle
11:0 DQS0CTL DQS0 input range control, 1 hot encoding
Unit: 1/2 DRAM clock cycle
18 TEK
1E0050E0 DQSCTL1 DQS INPUT RANGE CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ
@
SIE
RD A
NM DQSINCTL DQS3CTL[11:4]
OD
E
R DI
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3CTL[3:0] DQS2CTL
Type RW RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28 DQSIENMODE DQS gating mode selection
0: pulse mode
1: burst mode
26:24 DQSINCTL DQS input range control by M_CK
0/1/ .../7 = delay 0/1/ .../7T
Unit: DRAMC clock cycle
23:12 DQS3CTL DQS3 input range control, 1hot encoding
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MT7621 PROGRAMMING GUIDE
L Y
Unit: 1/2 DRAM clock cycle
SE AL
11:0 DQS2CTL DQS2 input range control, 1hot encoding
ON
Unit: 1/2 DRAM clock cycle
n U TI
1E0050E4 PADCTL4 PAD CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CLKPADCTL CMDPADCTL DQSPADCTL DQPADCTL
t.c EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DD ZQ BC DA
CK CK GD
EFI EFI DR
DQSRTT DQRTT R3E CS 4OT TLA
XO XO 3RS
.ne ID
N EN F T3
FF N T
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:28 CLKPADCTL Clock pad control
27:24 CMDPADCTL CMD pad control
23:20 DQSPADCTL DQS pad control
b-l CO
19:16 DQPADCTL DQ pad control
14:12 DQSRTT DQS termination control
10:8 DQRTT DQ termination control
7 DDR3EN enable DDR3 mode
0: Not enable DDR3
1: Enable
18 TEK
6 ZQCSEN ZQCS enable (ZQ calibration short), for DDR3 only
0: disable
1: enable
5 BC4OTF Burst chop 4 on the fly mode
0: disable
1: enable
4 DATLAT3 Read data latch timing control bit 3
@
RD A
3 CKEFIXOFF CKE always off
0: CKE hardware control
1: CKE always off
R DI
2 CKEFIXON CKE always on
0: CKE hardware control
1: CKE always on
1 GDDR3RST GDDR3/DDR3 reset pin enable
FO ME
0: reset disable
1: reset enable
1E0050E8 PADCTL5 PAD CONTROL 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3RDSEL DQS2RDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE AL
Name DQS1RDSEL DQS0RDSEL
Type RW RW
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
29:24 DQS3RDSEL DQS 3 RDSEL (duty cycle control)
Unit: 50ps
21:16 DQS2RDSEL DQS 2 RDSEL (duty cycle control)
Unit: 50ps
t.c EN
13:8 DQS1RDSEL DQS 1 RDSEL (duty cycle control)
Unit: 50ps
5:0 DQS0RDSEL DQS 0 RDSEL (duty cycle control)
Unit: 50ps
1E0050EC
.ne ID
PADCTL6 PAD CONTROL 3 0000000
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3RDSEL DQ2RDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name DQ1RDSEL DQ0RDSEL
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
29:24 DQ3RDSEL DQ Byte 3 RDSEL (duty cycle control)
18 TEK
Unit: 50ps
21:16 DQ2RDSEL DQ Byte 2 RDSEL (duty cycle control)
Unit: 50ps
13:8 DQ1RDSEL DQ Byte 1 RDSEL (duty cycle control)
Unit: 50ps
5:0 DQ0RDSEL DQ Byte 0 RDSEL (duty cycle control)
@
Unit: 50ps
RD A
R DI
1E0050F0 PHYCTL1 DDR PHY CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name DQ
PH
FIX
4B DQ
YR
MU SIE
ST
X N
Type RW RW RW
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
31 DQ4BMUX DQ 4-bit multiplex for DDR3
SE AL
0: Disable
1: Enable
ON
28 PHYRST PHY reset enable
0: disable
1: enable
n U TI
24 FIXDQSIEN DQS input enable always on
0: Hardware control
1: always on
t.c EN
1E0050F4 GDDR3CTL1 GDDR3 CONTROL 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
.ne ID
Name PH RD
_8B
YS AT
KE
YN RS
N
CM T
Type RW RW RW
ink NF
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
b-l CO
Bit(s) Name Description
28 PHYSYNCM SYNC MODE using inverted PHY_M_CK
25 RDATRST Read data counter reset
0: disable
1: enable reset
18 TEK
24 _8BKEN 8-bank device enable
0: for 4-bank device
1: for 8-bank device
1E0050F8 PADCTL7 PAD CONTROL 4 0000000
@
0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
R DI
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DR
AM LBT
FO ME
OE EST
N
Type RW RW
Reset 0 0
Bit(s) Name Description
9 DRAMOEN DRAM pin output enable
0: disable, DRAM pin will be Hi-Z
1: enable
8 LBTEST Loop-back test mode enable
0: disable
PGMT7621_V.1.0_130607 Page 259 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: enable
SE AL
ON
1E0050FC MISCTL0 MISC CONTROL 0 0000000
0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RE RE PB
AS
FP_ FA_ C_ MO
YN INT
TXP AR AR AR DE1
CE LBT
B_E B_E B_E 8V
t.c EN
N
N N N
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
.ne ID
Type
Reset
Bit(s) Name Description
ink NF
30:28 TXP tXP Timing setting
tXP = (2 + TXP) DRAMC clock cycles
26 REFP_ARB_EN Per-bank refresh blocks EMI arbitration
0: disable
1: enable
b-l CO
25 REFA_ARB_EN All-bank refresh blocks EMI arbitration
0: disable
1: enable
24 PBC_ARB_EN Block page-miss requests in EMI arbitration
0: disable
1: enable
18 TEK
20 ASYNCEN Asynchronous mode enabling between DRAMC & DDRPHY
0: synchronous mode
1: asynchronous mode
17 INTLBT IO internal loop back
0: disable
1: enable
16 MODE18V IO voltage operating condition
@
0: 1.2V
RD A
1: 1.8V
R DI
1E005100 OCDK OCD CALIBRATION CONTROL 0000000
0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WD WD WD WD WD WD WD WD
WD DR
AT AT AT AT AT AT AT AT INTREF_S
ATI VR
KE KE KE KE KE KE KE KE EL
TLV EF
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DR AU
DE TO
LS DRDELSWSEL CA AUTOKCNT
WE LD
N RV
PGMT7621_V.1.0_130607 Page 260 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Type RW RW RW RW
Reset
SE AL
0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31 WDATKEY7 Data encryption key bit 7
30 WDATKEY6 Data encryption key bit 6
n U TI
28 WDATITLV Data scramble enable
0: disable
1: enable
27 WDATKEY5 Data encryption key bit 5
t.c EN
26 WDATKEY4 Data encryption key bit 4
24 DRVREF Driving change only when refresh cycle
0: disable, change will be apply directly
1: enable, change will be apply during refresh
.ne ID
23 WDATKEY3 Data encryption key bit 3
22 WDATKEY2 Data encryption key bit 2
19 WDATKEY1 Data encryption key bit 1
18 WDATKEY0 Data encryption key bit 0
ink NF
17:16 INTREF_SEL Calibration I/O PAD VREF selection
00: 0.5*VDDQ
01: 0.6*VDDQ
10: 0.7*VDDQ
11: 0.8*VDDQ
b-l CO
15 DRDELSWEN Enable DQS input delay switching for different ranks
0: disable
1: enable
11:9 DRDELSWSEL Timing control of DQS input delay switching for different ranks
Unit: DRAMC clock
8 AUTOCALDRV OCD calibration
18 TEK
0: calibration disable
1: calibration enable
7:0 AUTOKCNT Auto calibration counter
Set timer for calibration cycle
Unit: DRAMC clock
@
RD A
1E005104 LBWDAT0 LOOP BACK DATA 0 0000000
0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name LBWDATA0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name LBWDATA0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 LBWDATA0 Loop-back test mode data 0
1E005108 LBWDAT1 LOOP BACK DATA 1 0000000
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MT7621 PROGRAMMING GUIDE
L Y
0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name LBWDATA1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name LBWDATA1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 LBWDATA1 Loop-back test mode data 1
.ne ID
1E00510C LBWDAT2 LOOP BACK DATA 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name LBWDATA2[31:16]
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LBWDATA2[15:0]
Type RW
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 LBWDATA2 Loop-back test mode data 2
18 TEK
1E005110 RKCFG RANK CONFIGURATION 0305110
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RKSIZE XRTW2W XRTW2R
Type RW RW RW
Reset 0 1 1 0 1 0 1
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name PB
MR RK
RE
XRTR2W XRTR2R S2R SW RKMODE
FE
K AP
R DI
N
Type RW RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 0 0 0 0
FO ME
Bit(s) Name Description
26:24 RKSIZE Rank address selection
000: ADDR[31]
001: ADDR[30]
010: ADDR[29]
011: ADDR[28]
100: ADDR[27]
101: ADDR[26]
110: ADDR[25]
111: ADDR[24]
19:18 XRTW2W cross rank timing W2W
Unit: DRAM controller clock
PGMT7621_V.1.0_130607 Page 262 of 349
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MT7621 PROGRAMMING GUIDE
L Y
17:16 XRTW2R cross rank timing W2R
SE AL
Unit: DRAM controller clock
ON
14:12 XRTR2W cross rank timing R2W; note that XRTR2W = 6/7 have the same setting
Unit: DRAM controller clock
10:8 XRTR2R cross rank timing R2R
Unit: DRAM controller clock
n U TI
7 PBREFEN Per-bank refresh enable for LPDDR2
0: disable
1: enable
4 MRS2RK MRS commands are sent to 2 ranks simulataneously
t.c EN
0: disable
1: enable
3 RKSWAP swap CS<->CS1
0: disable
1: enable
.ne ID
2:0 RKMODE Multi-rank mode support
Set to non-zero for multi-rank
ink NF
1E005114 CKPHDET CLOCK PHASE DETECTION SETTING 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name CK
PH
CN
TE
N
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name CKPHCHKCYC
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
23 CKPHCNTEN MEMPLL in/out clock phase detection counter enabling
@
0: disable
1: enable
RD A
15:0 CKPHCHKCYC MEMPLL in/out clock phase detection counter cycle
Unit: DRAMC clock
R DI
1E005124 DQSGCTL INPUT DQS GATING CONTROL 8000000
FO ME
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BY BY
PA PA
NE DM
SS_ SS_
WD YP
DM DM
QS AD
PA PA
G_ _RX
D_ D_
SEL SEL
CO CO
M1 M0
Type RW RW RW RW
Reset 1 0 0 0
PGMT7621_V.1.0_130607 Page 263 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE AL
Name DQSG_CO DQSG_CO
DQSG_FINE_DLY_COM1 DQSG_FINE_DLY_COM0 ARSE_DL ARSE_DL
ON
Y_COM1 Y_COM0
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31 NEWDQSG_SEL DQS gating control method
0: old
1: new
t.c EN
18 BYPASS_DMPAD_CO Bypass dummy PAD for DQS2/3 gating signal
M1 0: not bypass
1: bypass
17 BYPASS_DMPAD_CO Bypass dummy PAD for DQS0/1 gating signal
M0 0: not bypass
.ne ID
1: bypass
16 DMYPAD_RXSEL Select O/O1 pin of dummy PAD for gating signal input
0: O pin
1: O1 pin
ink NF
15:12 DQSG_FINE_DLY_CO Fine tune delay setting for DQS2/3 gating signal before dummy PAD
M1 Unit: 20ps
11:8 DQSG_FINE_DLY_CO Fine tune delay setting for DQS1/0 gating signal before dummy PAD
M0 Unit: 20ps
b-l CO
5:4 DQSG_COARSE_DLY Coarse tune delay setting for DQS2/3 gating signal before dummy PAD
_COM1 Unit: 0.25/0.5T of DRAMC clock under 2X/1X mode
1:0 DQSG_COARSE_DLY Coarse tune delay setting for DQS0/1 gating signal before dummy PAD
_COM0 Unit: 0.25/0.5T of DRAMC clock under 2X/1X mode
18 TEK
1E005130 CLKENCTL DRAM CLOCK ENABLE CONTROL 1000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CL CL
K1E K0E
N N
@
Type RW RW
RD A
Reset 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
R DI
Type
Reset
Bit(s) Name Description
FO ME
29 CLK1EN DRAM clock 1 enable
0: disable
1: enable
28 CLK0EN DRAM clock 0 enable
0: disable
1: enable
1E005140 DQSGCTL1 DQS gating delay control 1 0000000
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MT7621 PROGRAMMING GUIDE
L Y
0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name DQSIPRE1DLY DQSIPOS1DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name DQSIPRE0DLY DQSIPOS0DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
30:24 DQSIPRE1DLY DQS PRE delay control for DQS1
22:16 DQSIPOS1DLY DQS POS delay control for DQS1
14:8 DQSIPRE0DLY DQS PRE delay control for DQS0
6:0 DQSIPOS0DLY DQS POS delay control for DQS0
1E005144
.ne ID
DQSGCTL2 DQS gating delay control 2 0000000
ink NF
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQSIPRE3DLY DQSIPOS3DLY
Type RW RW
Reset
b-l CO
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQSIPRE2DLY DQSIPOS2DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
30:24 DQSIPRE3DLY DQS PRE delay control for DQS3
22:16 DQSIPOS3DLY DQS POS delay control for DQS3
14:8 DQSIPRE2DLY DQS PRE delay control for DQS2
6:0 DQSIPOS2DLY DQS POS delay control for DQS2
@
RD A
1E005168 ARBCTL0 ARBITRATION CONTROL 0 0000000
0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name MAXPENDCNT
Type RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7:0 MAXPENDCNT Maximum pending number to block the arbitration
1E0051A8 CMDDLY0 Command Delay CTL0 0000000
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MT7621 PROGRAMMING GUIDE
L Y
0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name RA3DLY RA2DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name RA1DLY RA0DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
27:24 RA3DLY RA output delay chain setting for bit3
Unit: 20ps
19:16 RA2DLY RA output delay chain setting for bit2
Unit: 20ps
.ne ID
11:8 RA1DLY RA output delay chain setting for bit1
Unit: 20ps
3:0 RA0DLY RA output delay chain setting for bit0
Unit: 20ps
ink NF
1E0051AC CMDDLY1 Command Delay CTL1 0000000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RA7DLY RA6DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RA5DLY RA4DLY
18 TEK
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 RA7DLY RA output delay chain setting for bit7
Unit: 20ps
19:16 RA6DLY RA output delay chain setting for bit6
@
RD A
Unit: 20ps
11:8 RA5DLY RA output delay chain setting for bit5
Unit: 20ps
R DI
3:0 RA4DLY RA output delay chain setting for bit4
Unit: 20ps
FO ME
1E0051B0 CMDDLY2 Command Delay CTL2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RA11DLY RA10DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RA9DLY RA8DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
27:24 RA11DLY RA output delay chain setting for bit11
Unit: 20ps
19:16 RA10DLY RA output delay chain setting for bit10
Unit: 20ps
n U TI
11:8 RA9DLY RA output delay chain setting for bit9
Unit: 20ps
3:0 RA8DLY RA output delay chain setting for bit8
t.c EN
Unit: 20ps
1E0051B4 CMDDLY3 Command Delay CTL3 0000000
.ne ID
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BA2DLY BA1DLY
Type RW RW
ink NF
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BA0DLY RA12DLY
Type RW RW
Reset 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
27:24 BA2DLY BA output delay chain setting for bit2
Unit: 20ps
19:16 BA1DLY BA output delay chain setting for bit1
Unit: 20ps
18 TEK
11:8 BA0DLY BA output delay chain setting for bit0
Unit: 20ps
3:0 RA12DLY RA output delay chain setting for bit12
Unit: 20ps
@
1E0051B8 CMDDLY4 Command Delay CTL4 0000000
RD A
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name CASDLY RASDLY
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name CS CS
MO MO
CKEDLY CSDLY
NS NE
EL N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
28:24 CASDLY CAS output delay chain setting
Unit: 20ps
20:16 RASDLY RAS output delay chain setting
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MT7621 PROGRAMMING GUIDE
L Y
Unit: 20ps
SE AL
12:8 CKEDLY CKE output delay chain setting
ON
Unit: 20ps
6 CSMONSEL DQSIEN monitor through CS select (only for 6517)
5 CSMONEN DQSIEN monitor through CS enable (only for 6517)
4:0 CSDLY CS output delay chain setting
n U TI
Unit: 20ps
t.c EN
1E0051BC CMDDLY5 Command Delay CTL5 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CS CS
XM XM
.ne ID
OTDLY RA13DLY
ON ON
SEL EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WEDLY
Type RW
Reset 0 0 0 0 0
b-l CO
Bit(s) Name Description
30 CSXMONSEL DQSIEN monitor through CS1 select (only for 6517)
29 CSXMONEN DQSIEN monitor through CS1 enable (only for 6517)
28:24 OTDLY OTD output delay chain setting
Unit: 20ps
20:16 RA13DLY RA output delay chain setting for bit13
18 TEK
Unit: 20ps
12:8 WEDLY WE output delay chain setting
Unit: 20ps
1E0051C0 DQSCAL0 DQS CAL CONTROL 0 0000000
@
RD A
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ST
R DI
BC
RA14DLY
AL
EN
Type RW RW
Reset 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ
DQ
SIE
SIE
NH
DQSIENHLMT NLL DQSIENLLMT
LM
MT
TE
EN
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
31 STBCALEN DQS strobe calibration enable
SE AL
0: disable
1: enable
ON
28:24 RA14DLY RA output delay chain setting for bit14
Unit: 20ps
15 DQSIENHLMTEN DQS strobe calibration high-limit enable
n U TI
0: disable
1: enable
14:8 DQSIENHLMT DQS strobe calibration high-limit value
7 DQSIENLLMTEN DQS strobe calibration low-limit enable
t.c EN
0: disable
1: enable
6:0 DQSIENLLMT DQS strobe calibration low-limit value
.ne ID
1E0051D8 DMMonitor Monitor parameter NA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name JMTRCNT
ink NF
Type RW
Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BU MO
SM NP JM
b-l CO
DSMONSEL ON AU TR_
EN_ SE_ EN
SW SW
Type RW RW RW RW
Reset 10b' 10b' 10b' 10b' 10b' 10b' 10b' 10b' 10b' 10b'
000 000 000 000 000 000 000 000 000 000
000 000 000 000 000 000 000 000 000 000 0 0 0
000 000 000 000 000 000 000 000 000 000
18 TEK
0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 JMTRCNT Set monitor Period for Jitter Meter
13:4 DSMONSEL DQSIEN monitor signal selection (only for 6517)
3 BUSMONEN_SW Bus monitor enable. Can't use with BUSMONEN_HW at the same time.
@
0: disable
RD A
1: enable
2 MONPAUSE_SW Pause Bus monitor Counter. Can't use with MONPAUSE_HW at the same time.
0: disable
R DI
1: enable
0 JMTR_EN Jitter meter enable
0: disable
1: enable
FO ME
1E0051DC DRAMC_PD_ PD mode parameter 0062284
CTRL 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name MIO
REF
CK DC
FRE
CT ME REFCNT_FR_CLK
RU
RL N
N
OF
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MT7621 PROGRAMMING GUIDE
L Y
F
SE AL
Type RW RW RW RW
Reset 0 0 0 0 1 1 0 0 0 1 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TXREFCNT DCMDLYREF
Type RW RW
Reset 0 0 1 0 1 0 0 0 1 0 0
n U TI
Bit(s) Name Description
26 MIOCKCTRLOFF dram clk gating parameter
t.c EN
1 : always no gating
0 : controlled by dramc
25 DCMEN DRAMC non-freerun clock gating function
0: disable
1: enable
24 REFFRERUN Using FREE-RUN CLK to count reflesh period
.ne ID
23:16 REFCNT_FR_CLK Refresh period = (REFCNT_FR_CLK) DRAMC FREE-RUN clock cycles
Setting the value according to DRAM spec and DRAMC FREE-RUN frequency
15:8 TXREFCNT tXSR
ink NF
258T/3T~258T for DDR3/LPDDR2
6:4 DCMDLYREF Number of delay cycles to wake up DCM by the refresh command, which is
counted by the FREE-RUN clock
Note that this value can't be set to 3'b000!
b-l CO
1E0051E0 LPDDR2 LPDDR2 setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name AD SEL
DD
LP WD
FA DD DD DD DD DD DD DD
DD
18 TEK
RD O1 DD AT RB
RA ST RC RO RC RC RR RC RW
EC AS R2E RG A[2:
14 OE S1 DT KE S AS AS E
EN O N O 2]
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DDRBA[1:
DDRA
0]
@
Type RW RW
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R DI
31 ADRDECEN DRAM address decode
0: by EMI
1: by DRAMC
FO ME
30 SELO1ASO Select IO O1 as output
0: select O
1: select O1
29 DDRA14 DDR mode for A[14] pin (LPDDR2 DDR command rate)
0: disable
1: enable
28 LPDDR2EN LPDDR2 enable
0: disable
1: enable
27 WDATRGO Enable register output data by DRAMC
0: disable
PGMT7621_V.1.0_130607 Page 270 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: enable
SE AL
26 FASTOE Fast IO output enable
ON
0: disable
1: enable
24 DDRCS1 DDR mode for CS1 pin (LPDDR2 DDR command rate)
0: disable
1: enable
n U TI
22 DDRODT DDR mode for ODT pin (LPDDR2 DDR command rate)
0: disable
1: enable
t.c EN
21 DDRCKE DDR mode for CKE pin (LPDDR2 DDR command rate)
0: disable
1: enable
20 DDRCS DDR mode for CS pin (LPDDR2 DDR command rate)
0: disable
.ne ID
1: enable
19 DDRRAS DDR mode for RAS pin (LPDDR2 DDR command rate)
0: disable
1: enable
ink NF
18 DDRCAS DDR mode for CAS pin (LPDDR2 DDR command rate)
0: disable
1: enable
17 DDRWE DDR mode for WE pin (LPDDR2 DDR command rate)
0: disable
b-l CO
1: enable
16:14 DDRBA DDR mode for BA[2:0] pin (LPDDR2 DDR command rate)
0: disable
1: enable
13:0 DDRA DDR mode for A[13:0] pin (LPDDR2 DDR command rate)
0: disable
1: enable
18 TEK
1E0051E4 SPCMD Special command mode 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@
Name PADRG_RDSEL ZQCSCNT
RD A
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DI
Name DQ DQ
CM SG SG TC ZQ AR PR MR MR
PP CN CN MD CE EFE EA RE WE
D TR TE EN N N EN N N
ST N
FO ME
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:28 PADRG_RDSEL PAD Ring RDSEL (only for 6517)
23:16 ZQCSCNT Every refresh number to issue ZQCS commands, only for DDR3
13 CMPPD Power down control of CMP IO
9 DQSGCNTRST DQS gating window counter Reset
8 DQSGCNTEN DQS gating window counter Enable
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MT7621 PROGRAMMING GUIDE
L Y
5 TCMDEN Test command enable
SE AL
0: disable
1: enable
ON
4 ZQCEN ZQ calibration enable
0: disable
1: enable
n U TI
3 AREFEN Auto Refresh command enable
0: disable
1: enable
2 PREAEN Precharge all command enable
t.c EN
0: disable
1: enable
1 MRREN Mode register read command enable
0: disable
1: enable
.ne ID
0 MRWEN Mode register write command enable
0: disable
1: enable
ink NF
1E0051E8 ACTIM1 DRAM AC TIMING SETTING 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b-l CO
Name TRPAB REFRCNT
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TR TFA TR
RD W_ C_
TRFCPB TRFC_BIT7_4
_BI BIT BIT
18 TEK
T2 4 4
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
25:24 TRPAB All-bank precharge timing for LPDDR2
tRPAB = TRP + TRPAB
@
23:16 REFRCNT Every refresh number to issue MRR commands for refresh rates, only for
RD A
LPDDR2
15:8 TRFCPB tRFCPB Timing setting
R DI
tRFCPB = (11 + TRFCPB[7:0]) DRAMC clock cycles
7:4 TRFC_BIT7_4 tRFC Timing setting for bit 7 ~ 4
3 TRRD_BIT2 tRRD Timing setting for bit 2
1 TFAW_BIT4 tFAW Timing setting for bit 4
FO ME
0 TRC_BIT4 tRC Timing setting for bit 4
1E0051EC PERFCTL0 PERFORMANCE CONTROL 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DIS
DM
OE
DIS
PGMT7621_V.1.0_130607 Page 272 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Type RW
Reset
SE AL
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Name RW RW RW RW
DU
CS2 AL
AG LLA HP OF
RA RWOFOWNUM SC
EE TE RIE OE
NK HE
N N N N
n U TI
N
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
16 DISDMOEDIS For power saving, the self-refresh may disable the IO output enable
0: enable the power saving function
1: disable the power saving function
12 CS2RANK CS0 is also applied to CS1
.ne ID
0: disable
1: enable
10 RWAGEEN Support EMI read/write aging tag
0: Not support
ink NF
1: Support
9 RWLLATEN Support EMI read/write low-latency
0: Not support
1: Support
8 RWHPRIEN Support EMI read/write high-priority
b-l CO
0: Not support
1: Support
7:5 RWOFOWNUM Coniinous write transactions allowed
4 RWOFOEN Enable read/write out of order control
0: disable
1: enable
18 TEK
0 DUALSCHEN Enable dual schedulers, only effective under FDIV2 = 1
0: disable
1: enable
1E0051F0 AC_DERATIN AC TIME DERATING CONTROL 0000000
@
G 0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TRPAB_D
TRRD_DERATE TRP_DERATE TRAS_DERATE
ERATE
R DI
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name AC
FO ME
DE
TRC_DERATE TRCD_DERATE RA
TEE
N
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:28 TRRD_DERATE tRRD de-rate timing setting
tRRD = (1 + TRRD_DERATE) DRAMC clock cycles
25:24 TRPAB_DERATE All-bank precharge de-rate timing for LPDDR2
PGMT7621_V.1.0_130607 Page 273 of 349
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MT7621 PROGRAMMING GUIDE
L Y
tRPAB = TRP_DERATE + TRPAB_DERATE
SE AL
23:20 TRP_DERATE tRP de-rate timing setting
ON
tRP = (1 + TRP_DERATE) DRAMC clock cycles
19:16 TRAS_DERATE tRAS de-rate timing setting
tRAS = (8 + TRAS_DERATE) DRAMC clock cycles
12:8 TRC_DERATE tRC de-rate timing setting
n U TI
tRC = (8 + TRC_DERATE) DRAMC clock cycles
7:4 TRCD_DERATE tRCD de-rate timing setting
tRCD = (1 + TRCD_DERATE) DRAMC clock cycles
t.c EN
0 ACDERATEEN Enable LPDDR2 AC timing de-rating control, effective when REFRESH_RATE >=
6
0: disable
1: enable
.ne ID
1E0051F4 RRRATE_CTL REFRESH RATE CONTROL 0002010
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ink NF
Name RR_BIT2_SEL
Type RW
Reset 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RR_BIT1_SEL RR_BIT0_SEL
b-l CO
Type RW RW
Reset 0 0 0 0 1 0 0 0 0 0
Bit(s) Name Description
20:16 RR_BIT2_SEL Refresh rate data bit 2 selection from 32-bit input read data
00000: select bit 0
18 TEK
00001: select bit 1
00010: select bit 2
.
11111: select bit 31
12:8 RR_BIT1_SEL Refresh rate data bit 1 selection from 32-bit input read data
00000: select bit 0
00001: select bit 1
00010: select bit 2
@
.
RD A
11111: select bit 31
4:0 RR_BIT0_SEL Refresh rate data bit 0 selection from 32-bit input read data
00000: select bit 0
R DI
00001: select bit 1
00010: select bit 2
.
11111: select bit 31
FO ME
1E0051F8 WPATCMP_D WRITE PATTERN COMPARE SETTING 0000000
AT 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WPATCMP[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WPATCMP[15:0]
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MT7621 PROGRAMMING GUIDE
L Y
Type RW
Reset
SE AL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
31:0 WPATCMP Write data pattern to be compared for interrupting write commands
n U TI
1E0051FC WPATCMP_C WRITE PATTERN COMPARE CONTROL 0000000
TL 0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WP
AT_
WPAT_BL
ST
KCYC
CL
.ne ID
R
Type RW RW
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WPAT_INVEN WPAT_CMPEN
ink NF
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
20 WPAT_STCLR Clear the write pattern hit counter WPAT_HIT_CNT (REG.3FC[7:0])
b-l CO
17:16 WPAT_BLKCYC Block write command cycles during interruption
0/1/2/3: 1/2/3/4T
15:8 WPAT_INVEN Inversion control for 8 sets of 32-bit write compare data WPATCMP
7:0 WPAT_CMPEN Enable write data compare sequence
bit 0: PAT0, PAT1, PAT2, PAT3, PAT4, PAT5, PAT6, PAT7
bit 1: PAT7, PAT0, PAT1, PAT2, PAT3, PAT4, PAT5, PAT6
18 TEK
bit 2: PAT6, PAT7, PAT0, PAT1, PAT2, PAT3, PAT4, PAT5
.
bit7: PAT1, PAT2, PAT3, PAT4, PAT5, PAT6, PAT7, PAT0
1E005200 DQODLY1 DQ output DELAY1 CHAIN setting 0000000
@
0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ7DLY DQ6DLY DQ5DLY DQ4DLY
R DI
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ3DLY DQ2DLY DQ1DLY DQ0DLY
Type RW RW RW RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:28 DQ7DLY DQ output delay chain setting for bit7
Unit: 20ps
27:24 DQ6DLY DQ output delay chain setting for bit6
Unit: 20ps
23:20 DQ5DLY DQ output delay chain setting for bit5
Unit: 20ps
PGMT7621_V.1.0_130607 Page 275 of 349
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MT7621 PROGRAMMING GUIDE
L Y
19:16 DQ4DLY DQ output delay chain setting for bit4
SE AL
Unit: 20ps
ON
15:12 DQ3DLY DQ output delay chain setting for bit3
Unit: 20ps
11:8 DQ2DLY DQ output delay chain setting for bit2
Unit: 20ps
n U TI
7:4 DQ1DLY DQ output delay chain setting for bit1
Unit: 20ps
3:0 DQ0DLY DQ output delay chain setting for bit0
t.c EN
Unit: 20ps
1E005204 DQODLY2 DQ output DELAY2 CHAIN setting 0000000
0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ15DLY DQ14DLY DQ13DLY DQ12DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ11DLY DQ10DLY DQ9DLY DQ8DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
31:28 DQ15DLY DQ output delay chain setting for bit15
Unit: 20ps
27:24 DQ14DLY DQ output delay chain setting for bit14
Unit: 20ps
18 TEK
23:20 DQ13DLY DQ output delay chain setting for bit13
Unit: 20ps
19:16 DQ12DLY DQ output delay chain setting for bit12
Unit: 20ps
15:12 DQ11DLY DQ output delay chain setting for bit11
Unit: 20ps
11:8 DQ10DLY DQ output delay chain setting for bit10
@
Unit: 20ps
RD A
7:4 DQ9DLY DQ output delay chain setting for bit9
Unit: 20ps
R DI
3:0 DQ8DLY DQ output delay chain setting for bit8
Unit: 20ps
FO ME
1E005208 DQODLY3 DQ output DELAY3 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ23DLY DQ22DLY DQ21DLY DQ20DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ19DLY DQ18DLY DQ17DLY DQ16DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31:28 DQ23DLY DQ output delay chain setting for bit23
Unit: 20ps
27:24 DQ22DLY DQ output delay chain setting for bit22
Unit: 20ps
n U TI
23:20 DQ21DLY DQ output delay chain setting for bit21
Unit: 20ps
19:16 DQ20DLY DQ output delay chain setting for bit20
t.c EN
Unit: 20ps
15:12 DQ19DLY DQ output delay chain setting for bit19
Unit: 20ps
11:8 DQ18DLY DQ output delay chain setting for bit18
Unit: 20ps
.ne ID
7:4 DQ17DLY DQ output delay chain setting for bit17
Unit: 20ps
3:0 DQ16DLY DQ output delay chain setting for bit16
Unit: 20ps
ink NF
1E00520C DQODLY4 DQ output DELAY4 CHAIN setting 0000000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ31DLY DQ30DLY DQ29DLY DQ28DLY
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ27DLY DQ26DLY DQ25DLY DQ24DLY
18 TEK
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:28 DQ31DLY DQ output delay chain setting for bit31
Unit: 20ps
@
27:24 DQ30DLY DQ output delay chain setting for bit30
RD A
Unit: 20ps
23:20 DQ29DLY DQ output delay chain setting for bit29
Unit: 20ps
R DI
19:16 DQ28DLY DQ output delay chain setting for bit28
Unit: 20ps
15:12 DQ27DLY DQ output delay chain setting for bit27
FO ME
Unit: 20ps
11:8 DQ26DLY DQ output delay chain setting for bit26
Unit: 20ps
7:4 DQ25DLY DQ output delay chain setting for bit25
Unit: 20ps
3:0 DQ24DLY DQ output delay chain setting for bit24
Unit: 20ps
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MT7621 PROGRAMMING GUIDE
L Y
1E005210 DQIDLY1 DQ input DELAY1 CHAIN setting 0000000
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3DEL DQ2DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ1DEL DQ0DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
27:24 DQ3DEL DQ input delay chain setting for bit3
Unit: 20ps
.ne ID
19:16 DQ2DEL DQ input delay chain setting for bit2
Unit: 20ps
11:8 DQ1DEL DQ input delay chain setting for bit1
Unit: 20ps
ink NF
3:0 DQ0DEL DQ input delay chain setting for bit0
Unit: 20ps
b-l CO
1E005214 DQIDLY2 DQ input DELAY2 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ7DEL DQ6DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ5DEL DQ4DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 DQ7DEL DQ input delay chain setting for bit7
@
Unit: 20ps
RD A
19:16 DQ6DEL DQ input delay chain setting for bit6
Unit: 20ps
R DI
11:8 DQ5DEL DQ input delay chain setting for bit5
Unit: 20ps
3:0 DQ4DEL DQ input delay chain setting for bit4
Unit: 20ps
FO ME
1E005218 DQIDLY3 DQ input DELAY3 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ11DEL DQ10DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ9DEL DQ8DEL
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MT7621 PROGRAMMING GUIDE
L Y
Type RW RW
Reset
SE AL
0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
27:24 DQ11DEL DQ input delay chain setting for bit11
Unit: 20ps
n U TI
19:16 DQ10DEL DQ input delay chain setting for bit10
Unit: 20ps
11:8 DQ9DEL DQ input delay chain setting for bit9
Unit: 20ps
t.c EN
3:0 DQ8DEL DQ input delay chain setting for bit8
Unit: 20ps
.ne ID
1E00521C DQIDLY4 DQ input DELAY4 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ink NF
Name DQ15DEL DQ14DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ13DEL DQ12DEL
Type RW RW
b-l CO
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 DQ15DEL DQ input delay chain setting for bit15
Unit: 20ps
19:16 DQ14DEL DQ input delay chain setting for bit14
18 TEK
Unit: 20ps
11:8 DQ13DEL DQ input delay chain setting for bit13
Unit: 20ps
3:0 DQ12DEL DQ input delay chain setting for bit12
Unit: 20ps
@
RD A
1E005220 DQIDLY5 DQ input DELAY5 CHAIN setting 0000000
0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ19DEL DQ18DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ17DEL DQ16DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
27:24 DQ19DEL DQ input delay chain setting for bit19
Unit: 20ps
19:16 DQ18DEL DQ input delay chain setting for bit18
Unit: 20ps
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MT7621 PROGRAMMING GUIDE
L Y
11:8 DQ17DEL DQ input delay chain setting for bit17
SE AL
Unit: 20ps
ON
3:0 DQ16DEL DQ input delay chain setting for bit16
Unit: 20ps
n U TI
1E005224 DQIDLY6 DQ input DELAY6 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name DQ23DEL DQ22DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ21DEL DQ20DEL
.ne ID
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
27:24 DQ23DEL DQ input delay chain setting for bit23
Unit: 20ps
19:16 DQ22DEL DQ input delay chain setting for bit22
Unit: 20ps
11:8 DQ21DEL DQ input delay chain setting for bit21
b-l CO
Unit: 20ps
3:0 DQ20DEL DQ input delay chain setting for bit20
Unit: 20ps
18 TEK
1E005228 DQIDLY7 DQ input DELAY7 CHAIN setting 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ27DEL DQ26DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name
RD A
DQ25DEL DQ24DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
27:24 DQ27DEL DQ input delay chain setting for bit27
Unit: 20ps
FO ME
19:16 DQ26DEL DQ input delay chain setting for bit26
Unit: 20ps
11:8 DQ25DEL DQ input delay chain setting for bit25
Unit: 20ps
3:0 DQ24DEL DQ input delay chain setting for bit24
Unit: 20ps
1E00522C DQIDLY8 DQ input DELAY8 CHAIN setting 0000000
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MT7621 PROGRAMMING GUIDE
L Y
0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name DQ31DEL DQ30DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name DQ29DEL DQ28DEL
Type RW RW
Reset 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
27:24 DQ31DEL DQ input delay chain setting for bit31
Unit: 20ps
19:16 DQ30DEL DQ input delay chain setting for bit30
Unit: 20ps
.ne ID
11:8 DQ29DEL DQ input delay chain setting for bit29
Unit: 20ps
3:0 DQ28DEL DQ input delay chain setting for bit28
Unit: 20ps
ink NF
1E005280 R2R_page_hit R2R_page_hit_counter 0000000
_counter 0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2R_page_hit_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2R_page_hit_counter[15:0]
18 TEK
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 R2R_page_hit_counter R2R_page_hit_counter
@
RD A
1E005284 R2R_page_mi R2R_page_miss_counter 0000000
ss_counter 0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2R_page_miss_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2R_page_miss_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 R2R_page_miss_count R2R_page_miss_counter
er
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MT7621 PROGRAMMING GUIDE
L Y
1E005288 R2R_interban R2R_interbank_counter 0000000
SE AL
k_counter 0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2R_interbank_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2R_interbank_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:0 R2R_interbank_counte R2R_interbank_counter
r
1E00528C
.ne ID
R2W_page_hi
t_counter
R2W_page_hit_counter 0000000
0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2W_page_hit_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name R2W_page_hit_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 R2W_page_hit_counte R2W_page_hit_counter
18 TEK
1E005290 R2W_page_mi R2W_page_miss_counter 0000000
ss_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@
Name
RD A
R2W_page_miss_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R2W_page_miss_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31:0 R2W_page_miss_coun R2W_page_miss_counter
ter
1E005294 R2W_interban R2W_interbank_counter 0000000
k_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name R2W_interbank_counter[31:16]
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MT7621 PROGRAMMING GUIDE
L Y
Type RO
Reset
SE AL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Name R2W_interbank_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:0 R2W_interbank_counte R2W_interbank_counter
r
t.c EN
1E005298 W2R_page_hi W2R_page_hit_counter 0000000
t_counter 0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2R_page_hit_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name W2R_page_hit_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
b-l CO
31:0 W2R_page_hit_counte W2R_page_hit_counter
r
1E00529C W2R_page_mi W2R_page_miss_counter 0000000
18 TEK
ss_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2R_page_miss_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2R_page_miss_counter[15:0]
@
Type RO
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
R DI
31:0 W2R_page_miss_coun W2R_page_miss_counter
ter
FO ME
1E0052A0 W2R_interban W2R_interbank_counter 0000000
k_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2R_interbank_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2R_interbank_counter[15:0]
Type RO
PGMT7621_V.1.0_130607 Page 283 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
ON
Bit(s) Name Description
31:0 W2R_interbank_counte W2R_interbank_counter
r
n U TI
1E0052A4 W2W_page_hi W2W_page_hit_counter 0000000
t_counter 0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2W_page_hit_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.ne ID
Name W2W_page_hit_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:0 W2W_page_hit_counte W2W_page_hit_counter
r
b-l CO
1E0052A8 W2W_page_m W2W_page_miss_counter 0000000
iss_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name W2W_page_miss_counter[31:16]
Type RO
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2W_page_miss_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
31:0 W2W_page_miss_cou W2W_page_miss_counter
RD A
nter
R DI
1E0052AC W2W_interba W2W_interbank_counter 0000000
nk_counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name W2W_interbank_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W2W_interbank_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 W2W_interbank_count W2W_interbank_counter
er
PGMT7621_V.1.0_130607 Page 284 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E0052B0 dramc_idle_c dramc_idle_counter 0000000
ounter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name dramc_idle_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Name dramc_idle_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:0 dramc_idle_counter dramc_idle_counter
ink NF
1E0052B4 freerun_26m_ freerun_26m_counter 0000000
counter 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name freerun_26m_counter[31:16]
Type RO
b-l CO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name freerun_26m_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:0 freerun_26m_counter freerun_26m_counter
1E0052B8 refresh_pop_ refresh_pop_counter 0000000
counter 0
@
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD A
Name refresh_pop_counter[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name refresh_pop_counter[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FO ME
Bit(s) Name Description
31:0 refresh_pop_counter refresh_pop_counter
1E0052BC JMETER_ST Jitter Meter Status 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name JM ONES_CNT
PGMT7621_V.1.0_130607 Page 285 of 349
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MT7621 PROGRAMMING GUIDE
L Y
TR_
SE AL
DO
NE
ON
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ZEROS_CNT
n U TI
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
t.c EN
31 JMTR_DONE Jitter meter result is updated.
0: not ready
1: update result.
30:16 ONES_CNT ones counter result
14:0 ZEROS_CNT zeros counter result
1E0052C0
.ne ID
DQ_CAL_MA DQ INPUT CALIBRATION per bit 3-0 0000000
ink NF
X_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ0_3_DLY_MAX DQ0_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ0_1_DLY_MAX DQ0_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
18 TEK
31:24 DQ0_3_DLY_MAX DQ bit3 input maximum delay
23:16 DQ0_2_DLY_MAX DQ bit2 input maximum delay
15:8 DQ0_1_DLY_MAX DQ bit1 input maximum delay
7:0 DQ0_0_DLY_MAX DQ bit0 input maximum delay
@
RD A
1E0052C4 DQ_CAL_MA DQ INPUT CALIBRATION per bit 7-4 0000000
X_1 0
R DI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ0_7_DLY_MAX DQ0_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name DQ0_5_DLY_MAX DQ0_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ0_7_DLY_MAX DQ bit7 input maximum delay
23:16 DQ0_6_DLY_MAX DQ bit6 input maximum delay
15:8 DQ0_5_DLY_MAX DQ bit5 input maximum delay
7:0 DQ0_4_DLY_MAX DQ bit4 input maximum delay
PGMT7621_V.1.0_130607 Page 286 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E0052C8 DQ_CAL_MA DQ INPUT CALIBRATION per bit 11-8 0000000
X_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name DQ1_3_DLY_MAX DQ1_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
t.c EN
Name DQ1_1_DLY_MAX DQ1_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
.ne ID
31:24 DQ1_3_DLY_MAX DQ bit11 input maximum delay
23:16 DQ1_2_DLY_MAX DQ bit10 input maximum delay
15:8 DQ1_1_DLY_MAX DQ bit9 input maximum delay
7:0 DQ1_0_DLY_MAX DQ bit8 input maximum delay
ink NF
1E0052CC DQ_CAL_MA DQ INPUT CALIBRATION per bit 15-12 0000000
X_3 0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ1_7_DLY_MAX DQ1_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ1_5_DLY_MAX DQ1_4_DLY_MAX
18 TEK
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ1_7_DLY_MAX DQ bit15 input maximum delay
23:16 DQ1_6_DLY_MAX DQ bit14 input maximum delay
@
15:8 DQ1_5_DLY_MAX DQ bit13 input maximum delay
RD A
7:0 DQ1_4_DLY_MAX DQ bit12 input maximum delay
R DI
1E0052D0 DQ_CAL_MA DQ INPUT CALIBRATION per bit 19-16 0000000
X_4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FO ME
Name DQ2_3_DLY_MAX DQ2_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ2_1_DLY_MAX DQ2_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ2_3_DLY_MAX DQ bit19 input maximum delay
PGMT7621_V.1.0_130607 Page 287 of 349
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MT7621 PROGRAMMING GUIDE
L Y
23:16 DQ2_2_DLY_MAX DQ bit18 input maximum delay
SE AL
15:8 DQ2_1_DLY_MAX DQ bit17 input maximum delay
ON
7:0 DQ2_0_DLY_MAX DQ bit16 input maximum delay
n U TI
1E0052D4 DQ_CAL_MA DQ INPUT CALIBRATION per bit 23-20 0000000
X_5 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
t.c EN
DQ2_7_DLY_MAX DQ2_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ2_5_DLY_MAX DQ2_4_DLY_MAX
Type RO RO
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQ2_7_DLY_MAX DQ bit23 input maximum delay
ink NF
23:16 DQ2_6_DLY_MAX DQ bit22 input maximum delay
15:8 DQ2_5_DLY_MAX DQ bit21 input maximum delay
7:0 DQ2_4_DLY_MAX DQ bit20 input maximum delay
b-l CO
1E0052D8 DQ_CAL_MA DQ INPUT CALIBRATION per bit 27-34 0000000
X_6 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3_3_DLY_MAX DQ3_2_DLY_MAX
18 TEK
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ3_1_DLY_MAX DQ3_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
RD A
31:24 DQ3_3_DLY_MAX DQ bit27 input maximum delay
23:16 DQ3_2_DLY_MAX DQ bit26 input maximum delay
R DI
15:8 DQ3_1_DLY_MAX DQ bit25 input maximum delay
7:0 DQ3_0_DLY_MAX DQ bit24 input maximum delay
FO ME
1E0052DC DQ_CAL_MA DQ INPUT CALIBRATION per bit 31-28 0000000
X_7 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3_7_DLY_MAX DQ3_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ3_5_DLY_MAX DQ3_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGMT7621_V.1.0_130607 Page 288 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31:24 DQ3_7_DLY_MAX DQ bit31 input maximum delay
23:16 DQ3_6_DLY_MAX DQ bit30 input maximum delay
15:8 DQ3_5_DLY_MAX DQ bit29 input maximum delay
n U TI
7:0 DQ3_4_DLY_MAX DQ bit28 input maximum delay
t.c EN
1E0052E0 DQS_CAL_MI DQS INPUT CALIBRATION per bit 3-0 0000000
N_0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS0_3_DLY_MIN DQS0_2_DLY_MIN
Type RO RO
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS0_1_DLY_MIN DQS0_0_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:24 DQS0_3_DLY_MIN DQS bit3 input minimum delay
23:16 DQS0_2_DLY_MIN DQS bit2 input minimum delay
b-l CO
15:8 DQS0_1_DLY_MIN DQS bit1 input minimum delay
7:0 DQS0_0_DLY_MIN DQS bit0 input minimum delay
1E0052E4 DQS_CAL_MI DQS INPUT CALIBRATION per bit 7-4 0000000
18 TEK
N_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS0_7_DLY_MIN DQS0_6_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS0_5_DLY_MIN DQS0_4_DLY_MIN
@
Type RO RO
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:24 DQS0_7_DLY_MIN DQS bit7 input minimum delay
23:16 DQS0_6_DLY_MIN DQS bit6 input minimum delay
15:8 DQS0_5_DLY_MIN DQS bit5 input minimum delay
FO ME
7:0 DQS0_4_DLY_MIN DQS bit4 input minimum delay
1E0052E8 DQS_CAL_MI DQS INPUT CALIBRATION per bit 11-8 0000000
N_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1_3_DLY_MIN DQS1_2_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE AL
Name DQS1_1_DLY_MIN DQS1_0_DLY_MIN
Type RO RO
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
31:24 DQS1_3_DLY_MIN DQS bit11 input minimum delay
23:16 DQS1_2_DLY_MIN DQS bit10 input minimum delay
15:8 DQS1_1_DLY_MIN DQS bit9 input minimum delay
7:0 DQS1_0_DLY_MIN DQS bit8 input minimum delay
t.c EN
1E0052EC DQS_CAL_MI DQS INPUT CALIBRATION per bit 15-12 0000000
N_3 0
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1_7_DLY_MIN DQS1_6_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_5_DLY_MIN DQS1_4_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
31:24 DQS1_7_DLY_MIN DQS bit15 input minimum delay
23:16 DQS1_6_DLY_MIN DQS bit14 input minimum delay
15:8 DQS1_5_DLY_MIN DQS bit13 input minimum delay
7:0 DQS1_4_DLY_MIN DQS bit12 input minimum delay
18 TEK
1E0052F0 DQS_CAL_MI DQS INPUT CALIBRATION per bit 19-16 0000000
N_4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS2_3_DLY_MIN DQS2_2_DLY_MIN
@
Type RO RO
RD A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS2_1_DLY_MIN DQS2_0_DLY_MIN
R DI
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
FO ME
31:24 DQS2_3_DLY_MIN DQS bit19 input minimum delay
23:16 DQS2_2_DLY_MIN DQS bit18 input minimum delay
15:8 DQS2_1_DLY_MIN DQS bit17 input minimum delay
7:0 DQS2_0_DLY_MIN DQS bit16 input minimum delay
1E0052F4 DQS_CAL_MI DQS INPUT CALIBRATION per bit 23-20 0000000
N_5 0
PGMT7621_V.1.0_130607 Page 290 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SE AL
Name DQS2_7_DLY_MIN DQS2_6_DLY_MIN
Type RO RO
ON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS2_5_DLY_MIN DQS2_4_DLY_MIN
Type RO RO
n U TI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
t.c EN
31:24 DQS2_7_DLY_MIN DQS bit23 input minimum delay
23:16 DQS2_6_DLY_MIN DQS bit22 input minimum delay
15:8 DQS2_5_DLY_MIN DQS bit21 input minimum delay
7:0 DQS2_4_DLY_MIN DQS bit20 input minimum delay
.ne ID
1E0052F8 DQS_CAL_MI DQS INPUT CALIBRATION per bit 27-34 0000000
N_6 0
ink NF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_3_DLY_MIN DQS3_2_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b-l CO
Name DQS3_1_DLY_MIN DQS3_0_DLY_MIN
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS3_3_DLY_MIN DQS bit27 input minimum delay
18 TEK
23:16 DQS3_2_DLY_MIN DQS bit26 input minimum delay
15:8 DQS3_1_DLY_MIN DQS bit25 input minimum delay
7:0 DQS3_0_DLY_MIN DQS bit24 input minimum delay
1E0052FC DQS_CAL_MI DQS INPUT CALIBRATION per bit 31-28 0000000
@
RD A
N_7 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_7_DLY_MIN DQS3_6_DLY_MIN
R DI
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3_5_DLY_MIN DQS3_4_DLY_MIN
FO ME
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS3_7_DLY_MIN DQS bit31 input minimum delay
23:16 DQS3_6_DLY_MIN DQS bit30 input minimum delay
15:8 DQS3_5_DLY_MIN DQS bit29 input minimum delay
7:0 DQS3_4_DLY_MIN DQS bit28 input minimum delay
PGMT7621_V.1.0_130607 Page 291 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1E005300 DQS_CAL_M DQS INPUT CALIBRATION per bit 3-0 0000000
SE AL
AX_0 0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS0_3_DLY_MAX DQS0_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS0_1_DLY_MAX DQS0_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:24 DQS0_3_DLY_MAX DQS bit3 input maximum delay
23:16 DQS0_2_DLY_MAX DQS bit2 input maximum delay
.ne ID
15:8 DQS0_1_DLY_MAX DQS bit1 input maximum delay
7:0 DQS0_0_DLY_MAX
ink NF DQS bit0 input maximum delay
1E005304 DQS_CAL_M DQS INPUT CALIBRATION per bit 7-4 0000000
AX_1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS0_7_DLY_MAX DQS0_6_DLY_MAX
b-l CO
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS0_5_DLY_MAX DQS0_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit(s) Name Description
31:24 DQS0_7_DLY_MAX DQS bit7 input maximum delay
23:16 DQS0_6_DLY_MAX DQS bit6 input maximum delay
15:8 DQS0_5_DLY_MAX DQS bit5 input maximum delay
7:0 DQS0_4_DLY_MAX DQS bit4 input maximum delay
@
RD A
1E005308 DQS_CAL_M DQS INPUT CALIBRATION per bit 11-8 0000000
R DI
AX_2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1_3_DLY_MAX DQS1_2_DLY_MAX
Type RO RO
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_1_DLY_MAX DQS1_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS1_3_DLY_MAX DQS bit11 input maximum delay
23:16 DQS1_2_DLY_MAX DQS bit10 input maximum delay
15:8 DQS1_1_DLY_MAX DQS bit9 input maximum delay
PGMT7621_V.1.0_130607 Page 292 of 349
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MT7621 PROGRAMMING GUIDE
L Y
7:0 DQS1_0_DLY_MAX DQS bit8 input maximum delay
SE AL
ON
1E00530C DQS_CAL_M DQS INPUT CALIBRATION per bit 15-12 0000000
AX_3 0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS1_7_DLY_MAX DQS1_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_5_DLY_MAX DQS1_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
31:24 DQS1_7_DLY_MAX DQS bit15 input maximum delay
23:16 DQS1_6_DLY_MAX DQS bit14 input maximum delay
15:8 DQS1_5_DLY_MAX DQS bit13 input maximum delay
ink NF
7:0 DQS1_4_DLY_MAX DQS bit12 input maximum delay
1E005310 DQS_CAL_M DQS INPUT CALIBRATION per bit 19-16 0000000
b-l CO
AX_4 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS2_3_DLY_MAX DQS2_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name DQS2_1_DLY_MAX DQS2_0_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 DQS2_3_DLY_MAX DQS bit19 input maximum delay
@
23:16 DQS2_2_DLY_MAX DQS bit18 input maximum delay
RD A
15:8 DQS2_1_DLY_MAX DQS bit17 input maximum delay
7:0 DQS2_0_DLY_MAX DQS bit16 input maximum delay
R DI
1E005314 DQS_CAL_M DQS INPUT CALIBRATION per bit 23-20 0000000
AX_5 0
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS2_7_DLY_MAX DQS2_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS2_5_DLY_MAX DQS2_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
PGMT7621_V.1.0_130607 Page 293 of 349
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MT7621 PROGRAMMING GUIDE
L Y
31:24 DQS2_7_DLY_MAX DQS bit23 input maximum delay
SE AL
23:16 DQS2_6_DLY_MAX DQS bit22 input maximum delay
ON
15:8 DQS2_5_DLY_MAX DQS bit21 input maximum delay
7:0 DQS2_4_DLY_MAX DQS bit20 input maximum delay
n U TI
1E005318 DQS_CAL_M DQS INPUT CALIBRATION per bit 27-34 0000000
AX_6 0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_3_DLY_MAX DQS3_2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3_1_DLY_MAX DQS3_0_DLY_MAX
.ne ID
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
31:24 DQS3_3_DLY_MAX DQS bit27 input maximum delay
23:16 DQS3_2_DLY_MAX DQS bit26 input maximum delay
15:8 DQS3_1_DLY_MAX DQS bit25 input maximum delay
7:0 DQS3_0_DLY_MAX DQS bit24 input maximum delay
b-l CO
1E00531C DQS_CAL_M DQS INPUT CALIBRATION per bit 31-28 0000000
AX_7 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
18 TEK
Name DQS3_7_DLY_MAX DQS3_6_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS3_5_DLY_MAX DQS3_4_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
RD A
Bit(s) Name Description
31:24 DQS3_7_DLY_MAX DQS bit31 input maximum delay
R DI
23:16 DQS3_6_DLY_MAX DQS bit30 input maximum delay
15:8 DQS3_5_DLY_MAX DQS bit29 input maximum delay
7:0 DQS3_4_DLY_MAX DQS bit28 input maximum delay
FO ME
1E005350 DQICAL0 DQS INPUT CALIBRATION 0 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQ3_DLY_MAX DQ2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQ1_DLY_MAX DQ0_DLY_MAX
Type RO RO
PGMT7621_V.1.0_130607 Page 294 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
ON
Bit(s) Name Description
30:24 DQ3_DLY_MAX DQ byte3 input maximum delay
22:16 DQ2_DLY_MAX DQ byte2 input maximum delay
14:8 DQ1_DLY_MAX DQ byte1 input maximum delay
n U TI
6:0 DQ0_DLY_MAX DQ byte0 input maximum delay
t.c EN
1E005354 DQICAL1 DQS INPUT CALIBRATION 1 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_DLY_MIN DQS2_DLY_MIN
.ne ID
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_DLY_MIN DQS0_DLY_MIN
Type RO RO
ink NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:24 DQS3_DLY_MIN DQS3 input minimum delay
b-l CO
22:16 DQS2_DLY_MIN DQS2 input minimum delay
14:8 DQS1_DLY_MIN DQS1 input minimum delay
6:0 DQS0_DLY_MIN DQS0 input minimum delay
18 TEK
1E005358 DQICAL2 DQS INPUT CALIBRATION 2 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_DLY_MAX DQS2_DLY_MAX
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name DQS1_DLY_MAX DQS0_DLY_MAX
RD A
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
30:24 DQS3_DLY_MAX DQS3 input maximum delay
22:16 DQS2_DLY_MAX DQS2 input maximum delay
FO ME
14:8 DQS1_DLY_MAX DQS1 input maximum delay
6:0 DQS0_DLY_MAX DQS0 input maximum delay
1E00535C DQICAL3 DQS INPUT CALIBRATION 3 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3_DLY_AVG DQS2_DLY_AVG
Type RO RO
PGMT7621_V.1.0_130607 Page 295 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DQS1_DLY_AVG DQS0_DLY_AVG
ON
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
30:24 DQS3_DLY_AVG DQS3 input delay average
22:16 DQS2_DLY_AVG DQS2 input delay average
14:8 DQS1_DLY_AVG DQS1 input delay average
t.c EN
6:0 DQS0_DLY_AVG DQS0 input delay average
1E005370 CMP_ERR CMP ERROR 0000000
.ne ID
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CMP_ERR[31:16]
Type RO
ink NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CMP_ERR[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
31:0 CMP_ERR bitwise auto test fail
18 TEK
1E005374 DQSIENDLY DQS INPUT GATING DELAY VALUE 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DQS3IENDLY DQS2IENDLY
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name DQS1IENDLY DQS0IENDLY
RD A
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
30:24 DQS3IENDLY DQS input gating delay for DQS3
22:16 DQS2IENDLY DQS input gating delay for DQS2
FO ME
14:8 DQS1IENDLY DQS input gating delay for DQS1
6:0 DQS0IENDLY DQS input gating delay for DQS0
1E00538C STBEN0 DQS RING COUNTER 0 0000000
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name STBEN0[31:16]
Type RO
PGMT7621_V.1.0_130607 Page 296 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SE AL
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STBEN0[15:0]
ON
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit(s) Name Description
n U TI
31:0 STBEN0 DQS0 ring counter
t.c EN
1E005390 STBEN1 DQS RING COUNTER 1 0000000
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name STBEN1[31:16]
.ne ID
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STBEN1[15:0]
Type RO
ink NF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit(s) Name Description
31:0 STBEN1 DQS1 ring counter
b-l CO
1E005394 STBEN2 DQS RING COUNTER 2 0000000
3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
18 TEK
Name STBEN2[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STBEN2[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
@
RD A
Bit(s) Name Description
31:0 STBEN2 DQS2 ring counter
R DI
1E005398 STBEN3 DQS RING COUNTER 3 0000000
3
FO ME
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name STBEN3[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name STBEN3[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit(s) Name Description
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MT7621 PROGRAMMING GUIDE
L Y
31:0 STBEN3 DQS3 ring counter
SE AL
ON
1E0053A0 DQSDLY0 DQS INPUT DELAY SETTING 0 0F0F0F0
F
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name DEL3DLY DEL2DLY
Type RO RO
Reset 0 0 0 1 1 1 1 0 0 0 1 1 1 1
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DEL1DLY DEL0DLY
Type RO RO
Reset 0 0 0 1 1 1 1 0 0 0 1 1 1 1
.ne ID
Bit(s) Name Description
30:24 DEL3DLY DQS input delay for DQS3
22:16 DEL2DLY DQS input delay for DQS2
14:8 DEL1DLY DQS input delay for DQS1
ink NF
6:0 DEL0DLY DQS input delay for DQS0
1E0053B8 SPCMDRESP SPECIAL COMMAND RESPONSE 0000030
b-l CO
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SR
EF_
ST
AT
18 TEK
E
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TC ZQ AR PR MR MR
MD C_ EF_ EA_ R_ W_
_RE RE RE RE RE RE
REFRESH_RATE
SP SP SP SP SP SP
@
ON ON ON ON ON ON
RD A
SE SE SE SE SE SE
Type RO RO RO RO RO RO RO
Reset 0 1 1 0 0 0 0 0 0
R DI
Bit(s) Name Description
16 SREF_STATE Self-refresh status
0: not enter
FO ME
1: enter
10:8 REFRESH_RATE Refresh rate reading from LPDDR2
001: 4 x tREFI
010: 2 x tREFI
011: 1 x tREFI
101: 0.25 x tREFI
110: 2.25 x tREFI
Others: Refer to LPDDR2 spec.
5 TCMD_RESPONSE TCMD command response
4 ZQC_RESPONSE ZQC command response
3 AREF_RESPONSE AREF command response
PGMT7621_V.1.0_130607 Page 298 of 349
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MT7621 PROGRAMMING GUIDE
L Y
2 PREA_RESPONSE PREA command response
SE AL
1 MRR_RESPONSE MRR command response
ON
0 MRW_RESPONSE MRW command response
n U TI
1E0053BC IORGCNT IO RING COUNTER 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
t.c EN
IO_RING_COUNTER
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IO_RING_COUNTER_K
Type RO
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:16 IO_RING_COUNTER 270 degree I/O clock offset counter for group 5
ink NF
15:0 IO_RING_COUNTER_ 180 degree I/O clock offset counter for group 5
K
b-l CO
1E0053C0 DQSGNWCNT DQS GATING WINODW COUNTER 0 0000000
0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs1r_gating_counter dqs1f_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs0r_gating_counter dqs0f_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 dqs1r_gating_counter rsing dqs gating counter for group 1
@
RD A
23:16 dqs1f_gating_counter falling dqs gating counter for group 1
15:8 dqs0r_gating_counter rsing dqs gating counter for group 0
7:0 dqs0f_gating_counter falling dqs gating counter for group 0
R DI
1E0053C4 DQSGNWCNT DQS GATING WINODW COUNTER 1 0000000
FO ME
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs3r_gating_counter dqs3f_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs2r_gating_counter dqs2f_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
31:24 dqs3r_gating_counter rsing dqs gating counter for group 3
ON
23:16 dqs3f_gating_counter falling dqs gating counter for group 3
15:8 dqs2r_gating_counter rsing dqs gating counter for group 2
7:0 dqs2f_gating_counter falling dqs gating counter for group 2
n U TI
1E0053C8 DQSGNWCNT DQS GATING WINODW COUNTER 2 0000000
t.c EN
2 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs0r_pre_gating_counter dqs0f_pre_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs0r_pos_gating_counter dqs0f_pos_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit(s) Name Description
31:24 dqs0r_pre_gating_cou rsing pre dqs gating counter for group 0
nter
23:16 dqs0f_pre_gating_coun falling pre dqs gating counter for group 0
b-l CO
ter
15:8 dqs0r_pos_gating_cou rsing pos dqs gating counter for group 0
nter
7:0 dqs0f_pos_gating_cou falling pos dqs gating counter for group 0
nter
18 TEK
1E0053CC DQSGNWCNT DQS GATING WINODW COUNTER 3 0000000
3 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs1r_pre_gating_counter dqs1f_pre_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
@
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD A
Name dqs1r_pos_gating_counter dqs1f_pos_gating_counter
Type RO RO
Reset
R DI
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 dqs1r_pre_gating_cou rsing pre dqs gating counter for group 1
FO ME
nter
23:16 dqs1f_pre_gating_coun falling pre dqs gating counter for group 1
ter
15:8 dqs1r_pos_gating_cou rsing pos dqs gating counter for group 1
nter
7:0 dqs1f_pos_gating_cou falling pos dqs gating counter for group 1
nter
1E0053D0 DQSGNWCNT DQS GATING WINODW COUNTER 4 0000000
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MT7621 PROGRAMMING GUIDE
L Y
4 0
SE AL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
Name dqs2r_pre_gating_counter dqs2f_pre_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n U TI
Name dqs2r_pos_gating_counter dqs2f_pos_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t.c EN
Bit(s) Name Description
31:24 dqs2r_pre_gating_cou rsing pre dqs gating counter for group 2
nter
23:16 dqs2f_pre_gating_coun falling pre dqs gating counter for group 2
ter
.ne ID
15:8 dqs2r_pos_gating_cou rsing pos dqs gating counter for group 2
nter
7:0 dqs2f_pos_gating_cou falling pos dqs gating counter for group 2
nter
ink NF
1E0053D4 DQSGNWCNT DQS GATING WINODW COUNTER 5 0000000
5 0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dqs3r_pre_gating_counter dqs3f_pre_gating_counter
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dqs3r_pos_gating_counter dqs3f_pos_gating_counter
Type RO RO
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 dqs3r_pre_gating_cou rsing pre dqs gating counter for group 3
nter
23:16 dqs3f_pre_gating_coun falling pre dqs gating counter for group 3
ter
@
RD A
15:8 dqs3r_pos_gating_cou rsing pos dqs gating counter for group 3
nter
7:0 dqs3f_pos_gating_cou falling pos dqs gating counter for group 3
R DI
nter
FO ME
1E0053D8 DQSSAMPLE DQS SAMPLE VALUE 0000000
V 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name sa sa sa sa
mpl mpl mpl mpl
CMPCNT e_o e_o e_o e_o
ut1 ut1 ut1 ut1
_D _D _D _D
PGMT7621_V.1.0_130607 Page 301 of 349
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MT7621 PROGRAMMING GUIDE
L Y
QS QS QS QS
SE AL
3 2 1 0
Type RO RO RO RO RO
ON
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
n U TI
9:4 CMPCNT CMP counter value
3 sample_out1_DQS3 Sampled value for DQS3
0: late
1: early
t.c EN
2 sample_out1_DQS2 Sampled value for DQS2
0: late
1: early
1 sample_out1_DQS1 Sampled value for DQS1
0: late
.ne ID
1: early
0 sample_out1_DQS0 Sampled value for DQS0
0: late
1: early
ink NF
1E0053DC DLLCNT0 DLL STATUS 0 0000000
0
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CM
PO
T
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
18 TEK
Name
Type
Reset
Bit(s) Name Description
31 CMPOT CMP pad calibration result
@
RD A
1E0053E8 CKPHCNT CLOCK PHASE DETECTION RESULT 0000000
R DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
FO ME
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CKPHCHKCNT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:0 CKPHCHKCNT MEMPLL in/out clock phase detection result counter
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MT7621 PROGRAMMING GUIDE
L Y
1E0053FC TESTRPT TEST AGENT STATUS 0000000
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CA
LI_ LB_ DLE
DO CM _CN
n U TI
NE_ P_F T_O
MO AIL K
N
Type RO RO RO
Reset
t.c EN
0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DM DM
_C _C
MP MP WPAT_HIT_CNT
_ER _CP
.ne ID
R T
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
28 CALI_DONE_MON calibration result is updated, SW can disable calibration
24 LB_CMP_FAIL Loop-back test mode compare fail
18 DLE_CNT_OK DLE counter is right for test agent 2
14 DM_CMP_ERR Read data compare error for test agent 2
b-l CO
10 DM_CMP_CPT Read data compare ready for test agent 2
7:0 WPAT_HIT_CNT Write pattern hit counter. Clear by WPAT_STCLR (REG.1FC[20])
1E005600 MEMPLL0 MEMPLL REGISTER SETTING 0 D000000
18 TEK
F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG RG
RG RG RG
RG _M _M
_M RG RG _M _M
_M EM EM
RG_MEMP EM _M _M EM EM
EM PLL PLL
LL_FBDIV PLL EM EM PLL RG_MEMPLL_DIVEN PLL
PLL _LV _M
@
2 _A PLL PLL _F _M
_B RO ON
RD A
CC _LF _BP ME ON
R DE CK
EN N EN
N EN
Type RW RW RW RW RW RW RW RW RW RW
R DI
Reset 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG
_M _M
RG_MEMP RG_MEMP RG_MEMP
EM EM
FO ME
LL_POSDI LL_PREDI LL_CKCTR RG_MEMPLL_FBDIV
PLL PLL
V V L
_RS _P
T WD
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit(s) Name Description
31:30 RG_MEMPLL_FBDIV2 Feedback clock select
2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
PGMT7621_V.1.0_130607 Page 303 of 349
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MT7621 PROGRAMMING GUIDE
L Y
29 RG_MEMPLL_ACCEN Fast Slew Enable
SE AL
1'b0: Disable
1'b1: Enable
ON
28 RG_MEMPLL_LF Frequency Band Control
always set 1
27 RG_MEMPLL_BR Resistance adjustment for Bandwidth
n U TI
1'b0: BW = Fref/10
1'b1: BW = Fref/20
26 RG_MEMPLL_BP Capacitance adjustment for Bandiwdth
1'b0: When RG_APLL_BR=1'b0
t.c EN
1'b1: When RG_APLL_BR=1'b1
25 RG_MEMPLL_FMEN PLL REF/FB monitor clock enable
1'b0: disable
1'b1: enable
24 RG_MEMPLL_LVROD REGV12 LVR overdrive enable
.ne ID
EN 1'b0: disable
1'b1: enable
23:18 RG_MEMPLL_DIVEN Time domain cap multiplication ratio
3'd0: x1
ink NF
3'd1: x2
3'd6: x64
17 RG_MEMPLL_MONCK Monitor clock enable
EN 1'b0: Disable
1'b1: Enable
b-l CO
16 RG_MEMPLL_MONEN Control voltage monitor enable
1'b0: Disable
1'b1: Enable
14 RG_MEMPLL_RST PLL reset control
1'b0: reset disable
1'b1: reset enable
13:12 RG_MEMPLL_POSDI Post-divider ratio for single-phase output
18 TEK
V 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
11:10 RG_MEMPLL_PREDIV Pre-divider ratio
2'b00: Fref = Fin/1
2'b01: Fref = Fin/2
2'b11: Fref = Fin/4
@
9:8 RG_MEMPLL_CKCTR Fast Slew Time Control
RD A
L 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
2'b10: 2^7 * Tin
R DI
2'b11: 2^6 * Tin
7:1 RG_MEMPLL_FBDIV Feedback divide ratio
7'd0: /1
7'd1: /2
FO ME
7'd127: /128
0 RG_MEMPLL_PWD Power Down
1'b0: Power On
1'b1: Power Down
(toggle from 1->0 to initialize)
1E005604 MEMPLL1 MEMPLL REGISTER SETTING 1 C000000
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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MT7621 PROGRAMMING GUIDE
L Y
Name RG_DMSS_PCW_NCPO[22:7]
SE AL
Type RW
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
_D
RG
MS
_M
n U TI
S_P
RG_MEMP EM
CW
RG_DMSS_PCW_NCPO[6:0] LL_RST_D PLL
_N
LY _V
CP
OD
O_
t.c EN
EN
CH
G
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 1
.ne ID
Bit(s) Name Description
31:9 RG_DMSS_PCW_NC DDS NCPO PCW
PO
8 RG_DMSS_PCW_NC DDS PCW change asynchrounous clock
ink NF
PO_CHG
2:1 RG_MEMPLL_RST_D ICO reset signal
LY 2'b00: reset delay min
2'b11: reset delay max
0 RG_MEMPLL_VODEN CHP OverDrive Enable
b-l CO
1'b0: Disable
1'b1: Enable
1E005608 MEMPLL2 MEMPLL REGISTER SETTING 2 4AC6001
C
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
RG RG RG
RG _D
_D _D _D
_D MS
MS MS MS
MS S_
RG_DMSS_SSC_DELTA1 S_S S_S RG_DMSS_PI_C S_P
S_S MO
SC_ SC_ I_R
SC_ NC
PHI TRI ST_
@
EN K_E
NI _EN SEL
RD A
N
Type RW RW RW RW RW RW RW
Reset 0 1 0 0 1 0 1 0 1 1 0 0 0 1 1 0
R DI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
_D
RG RG RG RG
RG MS RG RG
_D _D _D _M
_D S_F _D _D
FO ME
MS MS MS EM
MS IFO MS MS
S_P S_P S_N PLL RG_DMSS_PCW_NCPO
S_H _ST S_R S_P
I_P RE CP _D
F_E AR ST WD
L_E DIV O_ DS
N T_ B B
N 2 EN EN
MA
N
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
Bit(s) Name Description
31:24 RG_DMSS_SSC_DEL DDS SSC first spread disturbance amplitude
TA1
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MT7621 PROGRAMMING GUIDE
L Y
23 RG_DMSS_SSC_PHI FNPLL SSC initial spreading direction
SE AL
NI 1'b0: Upward
1'b1: Downward
ON
22 RG_DMSS_SSC_TRI_ DDS SSC modulation type
EN 1'b0: Square wave
1'b1: Triangular wave
n U TI
21 RG_DMSS_SSC_EN DDS SSC enable
1'b0: Disable
1'b1: Enable
20 RG_DMSS_MONCK_E DDS monitor clock enable
t.c EN
N 1'b0: Disable
1'b1: Enable
19:17 RG_DMSS_PI_C DMSS PI cap select
0: 165f
1: 150f
2: 135f
.ne ID
3: 120f
4: 105f
5: 90f
6: 75f
7: 60f
ink NF
16 RG_DMSS_PI_RST_S DDS PI reset selection
EL 0:analog reset
1:digital reset
15 RG_DMSS_PI_PL_EN DDS PI pull low function enable bar
b-l CO
1'b0: Enable
1'b1: Disable
14 RG_DMSS_HF_EN DDS high frequency mode enable
1'b0: When RG_LC_DDS_PREDIV2=1'b0
1'b1: When RG_LC_DDS_PREDIV2=1'b1
13 RG_DMSS_PREDIV2 DDS predivider
1'b0: /1
18 TEK
1'b1: /2
12 RG_DMSS_FIFO_STA DDS FIFO enable
RT_MAN 1'b0: Disable
1'b1: Enable
11 RG_DMSS_NCPO_EN DDS NCPO enable
1'b0: Disable
1'b1: Enable
@
RD A
10 RG_DMSS_RSTB DDS NCPO reset bar
1'b0: Reset
1'b1: Enable
R DI
9 RG_DMSS_PWDB DDS power down bar
1'b0: Power down
1'b1: Power on
8 RG_MEMPLL_DDSEN PLL DDS feedback enable
FO ME
1'b0: Integer-N mode
1'b1: Fractional-N mode
7:0 RG_DMSS_PCW_NC DDS NCPO PCW
PO
1E00560C MEMPLL3 MEMPLL REGISTER SETTING 3 90004A0
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_DMSS_SSC_PRD RG_DMSS_SSC_DELTA[15:8]
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MT7621 PROGRAMMING GUIDE
L Y
Type RW RW
Reset
SE AL
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON
Name RG_DMSS_SSC_DELTA[7:0] RG_DMSS_SSC_DELTA1
Type RW RW
Reset 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0
n U TI
Bit(s) Name Description
31:24 RG_DMSS_SSC_PRD DDS SSC modulation period
23:8 RG_DMSS_SSC_DEL DDS SSC disturbance amplitude
t.c EN
TA
7:0 RG_DMSS_SSC_DEL DDS SSC first spread disturbance amplitude
TA1
.ne ID
1E005610 MEMPLL4 MEMPLL REGISTER SETTING 4 000D080
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ink NF
Name RG
_M
EM
RG_DMSS_REV PLL RG_MEMPLL_DIV
_DI
V_E
b-l CO
N
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG RG
RG RG
_D _D _D
_D _D
MS MS MS
RG_DMSS_FRAC MS MS
18 TEK
S_L S_P S_C RG_DMSS_SSC_PRD
_MUTE S_S S_L
VR OS LK_
EL_ PF_
OD TDI PH_
EXT EN
EN V2 INV
Type RW RW RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
@
31:24 RG_DMSS_REV dummy reg
RD A
23 RG_MEMPLL_DIV_EN Enable the Divider for (APLL+DDS)
22:16 RG_MEMPLL_DIV Control bits of Divider for (APLL+DDS)
R DI
RG_MEMPLL_DIV[6]=1: /1
RG_MEMPLL_DIV[5:0]: /(N+2)
15 RG_DMSS_LVRODEN REGV12 LVR overdrive enable
1'b0: disable
FO ME
1'b1: enable
14:12 RG_DMSS_FRAC_MU REV
TE
11 RG_DMSS_SEL_EXT DDS output pulse width
0: 1T
1: 2T
10 RG_DMSS_POSTDIV2 DMSS output clock div by 2
0: disable
1: enable
9 RG_DMSS_CLK_PH_I DMSS phase inverter
NV 0: normal
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MT7621 PROGRAMMING GUIDE
L Y
1: inverter
SE AL
8 RG_DMSS_LPF_EN DMSS regualtor low pass filter enable
ON
0: disable
1: enable
7:0 RG_DMSS_SSC_PRD DDS SSC modulation period
n U TI
1E005614 MEMPLL5 MEMPLL REGISTER SETTING 5 5000801
3
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG RG
RG RG
RG
RG RG RG _M _M
_M _M _M
_M _M _M EM EM
RG_MEMP EM EM EM
EM EM EM PLL PLL
LL2_FBDI PLL PLL RG_MEMPLL2_DIVEN PLL
PLL PLL PLL 2_L 2_M
.ne ID
V2 2_A 2_F 2_M
2_L 2_B 2_B VR ON
CC ME ON
F R P OD CK
EN N EN
EN EN
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
ink NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
_M
RG RG
EM
_M _M
PLL RG_MEMP RG_MEMP RG_MEMP
EM EM
b-l CO
2_E LL2_POSD LL2_PRED LL2_CKCT RG_MEMPLL2_FBDIV
PLL PLL
XF IV IV RL
2_R 2_P
BDI
ST WD
V_E
N
Type RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
18 TEK
Bit(s) Name Description
31:30 RG_MEMPLL2_FBDIV Feedback clock select
2 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
29 RG_MEMPLL2_ACCE Fast Slew Enable
@
N 1'b0: Disable
RD A
1'b1: Enable
28 RG_MEMPLL2_LF Frequency Band Control
always set 1
R DI
27 RG_MEMPLL2_BR Resistance adjustment for Bandwidth
1'b0: BW = Fref/10
1'b1: BW = Fref/20
26 RG_MEMPLL2_BP Capacitance adjustment for Bandiwdth
FO ME
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
25 RG_MEMPLL2_FMEN PLL REF/FB monitor clock enable
1'b0: disable
1'b1: enable
24 RG_MEMPLL2_LVRO REGV12 LVR overdrive enable
DEN 1'b0: disable
1'b1: enable
23:18 RG_MEMPLL2_DIVEN Time domain cap multiplication ratio
3'd0: x1
3'd1: x2
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MT7621 PROGRAMMING GUIDE
L Y
3'd6: x64
SE AL
17 RG_MEMPLL2_MONC Monitor clock enable
KEN
ON
1'b0: Disable
1'b1: Enable
16 RG_MEMPLL2_MONE Control voltage monitor enable
N 1'b0: Disable
1'b1: Enable
n U TI
15 RG_MEMPLL2_EXFB Mux For Feeback clock
DIV_EN 1'b0: VCO loop
2'b1:outer loop
t.c EN
14 RG_MEMPLL2_RST PLL reset control
1'b0: reset disable
1'b1: reset enable
13:12 RG_MEMPLL2_POSDI Post-divider ratio for single-phase output
V 2'b00: VCO/1
.ne ID
2'b01: VCO/2
2'b11: VCO/4
11:10 RG_MEMPLL2_PREDI not use
V
9:8 RG_MEMPLL2_CKCT Fast Slew Time Control
ink NF
RL 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
2'b10: 2^7 * Tin
2'b11: 2^6 * Tin
7:1 RG_MEMPLL2_FBDIV Feedback divide ratio
b-l CO
7'd0: /1
7'd1: /2
7'd127: /128
0 RG_MEMPLL2_PWD Power Down
1'b0: Power On
1'b1: Power Down
(toggle from 1->0 to initialize)
18 TEK
1E005618 MEMPLL6 MEMPLL REGISTER SETTING 6 0000100
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
@
Name RG_MEMPLL2_REV
RD A
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DI
Name RG
RG RG
_M
_M _M RG
EM
EM EM _M
PLL
RG_MEMP PLL RG_MEMP PLL RG_MEMP EM
2_L
FO ME
LL2_TEST 2_F LL2_M4PD 2_M RG_MEMPLL2_SEL_MON LL2_RST_ PLL
DO
_DIV B_ IV 8PD DLY 2_V
_LV
MC IVM OD
RO
K_S ON EN
DE
EL _EN
N
Type RW RW RW RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
31:16 RG_MEMPLL2_REV dummy reg
14:13 RG_MEMPLL2_TEST_ Monitor clock divider for testmode
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MT7621 PROGRAMMING GUIDE
L Y
DIV 2'b00: /1
2'b01: /2
SE AL
2'b10: forbidden
ON
2'b11: /4
12 RG_MEMPLL2_FB_M Mux For Feeback clock
CK_SEL 1'b0: internal loop
2'b1:outer loop
n U TI
11 RG_MEMPLL2_LDO_L REGV12 LVR overdrive enable
VRODEN 1'b0: disable
1'b1: enable
10:9 RG_MEMPLL2_M4PDI Multi-phase divider ratio for 4-phase output
t.c EN
V 2'b00: VCO/2
2'b01: VCO/4
2'b10: VCO/8
8 RG_MEMPLL2_M8PDI
VMON_EN
.ne ID
7:3 RG_MEMPLL2_SEL_
MON
2:1 RG_MEMPLL2_RST_ ICO reset signal
DLY 2'b00: reset delay min
ink NF
2'b11: reset delay max
0 RG_MEMPLL2_VODE CHP OverDrive Enable
N 1'b0: Disable
1'b1: Enable
b-l CO
1E00561C MEMPLL7 MEMPLL REGISTER SETTING 7 1300000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
18 TEK
_M
EM
RG_MEMPLL3_FBDIV RG_MEMPLL2_DL_REV
PLL
3_P
WD
Type RW RW RW
Reset 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name RG_MEMPLL2_FB_DL RG_MEMPLL2_REF_DL
RD A
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R DI
Bit(s) Name Description
31:25 RG_MEMPLL3_FBDIV Feedback divide ratio
7'd0: /1
7'd1: /2
FO ME
7'd127: /128
24 RG_MEMPLL3_PWD Power Down
1'b0: Power On
1'b1: Power Down
(toggle from 1->0 to initialize)
23:16 RG_MEMPLL2_DL_R REV reg
EV
15:8 RG_MEMPLL2_FB_DL MEMPLL2 skew adjust between reference clock and feedback clock
7:0 RG_MEMPLL2_REF_ MEMPLL2 skew adjust between reference clock and feedback clock
DL
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
ON
1E005620 MEMPLL8 MEMPLL REGISTER SETTING 8 0150008
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
n U TI
Name RG RG RG
RG
RG RG RG _M
_M _M _M
_M _M _M EM
RG_MEMP EM RG_MEMP EM EM
EM EM EM PLL
RG_MEMPLL3_SEL_MON LL3_RST_ PLL LL3_FBDI PLL PLL
PLL PLL PLL 3_L
t.c EN
DLY 3_V V2 3_A 3_F
3_L 3_B 3_B VR
OD CC ME
F R P OD
EN EN N
EN
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.ne ID
Name RG
RG
RG _M
_M RG
_M EM
EM _M
EM PLL RG_MEMP RG_MEMP RG_MEMP
PLL EM
RG_MEMPLL3_DIVEN PLL 3_E LL3_POSD LL3_PRED LL3_CKCT
ink NF
3_M PLL
3_M XF IV IV RL
ON 3_R
ON BDI
CK ST
EN V_E
EN
N
Type RW RW RW RW RW RW RW RW
b-l CO
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit(s) Name Description
31:27 RG_MEMPLL3_SEL_
MON
26:25 RG_MEMPLL3_RST_ ICO reset signal
DLY
18 TEK
2'b00: reset delay min
2'b11: reset delay max
24 RG_MEMPLL3_VODE CHP OverDrive Enable
N 1'b0: Disable
1'b1: Enable
23:22 RG_MEMPLL3_FBDIV Feedback clock select
2 2'b00: VCO/1
@
2'b01: VCO/2
RD A
2'b11: VCO/4
21 RG_MEMPLL3_ACCE Fast Slew Enable
N 1'b0: Disable
R DI
1'b1: Enable
20 RG_MEMPLL3_LF Frequency Band Control
always set 1
19 RG_MEMPLL3_BR Resistance adjustment for Bandwidth
FO ME
1'b0: BW = Fref/10
1'b1: BW = Fref/20
18 RG_MEMPLL3_BP Capacitance adjustment for Bandiwdth
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
17 RG_MEMPLL3_FMEN PLL REF/FB monitor clock enable
1'b0: disable
1'b1: enable
16 RG_MEMPLL3_LVRO REGV12 LVR overdrive enable
DEN 1'b0: disable
1'b1: enable
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MT7621 PROGRAMMING GUIDE
L Y
15:10 RG_MEMPLL3_DIVEN Time domain cap multiplication ratio
SE AL
3'd0: x1
3'd1: x2
ON
3'd6: x64
9 RG_MEMPLL3_MONC Monitor clock enable
KEN 1'b0: Disable
1'b1: Enable
n U TI
8 RG_MEMPLL3_MONE Control voltage monitor enable
N 1'b0: Disable
1'b1: Enable
t.c EN
7 RG_MEMPLL3_EXFB Mux For Feeback clock
DIV_EN 1'b0: VCO loop
2'b1:outer loop
6 RG_MEMPLL3_RST PLL reset control
1'b0: reset disable
1'b1: reset enable
.ne ID
5:4 RG_MEMPLL3_POSDI Post-divider ratio for single-phase output
V 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
ink NF
3:2 RG_MEMPLL3_PREDI not use
V
1:0 RG_MEMPLL3_CKCT Fast Slew Time Control
RL 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
b-l CO
2'b10: 2^7 * Tin
2'b11: 2^6 * Tin
1E005624 MEMPLL9 MEMPLL REGISTER SETTING 9 0000001
0
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_MEMPLL3_REF_DL RG_MEMPLL3_REV[15:8]
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG RG
_M
@
_M _M
EM
RD A
EM EM
PLL
RG_MEMP PLL RG_MEMP PLL
3_L
RG_MEMPLL3_REV[7:0] LL3_TEST 3_F LL3_M4PD 3_M
DO
R DI
_DIV B_ IV 8PD
_LV
MC IVM
RO
K_S ON
DE
EL _EN
N
Type RW RW RW RW RW RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit(s) Name Description
31:24 RG_MEMPLL3_REF_ MEMPLL3 skew adjust between reference clock and feedback clock
DL
23:8 RG_MEMPLL3_REV dummy reg
6:5 RG_MEMPLL3_TEST_ Monitor clock divider for testmode
DIV 2'b00: /1
2'b01: /2
2'b10: forbidden
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MT7621 PROGRAMMING GUIDE
L Y
2'b11: /4
SE AL
4 RG_MEMPLL3_FB_M Mux For Feeback clock
CK_SEL
ON
1'b0: internal loop
2'b1:outer loop
3 RG_MEMPLL3_LDO_L REGV12 LVR overdrive enable
VRODEN 1'b0: disable
1'b1: enable
n U TI
2:1 RG_MEMPLL3_M4PDI Multi-phase divider ratio for 4-phase output
V 2'b00: VCO/2
2'b01: VCO/4
2'b10: VCO/8
t.c EN
0 RG_MEMPLL3_M8PDI
VMON_EN
.ne ID
1E005628 MEMPLL10 MEMPLL REGISTER SETTING 10 8013000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ink NF
Name RG
_M
RG RG
EM
_M _M
PLL RG_MEMP RG_MEMP RG_MEMP
EM EM
4_E LL4_POSD LL4_PRED LL4_CKCT RG_MEMPLL4_FBDIV
PLL PLL
XF IV IV RL
4_R 4_P
b-l CO
BDI
ST WD
V_E
N
Type RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_MEMPLL3_DL_REV RG_MEMPLL3_FB_DL
Type RW RW
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31 RG_MEMPLL4_EXFB Mux For Feeback clock
DIV_EN 1'b0: VCO loop
2'b1:outer loop
@
30 RG_MEMPLL4_RST PLL reset control
RD A
1'b0: reset disable
1'b1: reset enable
29:28 RG_MEMPLL4_POSDI Post-divider ratio for single-phase output
R DI
V 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
27:26 RG_MEMPLL4_PREDI not use
FO ME
V
25:24 RG_MEMPLL4_CKCT Fast Slew Time Control
RL 2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
2'b10: 2^7 * Tin
2'b11: 2^6 * Tin
23:17 RG_MEMPLL4_FBDIV Feedback divide ratio
7'd0: /1
7'd1: /2
7'd127: /128
16 RG_MEMPLL4_PWD Power Down
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MT7621 PROGRAMMING GUIDE
L Y
1'b0: Power On
1'b1: Power Down
SE AL
(toggle from 1->0 to initialize)
ON
15:8 RG_MEMPLL3_DL_R REV reg
EV
7:0 RG_MEMPLL3_FB_DL MEMPLL3 skew adjust between reference clock and feedback clock
n U TI
1E00562C MEMPLL11 MEMPLL REGISTER SETTING 11 1001500
0
t.c EN
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
RG RG
_M
_M _M RG
EM
EM EM _M
PLL
.ne ID
RG_MEMP PLL RG_MEMP PLL RG_MEMP EM
4_L
LL4_TEST 4_F LL4_M4PD 4_M RG_MEMPLL4_SEL_MON LL4_RST_ PLL
DO
_DIV B_ IV 8PD DLY 4_V
_LV
MC IVM OD
RO
K_S ON EN
DE
ink NF
EL _EN
N
Type RW RW RW RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG RG
RG RG RG
b-l CO
RG RG RG _M _M
_M _M _M
_M _M _M EM EM
RG_MEMP EM EM EM
EM EM EM PLL PLL
LL4_FBDI PLL PLL RG_MEMPLL4_DIVEN PLL
PLL PLL PLL 4_L 4_M
V2 4_A 4_F 4_M
4_L 4_B 4_B VR ON
CC ME ON
F R P OD CK
EN N EN
EN EN
Type RW RW RW RW RW RW RW RW RW RW
18 TEK
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
30:29 RG_MEMPLL4_TEST_ Monitor clock divider for testmode
DIV 2'b00: /1
2'b01: /2
2'b10: forbidden
@
2'b11: /4
RD A
28 RG_MEMPLL4_FB_M Mux For Feeback clock
CK_SEL 1'b0: internal loop
2'b1:outer loop
R DI
27 RG_MEMPLL4_LDO_L REGV12 LVR overdrive enable
VRODEN 1'b0: disable
1'b1: enable
26:25 RG_MEMPLL4_M4PDI Multi-phase divider ratio for 4-phase output
FO ME
V 2'b00: VCO/2
2'b01: VCO/4
2'b10: VCO/8
24 RG_MEMPLL4_M8PDI
VMON_EN
23:19 RG_MEMPLL4_SEL_
MON
18:17 RG_MEMPLL4_RST_ ICO reset signal
DLY 2'b00: reset delay min
2'b11: reset delay max
PGMT7621_V.1.0_130607 Page 314 of 349
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MT7621 PROGRAMMING GUIDE
L Y
16 RG_MEMPLL4_VODE CHP OverDrive Enable
SE AL
N 1'b0: Disable
1'b1: Enable
ON
15:14 RG_MEMPLL4_FBDIV Feedback clock select
2 2'b00: VCO/1
2'b01: VCO/2
2'b11: VCO/4
n U TI
13 RG_MEMPLL4_ACCE Fast Slew Enable
N 1'b0: Disable
1'b1: Enable
t.c EN
12 RG_MEMPLL4_LF Frequency Band Control
always set 1
11 RG_MEMPLL4_BR Resistance adjustment for Bandwidth
1'b0: BW = Fref/10
1'b1: BW = Fref/20
.ne ID
10 RG_MEMPLL4_BP Capacitance adjustment for Bandiwdth
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
9 RG_MEMPLL4_FMEN PLL REF/FB monitor clock enable
ink NF
1'b0: disable
1'b1: enable
8 RG_MEMPLL4_LVRO REGV12 LVR overdrive enable
DEN 1'b0: disable
1'b1: enable
b-l CO
7:2 RG_MEMPLL4_DIVEN Time domain cap multiplication ratio
3'd0: x1
3'd1: x2
3'd6: x64
1 RG_MEMPLL4_MONC Monitor clock enable
KEN 1'b0: Disable
1'b1: Enable
18 TEK
0 RG_MEMPLL4_MONE Control voltage monitor enable
N 1'b0: Disable
1'b1: Enable
1E005630 MEMPLL12 MEMPLL REGISTER SETTING 12 0000000
@
0
RD A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_MEMPLL4_FB_DL RG_MEMPLL4_REF_DL
R DI
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_MEMPLL4_REV
Type RW
FO ME
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:24 RG_MEMPLL4_FB_DL MEMPLL4 skew adjust between reference clock and feedback clock
23:16 RG_MEMPLL4_REF_ MEMPLL4 skew adjust between reference clock and feedback clock
DL
15:0 RG_MEMPLL4_REV dummy reg
PGMT7621_V.1.0_130607 Page 315 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1E005634 MEMPLL13 MEMPLL REGISTER SETTING 13 02005B0
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
_M
EM
n U TI
RG_MEMP RG_MEMP
PLL RG_MEMPLL_CK
LL_TEST_ LL_REFM RG_MEMPLL_MONSEL
_C MON_AMPADJ
DIV ON
KM
ON
_PD
t.c EN
Type RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG
_M RG RG
_M RG
.ne ID
EM _M _M
EM _M
PLL EM EM
PLL EM
RG_MEMPLL_RE _RE PLL PLL
_LD PLL RG_MEMPLL4_DL_REV
FCK_SEL FC _BI _BI
O_L _SE
K_ AS_ AS_
VR L_C
ink NF
MO RS PW
OD K
NE T D
EN
N
Type RW RW RW RW RW RW RW
Reset 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0
b-l CO
Bit(s) Name Description
29:28 RG_MEMPLL_TEST_ Monitor clock divider for testmode
DIV 2'b00: /1
2'b01: /2
2'b10: forbidden
2'b11: /4
18 TEK
27:26 RG_MEMPLL_REFMO Monitor clock for testmode
N 2'b01 Refernece clock
25 RG_MEMPLL_CKMON
_PD
24:22 RG_MEMPLL_CKMON
_AMPADJ
21:17 RG_MEMPLL_MONSE
@
L
RD A
15 RG_MEMPLL_LDO_L REGV12 LVR overdrive enable
VRODEN 1'b0: disable
1'b1: enable
R DI
14 RG_MEMPLL_SEL_C Monitor clock for debug enable
K 1'b0: Disable
1'b1: Enable
FO ME
13:11 RG_MEMPLL_REFCK MEMPLL input clock selection
_SEL 000 : XTAL
001 : FNPLL+Divider
10 RG_MEMPLL_REFCK MEMPLL2/3/4 refck monitor enable
_MONEN 1'b0: disable
1'b1: enable
9 RG_MEMPLL_BIAS_R Constant-Gm Bias Reset
ST 1'b0: For performance
1'b1: Reset for Fast Power On
8 RG_MEMPLL_BIAS_P Constant-Gm Bias Power Down
WD 1'b0:Power On
PGMT7621_V.1.0_130607 Page 316 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1'b1: Power Down
SE AL
7:0 RG_MEMPLL4_DL_R REV reg
EV
ON
1E005638 MEMPLL14 MEMPLL REGISTER SETTING 14 0000000
n U TI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_MEMP
t.c EN
LL_TOP_R
EV[15:14]
Type RW
Reset 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_MEMPLL_TOP_REV[13:0]
.ne ID
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
ink NF
17:2 RG_MEMPLL_TOP_R dummy reg
EV
b-l CO
1E005640 MEMPLL_DIVI MEMPLL DIVIDER REGISTER CONTROL 0000000
DER 3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R_D
R_ R_
M1 R_ R_
DM DM
PLL DM DM
PLL ALL
_SY BY BY
2CL CL
NC_ P_P P_P
K_E K_E
MO LL3 LL4
N N
DE
@
Type RW RW RW RW RW
RD A
Reset 0 0 0 1 1
Bit(s) Name Description
R DI
5 R_DMPLL2CLK_EN Enable 4-phase output clocks of PLL core 2
0: disable
1: enable
4 R_DMALLCLK_EN Enable 4-phase output clocks of all clocks
FO ME
0: disable
1: enable
2 R_DM1PLL_SYNC_M Synchronous mode under 1-PLL clock scheme
ODE 0: asynchronous mode
1: synchronous mode
1 R_DMBYP_PLL3 Bypass PLL core 3
0: not bypass
1: bypass
0 R_DMBYP_PLL4 Bypass PLL core 4
0: not bypass
PGMT7621_V.1.0_130607 Page 317 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1: bypass
SE AL
ON
1E005644 VREF VREF setting 0000000
0
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EN_ EN_
INTREF1_ INTREF1_ INTREF1_ INT INTREF0_ INTREF0_ INTREF0_ INT
REFN REFP DS RE REFN REFP DS RE
F1 F0
Type RW RW RW RW RW RW RW RW
.ne ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
15:14 INTREF1_REFN Fine tune Vref to lower level Control for internal VREF 1
ink NF
00: weakest
11: strongest to lower level
13:12 INTREF1_REFP Fine tune Vref to higher level Control for internal VREF 1
00: weakest
11: strongest to higher level
b-l CO
11:10 INTREF1_DS Current consumption control for internal VREF 1
00: weakest
11: strongest current consumption
8 EN_INTREF1 Internal VREF 1 Enalbe control
1 : enable
0 : disable
18 TEK
7:6 INTREF0_REFN Fine tune Vref to lower level Control for internal VREF 0
00: weakest
11: strongest to lower level
5:4 INTREF0_REFP Fine tune Vref to higher level Control for internal VREF 0
00: weakest
11: strongest to higher level
3:2 INTREF0_DS Current consumption control for internal VREF 0
@
00: weakest
RD A
11: strongest current consumption
0 EN_INTREF0 Internal VREF 0 Enalbe control
1 : enable
R DI
0 : disable
FO ME
PGMT7621_V.1.0_130607 Page 318 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.16 RBUS Matrix and QoS Arbiter
ON
2.16.1 Features
8 channel QoS Arbiter
Configurable Bandwidth and Duedate for each agent
n U TI
QoS classifier can be programmed for RR, BW RR, Fixed Priority and QoS Arb
2.16.2 Block Diagram
t.c EN
N requestors (N=8) Req#0 Req#1 Req#2 Req#7
.ne ID TRTC TRTC TRTC TRTC N Meters
ink NF
N Run time classifiers
(based on QoS type,
due date and color)
Classifier Classifier Classifier Classifier N Classifiers
b-l CO
M(=8) run time
QoS types
M first
LCgd LSg ... LCg BEy stage arbiters
arbiter arbiter arbiter arbiter (N ports/arbiter)
18 TEK
1 second
8 to 1 Strict priority arbiter
stage arbiter
(based on service priority)
(M ports)
N-port QoS Arbiter
@
RD A
R DI
Figure 2-9 QoS Arbitration Block Diagram
FO ME
PGMT7621_V.1.0_130607 Page 319 of 349
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MT7621 PROGRAMMING GUIDE
L Y
2.16.3 Registers of QoS Control
SE AL
DMA_CFG_ARB Changes LOG
ON
Revision Date Author Change Log
0.1 2012/10/5 Lancelot Initialization
0.2 2012/10/22 Lancelot Modify DMA debug message
n U TI
Module name: DMA_CFG_ARB Base address: (+1E000800h)
t.c EN
Address Name Widt Register Function
h
1E000800 DMA_ARB_CFG 32 DMA 8 to 1 arbiter setting
1E000804 DMA_AG_BW 32 DMA Channel BW/QoS_Type/DueDate Setting
.ne ID
1E000808 DMA_AG_MAP 32 DMA channel (AG) mapping
1E00080C DMA_ROUTE 32 DMA Routing
1E000810 DMA_DBG 32 DMA Debug
ink NF
1E000814 DMA_STATE 32 DMA Debug State
1E000818 DMA_BW 32 DMA Bandwidth
1E00081C DMA_LAT 32 DMA Latency
1E000820 R2P_MONITOR 32 Rbus to Pbus monitor
b-l CO
1E000824 R2P_ERR_ADDR 32 Rbus to Pbus ERR address
1E000800 DMA_ARB_C DMA 8 to 1 arbiter setting 04FAC6
FG 88
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name pre
clas
em trtc
s_e cls_priority[23:16]
pt_ _en
n
en
Type RW RW RW RW
Reset 1 0 0 1 1 1 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@
Name cls_priority[15:0]
RD A
Type RW
Reset 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
R DI
Bit(s) Name Description
26 preempt_en Preemption Enable
Request preemption, higher priority requestor may change current request transaction
FO ME
0: Disable Preemption
1: Enable Preemption
25 trtc_en Two Rate Three Color Bandwidth (TRTC) Meter Enable
0: Disable TRTC
1: Enable TRTC
24 class_en QoS Classifier Enable
0: Disable CLASS
1: Enable CLASS
TRTC (0) CLASS (0) Round Robin
TRTC (0) CLASS (1) Fixed Priority
TRTC (1) CLASS (0) BW RR
TRTC (1) CLASS (1) QoS Arb
PGMT7621_V.1.0_130607 Page 320 of 349
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MT7621 PROGRAMMING GUIDE
L Y
23:0 cls_priority Class Priority
SE AL
This field is used for class priority for second arbitration.
{BEy(3'd7), LCg(3'd6), BSy(3'd5), LSy(3'd4), BEg (3'd3), BSg (3'd2), LSg(3'd1),
ON
LCgd(3'd0)}
n U TI
1E000804 DMA_AG_BW DMA Channel BW/QoS_Type/DueDate Setting 0220802
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
t.c EN
Name ag_
ag_sel
ag_qos_ty
ag_duedate
wr pe
Type WO RW RW RW
Reset 0 0 0 0 1 0 0 0 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ag_pir ag_cir
.ne ID
Type RW RW
Reset 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Bit(s) Name Description
ink NF
31 ag_wr Agent Write
0: Read
1: Write
30:28 ag_sel DMA Agent Select
Selects a DMA agent to configure.
b-l CO
0: SDXC/ND/SPDIF
1: HS_GDMS/GDMS/UTIF
2: USB 3.0
3: FE(0)
4: FE(1)
5: PPE
6: PCIe
18 TEK
7: Crypto
25:24 ag_qos_type Agent QoS Type
0: Latency critical
1: Latency sensitive
2: Bandwidth sensitive (default)
3: Best Effort
23:16 ag_duedate Due date for latency critical agent
@
(unit: system bus clock cycle
- system bus is 300 MHz or 225 MHz depending on bootstrap value.)
RD A
15:8 ag_pir Peak Information Rate for the Agent
The PIR is greater than or equal to the CIR. Bandwidth which exceeds PIR is marked
R DI
red.
0x00: 0 MB/s
0x01: 4 MB/s
...
0x80: 512 MB/s (default)
FO ME
...
0xFF: 1020 MB/s (Max)
7:0 ag_cir Committed Information Rate for the Agent
Bandwidth which falls below the CIR is marked green. BW which exceeds the CIR but
is below the EIR is marked yellow.
0x00: 0 MB/s
0x01: 4 MB/s
...
0x20: 128 MB/s (default)
...
0xFF: 1020 MB/s (Max)
PGMT7621_V.1.0_130607 Page 321 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
1E000808 DMA_AG_MA DMA channel (AG) mapping 0000000
ON
P 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
n U TI
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dma_ch_ag_map
Type RW
t.c EN
Reset 0 0 0 0 0 0 0 0
Bit(s) Name Description
7:0 dma_ch_ag_map DMA AG map for 8 channel
.ne ID
1'b0 -> This channel will go to DRAM arbiter
1'b1-> This channel will go to IOCU
ink NF
1E00080C DMA_ROUTE DMA Routing 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
b-l CO
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dm
a_r
out
e
Type RW
18 TEK
Reset 0
Bit(s) Name Description
0 dma_route DMA routing
0: DMA will access to DRAM
1: DMA will access to CSR
@
RD A
1E000810 DMA_DBG DMA Debug 0000000
R DI
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
FO ME
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dma_sel
Type RW
Reset 0 0 0
Bit(s) Name Description
2:0 dma_sel DMA channel select for debug message dump
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MT7621 PROGRAMMING GUIDE
L Y
1E000814 DMA_STATE DMA Debug State 0000000
SE AL
0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
n U TI
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dm
a_r dma_state dma_length
w
t.c EN
Type RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
10 dma_rw DMA channel RW
.ne ID
9:8 dma_state DMA channel State
2'b00: IDLE
2'b01: REQ
2'b10: ACK
ink NF
2'b11: DATA
7:0 dma_length DMA channel burst length (Byte)
b-l CO
1E000818 DMA_BW DMA Bandwidth 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name bw_
avg_bw peak_bw[9:6]
rst
Type WO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 TEK
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name peak_bw[5:0] dma_bw
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
31 bw_rst Write 1 will reset BW values.
RD A
29:20 avg_bw Average BW (MB/S)
19:10 peak_bw Peak BW (MB/S)
R DI
9:0 dma_bw DMA channel BW (MB/S)
FO ME
1E00081C DMA_LAT DMA Latency 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name lat_
avg_lat peak_lat[9:6]
rst
Type WO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name peak_lat[5:0] rd_lat
Type RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
31 lat_rst Write 1 will reset latency values
29:20 avg_lat Average read latency (T)
19:10 peak_lat Peak read latency (T)
n U TI
9:0 rd_lat DMA channel read latency (T)
t.c EN
1E000820 R2P_MONITO Rbus to Pbus monitor 0000102
R 3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name r2p
_in
.ne ID
c_c
nt
Type W1
C
Reset 0
ink NF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name r2p_err_cnt r2p_inc_clr
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1
b-l CO
Bit(s) Name Description
16 r2p_inc_cnt R2P Interrupt Clear
Write 1 to clear this interrupt.
15:10 r2p_err_cnt R2P error counter
9:0 r2p_inc_clr R2P Interrupt Countdown Timer
Sets a delay timer which begins counting down when an R2P error is detected. When
18 TEK
the timer reaches zero the R2P interrupt is then triggered.
10'd0: Disable R2P monitoring
10'd1: 20 us
10'd2: 40 us
10'd1023: 40 ms
@
1E000824 R2P_ERR_AD Rbus to Pbus ERR address 0000000
RD A
DR 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DI
Name r2p_err_addr[31:16]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO ME
Name r2p_err_addr[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:0 r2p_err_addr R2P address record for previous error found
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.16.4 Registers of Rbus Matrix
ON
Rbus_Matrix_CTRL Changes LOG
Revision Date Author Change Log
n U TI
0.1 2012/10/2 Lancelot Initialization
0.2 2013/1/3 Lancelot Add sleep count
t.c EN
Module name: Rbus_Matrix_CTRL Base address: (+1E000400h)
Address Name Widt Register Function
h
.ne ID
1E000400 OCP_CFG0 32 OCP to Rbus configuration
1E000404 OCP_CFG1 32 Read bypass write mask
1E000410 DYN_CFG0 32 Dynamic cpu/ocp frequency control
1E000414 DYN_CFG1 32 CPU sleep step frequency control
ink NF
1E000418 DYN_CFG2 32 Dyn CFG Probe
1E00041C DYN_CFG3 32 Sleep Counter
1E000420 IOCU_CFG 32 IOCU MreqInfo Setting
b-l CO
1E000400 OCP_CFG0 OCP to Rbus configuration 0000000
7
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
18 TEK
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name syn
ocp
rbu rd_
_sy
c_ s_a byp
nc_
met syn ass
cm
hod c _wr
d
@
Type RW RW RW RW
RD A
Reset 0 1 1 1
Bit(s) Name Description
R DI
3 sync_method OCP Synchronization Command Method
0: All empty (Wait until all FIFOs are empty )
1: CMD empty (Wait until the CMD FIFO is empty)
FO ME
2 ocp_sync_cmd OCP Synchronization Command Method Enable
Remaps this RD CMD to address 0x0000_0000. Initiate DRAM control before enabling
this option.
0: Disable
1: Enable
1 rbus_async Async Mode for RBUS
0: Set HW to switch between sync or async mode dynamically.
1: Force RBUS to A.sync mode.
0 rd_bypass_wr Read Bypass Write Enable
Allows read commands to bypass write commands for OCP_IF when the address does
not conflict.
0: Disable
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MT7621 PROGRAMMING GUIDE
L Y
1: Enable
SE AL
ON
1E000404 OCP_CFG1 Read bypass write mask FFFFFF
FF
n U TI
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name rd_bypass_wr_mask[31:16]
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
t.c EN
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rd_bypass_wr_mask[15:0]
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name Description
.ne ID
31:0 rd_bypass_wr_mask
ink NF Mask bit for read bypass write address
1E000410 DYN_CFG0 Dynamic cpu/ocp frequency control 00000A0
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
b-l CO
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cpu_fdiv cpu_ffrac
Type RW RW
Reset 1 0 1 0 0 0 0 1
18 TEK
Bit(s) Name Description
11:8 cpu_fdiv CPU Frequency Divider
The frequency divider is used to generate the CPU frequency. The value must be
larger than or equal to CPU_FFRAC. Valid values range from 1 to 15.
3:0 cpu_ffrac CPU Frequency Fractional
A parameter used in conjunction with the CPU frequency divider to determine the CPU
frequency. Input a value in the following equation to determine the CPU frequency.
@
Valid values range from 0 to 15.
RD A
CPU frequency = (CPU_FFRAC/CPU_FDIV)*PLL_FREQ
NOTE: If the chip runs in USB OHCI mode, the OCP frequency cannot be lower than
30 MHz. It means that PLL_FREQ*(CPU_FFRAC/CPU_FDIV)/(CPU_OCP_RATIO+1)
R DI
>= 30 MHz.
FO ME
1E000414 DYN_CFG1 CPU sleep step frequency control 0020000
6
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ste
slp
p_e step_cnt
_en
n
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name step_ffrac
Type RW
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 1 1 0
SE AL
ON
Bit(s) Name Description
31 slp_en Sleep Mode Enable
Enables sleep mode when MIPS SI_Sleep is asserted.
0: Disable
n U TI
1: Enable
Sleep Mode CPU Frequency = (1/CPU_FDIV)*PLL_FREQ
30 step_en Step Jump Enable
Enables step jump after MIPS exits sleep mode. The CPU will jump to the normal
t.c EN
frequency in increments defined by STEP_FFRAC.bit[4:0] of this register.
0: Disable
1: Enable
27:20 step_cnt Step Counter
Sets the period of each step jump. When the counter counts down to zero, the CPU
clock automatically changes to the next step frequency.
.ne ID
The count period unit is 1 us.
3:0 step_ffrac Step Frequency Fraction
Sets the fractional size of the increment in CPU frequency after the CPU exits from
sleep mode and returns to normal operation. This step is only valid when
ink NF
SLP_STEP_EN is enabled.
FRAC_VALUE =
PREVIOUS_FRAC_VALUE + STEP_FFRAC
CPU Frequency = (FRAC_VALUE/CPU_FDIV)*PLL_FREQ
b-l CO
1E000418 DYN_CFG2 Dyn CFG Probe 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dyn_probe[31:16]
Type RO
18 TEK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dyn_probe[15:0]
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
@
31:0 dyn_probe Dynamic freq probe
RD A
[26:25] dfc_fsm
[18:16] cpu_ocp_ratio
[11:8] cpu_fdiv
R DI
[3:0] cpu_ffrac
FO ME
1E00041C DYN_CFG3 Sleep Counter 0000000
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name slp
_cn
Sleep_counter[27:16]
t_rs
t
Type WO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Sleep_counter[15:0]
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MT7621 PROGRAMMING GUIDE
L Y
Type RW
Reset
SE AL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ON
Bit(s) Name Description
28 slp_cnt_rst Sleep Counter Reset
27:0 Sleep_counter Sleep Counter
n U TI
1E000420 IOCU_CFG IOCU MreqInfo Setting 1111111
t.c EN
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name mreq_ag7 mreq_ag6 mreq_ag5 mreq_ag4
Type RW RW RW RW
Reset 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
.ne ID
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name mreq_ag3 mreq_ag2 mreq_ag1 mreq_ag0
Type RW RW RW RW
Reset 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
ink NF
Bit(s) Name Description
31:28 mreq_ag7 IO_MreqInfo Setting for Ag7
Please reference AG0 configuration
27:24 mreq_ag6 IO_MreqInfo Setting for Ag6
b-l CO
Please reference AG0 configuration
23:20 mreq_ag5 IO_MreqInfo Setting for Ag5
Please reference AG0 configuration
19:16 mreq_ag4 IO_MreqInfo Setting for Ag4
Please reference AG0 configuration
18 TEK
15:12 mreq_ag3 IO_MreqInfo Setting for Ag3
Please reference AG0 configuration
11:8 mreq_ag2 IO_MreqInfo Setting for Ag2
Please reference AG0 configuration
7:4 mreq_ag1 IO_MreqInfo Setting for Ag1
Please reference AG0 configuration
3:0 mreq_ag0 IO_MreqInfo Setting for Ag0
@
0: Non-Coherent, L2 cacheable no L2 allocate
RD A
1: Coherent, cacheable no L2 allocate
2: Non-Coherent, uncacheable
3: Illegal
R DI
4: Non-Coherent, L2 cacheable, L2 allocate
5: Coherent, cacheable, L2 allocate
6: Illegal
7-15 Reserved
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.17 External MC Arbiter
ON
n U TI
t.c EN
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
2.17.1 Registers
SE AL
EXT_MC_ARB Changes LOG
ON
Revision Date Author Change Log
0.1 2012/10/5 Lancelot Initialization
n U TI
Module name: EXT_MC_ARB Base address: (+1E006000h)
t.c EN
Address Name Widt Register Function
h
1E006000 MC_ARB_CFG 32 MC 2 to 1 arbiter setting
1E006004 MC_AG_BW 32 MC Channel BW/QoS_Type/DueDate Setting
1E006010 DRAM_SIZE 32 DRAM Size config
1E006000
.ne ID
MC_ARB_CF MC 2 to 1 arbiter setting 07FAC6
ink NF
G 88
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name pre
clas
em trtc
s_e cls_priority[23:16]
pt_ _en
b-l CO
n
en
Type RW RW RW RW
Reset 1 1 1 1 1 1 1 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cls_priority[15:0]
Type RW
Reset 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
18 TEK
Bit(s) Name Description
26 preempt_en Preemption Enable
Request preemption, higher priority requestor may change current request transaction
0: Disable Preemption
1: Enable Preemption
25 trtc_en Two Rate Three Color Bandwidth (TRTC) Meter Enable
@
RD A
0: Disable TRTC
1: Enable TRTC
24 class_en QoS Classifier Enable
R DI
0: Disable CLASS
1: Enable CLASS
TRTC (0) CLASS (0) Round Robin
TRTC (0) CLASS (1) Fixed Priority
TRTC (1) CLASS (0) BW RR
FO ME
TRTC (1) CLASS (1) QoS Arb
23:0 cls_priority Class Priority
This field is used for class priority for second arbitration.
{BEy(3'd7), LCg(3'd6), BSy(3'd5), LSy(3'd4), BEg (3'd3), BSg (3'd2), LSg(3'd1),
LCgd(3'd0)}
1E006004 MC_AG_BW MC Channel BW/QoS_Type/DueDate Setting 0210FF4
0
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MT7621 PROGRAMMING GUIDE
L Y
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SE AL
Name ag_ ag_qos_ty
ag_sel ag_duedate
wr pe
ON
Type WO RW RW RW
Reset 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ag_pir ag_cir
n U TI
Type RW RW
Reset 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0
Bit(s) Name Description
t.c EN
31 ag_wr Agent Write
0: Read
1: Write
30:28 ag_sel DMA Agent Select
Selects a DMA agent to configure.
.ne ID
0: CPU (Rbus0)
1: DMA (Rbus1)
25:24 ag_qos_type Agent QoS Type
0: Latency critical
ink NF
1: Latency sensitive (CPU)
2: Bandwidth sensitive (DMA)
3: Best Effort
23:16 ag_duedate Due date for latency critical agent
(unit: system bus clock cycle
b-l CO
- system bus is 300 MHz or 225 MHz depending on bootstrap value.)
15:8 ag_pir Peak Information Rate for the Agent
The PIR is greater than or equal to the CIR. Bandwidth which exceeds PIR is marked
red.
0x00: 0 MB/s
0x01: 8 MB/s
...
0x40: 512 MB/s
18 TEK
...
0xFF: 2040 MB/s (Max)
7:0 ag_cir Committed Information Rate for the Agent
Bandwidth which falls below the CIR is marked green. BW which exceeds the CIR but
is below the EIR is marked yellow.
0x00: 0 MB/s
0x01: 8 MB/s
@
...
RD A
0x40: 512 MB/s (default)
...
0xFF: 2040 MB/s (Max)
R DI
1E006010 DRAM_SIZE DRAM Size config 0000000
FO ME
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dra
m_
size
_1g
Type RW
Reset 0
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
Bit(s) Name Description
ON
0 dram_size_1g Dram size:
0: dram size is small or equal to 512MB
1: dram size is equal to 1GB
n U TI
t.c EN
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
2.18 Analog Macro Control
ON
n U TI
t.c EN
.ne ID
ink NF
b-l CO
18 TEK
@
RD A
R DI
FO ME
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MT7621 PROGRAMMING GUIDE
L Y
2.18.1 Registers
SE AL
ANA_CTRL Changes LOG
ON
Revision Date Author Change Log
1.1 2012/2 Diary draft
1.2 2012/11/28 Jeffrey change base address and review.
n U TI
Module name: ANA_CTRL Base address: (+1E000F00h)
t.c EN
Address Name Widt Register Function
h
1E000F00 XTAL_CTRL_1 32 XTAL control and status 1
1E000F04 XTAL_CTRL_2 32 XTAL control and status 2
.ne ID
1E000F08 XDRV_CTRL_1 32 XDRV control and status 1
1E000F0C CBG_CTRL_1 32 CBG control and status 1
1E000F10 PLLGP_CTRL_1 32 PLLGP control and status 1
ink NF
1E000F14 PLLGP_CTRL_2 32 PLLGP control and status 2
1E000F18 PLLGP_CTRL_3 32 PLLGP control and status 3
1E000F1C PLLGP_CTRL_4 32 PLLGP control and status 4
1E000F20 PLLGP_CTRL_5 32 PLLGP control and status 5
b-l CO
1E000F24 PLLGP_CTRL_6 32 PLLGP control and status 6
1E000F28 PLLGP_CTRL_7 32 PLLGP control and status 7
1E000F2C PLLGP_CTRL_8 32 PLLGP control and status 8
1E000F30 DA_CTRL_1 32 DA control and status 1
18 TEK
1E000F00 XTAL_CTRL_ XTAL control and status 1 0000800
1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
_XP
@
TL_
RD A
RG_XPTL_RESERVE2_D0 AM
P_V
TH[
4:4]
R DI
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG
FO ME
_XP
_XP RG
TL_
TL_ _XP
RG_XPTL_AMP_VTH[3:0 VR RG_XPTL_GM_P
AM TL_ RG_XPTL_CAP_ENB
] EG WD
PM CH
_LP
ON G
F_E
_EN
NB
Type RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description
31:20 RG_XPTL_RESERVE2 RG_XPTL_RESERVE2_D0
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MT7621 PROGRAMMING GUIDE
L Y
_D0 12'b000000000000: NORMAL/SCAN/OLT mode
SE AL
16:12 RG_XPTL_AMP_VTH XSTAL amplitude monitor threshold select
ON
00001: 0.9V
00010: 1.2V
00100: 1.5V
01000: 1.8V
10000: 2.1V
n U TI
11 RG_XPTL_AMPMON_ XSTAL amplitude monitor enable
EN 1'b1: NORMAL/SCAN/OLT mode
10 RG_XPTL_CHG GM pwd and CAP RG change
1'b0: NORMAL/SCAN/OLT mode
t.c EN
9:4 RG_XPTL_CAP_ENB on-chip capacitor disable
6'b000000: NORMAL/SCAN/OLT mode
3 RG_XPTL_VREG_LPF Regulator LPF disable
_ENB 1'b0: NORMAL/SCAN/OLT mode
.ne ID
2:0 RG_XPTL_GM_PWD XSTAL gain adjustment
ink NF 3'b000: NORMAL/SCAN/OLT mode
1E000F04 XTAL_CTRL_ XTAL control and status 2 0000008
2 8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
b-l CO
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG RG RG RG
_XP _XP _XP _XP
_XP
TL_ TL_ TL_ TL_
TL_ RG_XPTL_MON_ RG_XPTL_DXP_D RG_XPTL_AXP_D
MO MO DX AX
DIV DRV RV RV
18 TEK
N_ N_ P_C P_C
2_E
DC CK K_E K_E
N
_EN _EN N N
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 1 0 0 0 1 0 0 0
Bit(s) Name Description
@
13 RG_XPTL_DIV2_EN 1'b0: NORMAL/SCAN/OLT mode
RD A
12 RG_XPTL_MON_DC_ 1'b0: NORMAL/SCAN/OLT mode
EN
11 RG_XPTL_MON_CK_ 1'b0: NORMAL/SCAN/OLT mode
R DI
EN
10:8 RG_XPTL_MON_DRV 3'b000: NORMAL/SCAN/OLT mode
7 RG_XPTL_DXP_CK_E enable rg for DXP ck
N
FO ME
1'b1: NORMAL/SCAN/OLT mode
6:4 RG_XPTL_DXP_DRV XSTAL gain adjustment
3'b000: NORMAL/SCAN/OLT mode
3 RG_XPTL_AXP_CK_E enable rg for AXP ck
N 1'b1: NORMAL/SCAN/OLT mode
2:0 RG_XPTL_AXP_DRV XSTAL gain adjustment
3'b000: NORMAL/SCAN/OLT mode
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MT7621 PROGRAMMING GUIDE
L Y
1E000F08 XDRV_CTRL_ XDRV control and status 1 0000000
SE AL
1 0
ON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
RG _XD
_XD RV_
n U TI
RV_ OB
EN UF_
EN
Type RW RW
Reset
t.c EN
0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_XDRV_DRV RG_XDRV_RSV
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.ne ID
Bit(s) Name Description
24 RG_XDRV_EN CLOCK SQUARE PWD signal
0: Clock square power down
1: Clock square power on
ink NF
1'b1: NORMAL mode.
1'b0: SCAN/OLT mode.
16 RG_XDRV_OBUF_EN CLOCK SQUARE PWD signal
0: Clock square power down
1: Clock square power on
b-l CO
1'b1: NORMAL mode.
1'b0: SCAN/OLT mode.
14:12 RG_XDRV_DRV XSTAL gain adjustment
3'b000: NORMAL/SCAN/OLT mode
11:0 RG_XDRV_RSV 12'b000000000000: NORMAL/SCAN/OLT mode
18 TEK
1E000F0C CBG_CTRL_1 CBG control and status 1 0080215
7
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_CBG_AVOUTSEL RG_CBG_SET RG_CBG_TRIM
Type RW RW RW
@
Reset 0 0 0 0 0 0 0 0 1 0 0 0
RD A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_CBG_ RG_CBG_
RG_CBG_CHPSET RG_CBG_PWSET
RASEL RBSEL
R DI
Type RW RW RW RW
Reset 1 0 0 1 0 1 0 1 0 1 1 1
Bit(s) Name Description
FO ME
31:28 RG_CBG_AVOUTSEL Analog monitor out selection
0000: disbale
0001:
0010:
0011:
0100: USB3 (ADA_SSUSB_MONOUT)
0101: PLLGP (ADA_PLLGP_MON_DC)
0110:
0111: XPTL (ADA_XPTL_MON_DC)
1000: PCIe_x1 P2 (ADA_PE1_NS_VTOUT_P2)
1001: PCIe_x2 P1/P0 (ADA_PE1_NS_VTOUT)
others: reserved
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MT7621 PROGRAMMING GUIDE
L Y
4'b0000: NORMAL/SCAN/OLT mode
SE AL
27:24 RG_CBG_SET CBG set
ON
4'b0000: NORMAL/SCAN/OLT mode
23:20 RG_CBG_TRIM Bandgap VRT reference voltage selection
???
4'b1000: NORMAL/SCAN/OLT mode
n U TI
13:12 RG_CBG_RASEL Bandgap RA selection
2'b10: NORMAL/SCAN/OLT mode
9:8 RG_CBG_RBSEL Bandgap RB selection
2'b01: NORMAL/SCAN/OLT mode
t.c EN
7:4 RG_CBG_CHPSET Bandgap chopper set
[3] reserved
[2] Enable
0: disable
1: enable
.ne ID
[1:0] refclk dividing ratio
00: /2
01: /4
10: /8
11: /16
ink NF
4'b0101: NORMAL/SCAN/OLT mode
3:0 RG_CBG_PWSET Bandgap power force mode set
[3] force mode enable
[2] Bandgap power down bar
[1] Current mirror power down bar
[0] Low pass enable
b-l CO
4'b0111: NORMAL/SCAN/OLT mode
1E000F10 PLLGP_CTRL PLLGP control and status 1 801510E
_1 0
18 TEK
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
_G
MP
RG_GMPLL_FBDIV
LL_
PW
D
Type RW RW
@
Reset 1 0 0 1 0 1 0 1
RD A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_GMPL RG_GMPL RG_GMPL RG_GMPL RG_GMPLL_DIVE
L_PREDIV L_POSDIV L_CKCTRL L_FBSEL N
R DI
Type RW RW RW RW RW
Reset 0 1 0 0 1 1 1 0 0 0 0
Bit(s) Name Description
FO ME
31 RG_GMPLL_PWD Power Down
1'b0: Power On
1'b1: Power Down
1'b1: NORMAL/SCAN mode.
1'b0: OLT mode.
22:16 RG_GMPLL_FBDIV Feedback divide ratio (N+1 Divider)
7'd0: /1
7'd1: /2
7'd127: /128
13:12 RG_GMPLL_PREDIV Pre-divider ratio
2'b00: Fref = Fin/1
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MT7621 PROGRAMMING GUIDE
L Y
2'b01: Fref = Fin/2
2'b1X: Fref = Fin/4
SE AL
9:8 RG_GMPLL_POSDIV Post-divider ratio for single-phase output
ON
2'b00: VCO/1
2'b01: VCO/2
2'b1X: VCO/4
7:6 RG_GMPLL_CKCTRL Fast Slew Time Control
n U TI
2'b00: 2^9 * Tin
2'b01: 2^8 * Tin
2'b10: 2^7 * Tin
2'b11: 2^6 * Tin
t.c EN
5:4 RG_GMPLL_FBSEL Feedback clock select
(Fvco output < 700MHz => 2'b00
Fvco output > 700MHz => 2'b01)
2'b00: Fvco/1
2'b01: Fvco/2
2'b1X: Fvco/4
.ne ID
2:0 RG_GMPLL_DIVEN Time domain cap multiplication ratio
3'd0: x1
3'd1: x2
3'd6: x64
ink NF
1E000F14 PLLGP_CTRL PLLGP control and status 2 01401D6
_2 1
b-l CO
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
RG RG RG
RG _G RG
RG RG RG RG _G _G _G
_G MP _G
_G _G _G _G MP MP MP
MP LL_ MP
MP MP MP MP LL_ LL_ LL_ RG_GMPLL_RESERVE
LL_ MO LL_
LL_ LL_ LL_ LL_ MO AC VO
FPE NC FM
18 TEK
BP BR HF LF NE CE DE
N KE EN
N N N
N
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_APLL_FBDIV
RG_APLL_ RG_APLL_ RG_APLL_ RG_APLL_
PREDIV POSDIV CKCTRL FBSEL
Type RW RW RW RW RW
@
Reset 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1
RD A
Bit(s) Name Description
R DI
31 RG_GMPLL_BP Capacitance adjustment for Bandiwdth
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
1'b0: When RG_APLL_BR=1'b0
1'b1: When RG_APLL_BR=1'b1
FO ME
30 RG_GMPLL_BR Resistance adjustment for Bandwidth
1'b0: BW = Fref/10
1'b1: BW = Fref/20
1'b0: BW = Fref/10
1'b1: BW = Fref/20
29 RG_GMPLL_HF Boost to 1.4GHz don't quarantee MP
1'b0: Normal
1'b1: 1.4GHz Band
1'b0: Normal
1'b1: 1.4GHz Band
28 RG_GMPLL_LF Frequency Band Control
PGMT7621_V.1.0_130607 Page 338 of 349
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MT7621 PROGRAMMING GUIDE
L Y
1'b0: Band > 700MHz
1'b1: Band < 700MHz
SE AL
1'b0: Band > 700MHz
ON
1'b1: Band < 700MHz
27 RG_GMPLL_FPEN PLL four phase output enable
1'b0: 2 phase output
1'b1: 4 phase output
n U TI
1'b0: 2 phase output
1'b1: 4 phase output
26 RG_GMPLL_MONEN Monitor for debug enable
1'b0: Disable
t.c EN
1'b1: Enable
1'b0: Disable
1'b1: Enable
25 RG_GMPLL_ACCEN Fast Slew Enable
1'b0: Disable
1'b1: Enable
.ne ID
1'b0: Disable
1'b1: Enable
24 RG_GMPLL_VODEN CHP OverDrive Enable
1'b0: Disable
ink NF
1'b1: Enable
1'b0: Disable, and OLT mode
1'b1: Enable
22 RG_GMPLL_MONCKE
N
b-l CO
20 RG_GMPLL_FMEN PLL Ref/FB monitor clock enable
1'b0: Disable
1'b1: Enable
1'b0: Disable
1'b1: Enable
19:16 RG_GMPLL_RESERV
E
18 TEK
14:8 RG_APLL_FBDIV Feedback divide ratio
7'd0: /1
7'd1: /2
7'd127: /128
7'd0: /1
7'd1: /2
7'd127: /128
7:6 RG_APLL_PREDIV Pre-divider ratio
@
RD A
2'b00: /1
2'b01: /2
2'b1X: /4
2'b00: /1
R DI
2'b01: /2
2'b1X: /4
5:4 RG_APLL_POSDIV Post-divider ratio
2'b00: /1
FO ME
2'b01: /2
2'b1X: /4
2'b00: /1
2'b01: /2
2'b1X: /4
3:2 RG_APLL_CKCTRL Fast Slew & K-Band Time Control
2'b00: 2^9 * Tref
2'b01: 2^8 * Tref
2'b10: 2^7 * Tref
2'b11: 2^6 * Tref
2'b00: 2^9 * Tref
2'b01: 2^8 * Tref
PGMT7621_V.1.0_130607 Page 339 of 349
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MT7621 PROGRAMMING GUIDE
L Y
2'b10: 2^7 * Tref
2'b11: 2^6 * Tref
SE AL
1:0 RG_APLL_FBSEL Feedback clock select
ON
2'b00: Fvco/1
2'b01: Fvco/2
2'b1X: Fvco/4
(Fvco output < 700MHz => 2'b00
n U TI
Fvco output > 700MHz => 2'b01)
2'b00: Fvco/1
2'b01: Fvco/2
2'b1X: Fvco/4
t.c EN
1E000F18 PLLGP_CTRL PLLGP control and status 3 38233D0
_3 E
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG
_AP
RG_APLL_BP LL_ RG_APLL_DIVEN RG_APLL_BR RG_APLL_BIC
FPE
ink NF
N
Type RW RW RW RW RW
Reset 0 0 1 1 1 0 0 0 0 1 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG
RG
RG _AP
b-l CO
_AP _AP
_AP LL_
LL_ LL_
RG_APLL_ LL_ AU
RG_APLL_BIR AU LO
BC AC TO
TO AD
CE K_L
K_V _RS
N OA
CO TB
D
Type RW RW RW RW RW RW
18 TEK
Reset 1 1 1 1 0 1 0 1 1 1
Bit(s) Name Description
31:28 RG_APLL_BP P-path capacitance adjustment
MSB=1pF
LSB=125fF
27 RG_APLL_FPEN PLL four phase output enable
@
1'b0: 2 phase output
RD A
1'b1: 4 phase output
1'b0: 2 phase output
1'b1: 4 phase output
R DI
26:24 RG_APLL_DIVEN Time domain cap multiplication ratio
3'd0: x1
3'd1: x2
3'd6: x64
FO ME
3'd0: x1
3'd1: x2
3'd6: x64
22:20 RG_APLL_BR P-path resistance adjustment
100:20kohm
010:40kohm
001:60kohm
000:80kohm
100: 20kohm
010: 40kohm
001: 60kohm
000: 80kohm
PGMT7621_V.1.0_130607 Page 340 of 349
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MT7621 PROGRAMMING GUIDE
L Y
18:16 RG_APLL_BIC I-path current adjustment
SE AL
6.25u 6.25u 3.125u
ON
13:12 RG_APLL_BC I-path capacitance adjustment
00:0.5pF
01:1pF
10:1.5pF
11:2pF
n U TI
00: 0.5pF
01: 1pF
10: 1.5pF
11: 2pF
t.c EN
11:8 RG_APLL_BIR P-path current adjustment
25u 25u 12.5u 6.25u
4 RG_APLL_ACCEN Fast Slew Enable
1'b0: Disable
1'b1: Enable
.ne ID
1'b0: Disable
1'b1: Enable
3 RG_APLL_AUTOK_VC Band calibration enable
O 1'b0: Disable
1'b1: Enable
ink NF
1'b0: Disable
1'b1: Enable
2 RG_APLL_AUTOK_LO Load last-time band calibration result
AD 1'b0: Use register setting
1'b1: Load
b-l CO
1'b0: Use register setting
1'b1: Load
1 RG_APLL_LOAD_RST Band calibration result register reset
B 1'b0: Reset
1'b1: Normal
1'b0: Reset
1'b1: Normal
18 TEK
1E000F1C PLLGP_CTRL PLLGP control and status 4 8012000
_4 4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
@
RG
RD A
RG RG _AP
RG RG RG
_AP _AP LL_
_AP _AP _AP
LL_ LL_ RE
LL_ RG_APLL_BAND LL_ LL_
VO DD SE
R DI
PW CK FM
DE SE RV
D SEL EN
N N E[4:
4]
Type RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 1 0 0 1 0
FO ME
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG
_AP RG RG
RG _AP RG RG RG
RG LL_ _AP _AP
_AP LL_ _AP _AP _AP
_AP FIF LL_ LL_
LL_ PC LL_ LL_ LL_
RG_APLL_RESERVE[3:0 LL_ O_ DD DD
DD W_ DD DD DD
] NC ST S_P S_P
S_R NC S_H S_R S_P
PO AR RE I_P
ST PO F_E ST_ WD
_EN T_ DIV L_E
B _C N SEL B
MA 2 NB
HG
N
Type RW RW RW RW RW RW RW RW RW RW
PGMT7621_V.1.0_130607 Page 341 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0
SE AL
ON
Bit(s) Name Description
31 RG_APLL_PWD Power Down
1'b0: Power On
1'b1: Power Down
n U TI
1'b0: Power On/ OLT mode
1'b1: Power Down/ SCAN mode
29:24 RG_APLL_BAND Manual PLL Band Selection
6'b000001: Lowest Band
t.c EN
6'b111111: Highest Band
6'b000001: Lowest Band
6'b111111: Highest Band
20 RG_APLL_VODEN CHP OverDrive Enable
1'b0: Disable
1'b1: Enable
.ne ID
1'b0: Disable/OLT mode
1'b1: Enable
19 RG_APLL_CKSEL 00: XTAL_CK = 40MHz
01: ARMPLL_CK
ink NF
00: XTAL_CK = 40MHz
01: ARMPLL_CK
18 RG_APLL_FMEN PLL Ref/FB monitor clock enable
1'b0: Disable
1'b1: Enable
1'b0: Disable
b-l CO
1'b1: Enable
17 RG_APLL_DDSEN DDS Feedback Enable
1'b0: Disable
1'b1: Enable
1'b0: Disable
1'b1: Enable
18 TEK
16:12 RG_APLL_RESERVE
8 RG_APLL_DDS_RSTB APLL_DDS NCPO PI reset bar
1'b1: SCAN / OLT mode
7 RG_APLL_NCPO_EN APLL_DDS NCPO enable
1'b1: SCAN / OLT mode
6 RG_APLL_PCW_NCP APLL_DDS PCW asynchrounous clock
O_CHG
@
RD A
5 RG_APLL_FIFO_STA APLL_DDS FIFO manual start
RT_MAN
4 RG_APLL_DDS_HF_E APLL_DDS high frequency mode enable
R DI
N
3 RG_APLL_DDS_PRE APLL_DDS predivide by 2
DIV2
2 RG_APLL_DDS_PI_PL APLL_DDS PI pull low function enable bar
FO ME
_ENB
1 RG_APLL_DDS_RST_ APLL_DDS PI reset selection (0:INA/INB 1:DIG_RST)
SEL
0 RG_APLL_DDS_PWD APLL_DDS PI power down bar
B 1'b1: OLT mode.
1'b0: SCAN mode.
1E000F20 PLLGP_CTRL PLLGP control and status 5 1C7DBF
_5 48
PGMT7621_V.1.0_130607 Page 342 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SE AL
Name RG_APLL_PCW_NCPO[30:16]
Type RW
ON
Reset 0 0 1 1 1 0 0 0 1 1 1 1 1 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_APLL_PCW_NCPO[15:0]
Type RW
n U TI
Reset 1 0 1 1 1 1 1 1 0 1 0 0 1 0 0 0
Bit(s) Name Description
t.c EN
30:0 RG_APLL_PCW_NCP APLL_DDS NCPO PCW
O
1E000F24 PLLGP_CTRL PLLGP control and status 6 0148400
.ne ID
_6 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG RG RG RG RG
_AP _PL _PL _PL _PL
ink NF
LL_ LG LG LG LG
CL RG_APLL_DDS_PI_C P_B P_B P_A P_A
K_P IAS IAS BIS BIS
H_I _RS _P T_D T_D
NV T WD IV1 IV2
Type RW RW RW RW RW RW
b-l CO
Reset 1 0 1 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
RG
RG
_PL
_PL _PL
LG
LG LG
P_A RG_PLLGP_ABIST_DIV RG_PLLGP_MONSEL
P_T P_S
BIS
18 TEK
EST EL_
T_P
_EN CK
WD
Type RW RW RW RW RW
Reset 0 1 0 0 0 0 0 0 0 0 0 0 1
Bit(s) Name Description
24 RG_APLL_CLK_PH_I APLL_DDS clock inversion
@
NV
RD A
23:20 RG_APLL_DDS_PI_C APLL_DDS PI capacitor adjustment
19 RG_PLLGP_BIAS_RS Constant-Gm Bias Reset
R DI
T 1'b0: Use bias LPF for reference current
1'b1: Bybpass bias LPF initially
18 RG_PLLGP_BIAS_PW Constant-Gm Bias Power Down
D 1'b0:Power On
1'b1: Power Down
FO ME
1'b0: OLT mode.
1'b1: SCAN mode.
17 RG_PLLGP_ABIST_DI ABIST clock div 1
V1
16 RG_PLLGP_ABIST_DI ABIST clock div 2
V2
15 RG_PLLGP_TEST_EN PLL group test mode enable
0:disable
1:enable
14 RG_PLLGP_ABIST_P PLL group ABIST power down
PGMT7621_V.1.0_130607 Page 343 of 349
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MT7621 PROGRAMMING GUIDE
L Y
WD 0: normal
1: power down
SE AL
1'b0: OLT mode.
ON
1'b1: SCAN mode.
13:8 RG_PLLGP_ABIST_DI Selected clock / (RG_PLL_ABIST_DIV[5:0]+2)/2
V
7:4 RG_PLLGP_MONSEL PLL group monitor control
n U TI
0 RG_PLLGP_SEL_CK PLL group test mode control
0: AIO mode
1: CLK mode
t.c EN
1E000F28 PLLGP_CTRL PLLGP control and status 7 0000000
_7 1
.ne ID
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_APLL_DDS_DMY
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ink NF
Name RG
RG
RG _AP RG
_AP RG
_AP LL_ _PL
LL_ _AP
LL_ DD LG
MO LL_
MO S_ P_D
NC DIV
NE MO ET_
b-l CO
KE 34
N NE EN
N
N
Type RW RW RW RW RW
Reset 0 0 0 0 1
Bit(s) Name Description
18 TEK
27:16 RG_APLL_DDS_DMY APLL_DDS dummy registers
4 RG_APLL_MONEN
3 RG_APLL_MONCKEN
2 RG_APLL_DDS_MON
EN
1 RG_APLL_DIV34
@
0 RG_PLLGP_DET_EN
RD A
R DI
1E000F2C PLLGP_CTRL PLLGP control and status 8 0001150
_8 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RG_PLLGP_RESERVE
FO ME
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG
_US
RG_USBDIV BDI
V_E
N
Type RW RW
Reset 0 0 1 0 1 0 1 1
PGMT7621_V.1.0_130607 Page 344 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Bit(s) Name Description
SE AL
31:16 RG_PLLGP_RESERV dummy reg
ON
E
14:8 RG_USBDIV Feedback divide ratio (N+1 Divider)
7'd0: /1
7'd1: /2
n U TI
7'd127: /128
0 RG_USBDIV_EN
t.c EN
1E000F30 DA_CTRL_1 DA control and status 1 0000001
F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
.ne ID
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DA
DA DA DA
ink NF
DA_ _XP
_C _C _XP
CB TL_
BG BG TL_
G_L CL
_B _IM VR
PF_ KS
G_ R_E EG
EN Q_
EN N _EN
EN
b-l CO
Type RW RW RW RW RW
Reset 1 1 1 1 1
Bit(s) Name Description
4 DA_CBG_BG_EN Bandgap enable
1'b0: disable
1'b1: enable
18 TEK
3 DA_CBG_IMR_EN Current mirror enable
1'b0: disable
1'b1: enable
2 DA_CBG_LPF_EN Low pass filter enable
1'b0: disable (time constant=0.3us, settle needs 2us)
1'b1: enable (time constant=4us, settle needs 25us. BW= 40KHz)
@
1 DA_XPTL_VREG_EN Crystal PWD signal
RD A
0: Crystal power down
1: Crystal power on
0 DA_XPTL_CLKSQ_EN CLOCK SQUARE EN signal
R DI
0: Clock square power down
1: Clock square power on
FO ME
PGMT7621_V.1.0_130607 Page 345 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
3. List
ON
Abbrev. Description Abbrev. Description
AC Access Category CRC Cyclic Redundancy Check
ACK Acknowledge/ Acknowledgement CSR Control Status Register
n U TI
ACL Access Control List CTS Clear to Send
ACPR Adjacent Channel Power Ratio CW Contention Window
AD/DA Analog to Digital/Digital to Analog CWmax Maximum Contention Window
t.c EN
converter CWmin Minimum Contention Window
ADC Analog-to-Digital Converter DAC Digital-To-Analog Converter
AES Advanced Encryption Standard DCF Distributed Coordination Function
AFC Automatic Frequency Calibration DDONE DMA Done
.ne ID
AGC Auto Gain Control DDR Double Data Rate
AIFS Arbitration Inter-Frame Space DFT Discrete Fourier Transform
AIFSN Arbitration Inter-Frame Spacing DIFS DCF Inter-Frame Space
Number
ink NF
DMA Direct Memory Access
ALC Automatic Level Control DQ DRAM Data
A-MPDU Aggregate MAC Protocol Data Unit DQS Data Strobe
A-MSDU Aggregation of MAC Service Data Units DSCP Differentiated Services Code Point
b-l CO
AP Access Point DSP Digital Signal Processor
ASIC Application-Specific Integrated Circuit DW DWORD
ASME American Society of Mechanical EAP Expert Antenna Processor
Engineers
ED Energy Detection
ASYNC Asynchronous EDCA Enhanced Distributed Channel Access
BA Block Acknowledgement
18 TEK
EECS EEPROM chip select
BAC Block Acknowledgement Control EEDI EEPROM data input
BAR Base Address Register
EEDO EEPROM data output
BBP Baseband Processor EEPROM Electrically Erasable Programmable
BGSEL Band Gap Select Read-Only Memory
BIST Built-In Self-Test eFUSE electrical Fuse
@
BSC Basic Spacing between Centers EESK EEPROM source clock
RD A
BJT Bipolar Junction Transistor EIFS Extended Inter-Frame Space
BSSID Basic Service Set Identifier EIV Extend Initialization Vector
R DI
BW Bandwidth EVM Error Vector Magnitude
CAS Column Address Strobe FDS Frequency Domain Spreading
CCA Clear Channel Assessment FEM Front-End Module
FO ME
CCK Complementary Code Keying FEQ Frequency Equalization
CCMP Counter Mode with Cipher Block FIFO First In First Out
Chaining Message Authentication
FSM Finite-State Machine
Code Protocol
GDM GTP Director Module
CCX Cisco Compatible Extensions
GEM GPON Encapsulation Method
CF-END Control Frame End
GF Green Field
CF-ACK Control Frame Acknowledgement
GND Ground
CLK Clock
GP General Purpose
CPU Central Processing Unit
PGMT7621_V.1.0_130607 Page 346 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Abbrev. Description Abbrev. Description
SE AL
GPO General Purpose Output MLNA Monolithic Low Noise Amplifier
ON
GPON Gigabit Passive Optical Network MM Mixed Mode
GPIO General Purpose Input/Output MOSFET Metal Oxide Semiconductor Field
GPRS General Packet Radio Service Effect Transistor
n U TI
GTP GPRS Tunneling Protocol MPDU MAC Protocol Data Units
HCCA HCF Controlled Channel Access MSB Most Significant Bit
HCF Hybrid Coordination Function NAV Network Allocation Vector
t.c EN
HT High Throughput NAS Network-Attached Server
HTC High Throughput Control NAT Network Address Translation
I In phase NDP Null Data Packet
ICV Integrity Check Value NVM Non-Volatile Memory
.ne ID
IFS Inter-Frame Space OCP Open Core Protocol
iNIC Intelligent Network Interface Card ODT On-die Termination
IV Initialization Vector Oen Output Enable
2
OFDM Orthogonal Frequency-Division
ink NF
IC Inter-Integrated Circuit
IS
2
Integrated Inter-Chip Sound Multiplexing
I/O Input/Output OoS Out-of-Service
IPI Idle Power Indicator OSC Open Sound Control
PA Power Amplifier
b-l CO
IQ In phase/Quadrature phase
JEDEC Joint Electron Devices Engineering PAPE Provider Authentication Policy
Council Extension
JTAG Joint Test Action Group PBC Push Button Configuration
kbps kilo (1000) bits per second PBF Packet Buffer
KB Kilo (1024) Bytes PCB Printed Circuit Board
18 TEK
LCP Linear Complementarity Problem PCF Point Coordination Function
LDO Low-Dropout Regulator PCM Pulse-Code Modulation
LDODIG LDO for DIGital part output voltage PD Preamble Detection
LED Light-Emitting Diode PFD Phase-Frequency Detector
LTSSM Link Training and Status State Machine PHY Physical Layer
@
LNA Low Noise Amplifier PIFS PCF Interframe Space
RD A
LO Local Oscillator PLCP Physical Layer Convergence Protocol
L-SIG Legacy Signal Field PLL Phase-Locked Loop
R DI
MAC Medium Access Control PME Physical Medium Entities
MCU Microcontroller Unit PMU Power Management Unit
MCS Modulation and Coding Scheme PN Packet Number
FO ME
MDC Management Data Clock PPLL Programmable PLL
MDIO Management Data Input/Output PROM Programmable Read-Only Memory
MEM Memory PSDU Physical layer Service Data Unit
MFB MCS Feedback PSI Power supply Strength Indication
MFS MFB Sequence PSM Power Save Mode
MIC Message Integrity Code PTN Packet Transport Network
MIMO Multiple-Input Multiple-Output QoS Quality of Service
MLD Multicast Listener Discovery Q Quadrature
PGMT7621_V.1.0_130607 Page 347 of 349
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MT7621 PROGRAMMING GUIDE
L Y
Abbrev. Description Abbrev. Description
SE AL
R2P Rbus to Pbus TA Transmitter Address
ON
RDG Reverse Direction Grant TBTT Target Beacon Transmission Time
RAM Random Access Memory TDLS Tunnel Direct Link Setup
RC Root Complex TKIP Temporal Key Integrity Protocol
n U TI
RF Radio Frequency TOS Tx Offset
RGMII Reduced Gigabit Media Independent TRSW Tx/Rx Switch
Interface TSF Timing Synchronization Function
t.c EN
RH Relative Humidity TSSI Transmit Signal Strength Indication
RoHS Restriction on Hazardous Substances Tx Transmit
ROM Read-Only Memory TxBF Transmit Beamforming
ROS Rx Offset TXD Transmitted Data
.ne ID
RSSI Received Signal Strength Indication TXDAC Transmit Digital-Analog Converter
(Indicator) TXINFO Transmit Information
RTS Request to Send TXOP Opportunity to Transmit
RvMII Reverse Media Independent Interface
ink NF
TXWI Tx Wireless Information
Rx Receive UART Universal Asynchronous Rx/ Tx
RXD Received Data USB Universal Serial Bus
RXINFO Receive Information UTIF Universal Test Interface
RXWI Receive Wireless Information
b-l CO
VGA Variable Gain Amplifier
S Stream VCO Voltage Controlled Oscillator
SDHC Secure Digital High Capacity VIH High Level Input Voltage
SDIO Secure Digital Input Output VIL Low Level Input Voltage
SDRAM Synchronous Dynamic Random Access VoIP Voice over IP
Memory
18 TEK
VPID Virtual Path Identifier
SEC Security WCID Wireless Client Identification
SGI Short Guard Interval WEP Wired Equivalent
SIFS Short Inter-Frame Space WI Wireless Information
SoC System-on-a-Chip WIV Wireless Information Valid
SPI Serial Peripheral Interface WMM Wi-Fi Multimedia
@
SRAM Static Random Access Memory WPA Wi-Fi Protected Access
RD A
SSCG Spread Spectrum Clock Generator WPDMA Wireless Polarization Division Multiple
STBC Space–Time Block Code Access
R DI
SW Switch Regulator WS Word Select
FO ME
PGMT7621_V.1.0_130607 Page 348 of 349
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MT7621 PROGRAMMING GUIDE
L Y
SE AL
4. Revision History
ON
Rev Date From Description
1.0 2013/06/7 Leon Chung Preliminary
n U TI
t.c EN
.ne ID
ink NF
This product is not designed for use in medical, life support applications. Do not use this product in these types of equipments or
b-l CO
applications .This document is subject to change without notice and Ralink assumes no responsibility for any inaccuracies that nay be
contained in this document. Ralink reserves the right to make change in the products to improve function, performance, reliability, and to
attempt to supply the best product possible.
18 TEK
@
RD A
R DI
FO ME
PGMT7621_V.1.0_130607 Page 349 of 349
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