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Lab5_Counter

This lab focuses on designing a 3-bit counter with an external input that can count in both clockwise and anticlockwise directions. Students will learn to build and simulate the counter using VHDL, including creating D Flip-Flops and a slow-down clock. The final task involves testing the counter on a BASYS 3 board and submitting a comprehensive lab report.

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3 views

Lab5_Counter

This lab focuses on designing a 3-bit counter with an external input that can count in both clockwise and anticlockwise directions. Students will learn to build and simulate the counter using VHDL, including creating D Flip-Flops and a slow-down clock. The final task involves testing the counter on a BASYS 3 board and submitting a comprehensive lab report.

Uploaded by

nadun.emailclient
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab 5 – Counter with External Input

CS 2052 Computer
CS1050 Computer Architecture
Organization and Digital Design
Dept. of Computer Science and Engineering, University of Moratuwa

Learning Outcomes
In this lab, we will design a 3-bit counter with an external input. After completing the lab,
you will be able to:
• design and develop a 3-bit counter
• count in clockwise and anticlockwise directions based on an external input
• verify its functionality via simulation and on the development board

Introduction
A register that goes through a predetermined sequence of states is called a counter. In
this lab, we will design a 3-bit counter that can show the sequence of LEDs (dark circles indicate
LEDs that are lit) defined in Fig. 1. We will control the direction of counting (clockwise or
anticlockwise) based on an external input. When the input button is switched off, we will count in
the clockwise direction. When it is switched on, we will count in the anticlockwise direction.

Figure 1 – Counter pattern.


Building the Circuits
Step 1: Using the Excitation Table of a D Flip-Flop complete the following table.
Qt Button Qt+1 D2 D1 D0
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 0 1
0 0 0 1 1 0 0
0 0 1 0 0 1 1
0 0 1 1 0 0 0
… … … … … … …
… … … … … … …
Identify the inputs to D Flip Flops D0, D1, and D2. Use Karnaugh Maps to simplify
the expressions. Interpret the combinations that will not occur as don’t’ care.
Step 2: Building D Flip Flop.
In VHDL we can build a D Flip-Flop (FF) by defining its behavior. Let us build a D
FF like the one below:

where D is the data input, reset clears FF to 0 (i.e., resets the value of FF), and
FF is driven by a clock. Q and Qbar are the 2 outputs.
So far we have used VHDL to define the behavior of our circuits as a sequence
of logic operations (this is referred to as Structural Modelling). VHDL also allows
us to define how a circuit should behave more abstractly. This style of circuit
definition is referred to as VHDL Behavioral Modelling. Behavioral modeling
describes how the circuit should behave using high-level programming constructs
such as variables, conditions, and procedures. Given a circuit defined using
behavioral modeling, the VHDL synthesizer tool will decide the actual circuit
implementation.
Crete a new VHDL file and name it as . Set the inputs as , , and
and outputs as and .
Then add the code given in Fig. 2 to define the behavior of the D FF. The
process is the key structure that defines the behavior of the VHDL model. It
defines the functionality of an entity. Here we name the process as Clk. Then we
detect the rising edge of the clock using rising_edge()function. When the
clock is high, we either set the output based on the D input or reset it to 0, if reset
input is high (if Ref = ‘1’).
Figure 2 – Behavioral model of D flip-flop.

Simulate the D_FF using XSim and make sure it functions correctly. Name the
simulation files as .

Step 3: Building the slow down clock.


As we want our FF to respond based on the clock signal (i.e., at rising edge) we
need to use the internal clock of BASYS 3. However, the internal clock on
BASYS 3 runs at 100 MHz. At this rate, we will not be able to see the changes in
LEDs. Therefore, we need to slow down our clock input to at least a few hundred
milliseconds. While the clock on BASYS 3 can be slow down to some extent – by
changing the parameters in Design Constraints File – we can slow it down to a
few Hz from the initial 100 MHz.
Therefore, we use a slowdown counter, which can emit an output only when a
certain number of changes in the input is detected. For example, we can build an
entity that emits 1 Hz clock pulses for every 100 million clock pulses generated
by the 100 MHz clock. Fig. 3 shows the VHDL behavioral model for a 100 MHz to
1 Hz slow-down counter. In this example, we change the output clock plus every
0.5 seconds with a period of 1 second. count and clk_status are 2 variables
where count is an integer set to 1 and clk_status is a logic value set to 0.
Create a new VHDL file and name it as . Defines the input and output
as and , respectively.
Simulate the Slow_Clk and make sure it functions correctly. Name the simulation
files as . For simulation purposes, you may want to reduce 50
million to a smaller value like 5 or 10.

Step 4: Building the counter.


Create a VHDL file and name it as . Label in the inputs as (i.e.,
Direction Select), (reset), and (clock). Let the output be a 3-bit bus.
Figure 3 – Behavioral model of slowdown counter.

Connect input signal to in and internal output


to . Clocks connected to all 3 FFs should be based on .
Build the counter based on the Boolean expressions you derived in Step 1.
Following is part of the VHDL code to build the counter. You need to fill the
missing pieces. This is given as a reference only so you can understand the
structure of the solution.
architecture Behavioral of Counter is

component D_FF
port (
D : in STD_LOGIC;
Res: in STD_LOGIC;
Clk : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar : out STD_LOGIC);
end component;

component Slow_Clk
port (
Clk_in : in STD_LOGIC;
Clk_out: out STD_LOGIC);
end component;

signal D0, D1, D2 : std_logic; -- Internal signals


signal Q0, Q1, Q2 : std_logic; -- Internal signals
signal Clk_slow : std_logic; -- Internal clock

begin

Slow_Clk0 : Slow_Clk
port map (
Clk_in => Clk,
Clk_out => Clk_slow);

D0 <= ((not Q2) and (not Dir)) or (Q1 and Dir);


D1 <= ... --Fill missing details
D2 <= ... --Fill missing details

D_FF0 : D_FF
port map (
D => D0,
Res => Res,
Clk => Clk_slow,
Q => Q0);

D_FF1 : D_FF
port map (
...); --Fill missing details

D_FF2 : D_FF
port map (
...); --Fill missing details

Q(0) <= Q0;


... --Fill missing details

end Behavioral;

Verify the functionality of your counter using the simulator. Name the simulation
file as . For simulation purposes, you may want to reduce counter
value in slow-down counter, but make sure to reset it to 50 million before
generating the bitstream.

Step 5: Test on BASYS 3.


Connect switch as the external input and as the . Connect
outputs - to LEDs - .
To enable the internal clock, you need to uncomment the relevant lines on
Design Constraints File as in Fig. 4.

Figure 4 – Using the clock on BASYS 3.


Make sure to use by replacing the default values in all 3 lines. Here 10.00
-waveform {0 5} indicates a 100 MHz clock (i.e., delay of 10 ps) and signal
high to low ratio is 0.5.
Generate the programming file (i.e., bitstream) and load it to the BASYS 3 board.
Change the switches on the board and verify the functionality of your circuit.
Demonstrate the circuit to the instructor and get the Lab Completion Log singed.

Step 6: Lab Report


You need to submit a report for this lab. Your report should include the following:
• Student name, index number, and group. Do not attach a separate front
page
• State the assigned lab task in a few sentences
• Completed table in Step 1. Simplified expressions for D0, D1, and D2
using Karnaugh Maps
• All VHDL codes
• All timing diagrams
• Conclusions from the lab.
to the
Submit the lab report at thebeginning
moodle. of the next lab.

Bibliography
• Modeling Latches and Flip-flops, Xilinx, “Vivado Tutorial – Lab Workbook,” 2015.
• Modeling Registers and Counters, Xilinx, “Vivado Tutorial – Lab Workbook,” 2015.
Prepared By
• Dilum Bandara, PhD – Mar 26, 2014.
• Updated on Oct 11, 2018

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