ST72334J/N,

ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

■ Memories
– 8K or 16K Program memory (ROM or single
voltage FLASH) with read-out protection and
in-situ programming (remote ISP)
– 256 bytes EEPROM Data memory (with read-
out protection option in ROM devices)
– 384 or 512 bytes RAM
■ Clock, Reset and Supply Management
PSDIP56 PSDIP42
– Enhanced reset system
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
– Beep and clock-out capabilities
TQFP64 TQFP44
■ Interrupt Management
14 x 14 10 x 10
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (4 vectors)
■ 44 or 32 I/O Ports ■ 1 Analog Peripheral
– 44 or 32 multifunctional bidirectional I/O lines: – 8-bit ADC with 8 input channels (6 only on
– 21 or 19 alternate function lines ST72334Jx, not available on ST72124J2)
– 12 or 8 high sink outputs
■ 4 Timers ■ Instruction Set
– Configurable watchdog timer – 8-bit data manipulation
– Realtime base – 63 basic instructions
– Two 16-bit timers with: 2 input captures (only – 17 main addressing modes
one on timer A), 2 output compares (only one
on timer A), External clock input on timer A, – 8 x 8 unsigned multiply instruction
PWM and Pulse generator modes – True bit manipulation
■ 2 Communications Interfaces
– SPI synchronous serial interface ■ Development Tools
– SCI asynchronous serial interface (LIN com- – Full hardware/software development package
patible)
Device Summary
Features ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
Program memory - bytes 8K 8K 16K 8K 16K 8K 16K 8K 16K
RAM (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256)
EEPROM - bytes - - - - - 256 256 256 256
Watchdog, Two 16-bit Timers, SPI, SCI
Peripherals
- ADC
Operating Supply 3.2V to 5.5V
CPU Frequency Up to 8 MHz (with up to 16 MHz oscillator)
Operating Temperature -40°C to +85°C (-40°C to +105/125°C optional)
Packages TQFP44 / SDIP42 TQFP64 / SDIP56 TQFP44 / SDIP42 TQFP64 / SDIP56

Rev. 2.4

July 2002 1/151

1
Table of Contents
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
5.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 DATA EEPROM Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 READ-OUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 31
10 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
151
12.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2/151
2
Table of Contents
12.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.3 REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
14 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
14.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 51
14.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
15 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
15.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
15.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
16.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
16.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
16.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
16.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
16.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
16.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
16.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 134
16.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
17 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
17.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
17.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 143
18.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
18.2 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
18.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
18.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
18.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
19 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

3/151

3
ST72334J/N, ST72314J/N, ST72124J

1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION

New Features available on the ST72C334 New Memory Locations in ST72C334
■ 8 or 16K FLASH/ROM with In-Situ ■ 20h: MISCR register becomes MISCR1 register
Programming and Read-out protection (naming change)
■ New ADC with a better accuracy and conversion ■ 29h: new control/status register for the MCC
time module
■ New configurable Clock, Reset and Supply ■ 2Bh: new control/status register for the Clock,
system Reset and Supply control. This register replaces
■ New power saving mode with real time base: the WDGSR register keeping the WDOGF flag
Active Halt compatibility.
■ Beep capability on PF1 ■ 40h: new MISCR2 register

■ New interrupt source: Clock security system

(CSS) or Main clock controller (MCC)
ST72C334 I/O Configuration and Pinout
■ Same pinout as ST72E331

■ PA6 and PA7 are true open drain I/O ports

without pull-up (same as ST72E331)
■ PA3, PB3, PB4 and PF2 have no pull-up
configuration (all I/Os present on TQFP44)
■ PA5:4, PC3:2, PE7:4 and PF7:6 have high sink
capabilities (20mA on N-buffer, 2mA on P-buffer
and pull-up). On the ST72E331, all these pads
(except PA5:4) were 2mA push-pull pads
without high sink capabilities. PA4 and PA5
were 20mA true open drains.

4/151
ST72334J/N, ST72314J/N, ST72124J

2 INTRODUCTION FLASH memory with byte-by-byte In-Situ Pro-

gramming (ISP) capability.
The ST72334J/N, ST72314J/N and ST72124J de-
vices are members of the ST7 microcontroller fam- Under software control, all devices can be placed
ily. They can be grouped as follows: in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
– ST72334J/N devices are designed for mid-range is in idle or standby state.
applications with Data EEPROM, ADC, SPI and
SCI interface capabilities. The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
– ST72314J/N devices target the same range of software developers, enabling the design of highly
applications but without Data EEPROM. efficient and compact application code. In addition
– ST72124J devices are for applications that do to standard 8-bit data management, all ST7 micro-
not need Data EEPROM and the ADC peripher- controllers feature true bit manipulation, 8x8 un-
al. signed multiplication and indirect addressing
modes.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc- For easy reference, all parametric data are located
tion set. in Section 16 on page 106.
The ST72C334J/N, ST72C314J/N and
ST72C124J versions feature single-voltage

Figure 1. General Block Diagram

8-BIT CORE
PROGRAM
ALU
MEMORY
(8K or 16K Bytes)
RESET
CONTROL
ISPSEL
RAM
VDD (384 or 512 Bytes)
VSS LVD

MULTI OSC EEPROM

OSC1 (256 Bytes)
+
OSC2 CLOCK FILTER
ADDRESS AND DATA BUS

MCC/RTC PA7:0
PORT A (8-BIT for N versions)
(5-BIT for J versions)
PORT B PB7:0
PORT F (8-BIT for N versions)
PF7,6,4,2:0 (5-BIT for J versions)
(6-BIT)
TIMER A PORT C

TIMER B PC7:0
BEEP (8-BIT)

PORT E SPI
PE7:0
(6-BIT for N versions)
(2-BIT for J versions) SCI PORT D
PD7:0
(8-BIT for N versions)
8-BIT ADC (6-BIT for J versions)
WATCHDOG
VDDA
VSSA

5/151
ST72334J/N, ST72314J/N, ST72124J

3 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout (N versions)

PE0 / TDO
PE1 / RDI

PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
ISPSEL
RESET
VDD_2

VSS_2
OSC1
OSC2
NC
NC

NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
(HS) PE4 1 48 VSS_1
(HS) PE5 2 47 VDD_1
(HS) PE6 3 46 PA3
(HS) PE7 4 45 PA2
ei0
PB0 5 44 PA1
PB1 6 43 PA0
PB2 ei2 42 PC7 / SS
7
PB3 8 41 PC6 / SCK / ISPCLK
PB4 9 40 PC5 / MOSI
PB5 10 39 PC4 / MISO / ISPDATA
PB6 11 ei3 38 PC3 (HS) / ICAP1_B
PB7 12 37 PC2 (HS) / ICAP2_B
AIN0 / PD0 13 36 PC1 / OCMP1_B
AIN1 / PD1 14 35 PC0 / OCMP2_B
AIN2 / PD2 15 ei1 34 VSS_0
AIN3 / PD3 16 33 VDD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_3
VSS_3
VDDA
VSSA

NC

NC
AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7

MCO / PF0

PF2

OCMP1_A / PF4

ICAP1_A / (HS) PF6

BEEP / PF1

EXTCLK_A / (HS) PF7

(HS) 20mA high sink capability

ei x associated external interrupt vector

6/151
ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont’d)

Figure 3. 56-Pin SDIP Package Pinout (N versions)

PB4 1 56 PB3
PB5 2 55 PB2
ei3 ei2
PB6 3 54 PB1
PB7 4 53 PB0
AIN0 / PD0 5 52 PE7 (HS)
AIN1 / PD1 6 51 PE6 (HS)
AIN2 / PD2 7 50 PE5 (HS)
AIN3 / PD3 8 49 PE4 (HS)
AIN4 / PD4 9 48 PE1 / RDI
AIN5 / PD5 10 47 PE0 / TDO
AIN6 / PD6 11 46 VDD_2
AIN7 / PD7 12 45 OSC1
VDDA 13 44 OSC2
VSSA 14 43 VSS_2
MCO / PF0 15 42 RESET
BEEP / PF1 16 ei1 41 ISPSEL
PF2 17 40 PA7 (HS)
OCMP1_A / PF4 18 39 PA6 (HS)I
ICAP1_A / (HS) PF6 19 38 PA5 (HS)
EXTCLK_A / (HS) PF7 20 37 PA4 (HS)
VDD_0 21 36 VSS_1
VSS_0 22 35 VDD_1
OCMP2_B / PC0 23 34 PA3
OCMP1_B / PC1 24 33 PA2
ei0
ICAP2_B / (HS) PC2 25 32 PA1
ICAP1_B / (HS) PC3 26 31 PA0
ISPDATA/ MISO / PC4 27 30 PC7 / SS
MOSI / PC5 28 29 PC6 / SCK / ISPCLK

(HS) 20mA high sink capability

eix associated external interrupt vector

7/151
ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont’d)

Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)

PE0 / TDO

PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
ISPSEL
RESET
VDD_2

VSS_2
OSC1
OSC2
44 43 42 41 40 39 38 37 36 35 34
PE1 / RDI 1 33 VSS_1
PB0 2 32 VDD_1
PB1 3 ei0 31 PA3
ei2
PB2 4 30 PC7 / SS
PB3 5 29 PC6 / SCK / ISPCLK
PB4 6 ei3 28 PC5 / MOSI
AIN0 / PD0 7 27 PC4 / MISO / ISPDATA
AIN1 / PD1 8 26 PC3 (HS) / ICAP1_B
AIN2 / PD2 9 25 PC2 (HS) / ICAP2_B
AIN3 / PD3 10 ei1 24 PC1 / OCMP1_B
AIN4 / PD4 11 23 PC0 / OCMP2_B
12 13 14 15 16 17 18 19 20 21 22
VDDA
VSSA
AIN5 / PD5

MCO / PF0

PF2
BEEP / PF1

OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
VDD_0
VSS_0

PB4 1 EI3 42 PB3

AIN0 / PD0 2 41 PB2
AIN1 / PD1 3 ei2 PB1
40
AIN2 / PD2 4 39 PB0
AIN3 / PD3 5 38 PE1 / RDI
AIN4 / PD4 6 37 PE0 / TDO
AIN5 / PD5 7 36 VDD_2
VDDA 8 35 OSC1
VSSA 9 34 OSC2
MCO / PF0 10 33 VSS_2
BEEP / PF1 11 ei1 32 RESET
PF2 12 31 ISPSEL
OCMP1_A / PF4 13 30 PA7 (HS)
ICAP1_A / (HS) PF6 14 29 PA6 (HS)
EXTCLK_A / (HS) PF7 15 28 PA5 (HS)
OCMP2_B / PC0 16 27 PA4 (HS)
OCMP1_B / PC1 17 26 VSS_1
ICAP2_B/ (HS) PC2 18 25 VDD_1
ICAP1_B / (HS) PC3 19 ei0 24 PA3
ISPDATA / MISO / PC4 20 23 PC7 / SS
MOSI / PC5 21 22 PC6 / SCK / ISPCLK

(HS) 20mA high sink capability

eix associated external interrupt vector

8/151
ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 16 "ELECTRICAL CHARACTERISTICS" on page
106.
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output: OD = open drain 2), PP = push-pull
Refer to Section 12 "I/O PORTS" on page 38 for more details on the software configuration of the I/O
ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n° Level Port Main
Type
TQFP64

Input Output function

Output
SDIP56

SDIP42
QFP44

Pin Name Alternate function

Input

(after
float
wpu

ana

OD

PP
int

reset)
1 49 PE4 (HS) I/O CT HS X X X X Port E4
2 50 PE5 (HS) I/O CT HS X X X X Port E5
3 51 PE6 (HS) I/O CT HS X X X X Port E6
4 52 PE7 (HS) I/O CT HS X X X X Port E7
5 53 2 39 PB0 I/O CT X ei2 X X Port B0
6 54 3 40 PB1 I/O CT X ei2 X X Port B1
7 55 4 41 PB2 I/O CT X ei2 X X Port B2
8 56 5 42 PB3 I/O CT X ei2 X X Port B3
9 1 6 1 PB4 I/O CT X ei3 X X Port B4
10 2 PB5 I/O CT X ei3 X X Port B5
11 3 PB6 I/O CT X ei3 X X Port B6
12 4 PB7 I/O CT X ei3 X X Port B7
13 5 7 2 PD0/AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0
14 6 8 3 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1
15 7 9 4 PD2/AIN2 I/O CT X X X X X Port D2 ADC Analog Input 2
16 8 10 5 PD3/AIN3 I/O CT X X X X X Port D3 ADC Analog Input 3
17 9 11 6 PD4/AIN4 I/O CT X X X X X Port D4 ADC Analog Input 4
18 10 12 7 PD5/AIN5 I/O CT X X X X X Port D5 ADC Analog Input 5
19 11 PD6/AIN6 I/O CT X X X X X Port D6 ADC Analog Input 6
20 12 PD7/AIN7 I/O CT X X X X X Port D7 ADC Analog Input 7
21 13 13 8 VDDA S Analog Power Supply Voltage
22 14 14 9 VSSA S Analog Ground Voltage
23 VDD_3 S Digital Main Supply Voltage

9/151
ST72334J/N, ST72314J/N, ST72124J

Pin n° Level Port Main

Type
TQFP64

Input Output function

Output
SDIP56

SDIP42

Pin Name Alternate function

QFP44

Input
(after

float
wpu

ana

OD

PP
int
reset)
24 VSS_3 S Digital Ground Voltage
25 15 15 10 PF0/MCO I/O CT X ei1 X X Port F0 Main clock output (fOSC/2)
26 16 16 11 PF1/BEEP I/O CT X ei1 X X Port F1 Beep signal output
27 17 17 12 PF2 I/O CT X ei1 X X Port F2
28 NC Not Connected
29 18 18 13 PF4/OCMP1_A I/O CT X X X X Port F4 Timer A Output Compare 1
30 NC Not Connected
31 19 19 14 PF6 (HS)/ICAP1_A I/O CT HS X X X X Port F6 Timer A Input Capture 1
32 20 20 15 PF7 (HS)/EXTCLK_A I/O CT HS X X X X Port F7 Timer A External Clock Source
33 21 21 VDD_0 S Digital Main Supply Voltage
34 22 22 VSS_0 S Digital Ground Voltage
35 23 23 16 PC0/OCMP2_B I/O CT X X X X Port C0 Timer B Output Compare 2
36 24 24 17 PC1/OCMP1_B I/O CT X X X X Port C1 Timer B Output Compare 1
37 25 25 18 PC2 (HS)/ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2
38 26 26 19 PC3 (HS)/ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1
39 27 27 20 PC4/MISO I/O CT X X X X Port C4 SPI Master In / Slave Out Data
40 28 28 21 PC5/MOSI I/O CT X X X X Port C5 SPI Master Out / Slave In Data
41 29 29 22 PC6/SCK I/O CT X X X X Port C6 SPI Serial Clock
42 30 30 23 PC7/SS I/O CT X X X X Port C7 SPI Slave Select (active low)
43 31 PA0 I/O CT X ei0 X X Port A0
44 32 PA1 I/O CT X ei0 X X Port A1
45 33 PA2 I/O CT X ei0 X X Port A2
46 34 31 24 PA3 I/O CT X ei0 X X Port A3
47 35 32 25 VDD_1 S Digital Main Supply Voltage
48 36 33 26 VSS_1 S Digital Ground Voltage
49 37 34 27 PA4 (HS) I/O CT HS X X X X Port A4
50 38 35 28 PA5 (HS) I/O CT HS X X X X Port A5
51 39 36 29 PA6 (HS) I/O CT HS X T Port A6
52 40 37 30 PA7 (HS) I/O CT HS X T Port A7
Must be tied low in user mode. In pro-
gramming mode when available, this pin
53 41 38 31 ISPSEL I
acts as In-Situ Programming mode se-
lection.
Top priority non maskable interrupt (ac-
54 42 39 32 RESET I/O C X X
tive low)
55 NC
Not Connected
56 NC
57 43 40 33 VSS_3 S Digital Ground Voltage
Resonator oscillator inverter output or
58 44 41 34 OSC2 3) O
capacitor input for RC oscillator

10/151
ST72334J/N, ST72314J/N, ST72124J

Pin n° Level Port Main

Type
TQFP64

Input Output function

Output
SDIP56

SDIP42

Pin Name Alternate function

QFP44

Input
(after

float
wpu

ana

OD

PP
int
reset)
External clock input or Resonator oscilla-
59 45 42 35 OSC1 3) I tor inverter input or resistor input for RC
oscillator
60 46 43 36 VDD_3 S Digital Main Supply Voltage
61 47 44 37 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out
62 48 1 38 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In
63 NC
Not Connected
64 NC

Notes:
1. In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See Section 12 "I/O PORTS" on page 38 and Section 16.8 "I/O PORT PIN CHAR-
ACTERISTICS" on page 127 for more details.
3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 3 "PIN DESCRIPTION" on page 6 and Section 16.5 "CLOCK AND TIM-
ING CHARACTERISTICS" on page 115 for more details.

11/151
ST72334J/N, ST72314J/N, ST72124J

4 REGISTER & MEMORY MAP

As shown in the Figure 5, the MCU is capable of space includes up to 256 bytes for the stack from
addressing 64K bytes of memories and I/O regis- 0100h to 01FFh.
ters. The highest address bytes contain the user reset
The available memory locations consist of 128 and interrupt vectors.
bytes of register locations, 384 or 512 bytes of IMPORTANT: Memory locations marked as “Re-
RAM, up to 256 bytes of data EEPROM and 4 or served” must never be accessed. Accessing a re-
8 Kbytes of user program memory. The RAM served area can have unpredictable effects on the
device.
Figure 5. Memory Map

0000h 0080h Short Addressing RAM

HW Registers Zero page
(see Table 2) (128 Bytes)
007Fh 00FFh
0080h 0100h Stack or
16-bit Addressing RAM
384 Bytes RAM (256 Bytes)
01FFh 01FFh

512 Bytes RAM

027Fh
0080h Short Addressing RAM
0200h / 0280h Zero page
Reserved 00FFh
(128 Bytes)
0BFFh 0100h
0C00h Stack or
256 Bytes Data EEPROM 16-bit Addressing RAM
0CFFh 01FFh (256 Bytes)
0D00h
Reserved 0200h 16-bit Addressing
BFFFh
RAM
C000h 027Fh
16K Bytes
E000h 8K Bytes Program C000h
Program Memory 16 KBytes
FFDFh Memory
E000h
FFE0h 8 KBytes
Interrupt & Reset Vectors FFFFh
(see Table 5 on page 33)
FFFFh

12/151
ST72334J/N, ST72314J/N, ST72124J

REGISTER & MEMORY MAP (Cont’d)

Table 2. Hardware Register Map

Register Reset
Address Block Register Name Remarks
Label Status

0000h PADR Port A Data Register 00h1) R/W

0001h Port A PADDR Port A Data Direction Register 00h R/W
0002h PAOR Port A Option Register 00h R/W 2)

0003h Reserved Area (1 Byte)

0004h PCDR Port C Data Register 00h1) R/W

0005h Port C PCDDR Port C Data Direction Register 00h R/W
0006h PCOR Port C Option Register 00h R/W

0007h Reserved Area (1 Byte)

0008h PBDR Port B Data Register 00h1) R/W

0009h Port B PBDDR Port B Data Direction Register 00h R/W
000Ah PBOR Port B Option Register 00h R/W 2)

000Bh Reserved Area (1 Byte)

000Ch PEDR Port E Data Register 00h1) R/W

000Dh Port E PEDDR Port E Data Direction Register 00h R/W
000Eh PEOR Port E Option Register 00h R/W 2)

000Fh Reserved Area (1 Byte)

0010h PDDR Port D Data Register 00h1) R/W

0011h Port D PDDDR Port D Data Direction Register 00h R/W
0012h PDOR Port D Option Register 00h R/W 2)

0013h Reserved Area (1 Byte)

0014h PFDR Port F Data Register 00h1) R/W

0015h Port F PFDDR Port F Data Direction Register 00h R/W
0016h PFOR Port F Option Register 00h R/W

0017h
to Reserved Area (9 Bytes)
001Fh

0020h MISCR1 Miscellaneous Register 1 00h R/W

0021h SPIDR SPI Data I/O Register xxh R/W

0022h SPI SPICR SPI Control Register 0xh R/W
0023h SPISR SPI Status Register 00h Read Only

0024h
to Reserved Area (5 Bytes)
0028h

0029h MCC MCCSR Main Clock Control / Status Register 01h R/W

13/151
ST72334J/N, ST72314J/N, ST72124J

Register Reset
Address Block Register Name Remarks
Label Status

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh CRSR Clock, Reset, Supply Control / Status Register 000x 000x R/W

002Ch Data-EEPROM EECSR Data-EEPROM Control/Status Register 00h R/W

002Dh
Reserved Area (4 Bytes)
0030h

0031h TACR2 Timer A Control Register 2 00h R/W

0032h TACR1 Timer A Control Register 1 00h R/W
0033h TASR Timer A Status Register xxh Read Only
0034h TAIC1HR Timer A Input Capture 1 High Register xxh Read Only
0035h TAIC1LR Timer A Input Capture 1 Low Register xxh Read Only
0036h TAOC1HR Timer A Output Compare 1 High Register 80h R/W
0037h TAOC1LR Timer A Output Compare 1 Low Register 00h R/W
0038h TIMER A TACHR Timer A Counter High Register FFh Read Only
0039h TACLR Timer A Counter Low Register FCh Read Only
003Ah TAACHR Timer A Alternate Counter High Register FFh Read Only
003Bh TAACLR Timer A Alternate Counter Low Register FCh Read Only
003Ch TAIC2HR Timer A Input Capture 2 High Register xxh Read Only 3)
003Dh TAIC2LR Timer A Input Capture 2 Low Register xxh Read Only 3)
003Eh TAOC2HR Timer A Output Compare 2 High Register 80h R/W 3)
003Fh TAOC2LR Timer A Output Compare 2 Low Register 00h R/W 3)

0040h MISCR2 Miscellaneous Register 2 00h R/W

0041h TBCR2 Timer B Control Register 2 00h R/W

0042h TBCR1 Timer B Control Register 1 00h R/W
0043h TBSR Timer B Status Register xxh Read Only
0044h TBIC1HR Timer B Input Capture 1 High Register xxh Read Only
0045h TBIC1LR Timer B Input Capture 1 Low Register xxh Read Only
0046h TBOC1HR Timer B Output Compare 1 High Register 80h R/W
0047h TBOC1LR Timer B Output Compare 1 Low Register 00h R/W
0048h TIMER B TBCHR Timer B Counter High Register FFh Read Only
0049h TBCLR Timer B Counter Low Register FCh Read Only
004Ah TBACHR Timer B Alternate Counter High Register FFh Read Only
004Bh TBACLR Timer B Alternate Counter Low Register FCh Read Only
004Ch TBIC2HR Timer B Input Capture 2 High Register xxh Read Only
004Dh TBIC2LR Timer B Input Capture 2 Low Register xxh Read Only
004Eh TBOC2HR Timer B Output Compare 2 High Register 80h R/W
004Fh TBOC2LR Timer B Output Compare 2 Low Register 00h R/W

0050h SCISR SCI Status Register C0h Read Only

0051h SCIDR SCI Data Register xxh R/W
0052h SCIBRR SCI Baud Rate Register 00xx xxxx R/W
0053h SCICR1 SCI Control Register 1 xxh R/W
SCI
0054h SCICR2 SCI Control Register 2 00h R/W
0055h SCIERPR SCI Extended Receive Prescaler Register 00h R/W
0056h Reserved area ---
0057h SCIETPR SCI Extended Transmit Prescaler Register 00h R/W

14/151
ST72334J/N, ST72314J/N, ST72124J

Register Reset
Address Block Register Name Remarks
Label Status

0058h
Reserved Area (24 Bytes)
006Fh

0070h ADCDR Data Register xxh Read Only

ADC
0071h ADCCSR Control/Status Register 00h R/W

0072h
to Reserved Area (14 Bytes)
007Fh

Legend: x=undefined, R/W=read/write

Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset
status value. These bits must always keep their reset value.
3. External pin not available.

15/151
ST72334J/N, ST72314J/N, ST72124J

5 FLASH PROGRAM MEMORY

5.1 INTRODUCTION This mode needs five signals (plus the VDD signal
if necessary) to be connected to the programming
FLASH devices have a single voltage non-volatile tool. This signals are:
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-by- – RESET: device reset
byte basis. – VSS: device ground power supply
– ISPCLK: ISP output serial clock pin
5.2 MAIN FEATURES – ISPDATA: ISP input serial data pin
– ISPSEL: Remote ISP mode selection. This pin
■ Remote In-Situ Programming (ISP) mode must be connected to VSS on the application
board through a pull-down resistor.
■ Up to 16 bytes programmed in the same cycle
If any of these pins are used for other purposes on
■ MTP memory (Multiple Time Programmable) the application, a serial resistor has to be imple-
■ Read-out memory protection against piracy mented to avoid a conflict if the other device forces
the signal level.
5.3 STRUCTURAL ORGANISATION Figure 6 shows a typical hardware interface to a
standard ST7 programming tool. For more details
The FLASH program memory is organised in a on the pin locations, refer to the device pinout de-
single 8-bit wide memory block which can be used scription.
for storing both code and data constants. Figure 6. Typical Remote ISP Interface
The FLASH program memory is mapped in the up- HE10 CONNECTOR TYPE
per part of the ST7 addressing space and includes TO PROGRAMMING TOOL
XTAL
the reset and interrupt user vector area .

5.4 IN-SITU PROGRAMMING (ISP) MODE 1

CL0 CL1
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up-
ISPSEL
dated using a standard ST7 programming tools af-
OSC2

OSC1

VDD

ter the device is mounted on the application board. 10KΩ

This feature can be implemented with a minimum VSS
number of added components and board area im-
pact. RESET
An example Remote ISP hardware interface to the ISPCLK
standard ST7 programming tool is described be- ST7
low. For more details on ISP programming, refer to ISPDATA
the ST7 Programming Specification. 47KΩ
Remote ISP Overview
The Remote ISP mode is initiated by a specific se- APPLICATION
quence on the dedicated ISPSEL pin.
The Remote ISP is performed in three steps: 5.5 MEMORY READ-OUT PROTECTION
– Selection of the RAM execution mode
The read-out protection is enabled through an op-
– Download of Remote ISP code in RAM tion bit.
– Execution of Remote ISP code in RAM to pro- For FLASH devices, when this option is selected,
gram the user program into the FLASH the program and data stored in the FLASH memo-
Remote ISP hardware configuration ry are protected against read-out piracy (including
a re-write protection). When this protection option
In Remote ISP mode, the ST7 has to be supplied is removed the entire FLASH program memory is
with power (V DD and VSS) and a clock signal (os- first automatically erased. However, the E2PROM
cillator and application crystal circuit for example). data memory (when available) can be protected
only with ROM devices.

16/151
ST72334J/N, ST72314J/N, ST72124J

6 DATA EEPROM

6.1 INTRODUCTION 6.2 MAIN FEATURES

The Electrically Erasable Programmable Read ■ Up to 16 Bytes programmed in the same cycle
Only Memory can be used as a non volatile back- ■ EEPROM mono-voltage (charge pump)
up for storing data. Using the EEPROM requires a
■ Chained erase and programming cycles
basic access protocol described in this chapter.
■ Internal control of the global programming cycle
duration
■ End of programming cycle interrupt flag
■ WAIT mode management
Figure 7. EEPROM Block Diagram

FALLING
EEPROM INTERRUPT EDGE
DETECTOR

HIGH VOLTAGE
PUMP

RESERVED EEPROM
EECSR
0 0 0 0 0 IE LAT PGM

EEPROM
ADDRESS 4 ROW
MEMORY MATRIX
DECODER DECODER
(1 ROW = 16 x 8 BITS)

128 128

4 DATA 16 x 8 BITS
MULTIPLEXER DATA LATCHES

ADDRESS BUS DATA BUS

17/151
ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont’d)

6.3 MEMORY ACCESS When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
The Data EEPROM memory read/write access programmed in the EEPROM cells. The effective
modes are controlled by the LAT bit of the EEP- high address (row) is determined by the last EEP-
ROM Control/Status register (EECSR). The flow- ROM write sequence. To avoid wrong program-
chart in Figure 8 describes these different memory ming, the user must take care that all the bytes
access modes. written between two programming sequences
Read Operation (LAT=0) have the same high address: only the four Least
Significant Bits of the address can change.
The EEPROM can be read as a normal ROM loca-
tion when the LAT bit of the EECSR register is At the end of the programming cycle, the PGM and
cleared. In a read cycle, the byte to be accessed is LAT bits are cleared simultaneously, and an inter-
put on the data bus in less than 1 CPU clock cycle. rupt is generated if the IE bit is set. The Data EEP-
This means that reading data from EEPROM ROM interrupt request is cleared by hardware
takes the same time as reading data from when the Data EEPROM interrupt vector is
EPROM, but this memory cannot be used to exe- fetched.
cute machine code. Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
Write Operation (LAT=1) will over-program the memory (logical AND be-
To access the write mode, the LAT bit has to be tween the two write access data result) because
set by software (the PGM bit remains cleared). the data latches are only cleared at the end of the
When a write access to the EEPROM area occurs, programming cycle and by the falling edge of LAT
the value is latched inside the 16 data latches ac- bit.
It is not possible to read the latched data.
cording to its address. This note is ilustrated by the Figure 9.
Figure 8. Data EEPROM Programming Flowchart

READ MODE WRITE MODE

LAT=0 LAT=1
PGM=0 PGM=0

WRITE UP TO 16 BYTES
READ BYTES
IN EEPROM AREA
IN EEPROM AREA
(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

LAT=1
PGM=1 (set by software)

INTERRUPT GENERATION
IF IE=1 0 1
LAT

CLEARED BY HARDWARE

18/151
ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont’d)

6.4 POWER SAVING MODES 6.5 ACCESS ERROR HANDLING

Wait mode If a read access occurs while LAT=1, then the data
bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol- If a write access occurs while LAT=0, then the
ler. The DATA EEPROM will immediately enter data on the bus will not be latched.
this mode if there is no programming in progress, If a programming cycle is interrupted (by software/
otherwise the DATA EEPROM will finish the cycle RESET action), the memory data will not be guar-
and then enter WAIT mode. anteed.
Halt mode
The DATA EEPROM immediatly enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.

Figure 9. Data EEPROM Programming Cycle

READ OPERATION NOT POSSIBLE READ OPERATION POSSIBLE

INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE WRITE CYCLE

WRITE OF
DATA LATCHES
tPROG

LAT

PGM

EEPROM INTERRUPT

19/151
ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont’d)

6.6 REGISTER DESCRIPTION Bit 1 = LAT Latch Access Transfer

This bit is set by software. It is cleared by hard-
CONTROL/STATUS REGISTER (CSR) ware at the end of the programming cycle. It can
Read /Write only be cleared by software if PGM bit is cleared.
0: Read mode
Reset Value: 0000 0000 (00h) 1: Write mode
7 0
Bit 0 = PGM Programming control and status
0 0 0 0 0 IE LAT PGM This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware and an interrupt is generated
Bit 7:3 = Reserved, forced by hardware to 0. if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress
Bit 2 = IE Interrupt enable
This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the PGM Note: if the PGM bit is cleared during the program-
bit is cleared by hardware. The interrupt request is ming cycle, the memory data is not guaranteed
automatically cleared when the software enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled

20/151
ST72334J/N, ST72314J/N, ST72124J

7 DATA EEPROM Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

EECSR IE RWM PGM

002Ch
Reset Value 0 0 0 0 0 0 0 0

7.1 READ-OUT PROTECTION OPTION

The Data EEPROM can be optionally read-out list on page 145). ST72C334 Flash devices do not
protected in ST72334 ROM devices (see option have this protection option.

21/151
ST72334J/N, ST72314J/N, ST72124J

8 CENTRAL PROCESSING UNIT

8.1 INTRODUCTION Accumulator (A)

This CPU has a full 8-bit architecture and contains The Accumulator is an 8-bit general purpose reg-
six internal registers allowing efficient 8-bit data ister used to hold operands and the results of the
manipulation. arithmetic and logic calculations and to manipulate
data.
8.2 MAIN FEATURES Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
■ 63 basic instructions are used to create either effective addresses or
■ Fast 8-bit by 8-bit multiply temporary storage areas for data manipulation.
■ 17 main addressing modes (The Cross-Assembler generates a precede in-
■ Two 8-bit index registers struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
■ Low power modes matic procedures (not pushed to and popped from
■ Maskable hardware interrupts the stack).
■ Non-maskable software interrupt Program Counter (PC)
The program counter is a 16-bit register containing
8.3 CPU REGISTERS the address of the next instruction to be executed
The 6 CPU registers shown in Figure 10 are not by the CPU. It is made of two 8-bit registers PCL
present in the memory mapping and are accessed (Program Counter Low which is the LSB) and PCH
by specific instructions. (Program Counter High which is the MSB).

Figure 10. CPU Registers

7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh

15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 1 H I N Z C CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X

15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value

22/151
ST72334J/N, ST72314J/N, ST72124J

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)
Read/Write Bit 2 = N Negative.
Reset Value: 111x1xxx This bit is set and cleared by hardware. It is repre-
7 0
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
bit of the result.
1 1 1 H I N Z C
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
The 8-bit Condition Code register contains the in- (i.e. the most significant bit is a logic 1).
terrupt mask and four flags representative of the This bit is accessed by the JRMI and JRPL instruc-
result of the instruction just executed. This register tions.
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con- Bit 1 = Z Zero.
trolled by specific instructions.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
Bit 4 = H Half carry. or data manipulation is zero.
0: The result of the last operation is different from
This bit is set by hardware when a carry occurs be- zero.
tween bits 3 and 4 of the ALU during an ADD or 1: The result of the last operation is zero.
ADC instruction. It is reset by hardware during the
same instructions. This bit is accessed by the JREQ and JRNE test
0: No half carry has occurred. instructions.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc- Bit 0 = C Carry/borrow.
tion. The H bit is useful in BCD arithmetic subrou-
tines. This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
Bit 3 = I Interrupt mask. 0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except This bit is driven by the SCF and RCF instructions
the TRAP software interrupt. This bit is cleared by and tested by the JRC and JRNC instructions. It is
software. also affected by the “bit test and branch”, shift and
0: Interrupts are enabled. rotate instructions.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.

23/151
ST72334J/N, ST72314J/N, ST72124J

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP) The least significant byte of the Stack Pointer
Read/Write (called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
15 8 Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
0 0 0 0 0 0 0 1 stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
7 0 flow.
The stack is used to save the return address dur-
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
The Stack Pointer is a 16-bit register which is al- the stack by means of the PUSH and POP instruc-
ways pointing to the next free location in the stack. tions. In the case of an interrupt, the PCL is stored
It is then decremented after data has been pushed at the first location pointed to by the SP. Then the
onto the stack and incremented before data is other registers are stored in the next locations as
popped from the stack (see Figure 11). shown in Figure 11.
Since the stack is 256 bytes deep, the 8th most – When an interrupt is received, the SP is decre-
significant bits are forced by hardware. Following mented and the context is pushed on the stack.
an MCU Reset, or after a Reset Stack Pointer in- – On return from interrupt, the SP is incremented
struction (RSP), the Stack Pointer contains its re- and the context is popped from the stack.
set value (the SP7 to SP0 bits are set) which is the A subroutine call occupies two locations and an in-
stack higher address. terrupt five locations in the stack area.
Figure 11. Stack Manipulation Example

CALL Interrupt PUSH Y POP Y IRET RET

Subroutine Event or RSP

@ 0100h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

24/151
ST72334J/N, ST72314J/N, ST72124J

9 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72334J/N, ST72314J/N and ST72124J mi- ■ Multi-Oscillator (MO)
crocontrollers include a range of utility features for – 4 Crystal/Ceramic resonator oscillators
securing the application in critical situations (for
example in case of a power brown-out), and re- – 1 External RC oscillator
ducing the number of external components. An – 1 Internal RC oscillator
overview is shown in Figure 12. ■ Clock Security System (CSS)
See Section 16 "ELECTRICAL CHARACTERIS- – Clock Filter
TICS" on page 106 for more details. – Backup Safe Oscillator
Main Features
■ Supply Manager with main supply low voltage
detection (LVD)
■ Reset Sequence Manager (RSM)

Figure 12. Clock, Reset and Supply Block Diagram

CLOCK SECURITY SYSTEM

(CSS)

OSC2 MULTI- fOSC TO

CLOCK SAFE
OSCILLATOR MAIN CLOCK
OSC1 FILTER OSC CONTROLLER
(MO)

RESET SEQUENCE
RESET MANAGER FROM
WATCHDOG
(RSM)
PERIPHERAL

VDD LOW VOLTAGE

LVD CSS WDG
DETECTOR
VSS (LVD) CRSR 0 0 0 RF 0 IE D RF

CSS INTERRUPT

25/151
ST72334J/N, ST72314J/N, ST72124J

9.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management In these conditions, secure operation is always en-
features in the application, the Low Voltage Detec- sured for the application without the need for ex-
tor function (LVD) generates a static reset when ternal reset hardware.
the V DD supply voltage is below a VIT- reference During a Low Voltage Detector Reset, the RESET
value. This means that it secures the power-up as pin is held low, thus permitting the MCU to reset
well as the power-down keeping the ST7 in reset. other devices.
The VIT- reference value for a voltage drop is lower Notes:
than the VIT+ reference value for power-on in order 1. The LVD allows the device to be used without
to avoid a parasitic reset when the MCU starts run- any external RESET circuitry.
ning and sinks current on the supply (hysteresis). 2. Three different reference levels are selectable
The LVD Reset circuitry generates a reset when through the option byte according to the applica-
VDD is below: tion requirement.
– VIT+ when VDD is rising LVD application note
– VIT- when VDD is falling Application software can detect a reset caused by
The LVD function is illustrated in the Figure 13. the LVD by reading the LVDRF bit in the CRSR
register.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU This bit is set by hardware when a LVD reset is
can only be in two modes: generated and cleared by software (writing zero).
– under full software control
– in static safe reset
Figure 13. Low Voltage Detector vs Reset

VDD

Vhyst
VIT+
VIT-

RESET

26/151
ST72334J/N, ST72314J/N, ST72124J

9.2 RESET SEQUENCE MANAGER (RSM)

9.2.1 Introduction The 4096 CPU clock cycle delay allows the oscil-
The reset sequence manager includes three RE- lator to stabilise and ensures that recovery has
SET sources as shown in Figure 15: taken place from the Reset state.
■ External RESET source pulse The RESET vector fetch phase duration is 2 clock
cycles.
■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET Figure 14. RESET Sequence Phases

These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad- RESET
dresses FFFEh-FFFFh in the ST7 memory map. INTERNAL RESET FETCH
DELAY
4096 CLOCK CYCLES VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Delay depending on the RESET source

■ 4096 CPU clock cycle delay

■ RESET vector fetch

Figure 15. Reset Block Diagram

VDD INTERNAL
fCPU RESET
COUNTER

RON

RESET

WATCHDOG RESET

LVD RESET

27/151
ST72334J/N, ST72314J/N, ST72124J

RESET SEQUENCE MANAGER (Cont’d)

9.2.2 Asynchronous External RESET pin 9.2.3 Internal Low Voltage Detection RESET
The RESET pin is both an input and an open-drain Two different RESET sequences caused by the in-
output with integrated RON weak pull-up resistor. ternal LVD circuitry can be distinguished:
This pull-up has no fixed value but varies in ac- ■ Power-On RESET
cordance with the input voltage. It can be pulled
■ Voltage Drop RESET
low by external circuitry to reset the device. See
electrical characteristics section for more details. The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
A RESET signal originating from an external
VDD<VIT- (falling edge) as shown in Figure 16.
source must have a duration of at least t h(RSTL)in in
order to be recognized. This detection is asynchro- The LVD filters spikes on VDD larger than tg(VDD) to
nous and therefore the MCU can enter reset state avoid parasitic resets.
even in HALT mode.
9.2.4 Internal Watchdog RESET
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy The RESET sequence generated by a internal
environment, it is recommended to follow the Watchdog counter overflow is shown in Figure 16.
guidelines mentioned in the electrical characteris- Starting from the Watchdog counter underflow, the
tics section. device RESET pin acts as an output that is pulled
Two RESET sequences can be associated with low during at least tw(RSTL)out.
this RESET source: short or long external reset
pulse (see Figure 16).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Figure 16. RESET Sequences
VDD

VIT+
VIT-

LVD SHORT EXT. LONG EXT. WATCHDOG

RESET RESET RESET RESET
RUN RUN RUN RUN RUN
DELAY DELAY DELAY DELAY

tw(RSTL)out

th(RSTL)in th(RSTL)in tw(RSTL)out

EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (4096 TCPU)

FETCH VECTOR

28/151
ST72334J/N, ST72314J/N, ST72124J

9.3 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by Table 3. ST7 Clock Sources
four different source types coming from the multi-
Hardware Configuration
oscillator block:
■ an external source

■ 4 crystal or ceramic resonator oscillators ST7

External Clock
■ an external RC oscillator OSC1 OSC2
■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency

range in terms of consumption and is selectable
EXTERNAL
through the option byte. The associated hardware SOURCE
configuration are shown in Table 3. Refer to the
electrical characteristics section for more details.

Crystal/Ceramic Resonators
External Clock Source ST7
In this external clock mode, a clock signal (square, OSC1 OSC2
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro- CL1 CL2
ducing a very accurate rate on the main clock of LOAD
the ST7. The selection within a list of 4 oscillators CAPACITORS
with different frequency ranges has to be done by
option byte in order to reduce consumption. In this
ST7
External RC Oscillator

mode of the multi-oscillator, the resonator and the OSC1 OSC2

load capacitors have to be placed as close as pos-
sible to the oscillator pins in order to minimize out-
put distortion and start-up stabilization time. The
loading capacitance values must be adjusted ac-
cording to the selected oscillator. REX CEX
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
External RC Oscillator
Internal RC Oscillator

ST7
This oscillator allows a low cost solution for the
OSC1 OSC2
main clock of the ST7 using only an external resis-
tor and an external capacitor. The frequency of the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components. The corresponding formula
is fOSC=4/(REXCEX)
Internal RC Oscillator
The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ-
ing the resistance and the capacitance of the de-
vice. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.
In this mode, the two oscillator pins have to be tied
to ground.

29/151
ST72334J/N, ST72314J/N, ST72124J

9.4 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the Limitation detection
ST7 against main clock problems. To allow the in- The automatic safe oscillator selection is notified
tegration of the security features in the applica- by hardware setting the CSSD bit of the CRSR
tions, it is based on a clock filter control and an In- register. An interrupt can be generated if the CS-
ternal safe oscillator. The CSS can be enabled or SIE bit has been previously set.
disabled by option byte. These two bits are described in the CRSR register
9.4.1 Clock Filter Control description.
The clock filter is based on a clock frequency limi- 9.4.3 Low Power Modes
tation function.
Mode Description
This filter function is able to detect and filter high
No effect on CSS. CSS interrupt cause the
frequency spikes on the ST7 main clock. WAIT
device to exit from Wait mode.
If the oscillator is not working properly (e.g. work- The CRSR register is frozen. The CSS (in-
ing at a harmonic frequency of the resonator), the cluding the safe oscillator) is disabled until
current active oscillator clock can be totally fil- HALT mode is exited. The previous CSS
tered, and then no clock signal is available for the configuration resumes when the MCU is
ST7 from this oscillator anymore. If the original HALT
woken up by an interrupt with “exit from
clock source recovers, the filtering is stopped au- HALT mode” capability or from the counter
tomatically and the oscillator supplies the ST7 reset value when the MCU is woken up by a
clock. RESET.
9.4.2 Safe Oscillator Control
9.4.4 Interrupts
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 17). The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
If the clock signal disappears (due to a broken or set and the interrupt mask in the CC register is re-
disconnected resonator...) during a safe oscillator set (RIM instruction).
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some Enable Exit Exit
Event
rescue operations. Interrupt Event Control from from
Flag
Automatically, the ST7 clock source switches back Bit Wait Halt1)
from the safe oscillator if the original clock source CSS event detection
recovers. (safe oscillator acti- CSSD CSSIE Yes No
vated as main clock)

Note 1: This interrupt allows to exit from active-halt

mode if this mode is available in the MCU.
Figure 17. Clock Filter Function and Safe Oscillator Function
CLOCK FILTER
FUNCTION

fOSC/2

fCPU
SAFE OSCILLATOR

fOSC/2
FUNCTION

fSFOSC

fCPU

30/151
ST72334J/N, ST72314J/N, ST72124J

9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION

Read /Write Bit 1 = CSSD Clock security system detection
Reset Value: 000x 000x (xxh) This bit indicates that the safe oscillator of the
clock security system block has been selected by
7 0
hardware due to a disturbance on the main clock
signal (fOSC). It is set by hardware and cleared by
LVD CSS CSS WDG reading the CRSR register when the original oscil-
0 0 0 0 lator recovers.
RF IE D RF
0: Safe oscillator is not active
1: Safe oscillator has been activated
Bit 7:5 = Reserved, always read as 0. When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last RESET was gener- Bit 0 = WDGRF Watchdog reset flag
ated by the LVD block. It is set by hardware (LVD This bit indicates that the last RESET was gener-
reset) and cleared by software (writing zero). See ated by the watchdog peripheral. It is set by hard-
WDGRF flag description for more details. When ware (Watchdog RESET) and cleared by software
the LVD is disabled by option byte, the LVDRF bit (writing zero) or an LVD RESET (to ensure a sta-
value is undefined. ble cleared state of the WDGRF flag when the
CPU starts).
Bit 3 = Reserved, always read as 0. Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET Sources LVDRF WDGRF
Bit 2 = CSSIE Clock security syst interrupt enable
.

This bit enables the interrupt when a disturbance External RESET pin 0 0
is detected by the clock security system (CSSD bit Watchdog 0 1
set). It is set and cleared by software. LVD 1 X
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt mapping,” on page 33 Application notes
for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit The LVDRF flag is not cleared when another RE-
has no effect. SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

CRSR LVDRF CFIE CSSD WDGRF

002Bh
Reset Value 0 0 0 x 0 0 0 x

31/151
ST72334J/N, ST72314J/N, ST72124J

10 INTERRUPTS
The ST7 core may be interrupted by one of two dif- It will be serviced according to the flowchart on
ferent methods: maskable hardware interrupts as Figure 18.
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt 10.2 EXTERNAL INTERRUPTS
processing flowchart is shown in Figure 18.
The maskable interrupts must be enabled by External interrupt vectors can be loaded into the
clearing the I bit in order to be serviced. However, PC register if the corresponding external interrupt
disabled interrupts may be latched and processed occurred and if the I bit is cleared. These interrupts
when they are enabled (see external interrupts allow the processor to leave the Halt low power
subsection). mode.
Note: After reset, all interrupts are disabled. The external interrupt polarity is selected through
When an interrupt has to be serviced: the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution. An external interrupt triggered on edge will be
latched and the interrupt request automatically
– The PC, X, A and CC registers are saved onto cleared upon entering the interrupt service routine.
the stack.
If several input pins, connected to the same inter-
– The I bit of the CC register is set to prevent addi- rupt vector, are configured as interrupts, their sig-
tional interrupts. nals are logically NANDed before entering the
– The PC is then loaded with the interrupt vector of edge/level detection block.
the interrupt to service and the first instruction of Caution: The type of sensitivity defined in the Mis-
the interrupt service routine is fetched (refer to cellaneous or Interrupt register (if available) ap-
the Interrupt Mapping Table for vector address- plies to the ei source. In case of a NANDed source
es). (as described on the I/O ports section), a low level
The interrupt service routine should finish with the on an I/O pin configured as input with interrupt,
IRET instruction which causes the contents of the masks the interrupt request even in case of rising-
saved registers to be recovered from the stack. edge sensitivity.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will 10.3 PERIPHERAL INTERRUPTS
resume.
Different peripheral interrupt flags in the status
Priority Management register are able to cause an interrupt when they
By default, a servicing interrupt cannot be inter- are active if both:
rupted because the I bit is set by hardware enter- – The I bit of the CC register is cleared.
ing in interrupt routine.
– The corresponding enable bit is set in the control
In the case when several interrupts are simultane- register.
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map- If any of these two conditions is false, the interrupt
ping Table). is latched and thus remains pending.
Interrupts and Low Power Mode Clearing an interrupt request is done by:
All interrupts allow the processor to leave the – Writing “0” to the corresponding bit in the status
WAIT low power mode. Only external and specifi- register or
cally mentioned interrupts allow the processor to – Access to the status register while the flag is set
leave the HALT low power mode (refer to the “Exit followed by a read or write of an associated reg-
from HALT“ column in the Interrupt Mapping Ta- ister.
ble). Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
10.1 NON MASKABLE SOFTWARE abled) will therefore be lost if the clear sequence is
INTERRUPT executed.

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

32/151
ST72334J/N, ST72314J/N, ST72124J

INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart

FROM RESET

N
I BIT SET?

Y N INTERRUPT
PENDING?

FETCH NEXT INSTRUCTION Y

N
IRET?
STACK PC, X, A, CC
SET I BIT
Y LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 5. Interrupt mapping

Exit
Source Register Priority Address
N° Description from
Block Label Order Vector
HALT1)
RESET Reset Highest yes FFFEh-FFFFh
N/A Priority
TRAP Software Interrupt no FFFCh-FFFDh
0 Not used FFFAh-FFFBh
MCC/RTC Main Clock Controller Time Base Interrupt MCCSR yes
1 FFF8h-FFF9h
CSS or Clock Security System Interrupt CRSR
2 ei0 External Interrupt Port A3..0 FFF6h-FFF7h
3 ei1 External Interrupt Port F2..0 FFF4h-FFF5h
N/A
4 ei2 External Interrupt Port B3..0 FFF2h-FFF3h
5 ei3 External Interrupt Port B7..4 FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SPI SPI Peripheral Interrupts SPISR no FFECh-FFEDh
8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh
9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE9h
10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE7h
11 Data-EEPROM Data EEPROM Interrupt EECSR FFE4h-FFE5h
12 Lowest FFE2h-FFE3h
Not used
13 Priority FFE0h-FFE1h
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from
ACTIVE-HALT mode only.

33/151
ST72334J/N, ST72314J/N, ST72124J

11 POWER SAVING MODES

11.1 INTRODUCTION 11.2 SLOW MODE

To give a large measure of flexibility to the applica- This mode has two targets:
tion in terms of power consumption, four main – To reduce power consumption by decreasing the
power saving modes are implemented in the ST7 internal clock in the device,
(see Figure 19): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT. – To adapt the internal clock frequency (fCPU) to
the available supply voltage.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives SLOW mode is controlled by three bits in the
the device (CPU and embedded peripherals) by MISCR1 register: the SMS bit which enables or
means of a master clock which is based on the disables Slow mode and two CPx bits which select
main oscillator frequency divided by 2 (f CPU). the internal slow frequency (fCPU).
From RUN mode, the different power saving In this mode, the oscillator frequency can be divid-
modes may be selected by setting the relevant ed by 4, 8, 16 or 32 instead of 2 in normal operat-
register bits or by calling the specific ST7 software ing mode. The CPU and peripherals are clocked at
instruction whose action depends on the oscillator this lower frequency.
status. Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
Figure 19. Power Saving Mode Transitions SLOW mode.
Figure 20. SLOW Mode Clock Transitions
High

fOSC/4 fOSC/8 fOSC/2

RUN
fCPU

SLOW
fOSC/2
MISCR1

WAIT CP1:0 00 01

SMS
SLOW WAIT
NORMAL RUN MODE
NEW SLOW REQUEST
ACTIVE HALT
FREQUENCY
REQUEST

HALT

Low
POWER CONSUMPTION

34/151
ST72334J/N, ST72314J/N, ST72124J

POWER SAVING MODES (Cont’d)

11.3 WAIT MODE Figure 21. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con- OSCILLATOR ON
sumption mode by stopping the CPU. PERIPHERALS ON
This power saving mode is selected by calling the WFI INSTRUCTION
CPU OFF
‘WFI’ instruction. I BIT 0
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until N
RESET
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of Y
the interrupt or Reset service routine. N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up. Y
Refer to Figure 21. OSCILLATOR ON
PERIPHERALS OFF
CPU ON
I BIT 0

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR ON
PERIPHERALS ON
CPU ON
I BIT X 1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

35/151
ST72334J/N, ST72314J/N, ST72124J

POWER SAVING MODES (Cont’d)

11.4 ACTIVE-HALT AND HALT MODES Figure 22. ACTIVE-HALT Timing Overview
ACTIVE-HALT and HALT modes are the two low- ACTIVE
est power consumption modes of the MCU. They 4096 CPU CYCLE
RUN HALT DELAY RUN
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
RESET
or HALT mode is given by the MCC/RTC interrupt OR
enable flag (OIE bit in MCCSR register). HALT
INTERRUPT FETCH
INSTRUCTION
[MCCSR.OIE=1] VECTOR
MCCSR Power Saving Mode entered when HALT
OIE bit instruction is executed
0 HALT mode
Figure 23. ACTIVE-HALT Mode Flow-chart
1 ACTIVE-HALT mode OSCILLATOR ON
HALT INSTRUCTION PERIPHERALS 1) OFF
11.4.1 ACTIVE-HALT MODE (MCCSR.OIE=1) CPU OFF
I BIT 0
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con- N
RESET
troller Status register (MCCSR) is set (see Section
14.2 "MAIN CLOCK CONTROLLER WITH REAL Y
TIME CLOCK TIMER (MCC/RTC)" on page 51 for N
INTERRUPT 2)
more details on the MCCSR register).
The MCU can exit ACTIVE-HALT mode on recep- Y OSCILLATOR ON
tion of either an MCC/RTC interrupt, a specific in- PERIPHERALS 1) OFF
terrupt (see Table 5, “Interrupt mapping,” on CPU ON
page 33) or a RESET. When exiting ACTIVE- I BIT X 3)
HALT mode by means of a RESET or an interrupt,
a 4096 CPU cycle delay occurs. After the start up
4096 CPU CLOCK CYCLE
delay, the CPU resumes operation by servicing
DELAY
the interrupt or by fetching the reset vector which
woke it up (see Figure 23).
When entering ACTIVE-HALT mode, the I bit in OSCILLATOR ON
the CC register is cleared to enable interrupts. PERIPHERALS ON
Therefore, if an interrupt is pending, the MCU CPU ON
wakes up immediately. I BITS X 3)

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run- FETCH RESET VECTOR
ning to keep a wake-up time base. All other periph- OR SERVICE INTERRUPT
erals are not clocked except those which get their
Notes:
clock supply from another clock generator (such
as external or auxiliary oscillator). 1. Peripheral clocked with an external clock source
can still be active.
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt. 2. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
Note: As soon as the interrupt capability of one of mode (such as external interrupt). Refer to
the oscillators is selected (MCCSR.OIE bit set), Table 5, “Interrupt mapping,” on page 33 for more
entering ACTIVE-HALT mode while the Watchdog details.
is active does not generate a RESET. 3. Before servicing an interrupt, the CC register is
This means that the device cannot spend more pushed on the stack. The I bit of the CC register is
than a defined delay in this power saving mode. set during the interrupt routine and cleared when
the CC register is popped.

36/151
ST72334J/N, ST72314J/N, ST72124J

POWER SAVING MODES (Cont’d)

11.4.2 HALT MODE Figure 25. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the HALT INSTRUCTION
‘HALT’ instruction when the OIE bit of the Main (MCCSR.OIE=0)
Clock Controller Status register (MCCSR) is ENABLE
cleared (see Section 14.2 "MAIN CLOCK CON- WATCHDOG
TROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)" on page 51 for more details on the 0 DISABLE
WDGHALT 1)
MCCSR register).
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt WATCHDOG
mapping,” on page 33) or a RESET. When exiting OSCILLATOR OFF
RESET PERIPHERALS 2) OFF
HALT mode by means of a RESET or an interrupt,
CPU OFF
the oscillator is immediately turned on and the
I BIT 0
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 25). N
RESET
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore, Y
if an interrupt is pending, the MCU wakes immedi- N
INTERRUPT 3)
ately.
In HALT mode, the main oscillator is turned off Y OSCILLATOR ON
causing all internal processing to be stopped, in- PERIPHERALS OFF
cluding the operation of the on-chip peripherals. CPU ON
All peripherals are not clocked except the ones I BIT X 4)
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla- 4096 CPU CLOCK CYCLE
tor). DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
OSCILLATOR ON
tion bit of the option byte. The HALT instruction PERIPHERALS ON
when executed while the Watchdog system is en-
CPU ON
abled, can generate a Watchdog RESET (see I BITS X 4)
Section 18.1 on page 143 for more details).
Figure 24. HALT Timing Overview FETCH RESET VECTOR
OR SERVICE INTERRUPT
4096 CPU CYCLE
RUN HALT DELAY RUN Notes:
1. WDGHALT is an option bit. See option byte sec-
RESET tion for more details.
OR 2. Peripheral clocked with an external clock source
HALT INTERRUPT
can still be active.
INSTRUCTION FETCH
[MCCSR.OIE=0] VECTOR 3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5, “Interrupt mapping,” on page 33 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

37/151
ST72334J/N, ST72314J/N, ST72124J

12 I/O PORTS

12.1 INTRODUCTION programmable using the sensitivity bits in the Mis-

cellaneous register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and for specific pins: and interrupt section). If several input pins are se-
– external interrupt generation lected simultaneously as interrupt source, these
– alternate signal input/output for the on-chip pe- are logically NANDed. For this reason if one of the
ripherals. interrupt pins is tied low, it masks the other ones.
An I/O port contains up to 8 pins. Each pin can be In case of a floating input with interrupt configura-
programmed independently as digital input (with or tion, special care must be taken when changing
without interrupt generation) or digital output. the configuration (see Figure 27).
The external interrupts are hardware interrupts,
12.2 FUNCTIONAL DESCRIPTION which means that the request latch (not accessible
Each port has 2 main registers: directly by the application) is automatically cleared
when the corresponding interrupt vector is
– Data Register (DR) fetched. To clear an unwanted pending interrupt
– Data Direction Register (DDR) by software, the sensitivity bits in the Miscellane-
and one optional register: ous register must be modified.
– Option Register (OR) 12.2.2 Output Modes
Each I/O pin may be programmed using the corre- The output configuration is selected by setting the
sponding register bits in the DDR and OR regis- corresponding DDR register bit. In this case, writ-
ters: bit X corresponding to pin X of the port. The ing the DR register applies this digital value to the
same correspondence is used for the DR register. I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
The following description takes into account the
OR register, (for specific ports which do not pro- Two different output modes can be selected by
vide this register refer to the I/O Port Implementa- software through the OR register: Output push-pull
tion section). The generic I/O block diagram is and open-drain.
shown in Figure 26 DR register value and output pin status:
12.2.1 Input Modes DR Push-pull Open-drain
The input configuration is selected by clearing the 0 VSS Vss
corresponding DDR register bit. 1 VDD Floating
In this case, reading the DR register returns the
digital value applied to the external I/O pin. 12.2.3 Alternate Functions
Different input modes can be selected by software When an on-chip peripheral is configured to use a
through the OR register. pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
Notes: standard I/O programming.
1. Writing the DR register modifies the latch value
but does not affect the pin status. When the signal is coming from an on-chip periph-
2. When switching from input to output mode, the eral, the I/O pin is automatically configured in out-
DR register has to be written first to drive the cor- put mode (push-pull or open drain according to the
rect level on the pin as soon as the port is config- peripheral).
ured as an output.
When the signal is going to an on-chip peripheral,
External interrupt function the I/O pin must be configured in input mode. In
When an I/O is configured as Input with Interrupt, this case, the pin state is also digitally readable by
an event on this I/O can generate an external inter- addressing the DR register.
rupt request to the CPU. Note: Input pull-up configuration can cause unex-
Each pin can independently generate an interrupt pected value at the input of the alternate peripheral
request. The interrupt sensitivity is independently input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.

38/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORTS (Cont’d)

Figure 26. I/O Port General Block Diagram

ALTERNATE
REGISTER 1
OUTPUT VDD P-BUFFER
ACCESS
(see table below)
0
ALTERNATE
PULL-UP
ENABLE
(see table below)

DR VDD

DDR

PULL-UP
PAD
CONFIGURATION
OR
DATA BUS

If implemented

OR SEL

N-BUFFER
DIODES
(see table below)
DDR SEL
ANALOG
INPUT
CMOS
SCHMITT
DR SEL
1 TRIGGER

0
ALTERNATE
INPUT
EXTERNAL
FROM
INTERRUPT OTHER
SOURCE (eix) BITS
POLARITY
SELECTION

Table 6. I/O Port Mode Options

Diodes
Configuration Mode Pull-Up P-Buffer
to VDD to VSS
Floating with/without Interrupt Off
Input Off
Pull-up with/without Interrupt On
On
Push-pull On On
Off
Output Open Drain (logic level) Off
True Open Drain NI NI NI (see note)

Legend: NI - not implemented Note: The diode to V DD is not implemented in the

Off - implemented not activated true open drain pads. A local protection between
On - implemented and activated the pad and VSS is implemented to protect the de-
vice against positive stress.

39/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORTS (Cont’d)

Table 7. I/O Port Configurations
Hardware Configuration

NOT IMPLEMENTED IN DR REGISTER ACCESS

VDD
TRUE OPEN DRAIN
I/O PORTS
RPU PULL-UP
CONFIGURATION DR W
REGISTER DATA BUS
PAD R
INPUT 1)

ALTERNATE INPUT
FROM
OTHER
PINS EXTERNAL INTERRUPT
SOURCE (eix)

INTERRUPT POLARITY
CONFIGURATION SELECTION

ANALOG INPUT

NOT IMPLEMENTED IN DR REGISTER ACCESS

TRUE OPEN DRAIN VDD
OPEN-DRAIN OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

NOT IMPLEMENTED IN
DR REGISTER ACCESS
TRUE OPEN DRAIN VDD
PUSH-PULL OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.

40/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac- Standard Ports
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4
interrupts.
MODE DDR OR
Analog alternate function
floating input 0 0
When the pin is used as an ADC input, the I/O
pull-up input 0 1
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers) open drain output 1 0
switches the analog voltage present on the select- push-pull output 1 1
ed pin to the common analog rail which is connect-
ed to the ADC input. Interrupt Ports
It is recommended not to change the voltage level PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to MODE DDR OR
have clocking pins located close to a selected an- floating input 0 0
alog pin. pull-up interrupt input 0 1
WARNING: The analog input voltage level must open drain output 1 0
be within the limits stated in the absolute maxi- push-pull output 1 1
mum ratings.
PA3, PB4, PB3, PF2 (without pull-up)
12.3 I/O PORT IMPLEMENTATION
MODE DDR OR
The hardware implementation on each I/O port de- floating input 0 0
pends on the settings in the DDR and OR registers
floating interrupt input 0 1
and specific feature of the I/O port such as ADC In-
put or true open drain. open drain output 1 0
push-pull output 1 1
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi- True Open Drain Ports
tions are illustrated in Figure 27 Other transitions PA7:6
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects MODE DDR
such as spurious interrupt generation. floating input 0
open drain (high sink ports) 1
Figure 27. Interrupt I/O Port State Transitions

01 00 10 11

INPUT INPUT OUTPUT OUTPUT

floating/pull-up floating open-drain push-pull
interrupt (reset state)

XX = DDR, OR

The I/O port register configurations are summa-

rized as follows.

41/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORTS (Cont’d)

12.4 LOW POWER MODES 12.5 INTERRUPTS

Mode Description The external interrupt event generates an interrupt
if the corresponding configuration is selected with
No effect on I/O ports. External interrupts
WAIT DDR and OR registers and the I-bit in the CC reg-
cause the device to exit from WAIT mode.
ister is reset (RIM instruction).
No effect on I/O ports. External interrupts
HALT
cause the device to exit from HALT mode. Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
External interrupt on
DDRx
selected external - Yes Yes
ORx
event

Table 8. Port Configuration

Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1 High-Sink
PA7:6 floating true open-drain
Yes
PA5:4 floating pull-up open drain push-pull
Port A
PA3 floating floating interrupt open drain push-pull
PA2:0 floating pull-up interrupt open drain push-pull
PB4:3 floating floating interrupt open drain push-pull No
Port B
PB7:5, PB2:0 floating pull-up interrupt open drain push-pull
PC7:4, PC1:0 floating pull-up open drain push-pull
Port C
PC3:2 floating pull-up open drain push-pull Yes
Port D PD7:0 floating pull-up open drain push-pull No
PE7:4 floating pull-up open drain push-pull Yes
Port E
PE1:0 floating pull-up open drain push-pull No
PF7:6 floating pull-up open drain push-pull Yes
PF4 floating pull-up open drain push-pull
Port F
PF2 floating floating interrupt open drain push-pull No
PF1:0 floating pull-up interrupt open drain push-pull

42/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORTS (Cont’d)

12.5.1 Register Description

DATA REGISTER (DR) OPTION REGISTER (OR)
Port x Data Register Port x Option Register
PxDR with x = A, B, C, D, E or F. PxOR with x = A, B, C, D, E or F.
Read /Write Read /Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)

7 0 7 0

D7 D6 D5 D4 D3 D2 D1 D0 O7 O6 O5 O4 O3 O2 O1 O0

Bit 7:0 = D[7:0] Data register 8 bits. Bit 7:0 = O[7:0] Option register 8 bits.
The DR register has a specific behaviour accord- For specific I/O pins, this register is not implement-
ing to the selected input/output configuration. Writ- ed. In this case the DDR register is enough to se-
ing the DR register is always taken into account lect the I/O pin configuration.
even if the pin is configured as an input; this allows The OR register allows to distinguish: in input
to always have the expected level on the pin when mode if the pull-up with interrupt capability or the
toggling to output mode. Reading the DR register basic pull-up configuration is selected, in output
returns either the DR register latch content (pin mode if the push-pull or open drain configuration is
configured as output) or the digital value applied to selected.
the I/O pin (pin configured as input).
Each bit is set and cleared by software.
Input mode:
DATA DIRECTION REGISTER (DDR) 0: floating input
Port x Data Direction Register 1: pull-up input with or without interrupt
PxDDR with x = A, B, C, D, E or F.
Output mode:
Read /Write 0: output open drain (with P-Buffer deactivated)
Reset Value: 0000 0000 (00h) 1: output push-pull

7 0

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

Bit 7:0 = DD[7:0] Data direction register 8 bits.

The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode

43/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORTS (Cont’d)

Table 9. I/O Port Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

Reset Value
0 0 0 0 0 0 0 0
of all IO port registers
0000h PADR
0001h PADDR MSB LSB
0002h PAOR 1)
0004h PCDR
0005h PCDDR MSB LSB
0006h PCOR
0008h PBDR
0009h PBDDR MSB LSB
000Ah PBOR 1)
000Ch PEDR
000Dh PEDDR MSB LSB
000Eh PEOR 1)
0010h PDDR
0011h PDDDR MSB LSB
1)
0012h PDOR
0014h PFDR
0015h PFDDR MSB LSB
0016h PFOR
Notes:
1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.

44/151
ST72334J/N, ST72314J/N, ST72124J

13 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over Figure 28. Ext. Interrupt Sensitivity
several different features such as the external in-
terrupts or the I/O alternate functions.
MISCR1

13.1 I/O PORT INTERRUPT SENSITIVITY IS10 IS11

PB0 INTERRUPT
The external interrupt sensitivity is controlled by PB1 SOURCE SENSITIVITY
the ISxx bits of the MISCR1 miscellaneous regis- PB2 ei2 CONTROL
ter. This control allows to have two fully independ- PB3
ei3
ent external interrupt source sensitivities.
Each external interrupt source can be generated PB4
on four different events on the pin: PB5
■ Falling edge
PB6
PB7 MISCR1
■ Rising edge

■ Falling and rising edge IS20 IS21

■ Falling edge and low level PA0 INTERRUPT
PA1 SOURCE SENSITIVITY
To guarantee correct functionality, the sensitivity PA2 ei0 CONTROL
bits in the MISCR1 register must be modified only ei1
PA3
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
PF0
neous register descriptions for more details on the
programming. PF1
PF2

13.2 I/O PORT ALTERNATE FUNCTIONS

The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■ Main clock signal (fCPU) output on PF0

■ A beep signal output on PF1 (with 3 selectable

audio frequencies)
■ SPI pin configuration:

– SS pin internal control to use the PC7 I/O port

function while the SPI is active.
These functions are described in detail in the Sec-
tion 13 "MISCELLANEOUS REGISTERS" on
page 45.

45/151
ST72334J/N, ST72314J/N, ST72124J

MISCELLANEOUS REGISTERS (Cont’d)

13.3 REGISTERS DESCRIPTION

Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
MISCELLANEOUS REGISTER 1 (MISCR1)
The interrupt sensitivity, defined using the IS2[1:0]
Read /Write bits, is applied to the following external interrupts:-
Reset Value: 0000 0000 (00h) ei0 (port A3..0) and ei1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
7 0 is set to 1 (interrupt disabled).

IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity two bits are set and cleared by software
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts: fCPU in SLOW mode CP1 CP0
ei2 (port B3..0) and ei3 (port B7..4). These 2 bits fOSC / 4 0 0
can be written only when the I bit of the CC register fOSC / 8 1 0
is set to 1 (interrupt disabled).
fOSC / 16 0 1
External Interrupt Sensitivity IS11 IS10 fOSC / 32 1 1
Falling edge & low level 0 0
Rising edge only 0 1
Falling edge only 1 0 Bit 0 = SMS Slow mode select
Rising and falling edge 1 1
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC / 2
1: Slow mode. fCPU is given by CP1, CP0
See low power consumption mode and MCC
Bit 5 = MCO Main clock out selection chapters for more details.
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(fOSC/2 on I/O port)
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.

46/151
ST72334J/N, ST72314J/N, ST72124J

MISCELLANEOUS REGISTERS (Cont’d)

MISCELLANEOUS REGISTER 2 (MISCR2)
Read /Write
Reset Value: 0000 0000 (00h)

7 0

- - BC1 BC0 - - SSM SSI

Bit 7:6 = Reserved Must always be cleared

Bit 5:4 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.
Beep mode with fOSC=16MHz BC1 BC0
Off 0 0
~2-KHz 0 1
Output
~1-KHz Beep signal 1 0
~50% duty cycle
~500-Hz 1 1

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the
consumption.

Bit 3:2 = Reserved Must always be cleared

Bit 1 = SSM SS mode selection

It is set and cleared by software.
0: Normal mode - SS uses information coming
from the SS pin of the SPI.
1: I/O mode, the SPI uses the information stored
into bit SSI.

Bit 0 = SSI SS internal mode

This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.

Table 10. Miscellaneous Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

MISCR1 IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS

0020h
Reset Value 0 0 0 0 0 0 0 0
MISCR2 BC1 BC0 SSM SSI
0040h
Reset Value 0 0 0 0 0 0 0 0

47/151
ST72334J/N, ST72314J/N, ST72124J

14 ON-CHIP PERIPHERALS

14.1 WATCHDOG TIMER (WDG)

14.1.1 Introduction ■ Hardware Watchdog selectable by option byte
The Watchdog timer is used to detect the occur- ■ Watchdog Reset indicated by status flag (in
rence of a software fault, usually generated by ex- versions with Safe Reset option only)
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir- 14.1.3 Functional Description
cuit generates an MCU reset on expiry of a pro- The counter value stored in the CR register (bits
grammed time period, unless the program refresh- T[6:0]), is decremented every 12,288 machine cy-
es the counter’s contents before the T6 bit be- cles, and the length of the timeout period can be
comes cleared. programmed by the user in 64 increments.
14.1.2 Main Features If the watchdog is activated (the WDGA bit is set)
■ Programmable timer (64 increments of 12288 and when the 7-bit timer (bits T[6:0]) rolls over
CPU cycles) from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
■ Programmable reset
500ns.
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 29. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

WDGA T6 T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU CLOCK DIVIDER

÷12288

48/151
ST72334J/N, ST72314J/N, ST72124J

WATCHDOG TIMER (Cont’d)

The application program must write in the CR reg- 14.1.7 Register Description
ister at regular intervals during normal operation to CONTROL REGISTER (CR)
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h Read /Write
(see Table 11 .Watchdog Timing (fCPU = 8 MHz)): Reset Value: 0111 1111 (7Fh)
– The WDGA bit is set (watchdog enabled) 7 0
– The T6 bit is set to prevent generating an imme-
diate reset WDGA T6 T5 T4 T3 T2 T1 T0
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset. Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
Table 11.Watchdog Timing (fCPU = 8 MHz) hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
CR Register WDG timeout period 0: Watchdog disabled
initial value (ms) 1: Watchdog enabled
Max FFh 98.304 Note: This bit is not used if the hardware watch-
Min C0h 1.536 dog option is enabled by option byte.

Notes: Following a reset, the watchdog is disa- Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
bled. Once activated it cannot be disabled, except These bits contain the decremented value. A reset
by a reset. is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction STATUS REGISTER (SR)
will generate a Reset. Read /Write
Reset Value*: 0000 0000 (00h)
14.1.4 Hardware Watchdog Option 7 0
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in - - - - - - - WDOGF
the CR is not used.
Refer to the device-specific Option Byte descrip- Bit 0 = WDOGF Watchdog flag.
tion. This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
14.1.5 Low Power Modes for distinguishing power/on off or external reset
and watchdog reset.
Mode Description 0: No Watchdog reset occurred
WAIT No effect on Watchdog. 1: Watchdog reset occurred
Immediate reset generation as soon as
the HALT instruction is executed if the
HALT * Only by software and power on/off reset
Watchdog is activated (WDGA bit is
set). Note: This register is not used in versions without
LVD Reset.

14.1.6 Interrupts
None.

49/151
ST72334J/N, ST72314J/N, ST72124J

WATCHDOG TIMER (Cont’d)

Table 12. Watchdog Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
002Ah
Reset Value 0 1 1 1 1 1 1 1

50/151
ST72334J/N, ST72314J/N, ST72124J

14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)
The Main Clock Controller consists of three differ- 14.2.2 Clock-out capability
ent functions: The clock-out capability is an alternate function of
■ a programmable CPU clock prescaler an I/O port pin that outputs a fOSC/2 clock to drive
■ a clock-out signal to supply external devices external devices. It is controlled by the MCO bit in
■ a real time clock timer with interrupt capability
the MISCR1 register.
CAUTION: When selected, the clock out pin sus-
Each function can be used independently and si- pends the clock during ACTIVE-HALT mode.
multaneously.
14.2.3 Real time clock timer (RTC)
14.2.1 Programmable CPU clock prescaler
The counter of the real time clock timer allows an
The programmable CPU clock prescaler supplies interrupt to be generated based on an accurate
the clock for the ST7 CPU and its internal periph- real time clock. Four different time bases depend-
erals. It manages SLOW power saving mode (See ing directly on fOSC are available. The whole func-
Section 11.2 "SLOW MODE" on page 34 for more tionality is controlled by four bits of the MCCSR
details). register: TB[1:0], OIE and OIF.
The prescaler selects the fCPU main clock frequen- When the RTC interrupt is enabled (OIE bit set),
cy and is controlled by three bits in the MISCR1 the ST7 enters ACTIVE-HALT mode when the
register: CP[1:0] and SMS. HALT instruction is executed. See Section 11.4
CAUTION: The prescaler does not act on the CAN "ACTIVE-HALT AND HALT MODES" on page 36
peripheral clock source. This peripheral is always for more details.
supplied by the f OSC/2 clock source.

Figure 30. Main Clock Controller (MCC/RTC) Block Diagram

PORT
ALTERNATE
fOSC/2 FUNCTION MCO

MISCR1

- - MCO - - CP1 CP0 SMS

fOSC
DIV 2 DIV 2, 4, 8, 16
CPU CLOCK
fCPU TO CPU AND
RTC
COUNTER PERIPHERALS

MCCSR

0 0 0 0 TB1 TB0 OIE OIF

MCC/RTC INTERRUPT

51/151
ST72334J/N, ST72314J/N, ST72124J

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)

MISCELLANEOUS REGISTER 1 (MISCR1) Bit 0 = OIF Oscillator interrupt flag
See Section 13 on page 45. This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
MAIN CLOCK CONTROL/STATUS REGISTER that the main oscillator has measured the selected
(MCCSR) elapsed time (TB1:0).
Read /Write 0: Timeout not reached
Reset Value: 0000 0001 (01h) 1: Timeout reached
CAUTION: The BRES and BSET instructions
7 0 must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
0 0 0 0 TB1 TB0 OIE OIF
14.2.4 Low Power Modes
Mode Description
Bit 7:4 = Reserved, always read as 0.
No effect on MCC/RTC peripheral.
WAIT MCC/RTC interrupt cause the device to exit
Bit 3:2 = TB[1:0] Time base control from WAIT mode.
These bits select the programmable divider time No effect on MCC/RTC counter (OIE bit is
base. They are set and cleared by software. ACTIVE- set), the registers are frozen.
HALT MCC/RTC interrupt cause the device to exit
Time Base from ACTIVE-HALT mode.
Counter
TB1 TB0 MCC/RTC counter and registers are frozen.
Prescaler fOSC =8MHz fOSC=16MHz MCC/RTC operation resumes when the
HALT
32000 4ms 2ms 0 0 MCU is woken up by an interrupt with “exit
from HALT” capability.
64000 8ms 4ms 0 1
160000 20ms 10ms 1 0 14.2.5 Interrupts
400000 50ms 25ms 1 1 The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
A modification of the time base is taken into ac- the interrupt mask in the CC register is not active
count at the end of the current period (previously (RIM instruction).
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock. Event
Enable Exit Exit
Interrupt Event Control from from
Flag
Bit Wait Halt
Bit 1 = OIE Oscillator interrupt enable
Time base overflow
This bit set and cleared by software. OIF OIE Yes No 1)
event
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled Note:
This interrupt allows to exit from ACTIVE-HALT
mode. 1. The MCC/RTC interrupt allows to exit from AC-
TIVE-HALT mode, not from HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode.

Table 13. MCC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

MCCSR TB1 TB0 OIE OIF

0029h
Reset Value 0 0 0 0 0 0 0 1

52/151
ST72334J/N, ST72314J/N, ST72124J

14.3 16-BIT TIMER

14.3.1 Introduction 14.3.3 Functional Description
The timer consists of a 16-bit free-running counter 14.3.3.1 Counter
driven by a programmable prescaler. The main block of the Programmable Timer is a
It may be used for a variety of purposes, including 16-bit free running upcounter and its associated
measuring the pulse lengths of up to two input sig- 16-bit registers. The 16-bit registers are made up
nals ( input capture) or generating up to two output of two 8-bit registers called high & low.
waveforms (output compare and PWM ). Counter Register (CR):
Pulse lengths and waveform periods can be mod- – Counter High Register (CHR) is the most sig-
ulated from a few microseconds to several milli- nificant byte (MS Byte).
seconds using the timer prescaler and the CPU
clock prescaler. – Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not Alternate Counter Register (ACR)
share any resources. They are synchronized after – Alternate Counter High Register (ACHR) is the
a MCU reset as long as the timer clock frequen- most significant byte (MS Byte).
cies are not modified. – Alternate Counter Low Register (ACLR) is the
This description covers one or two 16-bit timers. In least significant byte (LS Byte).
ST7 devices with two timers, register names are These two read-only 16-bit registers contain the
prefixed with TA (Timer A) or TB (Timer B). same value but with the difference that reading the
14.3.2 Main Features ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register (SR).
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
(See note at the end of paragraph titled 16-bit read
■ Overflow status flag and maskable interrupt sequence).
■ External clock input (must be at least 4 times
Writing in the CLR register or ACLR register resets
slower than the CPU clock speed) with the choice the free running counter to the FFFCh value.
of active edge Both counters have a reset value of FFFCh (this is
■ Output compare functions with: the only value which is reloaded in the 16-bit tim-
– 2 dedicated 16-bit registers er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 2 dedicated programmable signals
– 2 dedicated status flags
The timer clock depends on the clock control bits
– 1 dedicated maskable interrupt of the CR2 register, as illustrated in Table 14 Clock
■ Input capture functions with: Control Bits. The value in the counter register re-
– 2 dedicated 16-bit registers peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
– 2 dedicated active edge selection signals The timer frequency can be fCPU/2, fCPU/4, fCPU/8
– 2 dedicated status flags or an external frequency.
– 1 dedicated maskable interrupt
■ Pulse Width Modulation mode (PWM)

■ One Pulse mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 31.

*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.

53/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

Figure 31. Timer Block Diagram

ST7 INTERNAL BUS

fCPU
MCU-PERIPHERAL INTERFACE

8 high 8 low
8-bit 8 8 8 8 8 8 8 8
buffer

high
high

high

high
low

low

low

low
EXEDG

16

OUTPUT OUTPUT INPUT INPUT

1/2 COUNTER
COMPARE COMPARE CAPTURE CAPTURE
1/4
REGISTER REGISTER REGISTER REGISTER REGISTER
1/8
1 2 1 2
EXTCLK ALTERNATE
pin COUNTER
16 16
REGISTER
16
CC[1:0]
TIMER INTERNAL BUS
16 16

OVERFLOW
OUTPUT COMPARE EDGE DETECT ICAP1
DETECT
CIRCUIT CIRCUIT1 pin
CIRCUIT

6 EDGE DETECT ICAP2

CIRCUIT2 pin

LATCH1 OCMP1
pin
ICF1 OCF1 TOF ICF2 OCF2 0 0 0
LATCH2 OCMP2
(Status Register) SR
pin

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

(Control Register 1) CR1 (Control Register 2) CR2

(See note)

TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)

54/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

16-bit Read Sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register). two steps:
Beginning of the sequence 1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Read LS Byte Note: The TOF bit is not cleared by accessing the
At t0 MS Byte is buffered ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
Other it allows simultaneous use of the overflow function
instructions and reading the free running counter at random
times (for example, to measure elapsed time) with-
Read Returns the buffered out the risk of clearing the TOF bit erroneously.
At t0 +∆t LS Byte LS Byte value at t0 The timer is not affected by WAIT mode.
Sequence completed In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
The user must read the MS Byte first, then the LS previous count (MCU awakened by an interrupt) or
Byte value is buffered automatically. from the reset count (MCU awakened by a Reset).
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the 14.3.3.2 External Clock
user reads the MS Byte several times.
The external clock (where available) is selected if
After a complete reading sequence, if only the CC0=1 and CC1=1 in the CR2 register.
CLR register or ACLR register are read, they re-
The status of the EXEDG bit in the CR2 register
turn the LS Byte of the count value at the time of
determines the type of level transition on the exter-
the read.
nal clock pin EXTCLK that will trigger the free run-
Whatever the timer mode used (input capture, out- ning counter.
put compare, One Pulse mode or PWM mode) an
The counter is synchronised with the falling edge
overflow occurs when the counter rolls over from
of the internal CPU clock.
FFFFh to 0000h then:
A minimum of four falling edges of the CPU clock
– The TOF bit of the SR register is set.
must occur between two consecutive active edges
– A timer interrupt is generated if: of the external clock; thus the external clock fre-
– TOIE bit of the CR1 register is set and quency must be less than a quarter of the CPU
clock frequency.
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

55/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

Figure 32. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFD FFFE FFFF 0000 0001 0002 0003

TIMER OVERFLOW FLAG (TOF)

Figure 33. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000 0001

TIMER OVERFLOW FLAG (TOF)

Figure 34. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.

56/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

14.3.3.3 Input Capture When an input capture occurs:
In this section, the index, i, may be 1 or 2 because – The ICFi bit is set.
there are 2 input capture functions in the 16-bit – The ICiR register contains the value of the free
timer. running counter on the active transition on the
The two input capture 16-bit registers (IC1R and ICAPi pin (see Figure 36).
IC2R) are used to latch the value of the free run- – A timer interrupt is generated if the ICIE bit is set
ning counter after a transition is detected by the and the I bit is cleared in the CC register. Other-
ICAP i pin (see figure 5). wise, the interrupt remains pending until both
MS Byte LS Byte conditions become true.
ICiR ICiHR ICiLR Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
The ICiR register is a read-only register. 1. Reading the SR register while the ICFi bit is set.
The active transition is software programmable 2. An access (read or write) to the ICiLR register.
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]). Notes:
1. After reading the ICiHR register, the transfer of
input capture data is inhibited and ICFi will
Procedure: never be set until the ICiLR register is also
To use the input capture function, select the fol- read.
lowing in the CR2 register: 2. The ICiR register contains the free running
– Select the timer clock (CC[1:0]) (see Table 14 counter value which corresponds to the most
Clock Control Bits). recent input capture.
– Select the edge of the active transition on the 3. The 2 input capture functions can be used
ICAP2 pin with the IEDG2 bit (the ICAP2 pin together even if the timer also uses the 2 output
must be configured as a floating input or input compare functions.
with pull-up without interrupt if this configuration 4. In One Pulse mode and PWM mode only the
is available). input capture 2 function can be used.
And select the following in the CR1 register: 5. The alternate inputs (ICAP1 & ICAP2) are
– Set the ICIE bit to generate an interrupt after an always directly connected to the timer. So any
input capture coming from either the ICAP1 pin transitions on these pins activate the input cap-
or the ICAP2 pin ture function.
– Select the edge of the active transition on the Moreover if one of the ICAPi pin is configured
ICAP1 pin with the IEDG1 bit (the ICAP1 pin as an input and the second one as an output,
must be configured as a floating input or input an interrupt can be generated if the user tog-
with pull-up without interrupt if this configuration gles the output pin and if the ICIE bit is set.
is available). This can be avoided if the input capture func-
tion i is disabled by reading the IC iHR (see note
1).
6. The TOF bit can be used with an interrupt in
order to measure events that exceed the timer
range (FFFFh).

57/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

Figure 35. Input Capture Block Diagram

ICAP1 (Control Register 1) CR1

pin
EDGE DETECT EDGE DETECT ICIE IEDG1
ICAP2 CIRCUIT2 CIRCUIT1
pin (Status Register) SR

IC2R Register IC1R Register ICF1 ICF2 0 0 0

(Control Register 2) CR2

16-BIT
16-BIT FREE RUNNING CC1 CC0 IEDG2
COUNTER

Figure 36. Input Capture Timing Diagram

TIMER CLOCK

COUNTER REGISTER FF01 FF02 FF03

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER FF03

Note: Active edge is rising edge.

58/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

14.3.3.4 Output Compare – The OCMP i pin takes OLVLi bit value (OCMPi
In this section, the index, i, may be 1 or 2 because pin latch is forced low during reset).
there are 2 output compare functions in the 16-bit – A timer interrupt is generated if the OCIE bit is
timer. set in the CR1 register and the I bit is cleared in
This function can be used to control an output the CC register (CC).
waveform or indicate when a period of time has
elapsed. The OCiR register value required for a specific tim-
When a match is found between the Output Com- ing application can be calculated using the follow-
pare register and the free running counter, the out- ing formula:
put compare function:
– Assigns pins with a programmable value if the ∆t * fCPU
OCiE bit is set ∆ OCiR =
PRESC
– Sets a flag in the status register
Where:
– Generates an interrupt if enabled
∆t = Output compare period (in seconds)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R) fCPU = CPU clock frequency (in hertz)
contain the value to be compared to the counter PRESC = Timer prescaler factor (2, 4 or 8 de-
register each timer clock cycle. pending on CC[1:0] bits, see Table 14
MS Byte LS Byte
Clock Control Bits)
OCiR OCiHR OCiLR
If the timer clock is an external clock, the formula
These registers are readable and writable and are is:
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h. ∆ OCiR = ∆t * fEXT
Timing resolution is one count of the free running Where:
counter: (fCPU/CC[1:0]).
∆t = Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register: Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i 1. Reading the SR register while the OCFi bit is
signal. set.
– Select the timer clock (CC[1:0]) (see Table 14 2. An access (read or write) to the OCiLR register.
Clock Control Bits). The following procedure is recommended to pre-
And select the following in the CR1 register: vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMP i pins
after the match occurs. – Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed. – Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register: – Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.

59/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

Notes:
1. After a processor write cycle to the OCiHR reg- Forced Compare Output capability
ister, the output compare function is inhibited When the FOLVi bit is set by software, the OLVLi
until the OCiLR register is also written. bit is copied to the OCMPi pin. The OLVi bit has to
2. If the OCiE bit is not set, the OCMPi pin is a be toggled in order to toggle the OCMPi pin when
general I/O port and the OLVLi bit will not it is enabled (OCiE bit=1). The OCFi bit is then not
appear when a match is found but an interrupt set by hardware, and thus no interrupt request is
could be generated if the OCIE bit is set. generated.
3. When the timer clock is fCPU/2, OCFi and FOLVLi bits have no effect in either One-Pulse
OCMPi are set while the counter value equals mode or PWM mode.
the OCiR register value (see Figure 38 on page
61). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 39 on page 61).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 37. Output Compare Block Diagram

16 BIT FREE RUNNING OC1E OC2E CC1 CC0

COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE Latch
OCIE FOLV2 FOLV1 OLVL2 OLVL1 OCMP1
CIRCUIT 1
Pin
16-bit 16-bit
Latch
2
OCMP2
OC1R Register Pin
OCF1 OCF2 0 0 0
OC2R Register
(Status Register) SR

60/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

Figure 38. Output Compare Timing Diagram, fTIMER =fCPU/2

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 39. Output Compare Timing Diagram, fTIMER =fCPU/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

61/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

14.3.3.5 One Pulse Mode Clearing the Input Capture interrupt request (i.e.
One Pulse mode enables the generation of a clearing the ICFi bit) is done in two steps:
pulse when an external event occurs. This mode is 1. Reading the SR register while the ICFi bit is set.
selected via the OPM bit in the CR2 register. 2. An access (read or write) to the ICiLR register.
The One Pulse mode uses the Input Capture1 The OC1R register value required for a specific
function and the Output Compare1 function. timing application can be calculated using the fol-
Procedure: lowing formula:
To use One Pulse mode: t * fCPU -5
OCiR Value =
1. Load the OC1R register with the value corre- PRESC
sponding to the length of the pulse (see the for- Where:
mula in the opposite column). t = Pulse period (in seconds)
2. Select the following in the CR1 register: fCPU = CPU clock frequency (in hertz)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse. PRESC = Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 14
– Using the OLVL2 bit, select the level to be ap- Clock Control Bits)
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin OCiR = t * fEXT -5
must be configured as floating input).
Where:
3. Select the following in the CR2 register:
t = Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function. fEXT = External timer clock frequency (in hertz)
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 14 When the value of the counter is equal to the value
Clock Control Bits). of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin (see Figure 40).

One Pulse mode cycle Notes:

1. The OCF1 bit cannot be set by hardware in
When One Pulse mode but the OCF2 bit can generate
event occurs OCMP1 = OLVL2
on ICAP1 an Output Compare interrupt.
Counter is reset
to FFFCh 2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
ICF1 bit is set PWM mode is the only active one.
When 3. If OLVL1=OLVL2 a continuous signal will be
Counter seen on the OCMP1 pin.
= OC1R OCMP1 = OLVL1
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
Then, on a valid event on the ICAP1 pin, the coun- loaded) but the user must take care that the
ter is initialized to FFFCh and the OLVL2 bit is counter is reset each time a valid edge occurs
loaded on the OCMP1 pin, the ICF1 bit is set and on the ICAP1 pin and ICF1 can also generates
the value FFFDh is loaded in the IC1R register. interrupt if ICIE is set.
Because the ICF1 bit is set when an active edge 5. When One Pulse mode is used OC1R is dedi-
occurs, an interrupt can be generated if the ICIE cated to this mode. Nevertheless OC2R and
bit is set. OCF2 can be used to indicate that a period of
time has elapsed but cannot generate an output
waveform because the OLVL2 level is dedi-
cated to One Pulse mode.

62/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

Figure 40. One Pulse Mode Timing Example

FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD

COUNTER
2ED3

ICAP1

OCMP1 OLVL2 OLVL1 OLVL2

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 41. Pulse Width Modulation Mode Timing Example

2ED0 2ED1 2ED2 34E2 FFFC

COUNTER 34E2 FFFC FFFD FFFE

OCMP1
OLVL2 OLVL1 OLVL2
compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

63/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

14.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the The OCiR register value required for a specific tim-
generation of a signal with a frequency and pulse ing application can be calculated using the follow-
length determined by the value of the OC1R and ing formula:
OC2R registers. t * fCPU
OCiR Value =
-5
The Pulse Width Modulation mode uses the com-
PRESC
plete Output Compare 1 function plus the OC2R
register, and so these functions cannot be used Where:
when the PWM mode is activated. t = Signal or pulse period (in seconds)
Procedure fCPU = CPU clock frequency (in hertz)
To use Pulse Width Modulation mode: PRESC = Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 14 Clock
1. Load the OC2R register with the value corre- Control Bits)
sponding to the period of the signal using the
formula in the opposite column. If the timer clock is an external clock the formula is:
2. Load the OC1R register with the value corre- OCiR = t * fEXT -5
sponding to the period of the pulse if OLVL1=0
and OLVL2=1, using the formula in the oppo- Where:
site column. t = Signal or pulse period (in seconds)
3. Select the following in the CR1 register: fEXT = External timer clock frequency (in hertz)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register. The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 41)
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful Notes:
comparison with OC2R register. 1. After a write instruction to the OCiHR register,
4. Select the following in the CR2 register: the output compare function is inhibited until the
OCiLR register is also written.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function. 2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode, therefore the Output
– Set the PWM bit.
Compare interrupt is inhibited.
– Select the timer clock (CC[1:0]) (see Table 14
3. The ICF1 bit is set by hardware when the coun-
Clock Control Bits).
ter reaches the OC2R value and can produce a
If OLVL1=1 and OLVL2=0, the length of the posi- timer interrupt if the ICIE bit is set and the I bit is
tive pulse is the difference between the OC2R and cleared.
OC1R registers.
4. In PWM mode the ICAP1 pin can not be used
If OLVL1=OLVL2 a continuous signal will be seen to perform input capture because it is discon-
on the OCMP1 pin. nected from the timer. The ICAP2 pin can be
used to perform input capture (ICF2 can be set
Pulse Width Modulation cycle and IC2R can be loaded) but the user must
take care that the counter is reset after each
period and ICF1 can also generate an interrupt
When if ICIE is set.
Counter OCMP1 = OLVL1
= OC1R 5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
When OCMP1 = OLVL2
Counter Counter is reset
= OC2R to FFFCh
ICF1 bit is set

64/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

14.3.4 Low Power Modes
Mode Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
HALT reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.

14.3.5 Interrupts
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Input Capture 1 event/Counter reset in PWM mode ICF1 Yes No
ICIE
Input Capture 2 event ICF2 Yes No
Output Compare 1 event (not available in PWM mode) OCF1 Yes No
OCIE
Output Compare 2 event (not available in PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).

14.3.6 Summary of Timer modes

AVAILABLE RESOURCES
MODES
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2) Yes Yes Yes Yes
Output Compare (1 and/or 2) Yes Yes Yes Yes
1)
One Pulse mode No Not Recommended No Partially 2)
3)
PWM Mode No Not Recommended No No
1) See note 4 in Section 14.3.3.5 "One Pulse Mode" on page 62
2)
See note 5 in Section 14.3.3.5 "One Pulse Mode" on page 62
3)
See note 4 in Section 14.3.3.6 "Pulse Width Modulation Mode" on page 64

65/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

14.3.7 Register Description Bit 4 = FOLV2 Forced Output Compare 2.
Each Timer is associated with three control and This bit is set and cleared by software.
status registers, and with six pairs of data registers 0: No effect on the OCMP2 pin.
(16-bit values) relating to the two input captures, 1: Forces the OLVL2 bit to be copied to the
the two output compares, the counter and the al- OCMP2 pin, if the OC2E bit is set and even if
ternate counter. there is no successful comparison.

CONTROL REGISTER 1 (CR1) Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.
Read/Write 0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h) 1: Forces OLVL1 to be copied to the OCMP1 pin, if
7 0 the OC1E bit is set and even if there is no suc-
cessful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable. This bit is copied to the OCMP2 pin whenever a
0: Interrupt is inhibited. successful comparison occurs with the OC2R reg-
1: A timer interrupt is generated whenever the ister and OCxE is set in the CR2 register. This val-
ICF1 or ICF2 bit of the SR register is set. ue is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
Bit 6 = OCIE Output Compare Interrupt Enable. This bit determines which type of level transition
0: Interrupt is inhibited. on the ICAP1 pin will trigger the capture.
1: A timer interrupt is generated whenever the 0: A falling edge triggers the capture.
OCF1 or OCF2 bit of the SR register is set. 1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable. Bit 0 = OLVL1 Output Level 1.
0: Interrupt is inhibited. The OLVL1 bit is copied to the OCMP1 pin when-
1: A timer interrupt is enabled whenever the TOF ever a successful comparison occurs with the
bit of the SR register is set. OC1R register and the OC1E bit is set in the CR2
register.

66/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2) Bit 4 = PWM Pulse Width Modulation.
Read/Write 0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Reset Value: 0000 0000 (00h) programmable cyclic signal; the length of the
7 0
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bits 3:2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com- Table 14. Clock Control Bits
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E Timer Clock CC1 CC0
bit, the internal Output Compare 1 function of the fCPU / 4 0 0
timer remains active. fCPU / 2 0 1
0: OCMP1 pin alternate function disabled (I/O pin fCPU / 8 1 0
free for general-purpose I/O).
External Clock (where
1: OCMP1 pin alternate function enabled. 1 1
available)

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the Note: If the external clock pin is not available, pro-
timer on the OCMP2 pin (OLV2 in Output Com- gramming the external clock configuration stops
pare mode). Whatever the value of the OC2E bit, the counter.
the internal Output Compare 2 function of the timer
remains active.
Bit 1 = IEDG2 Input Edge 2.
0: OCMP2 pin alternate function disabled (I/O pin This bit determines which type of level transition
free for general-purpose I/O).
on the ICAP2 pin will trigger the capture.
1: OCMP2 pin alternate function enabled.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse mode.
0: One Pulse mode is not active. Bit 0 = EXEDG External Clock Edge.
1: One Pulse mode is active, the ICAP1 pin can be This bit determines which type of level transition
used to trigger one pulse on the OCMP1 pin; the
on the external clock pin (EXTCLK) will trigger the
active transition is given by the IEDG1 bit. The counter register.
length of the generated pulse depends on the 0: A falling edge triggers the counter register.
contents of the OC1R register.
1: A rising edge triggers the counter register.

67/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

STATUS REGISTER (SR) INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only Read Only
Reset Value: 0000 0000 (00h) Reset Value: Undefined
The three least significant bits are not used. This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
7 0 input capture 1 event).
ICF1 OCF1 TOF ICF2 OCF2 0 0 0 7 0

MSB LSB
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR INPUT CAPTURE 1 LOW REGISTER (IC1LR)
register, then read or write the low byte of the Read Only
IC1R (IC1LR) register. Reset Value: Undefined
This is an 8-bit read only register that contains the
Bit 6 = OCF1 Output Compare Flag 1. low part of the counter value (transferred by the in-
0: No match (reset value). put capture 1 event).
1: The content of the free running counter matches
the content of the OC1R register. To clear this 7 0
bit, first read the SR register, then read or write
the low byte of the OC1R (OC1LR) register. MSB LSB

Bit 5 = TOF Timer Overflow Flag. OUTPUT COMPARE 1 HIGH REGISTER

0: No timer overflow (reset value). (OC1HR)
1: The free running counter has rolled over from
FFFFh to 0000h. To clear this bit, first read the Read/Write
SR register, then read or write the low byte of Reset Value: 1000 0000 (80h)
the CR (CLR) register. This is an 8-bit register that contains the high part
Note: Reading or writing the ACLR register does of the value to be compared to the CHR register.
not clear TOF. 7 0

Bit 4 = ICF2 Input Capture Flag 2. MSB LSB

0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R OUTPUT COMPARE 1 LOW REGISTER
(IC2LR) register. (OC1LR)
Read/Write
Bit 3 = OCF2 Output Compare Flag 2. Reset Value: 0000 0000 (00h)
0: No match (reset value). This is an 8-bit register that contains the low part of
1: The content of the free running counter matches the value to be compared to the CLR register.
the content of the OC2R register. To clear this
bit, first read the SR register, then read or write 7 0
the low byte of the OC2R (OC2LR) register.
MSB LSB
Bit 2-0 = Reserved, forced by hardware to 0.

68/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

OUTPUT COMPARE 2 HIGH REGISTER ALTERNATE COUNTER HIGH REGISTER
(OC2HR) (ACHR)
Read/Write Read Only
Reset Value: 1000 0000 (80h) Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part This is an 8-bit register that contains the high part
of the value to be compared to the CHR register. of the counter value.
7 0 7 0

MSB LSB MSB LSB

OUTPUT COMPARE 2 LOW REGISTER ALTERNATE COUNTER LOW REGISTER

(OC2LR) (ACLR)
Read/Write Read Only
Reset Value: 0000 0000 (00h) Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of This is an 8-bit register that contains the low part of
the value to be compared to the CLR register. the counter value. A write to this register resets the
counter. An access to this register after an access
7 0 to SR register does not clear the TOF bit in SR
register.
MSB LSB
7 0

COUNTER HIGH REGISTER (CHR) MSB LSB

Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value. Read Only
Reset Value: Undefined
7 0 This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
MSB LSB Input Capture 2 event).
7 0

COUNTER LOW REGISTER (CLR) MSB LSB

Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of INPUT CAPTURE 2 LOW REGISTER (IC2LR)
the counter value. A write to this register resets the
counter. An access to this register after accessing Read Only
the SR register clears the TOF bit. Reset Value: Undefined
This is an 8-bit read only register that contains the
7 0 low part of the counter value (transferred by the In-
put Capture 2 event).
MSB LSB
7 0

MSB LSB

69/151
ST72334J/N, ST72314J/N, ST72124J

16-BIT TIMER (Cont’d)

Table 15. 16-Bit Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

Timer A: 32 CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Timer B: 42 Reset Value 0 0 0 0 0 0 0 0
Timer A: 31 CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer B: 41 Reset Value 0 0 0 0 0 0 0 0
Timer A: 33 SR ICF1 OCF1 TOF ICF2 OCF2 - - -
Timer B: 43 Reset Value 0 0 0 0 0 0 0 0
Timer A: 34 ICHR1 MSB LSB
- - - - - -
Timer B: 44 Reset Value - -

Timer A: 35 ICLR1 MSB LSB

- - - - - -
Timer B: 45 Reset Value - -

Timer A: 36 OCHR1 MSB LSB

- - - - - -
Timer B: 46 Reset Value - -

Timer A: 37 OCLR1 MSB LSB

- - - - - -
Timer B: 47 Reset Value - -

Timer A: 3E OCHR2 MSB LSB

- - - - - -
Timer B: 4E Reset Value - -

Timer A: 3F OCLR2 MSB LSB

- - - - - -
Timer B: 4F Reset Value - -

Timer A: 38 CHR MSB LSB

Timer B: 48 Reset Value 1 1 1 1 1 1 1 1

Timer A: 39 CLR MSB LSB

Timer B: 49 Reset Value 1 1 1 1 1 1 0 0

Timer A: 3A ACHR MSB LSB

Timer B: 4A Reset Value 1 1 1 1 1 1 1 1

Timer A: 3B ACLR MSB LSB

Timer B: 4B Reset Value 1 1 1 1 1 1 0 0

Timer A: 3C ICHR2 MSB LSB

- - - - - -
Timer B: 4C Reset Value - -

Timer A: 3D ICLR2 MSB LSB

- - - - - -
Timer B: 4D Reset Value - -

70/151
ST72334J/N, ST72314J/N, ST72124J

14.4 SERIAL PERIPHERAL INTERFACE (SPI)

14.4.1 Introduction 14.4.3 General description
The Serial Peripheral Interface (SPI) allows full- The SPI is connected to external devices through
duplex, synchronous, serial communication with 4 alternate pins:
external devices. An SPI system may consist of a – MISO: Master In Slave Out pin
master and one or more slaves or a system in
which devices may be either masters or slaves. – MOSI: Master Out Slave In pin
The SPI is normally used for communication be- – SCK: Serial Clock pin
tween the microcontroller and external peripherals – SS: Slave select pin
or another microcontroller.
Refer to the Pin Description chapter for the device- A basic example of interconnections between a
specific pin-out. single master and a single slave is illustrated on
Figure 42.
14.4.2 Main Features The MOSI pins are connected together as are
■ Full duplex, three-wire synchronous transfers MISO pins. In this way data is transferred serially
between master and slave (most significant bit
■ Master or slave operation
first).
■ Four master mode frequencies
When the master device transmits data to a slave
■ Maximum slave mode frequency = fCPU/4.
device via MOSI pin, the slave device responds by
■ Four programmable master bit rates sending data to the master device via the MISO
■ Programmable clock polarity and phase pin. This implies full duplex transmission with both
■ End of transfer interrupt flag
data out and data in synchronized with the same
clock signal (which is provided by the master de-
■ Write collision flag protection vice via the SCK pin).
■ Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 45) but master and slave
must be programmed with the same timing mode.
Figure 42. Serial Peripheral Interface Master/Slave

MASTER SLAVE

MSBit LSBit MSBit LSBit

MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI
SCK SCK
CLOCK
GENERATOR
SS +5V SS

71/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 43. Serial Peripheral Interface Block Diagram

Internal Bus

Read
DR

Read Buffer IT
request
MOSI
SR
MISO 8-Bit Shift Register
SPIF WCOL - MODF - - - -

Write

SPI
STATE
SCK
CONTROL
SS

CR

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER
CONTROL

SERIAL
CLOCK
GENERATOR

72/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4 Functional Description In this configuration the MOSI pin is a data output
Figure 42 shows the serial peripheral interface and to the MISO pin is a data input.
(SPI) block diagram.
This interface contains 3 dedicated registers: Transmit sequence
– A Control Register (CR) The transmit sequence begins when a byte is writ-
– A Status Register (SR) ten the DR register.
– A Data Register (DR) The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
Refer to the CR, SR and DR registers in Section and then shifted out serially to the MOSI pin most
14.4.7for the bit definitions. significant bit first.

14.4.4.1 Master Configuration When data transfer is complete:

In a master configuration, the serial clock is gener- – The SPIF bit is set by hardware
ated on the SCK pin.
– An interrupt is generated if the SPIE bit is set
Procedure and the I bit in the CCR register is cleared.
– Select the SPR0 & SPR1 bits to define the se- During the last clock cycle the SPIF bit is set, a
rial clock baud rate (see CR register). copy of the data byte received in the shift register
– Select the CPOL and CPHA bits to define one is moved to a buffer. When the DR register is read,
of the four relationships between the data the SPI peripheral returns this buffered value.
transfer and the serial clock (see Figure 45). Clearing the SPIF bit is performed by the following
– The SS pin must be connected to a high level software sequence:
signal during the complete byte transmit se- 1. An access to the SR register while the SPIF bit
quence. is set
– The MSTR and SPE bits must be set (they re- 2. A read to the DR register.
main set only if the SS pin is connected to a
high level signal). Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.

73/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.2 Slave Configuration When data transfer is complete:
In slave configuration, the serial clock is received – The SPIF bit is set by hardware
on the SCK pin from the master device. – An interrupt is generated if SPIE bit is set and
The value of the SPR0 & SPR1 bits is not used for I bit in CCR register is cleared.
the data transfer. During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
Procedure is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– For correct data transfer, the slave device
must be in the same timing mode as the mas- Clearing the SPIF bit is performed by the following
ter device (CPOL and CPHA bits). See Figure software sequence:
45. 1. An access to the SR register while the SPIF bit
– The SS pin must be connected to a low level is set.
signal during the complete byte transmit se- 2.A read to the DR register.
quence.
– Clear the MSTR bit and set the SPE bit to as- Notes: While the SPIF bit is set, all writes to the
sign the pins to alternate function. DR register are inhibited until the SR register is
In this configuration the MOSI pin is a data input read.
and the MISO pin is a data output. The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
Transmit Sequence the second SPIF bit in order to prevent an overrun
condition (see Section 14.4.4.6).
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle Depending on the CPHA bit, the SS pin has to be
and then shifted out serially to the MISO pin most set to write to the DR register between each data
significant bit first. byte transfer to avoid a write collision (see Section
14.4.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.

74/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.3 Data Transfer Format The master device applies data to its MOSI pin-
During an SPI transfer, data is simultaneously clock edge before the capture clock edge.
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn- CPHA bit is set
chronize the data transfer during a sequence of
eight clock pulses. The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
The SS pin allows individual selection of a slave set) is the MSBit capture strobe. Data is latched on
device; the other slave devices that are not select- the occurrence of the second clock transition.
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Clock Phase and Clock Polarity Figure 44).
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits. CPHA bit is reset
The CPOL (clock polarity) bit controls the steady The first edge on the SCK pin (falling edge if CPOL
state value of the clock when no data is being bit is set, rising edge if CPOL bit is reset) is the
transferred. This bit affects both master and slave MSBit capture strobe. Data is latched on the oc-
modes. currence of the first clock transition.
The combination between the CPOL and CPHA The SS pin must be toggled high and low between
(clock phase) bits selects the data capture clock each byte transmitted (see Figure 44).
edge.
To protect the transmission from a write collision a
Figure 45, shows an SPI transfer with the four low value on the SS pin of a slave device freezes
combinations of the CPHA and CPOL bits. The di- the data in its DR register and does not allow it to
agram may be interpreted as a master or slave be altered. Therefore the SS pin must be high to
timing diagram where the SCK pin, the MISO pin, write a new data byte in the DR without producing
the MOSI pin are directly connected between the a write collision.
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.

Figure 44. CPHA / SS Timing Diagram

MOSI/MISO Byte 1 Byte 2 Byte 3

Master SS

Slave SS
(CPHA=0)

Slave SS
(CPHA=1)
VR02131A

75/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 45. Data Clock Timing Diagram

CPHA =1
SCLK (with
CPOL = 1)

SCLK (with
CPOL = 0)

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO
(from master)

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MOSI
(from slave)

SS
(to slave)
CAPTURE STROBE

CPHA =0

CPOL = 1

CPOL = 0

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter. VR02131B

76/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.4 Write Collision Error When the CPHA bit is reset:
A write collision occurs when the software tries to Data is latched on the occurrence of the first clock
write to the DR register while a data transfer is tak- transition. The slave device does not have any
ing place with an external device. When this hap- way of knowing when that transition will occur;
pens, the transfer continues uninterrupted; and therefore, the slave device collision occurs when
the software write will be unsuccessful. software attempts to write the DR register after its
Write collisions can occur both in master and slave SS pin has been pulled low.
mode. For this reason, the SS pin must be high, between
Note: a "read collision" will never occur since the each data byte transfer, to allow the CPU to write
received data byte is placed in a buffer in which in the DR register without generating a write colli-
access is always synchronous with the MCU oper- sion.
ation.
In Slave mode In Master mode
When the CPHA bit is set: Collision in the master device is defined as a write
The slave device will receive a clock (SCK) edge of the DR register while the internal serial clock
prior to the latch of the first data transfer. This first (SCK) is in the process of transfer.
clock edge will freeze the data in the slave device The SS pin signal must be always high on the
DR register and output the MSBit on to the exter- master device.
nal MISO pin of the slave device.
The SS pin low state enables the slave device but WCOL bit
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock The WCOL bit in the SR register is set if a write
edge. collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 46).

Figure 46. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SR Read SR
1st Step
OR
THEN
THEN SPIF =0
2nd Step Read DR SPIF =0 Write DR WCOL=0 if no transfer has started
WCOL=0 WCOL=1 if a transfer has started
before the 2nd step

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SR
1st Step

THEN
Note: Writing to the DR register
2nd Step Read DR WCOL=0 instead of reading in it does not
reset the WCOL bit

77/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.5 Master Mode Fault may be restored to their original state during or af-
Master mode fault occurs when the master device ter this clearing sequence.
has its SS pin pulled low, then the MODF bit is set. Hardware does not allow the user to set the SPE
Master mode fault affects the SPI peripheral in the and MSTR bits while the MODF bit is set except in
following ways: the MODF bit clearing sequence.
– The MODF bit is set and an SPI interrupt is In a slave device the MODF bit can not be set, but
generated if the SPIE bit is set. in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph- The MODF bit indicates that there might have
eral. been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
– The MSTR bit is reset, thus forcing the device set or default system state using an interrupt rou-
into slave mode. tine.

Clearing the MODF bit is done through a software 14.4.4.6 Overrun Condition
sequence:
An overrun condition occurs when the master de-
1. A read or write access to the SR register while vice has sent several data bytes and the slave de-
the MODF bit is set. vice has not cleared the SPIF bit issuing from the
2. A write to the CR register. previous data byte transmitted.
In this case, the receiver buffer contains the byte
Notes: To avoid any multiple slave conflicts in the sent after the SPIF bit was last cleared. A read to
case of a system comprising several MCUs, the the DR register returns this byte. All other bytes
SS pin must be pulled high during the clearing se- are lost.
quence of the MODF bit. The SPE and MSTR bits This condition is not detected by the SPI peripher-
al.

78/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems: For more security, the slave device may respond
– Single Master System to the master with the received data byte. Then the
master will receive the previous byte back from the
– Multimaster System slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
Single Master System
A typical single master system may be configured, Other transmission security methods can use
ports for handshake lines or data bytes with com-
using an MCU as the master and four MCUs as
mand fields.
slaves (see Figure 47).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control A multi-master system may also be configured by
the four SS pins of the slave devices. the user. Transfer of master control could be im-
plemented using a handshake method through the
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at I/O ports or by an exchange of code messages
through the serial peripheral interface system.
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
Note: To prevent a bus conflict on the MISO line in the SR register.
the master allows only one active slave device
during a transmission.
Figure 47. Single Master Configuration

SS SS SS SS
SCK SCK SCK SCK
Slave Slave Slave Slave
MCU MCU MCU MCU

MOSI MISO MOSI MISO MOSI MISO MOSI MISO

MOSI MISO
SCK
Ports

Master
MCU

5V SS

79/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.5 Low Power Modes
Mode Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
HALT In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.

14.4.6 Interrupts

Enable Exit Exit

Event
Interrupt Event Control from from
Flag
Bit Wait Halt
SPI End of Transfer Event SPIF Yes No
SPIE
Master Mode Fault Event MODF Yes No

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).

80/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.7 Register Description
CONTROL REGISTER (CR)
Read/Write Bit 3 = CPOL Clock polarity.
Reset Value: 0000xxxx (0xh) This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
7 0 CPOL bit affects both the master and slave
modes.
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software. Bit 2 = CPHA Clock phase.
0: Interrupt is inhibited This bit is set and cleared by software.
1: An SPI interrupt is generated whenever SPIF=1 0: The first clock transition is the first data capture
or MODF=1 in the SR register edge.
1: The second clock transition is the first capture
Bit 6 = SPE Serial peripheral output enable. edge.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0 Bit 1:0 = SPR[1:0] Serial peripheral rate.
(see Section 14.4.4.5 "Master Mode Fault" on These bits are set and cleared by software.Used
page 78). with the SPR2 bit, they select one of six baud rates
0: I/O port connected to pins to be used as the serial clock when the device is a
1: SPI alternate functions connected to pins master.
The SPE bit is cleared by reset, so the SPI periph- These 2 bits have no effect in slave mode.
eral is not initially connected to the external pins.
Table 16. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable. Serial Clock SPR2 SPR1 SPR0
this bit is set and cleared by software and it is fCPU/4 1 0 0
cleared by reset. It is used with the SPR[1:0] bits to fCPU/8 0 0 0
set the baud rate. Refer to Table 16.
fCPU/16 0 0 1
0: Divider by 2 enabled
1: Divider by 2 disabled fCPU/32 1 1 0
fCPU/64 0 1 0
Bit 4 = MSTR Master. fCPU/128 0 1 1
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 14.4.4.5 "Master Mode Fault" on
page 78).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.

81/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

STATUS REGISTER (SR) DATA I/O REGISTER (DR)
Read Only Read/Write
Reset Value: 0000 0000 (00h) Reset Value: Undefined
7 0 7 0

SPIF WCOL - MODF - - - - D7 D6 D5 D4 D3 D2 D1 D0

Bit 7 = SPIF Serial Peripheral data transfer flag. The DR register is used to transmit and receive
This bit is set by hardware when a transfer has data on the serial bus. In the master device only a
been completed. An interrupt is generated if write to this register will initiate transmission/re-
SPIE=1 in the CR register. It is cleared by a soft- ception of another byte.
ware sequence (an access to the SR register fol- Notes: During the last clock cycle the SPIF bit is
lowed by a read or write to the DR register). set, a copy of the received data byte in the shift
0: Data transfer is in progress or has been ap- register is moved to a buffer. When the user reads
proved by a clearing sequence. the serial peripheral data I/O register, the buffer is
1: Data transfer between the device and an exter- actually being read.
nal device has been completed.
Warning:
Note: While the SPIF bit is set, all writes to the DR
register are inhibited. A write to the DR register places data directly into
the shift register for transmission.
A read to the the DR register returns the value lo-
Bit 6 = WCOL Write Collision status. cated in the buffer and not the contents of the shift
This bit is set by hardware when a write to the DR register (See Figure 43 ).
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 46).
0: No write collision occurred
1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF Mode Fault flag.

This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 14.4.4.5
"Master Mode Fault" on page 78). An SPI interrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An ac-
cess to the SR register while MODF=1 followed by
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected

Bits 3-0 = Unused.

82/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 17. SPI Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

SPIDR MSB LSB

0021h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0022h
Reset Value 0 0 0 0 x x x x
SPISR SPIF WCOL MODF
0023h
Reset Value 0 0 0 0 0 0 0 0

83/151
ST72334J/N, ST72314J/N, ST72124J

14.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

14.5.1 Introduction 14.5.3 General Description
The Serial Communications Interface (SCI) offers The interface is externally connected to another
a flexible means of full-duplex data exchange with device by two pins (see Figure 49):
external equipment requiring an industry standard – TDO: Transmit Data Output. When the transmit-
NRZ asynchronous ter is disabled, the output pin returns to its I/O
serial data format. The SCI offers a very wide port configuration. When the transmitter is ena-
range of baud rates using two baud rate generator bled and nothing is to be transmitted, the TDO
systems. pin is at high level.
14.5.2 Main Features – RDI: Receive Data Input is the serial data input.
■ Full duplex, asynchronous communications Oversampling techniques are used for data re-
covery by discriminating between valid incoming
■ NRZ standard format (Mark/Space)
data and noise.
■ Dual baud rate generator systems
Through this pins, serial data is transmitted and re-
■ Independently programmable transmit and ceived as frames comprising:
receive baud rates up to 250K baud using
conventional baud rate generator and up to – An Idle Line prior to transmission or reception
500K baud using the extended baud rate – A start bit
generator. – A data word (8 or 9 bits) least significant bit first
■ Programmable data word length (8 or 9 bits)
– A Stop bit indicating that the frame is complete.
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags This interface uses two types of baud rate generator:
■ Two receiver wake-up modes:
– A conventional type for commonly-used baud
rates,
– Address bit (MSB)
– An extended type with a prescaler offering a very
– Idle line wide range of baud rates even with non-standard
■ Muting function for multiprocessor configurations oscillator frequencies.
■ LIN compatible (if MCU clock frequency 14.5.4 LIN Protocol support
tolerance ≤2%)
For LIN applications where resynchronization is
■ Separate enable bits for Transmitter and not required (application clock tolerance less than
Receiver or equal to 2%) the LIN protocol can be efficiently
■ Three error detection flags: implemented with this standard SCI.
– Overrun error
– Noise error
– Frame error
■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected

84/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 48. SCI Block Diagram

Write Read (DATA REGISTER) DR

Transmit Data Register (TDR) Received Data Register (RDR)

TDO

Transmit Shift Register Received Shift Register

RDI

CR1
R8 T8 - M WAKE - - -

WAKE
TRANSMIT UP RECEIVER RECEIVER
CONTROL UNIT CONTROL CLOCK

CR2 SR
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE -

SCI
INTERRUPT
CONTROL

TRANSMITTER
CLOCK

TRANSMITTER RATE
CONTROL
fCPU
/16 /2 /PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

85/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.5 Functional Description 14.5.5.1 Serial Data Format
The block diagram of the Serial Control Interface, Word length may be selected as being either 8 or 9
is shown in Figure 48. It contains 6 dedicated reg- bits by programming the M bit in the CR1 register
isters: (see Figure 48).
– Two control registers (CR1 & CR2) The TDO pin is in low state during the start bit.
– A status register (SR) The TDO pin is in high state during the stop bit.
– A baud rate register (BRR) An Idle character is interpreted as an entire frame
– An extended prescaler receiver register (ERPR) of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler transmitter register (ETPR)
A Break character is interpreted on receiving “0”s
Refer to the register descriptions in Section for some multiple of the frame period. At the end of
14.5.8for the definitions of each bit. the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 49. Word length programming

9-bit Word length (M bit is set)

Possible Next Data Frame
Parity
Data Frame Bit Next
Start
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Stop Start
Bit
Bit Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

8-bit Word length (M bit is reset)

Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

86/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.5.2 Transmitter When a frame transmission is complete (after the
The transmitter can send data words of either 8 or stop bit or after the break frame) the TC bit is set
9 bits depending on the M bit status. When the M and an interrupt is generated if the TCIE is set and
bit is set, word length is 9 bits and the 9th bit (the the I bit is cleared in the CCR register.
MSB) has to be stored in the T8 bit in the CR1 reg- Clearing the TC bit is performed by the following
ister. software sequence:
Character Transmission 1. An access to the SR register
2. A write to the DR register
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode, Note: The TDRE and TC bits are cleared by the
the DR register consists of a buffer (TDR) between same software sequence.
the internal bus and the transmit shift register (see Break Characters
Figure 48). Setting the SBK bit loads the shift register with a
Procedure break character. The break frame length depends
– Select the M bit to define the word length. on the M bit (see Figure 49).
– Select the desired baud rate using the BRR and As long as the SBK bit is set, the SCI send break
the ETPR registers. frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
– Set the TE bit to assign the TDO pin to the alter- the last break frame to guarantee the recognition
nate function and to send a idle frame as first of the start bit of the next frame.
transmission.
Idle Characters
– Access the SR register and write the data to
send in the DR register (this sequence clears the Setting the TE bit drives the SCI to send an idle
TDRE bit). Repeat this sequence for each data to frame before the first data frame.
be transmitted. Clearing and then setting the TE bit during a trans-
Clearing the TDRE bit is always performed by the mission sends an idle frame after the current word.
following software sequence: Note: Resetting and setting the TE bit causes the
1. An access to the SR register data in the TDR register to be lost. Therefore the
2. A write to the DR register best time to toggle the TE bit is when the TDRE bit
The TDRE bit is set by hardware and it indicates: is set i.e. before writing the next byte in the DR.
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.

87/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.5.3 Receiver Overrun Error
The SCI can receive data words of either 8 or 9 An overrun error occurs when a character is re-
bits. When the M bit is set, word length is 9 bits ceived when RDRF has not been reset. Data can
and the MSB is stored in the R8 bit in the CR1 reg- not be transferred from the shift register to the
ister. TDR register as long as the RDRF bit is not
Character reception cleared.
During a SCI reception, data shifts in least signifi- When a overrun error occurs:
cant bit first through the RDI pin. In this mode, DR – The OR bit is set.
register consists in a buffer (RDR) between the in- – The RDR content will not be lost.
ternal bus and the received shift register (see Fig-
ure 48). – The shift register will be overwritten.
Procedure – An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Select the M bit to define the word length.
The OR bit is reset by an access to the SR register
– Select the desired baud rate using the BRR and followed by a DR register read operation.
the ERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit. Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
When a character is received: and noise.
– The RDRF bit is set. It indicates that the content When noise is detected in a frame:
of the shift register is transferred to the RDR.
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register. – Data is transferred from the Shift register to the
DR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re- – No interrupt is generated. However this bit rises
ception. at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by: The NF bit is reset by a SR register read operation
followed by a DR register read operation.
1. An access to the SR register
Framing Error
2. A read to the DR register.
A framing error is detected when:
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun – The stop bit is not recognized on reception at the
error. expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SCI han-
dles it as a framing error. When the framing error is detected:
Idle Character – the FE bit is set by hardware
When a idle frame is detected, there is the same – Data is transferred from the Shift register to the
procedure as a data received character plus an in- DR register.
terrupt if the ILIE bit is set and the I bit is cleared in – No interrupt is generated. However this bit rises
the CCR register. at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.

88/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 50. SCI Baud Rate and Extended Prescaler Block Diagram

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER

ERPR
EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

fCPU TRANSMITTER
CLOCK

TRANSMITTER RATE
CONTROL
/16 /2 /PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER
CLOCK

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

89/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.5.4 Conventional Baud Rate Generation than zero. The baud rates are calculated as fol-
The baud rate for the receiver and transmitter (Rx lows:
and Tx) are set independently and calculated as
follows: fCPU fCPU
Tx = Rx =
fCPU fCPU 16*ETPR 16*ERPR
Tx = Rx =
(32*PR)*TR (32*PR)*RR
with:
with: ETPR = 1,..,255 (see ETPR register)
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) ERPR = 1,.. 255 (see ERPR register)
TR = 1, 2, 4, 8, 16, 32, 64,128 14.5.5.6 Receiver Muting and Wake-up Feature
(see SCT0, SCT1 & SCT2 bits) In multiprocessor configurations it is often desira-
RR = 1, 2, 4, 8, 16, 32, 64,128 ble that only the intended message recipient
(see SCR0,SCR1 & SCR2 bits) should actively receive the full message contents,
thus reducing redundant SCI service overhead for
All this bits are in the BRR register. all non addressed receivers.
Example: If fCPU is 8 MHz (normal mode) and if The non addressed devices may be placed in
PR=13 and TR=RR=1, the transmit and receive sleep mode by means of the muting function.
baud rates are 19200 baud.
Setting the RWU bit by software puts the SCI in
Note: the baud rate registers MUST NOT be sleep mode:
changed while the transmitter or the receiver is en-
abled. All the reception status bits can not be set.
14.5.5.5 Extended Baud Rate Generation All the receive interrupt are inhibited.
The extended prescaler option gives a very fine A muted receiver may be awakened by one of the
tuning on the baud rate, using a 255 value prescal- following two ways:
er, whereas the conventional Baud Rate Genera- – by Idle Line detection if the WAKE bit is reset,
tor retains industry standard software compatibili- – by Address Mark detection if the WAKE bit is set.
ty.
Receiver wakes-up by Idle Line detection when
The extended baud rate generator block diagram the Receive line has recognised an Idle Frame.
is described in the Figure 50. Then the RWU bit is reset by hardware but the
The output clock rate sent to the transmitter or to IDLE bit is not set.
the receiver will be the output from the 16 divider Receiver wakes-up by Address Mark detection
divided by a factor ranging from 1 to 255 set in the when it received a “1” as the most significant bit of
ERPR or the ETPR register. a word, thus indicating that the message is an ad-
Note: the extended prescaler is activated by set- dress. The reception of this particular word wakes
ting the ETPR or ERPR register to a value other up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.

90/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.6 Low Power Modes
Mode Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

14.5.7 Interrupts
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Transmit Data Register Empty TDRE TIE Yes No
Transmission Complete TC TCIE Yes No
Received Data Ready to be Read RDRF Yes No
RIE
Overrrun Error Detected OR Yes No
Idle Line Detected IDLE ILIE Yes No

The SCI interrupt events are connected to the These events generate an interrupt if the corre-
same interrupt vector (see Interrupts chapter). sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).

91/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.8 Register Description Note: The IDLE bit will not be set again until the
STATUS REGISTER (SR) RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
Read Only ceiver wakes up from wake-up mode.
Reset Value: 1100 0000 (C0h)
7 0 Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
TDRE TC RDRF IDLE OR NF FE - being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
Bit 7 = TDRE Transmit data register empty. ister. It is cleared by a software sequence (an ac-
This bit is set by hardware when the content of the cess to the SR register followed by a read to the
TDR register has been transferred into the shift DR register).
register. An interrupt is generated if the TIE =1 in 0: No Overrun error
the CR2 register. It is cleared by a software se- 1: Overrun error is detected
quence (an access to the SR register followed by a
write to the DR register).
0: Data is not transferred to the shift register Note: When this bit is set RDR register content will
1: Data is transferred to the shift register not be lost but the shift register will be overwritten.
Note: data will not be transferred to the shift regis- Bit 2 = NF Noise flag.
ter as long as the TDRE bit is not reset. This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SR register followed by a
Bit 6 = TC Transmission complete. read to the DR register).
This bit is set by hardware when transmission of a 0: No noise is detected
frame containing Data, a Preamble or a Break is 1: Noise is detected
complete. An interrupt is generated if TCIE=1 in Note: This bit does not generate interrupt as it ap-
the CR2 register. It is cleared by a software se- pears at the same time as the RDRF bit which it-
quence (an access to the SR register followed by a self generates an interrupt.
write to the DR register).
0: Transmission is not complete
1: Transmission is complete Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
Bit 5 = RDRF Received data ready flag. tion, excessive noise or a break character is de-
This bit is set by hardware when the content of the tected. It is cleared by a software sequence (an
RDR register has been transferred into the DR access to the SR register followed by a read to the
register. An interrupt is generated if RIE=1 in the DR register).
CR2 register. It is cleared by a software sequence 0: No Framing error is detected
(an access to the SR register followed by a read to 1: Framing error or break character is detected
the DR register). Note: This bit does not generate interrupt as it ap-
0: Data is not received pears at the same time as the RDRF bit which it-
1: Received data is ready to be read self generates an interrupt. If the word currently
being transferred causes both frame error and
Bit 4 = IDLE Idle line detect. overrun error, it will be transferred and only the OR
This bit is set by hardware when a Idle Line is de- bit will be set.
tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by a software se- Bit 0 = Unused.
quence (an access to the SR register followed by a
read to the DR register).
0: No Idle Line is detected
1: Idle Line is detected

92/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (CR1) 1: An SCI interrupt is generated whenever TC=1 in
Read/Write the SR register
Reset Value: Undefined
Bit 5 = RIE Receiver interrupt enable .
7 0 This bit is set and cleared by software.
0: interrupt is inhibited
R8 T8 - M WAKE - - - 1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received Bit 4 = ILIE Idle line interrupt enable.
word when M=1. This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
Bit 6 = T8 Transmit data bit 8. in the SR register.
This bit is used to store the 9th bit of the transmit-
ted word when M=1. Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
Bit 4 = M Word length.
cleared by software.
This bit determines the word length. It is set or
0: Transmitter is disabled, the TDO pin is back to
cleared by software.
the I/O port configuration.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: Transmitter is enabled
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
Bit 3 = WAKE Wake-Up method. current word.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line Bit 2 = RE Receiver enable.
1: Address Mark This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled.
CONTROL REGISTER 2 (CR2) 1: Receiver is enabled and begins searching for a
Read/Write start bit.
Reset Value: 0000 0000 (00 h)
Bit 1 = RWU Receiver wake-up.
7 0 This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
TIE TCIE RIE ILIE TE RE RWU SBK cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
Bit 7 = TIE Transmitter interrupt enable. 1: Receiver in mute mode
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever Bit 0 = SBK Send break.
TDRE=1 in the SR register. This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
Bit 6 = TCIE Transmission complete interrupt ena- 1: Break characters are transmitted
ble
Note: If the SBK bit is set to “1” and then to “0”, the
This bit is set and cleared by software. transmitter will send a BREAK word at the end of
0: interrupt is inhibited the current word.

93/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (DR) Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write These 3 bits, in conjunction with the SCP1 & SCP0
Reset Value: Undefined bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
Contains the Received or Transmitted data char- al Baud Rate Generator mode.
acter, depending on whether it is read from or writ-
ten to. TR dividing factor SCT2 SCT1 SCT0
1 0 0 0
7 0
2 0 0 1
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 4 0 1 0
8 0 1 1
The Data register performs a double function (read 16 1 0 0
and write) since it is composed of two registers, 32 1 0 1
one for transmission (TDR) and one for reception
(RDR). 64 1 1 0
The TDR register provides the parallel interface 128 1 1 1
between the internal bus and the output shift reg-
ister (see Figure 48). Note: this TR factor is used only when the ETPR
The RDR register provides the parallel interface fine tuning factor is equal to 00h; otherwise, TR is
between the input shift register and the internal replaced by the ETPR dividing factor.
bus (see Figure 48).
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
BAUD RATE REGISTER (BRR)
These 3 bits, in conjunction with the SCP1 & SCP0
Read/Write bits define the total division applied to the bus
Reset Value: 00xx xxxx (XXh) clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
7 0
RR dividing factor SCR2 SCR1 SCR0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 1 0 0 0
2 0 0 1
Bit 7:6= SCP[1:0] First SCI Prescaler 4 0 1 0
These 2 prescaling bits allow several standard
8 0 1 1
clock division ranges:
16 1 0 0
PR Prescaling factor SCP1 SCP0
32 1 0 1
1 0 0 64 1 1 0
3 0 1
128 1 1 1
4 1 0
13 1 1 Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.

94/151
ST72334J/N, ST72314J/N, ST72124J

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ERPR) REGISTER (ETPR)
Read/Write Read/Write
Reset Value: 0000 0000 (00 h) Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit. sion factor for the transmit circuit.
7 0 7 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres- Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register. caler Register.
The extended Baud Rate Generator is activated The extended Baud Rate Generator is activated
when a value different from 00h is stored in this when a value different from 00h is stored in this
register. Therefore the clock frequency issued register. Therefore the clock frequency issued
from the 16 divider (see Figure 50) is divided by from the 16 divider (see Figure 50) is divided by
the binary factor set in the ERPR register (in the the binary factor set in the ETPR register (in the
range 1 to 255). range 1 to 255).
The extended baud rate generator is not used af- The extended baud rate generator is not used af-
ter a reset. ter a reset.

Table 18. SCI Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

SCISR TDRE TC RDRF IDLE OR NF FE

0050h
Reset Value 1 1 0 0 0 0 0 0
SCIDR MSB LSB
0051h
Reset Value x x x x x x x x
SCIBRR SOG VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV
0052h
Reset Value 0 0 x x x x x x
SCICR1 R8 T8 M WAKE
0053h
Reset Value x x 0 x x 0 0 0
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
0054h
Reset Value 0 0 0 0 0 0 0 0
SCIPBRR MSB LSB
0055h
Reset Value 0 0 0 0 0 0 0 0
SCIPBRT MSB LSB
0057h
Reset Value 0 0 0 0 0 0 0 0

95/151
ST72334J/N, ST72314J/N, ST72124J

14.6 8-BIT A/D CONVERTER (ADC)

14.6.1 Introduction 14.6.3 Functional Description

The on-chip Analog to Digital Converter (ADC) pe- 14.6.3.1 Analog Power Supply
ripheral is a 8-bit, successive approximation con- VDDA and VSSA are the high and low level refer-
verter with internal sample and hold circuitry. This ence voltage pins. In some devices (refer to device
peripheral has up to 16 multiplexed analog input pin out description) they are internally connected
channels (refer to device pin out description) that to the VDD and V SS pins.
allow the peripheral to convert the analog voltage
levels from up to 16 different sources. Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
The result of the conversion is stored in a 8-bit loaded or badly decoupled power supply lines.
Data Register. The A/D converter is controlled
through a Control/Status Register. See electrical characteristics section for more de-
tails.
14.6.2 Main Features
■ 8-bit conversion

■ Up to 16 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The block diagram is shown in Figure 51.

Figure 51. ADC Block Diagram

fCPU fADC
DIV 2

COCO 0 ADON 0 CH3 CH2 CH1 CH0 ADCCSR

AIN0
HOLD CONTROL

AIN1 RADC
ANALOG ANALOG TO DIGITAL
MUX CONVERTER

AINx CADC

ADCDR D7 D6 D5 D4 D3 D2 D1 D0

96/151
ST72334J/N, ST72314J/N, ST72124J

8-BIT A/D CONVERTER (ADC) (Cont’d)

14.6.3.2 Digital A/D Conversion Result The analog input ports must be configured as in-
The conversion is monotonic, meaning that the re- put, no pull-up, no interrupt. Refer to the «I/O
sult never decreases if the analog input does not ports» chapter. Using these pins as analog inputs
and never increases if the analog input does not. does not affect the ability of the port to be read as
a logic input.
If the input voltage (VAIN) is greater than or equal
to V DDA (high-level voltage reference) then the In the CSR register:
conversion result in the DR register is FFh (full – Select the CH[3:0] bits to assign the analog
scale) without overflow indication. channel to be converted.
If input voltage (VAIN) is lower than or equal to ADC Conversion
VSSA (low-level voltage reference) then the con- In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
The A/D converter is linear and the digital result of and to start the first conversion. From this time
the conversion is stored in the ADCDR register. on, the ADC performs a continuous conver-
The accuracy of the conversion is described in the sion of the selected channel.
parametric section. When a conversion is complete
RAIN is the maximum recommended impedance – The COCO bit is set by hardware.
for an analog input signal. If the impedance is too – No interrupt is generated.
high, this will result in a loss of accuracy due to – The result is in the DR register and remains
leakage and sampling not being completed in the valid until the next conversion has ended.
alloted time. A write to the CSR register (with ADON set) aborts
14.6.3.3 A/D Conversion Phases the current conversion, resets the COCO bit and
The A/D conversion is based on two conversion starts a new conversion.
phases as shown in Figure 52:
Figure 52. ADC Conversion Timings
■ Sample capacitor loading [duration: tLOAD]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample ADON
ADCCSR WRITE
capacitor. tCONV
OPERATION
■ A/D conversion [duration: tCONV]
During this phase, the A/D conversion is HOLD
computed (8 successive approximations cycles) CONTROL
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum tLOAD
analog to digital conversion accuracy. COCO BIT SET

While the ADC is on, these two phases are contin-

uously repeated. 14.6.4 Low Power Modes
At the end of each conversion, the sample capaci- Mode Description
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it WAIT No effect on A/D Converter
minimizes the current consumption on the analog A/D Converter disabled.
pin in case of single input channel measurement. After wakeup from Halt mode, the A/D Con-
HALT
verter requires a stabilisation time before ac-
14.6.3.4 Software Procedure
curate conversions can be performed.
Refer to the control/status register (CSR) and data
register (DR) in Section 14.6.6 for the bit defini- Note: The A/D converter may be disabled by reset-
tions and to Figure 52 for the timings. ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
ADC Configuration and between single shot conversions.
The total duration of the A/D conversion is 12 ADC
clock periods (1/fADC=2/fCPU). 14.6.5 Interrupts
None

97/151
ST72334J/N, ST72314J/N, ST72124J

8-BIT A/D CONVERTER (ADC) (Cont’d)

14.6.6 Register Description
CONTROL/STATUS REGISTER (CSR) DATA REGISTER (DR)
Read /Write Read Only
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)

7 0 7 0

COCO 0 ADON 0 CH3 CH2 CH1 CH0 D7 D6 D5 D4 D3 D2 D1 D0

Bit 7 = COCO Conversion Complete

This bit is set by hardware. It is cleared by soft- Bits 7:0 = D[7:0] Analog Converted Value
ware reading the result in the DR register or writing This register contains the converted analog value
to the CSR register. in the range 00h to FFh.
0: Conversion is not complete
1: Conversion can be read from the DR register Note: Reading this register reset the COCO flag.

Bit 6 = Reserved. must always be cleared.

Bit 5 = ADON A/D Converter On

This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on

Bit 4 = Reserved. must always be cleared.

Bits 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin* CH3 CH2 CH1 CH0
AIN0 0 0 0 0
AIN1 0 0 0 1
AIN2 0 0 1 0
AIN3 0 0 1 1
AIN4 0 1 0 0
AIN5 0 1 0 1
AIN6 0 1 1 0
AIN7 0 1 1 1
AIN8 1 0 0 0
AIN9 1 0 0 1
AIN10 1 0 1 0
AIN11 1 0 1 1
AIN12 1 1 0 0
AIN13 1 1 0 1
AIN14 1 1 1 0
AIN15 1 1 1 1
*Note: The number of pins AND the channel selec-
tion varies according to the device. Refer to the de-
vice pinout.

98/151
ST72334J/N, ST72314J/N, ST72124J

8-BIT A/D CONVERTER (ADC) (Cont’d)

Table 19. ADC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

ADCDR D7 D6 D5 D4 D3 D2 D1 D0
0070h
Reset Value 0 0 0 0 0 0 0 0
ADCCSR COCO ADON CH3 CH2 CH1 CH0
0071h
Reset Value 0 0 0 0 0 0 0 0

99/151
ST72334J/N, ST72314J/N, ST72124J

15 INSTRUCTION SET

15.1 ST7 ADDRESSING MODES so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups: – Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
Addressing Mode Example however it uses more bytes and more CPU cy-
Inherent nop cles.
Immediate ld A,#$55 – Short addressing mode is less powerful because
it can generally only access page zero (0000h -
Direct ld A,$55 00FFh range), but the instruction size is more
Indexed ld A,($55,X) compact, and faster. All memory to memory in-
Indirect ld A,([$55],X) structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
Relative jrne loop INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Bit operation bset byte,#5 The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 20. ST7 Addressing Mode Overview

Pointer Pointer
Destination/ Length
Mode Syntax Address Size
Source (Bytes)
(Hex.) (Hex.)
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X register)
No Offset Direct Indexed ld A,(X) 00..FF
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF +2
Short Indirect ld A,[$10] 00..FF 00..FF byte +2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2
1)
Relative Direct jrne loop PC-128/PC+127 +1
Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte +2
Bit Direct bset $10,#7 00..FF +1
Bit Indirect bset [$10],#7 00..FF 00..FF byte +2
Bit Direct Relative btjt $10,#7,skip 00..FF +2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.

100/151
ST72334J/N, ST72314J/N, ST72124J

ST7 ADDRESSING MODES (Cont’d)

15.1.1 Inherent 15.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent Instruction Function modes:
NOP No operation Direct (short)
TRAP S/W Interrupt The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
Wait For Interrupt (Low Power ing space.
WFI
Mode)
Direct (long)
Halt Oscillator (Lowest Power
HALT The address is a word, thus allowing 64 Kbyte ad-
Mode)
dressing space, but requires 2 bytes after the op-
RET Sub-routine Return code.
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask
15.1.4 Indexed (No Offset, Short, Long)
RIM Reset Interrupt Mask
In this mode, the operand is referenced by its
SCF Set Carry Flag memory address, which is defined by the unsigned
RCF Reset Carry Flag addition of an index register (X or Y) with an offset.
RSP Reset Stack Pointer The indirect addressing mode consists of three
sub-modes:
LD Load
Indexed (No Offset)
CLR Clear
There is no offset, (no extra byte after the opcode),
PUSH/POP Push/Pop to/from the stack
and allows 00 - FF addressing space.
INC/DEC Increment/Decrement
Indexed (Short)
TNZ Test Negative or Zero
The offset is a byte, thus requires only one byte af-
CPL, NEG 1 or 2 Complement ter the opcode and allows 00 - 1FE addressing
MUL Byte Multiplication space.
SLL, SRL, SRA, RLC, Indexed (long)
Shift and Rotate Operations
RRC The offset is a word, thus allowing 64 Kbyte ad-
SWAP Swap Nibbles dressing space and requires 2 bytes after the op-
code.
15.1.2 Immediate
Immediate instructions have two bytes, the first 15.1.5 Indirect (Short, Long)
byte contains the opcode, the second byte con- The required data byte to do the operation is found
tains the operand value.
by its memory address, located in memory (point-
Immediate Instruction Function er).
LD Load The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP Compare
Indirect (short)
BCP Bit Compare
The pointer address is a byte, the pointer size is a
AND, OR, XOR Logical Operations
byte, thus allowing 00 - FF addressing space, and
ADC, ADD, SUB, SBC Arithmetic Operations requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

101/151
ST72334J/N, ST72314J/N, ST72124J

ST7 ADDRESSING MODES (Cont’d)

15.1.6 Indirect Indexed (Short, Long) SWAP Swap Nibbles
This is a combination of indirect and short indexed CALL, JP Call or Jump subroutine
addressing modes. The operand is referenced by
its memory address, which is defined by the un- 15.1.7 Relative Mode (Direct, Indirect)
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point- This addressing mode is used to modify the PC
er address follows the opcode. register value by adding an 8-bit signed offset to it.
The indirect indexed addressing mode consists of Available Relative Direct/
Function
two sub-modes: Indirect Instructions
Indirect Indexed (Short) JRxx Conditional Jump
The pointer address is a byte, the pointer size is a CALLR Call Relative
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode. The relative addressing mode consists of two sub-
Indirect Indexed (Long) modes:
The pointer address is a byte, the pointer size is a Relative (Direct)
word, thus allowing 64 Kbyte addressing space, The offset follows the opcode.
and requires 1 byte after the opcode. Relative (Indirect)
Table 21. Instructions Supporting Direct, The offset is defined in memory, of which the ad-
Indexed, Indirect and Indirect Indexed dress follows the opcode.
Addressing Modes
Long and Short
Function
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Addition/subtrac-
ADC, ADD, SUB, SBC
tion operations
BCP Bit Compare

Short Instructions Only Function

CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC,
Shift and Rotate Operations
RRC

102/151
ST72334J/N, ST72314J/N, ST72124J

15.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in
consisting of 63 instructions. The instructions may the following table:
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF

Using a pre-byte
The instructions are described with one to four These prebytes enable instruction in Y as well as
bytes. indirect addressing modes to be implemented.
In order to extend the number of available op- They precede the opcode of the instruction in X or
codes for an 8-bit CPU (256 opcodes), three differ- the instruction using direct addressing mode. The
ent prebyte opcodes are defined. These prebytes prebytes are:
modify the meaning of the instruction they pre- PDY 90 Replace an X based instruction using
cede. immediate, direct, indexed, or inherent
The whole instruction becomes: addressing mode by a Y one.
PC-2 End of previous instruction PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
PC-1 Prebyte mode to an instruction using the corre-
PC Opcode sponding indirect addressing mode.
It also changes an instruction using X
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the indexed addressing mode to an instruc-
tion using indirect X indexed addressing
effective address
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.

103/151
ST72334J/N, ST72314J/N, ST72124J

INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with Carry A=A+M+C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL Jump if ext. interrupt = 0
JRH Jump if H = 1 H=1?
JRNH Jump if H = 0 H=0?
JRM Jump if I = 1 I=1?
JRNM Jump if I = 0 I=0?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >

104/151
ST72334J/N, ST72314J/N, ST72124J

INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z

MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0

NEG Negate (2’s compl) neg $10 reg, M N Z C

NOP No Operation

OR OR operation A=A+M A M N Z

POP Pop from the Stack pop reg reg M

pop CC CC M H I N Z C

PUSH Push onto the Stack push Y M reg, CC

RCF Reset carry flag C=0 0

RET Subroutine Return

RIM Enable Interrupts I=0 0

RLC Rotate left true C C <= Dst <= C reg, M N Z C

RRC Rotate right true C C => Dst => C reg, M N Z C

RSP Reset Stack Pointer S = Max allowed

SBC Subtract with Carry A=A-M-C A M N Z C

SCF Set carry flag C=1 1

SIM Disable Interrupts I=1 1

SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C

SLL Shift left Logic C <= Dst <= 0 reg, M N Z C

SRL Shift right Logic 0 => Dst => C reg, M 0 Z C

SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C

SUB Subtraction A=A-M A M N Z C

SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z

TNZ Test for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1

WFI Wait for Interrupt 0

XOR Exclusive OR A = A XOR M A M N Z

105/151
ST72334J/N, ST72314J/N, ST72124J

16 ELECTRICAL CHARACTERISTICS

16.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re- 16.1.5 Pin input voltage
ferred to V SS. The input voltage measurement on a pin of the de-
16.1.1 Minimum and Maximum values vice is described in Figure 54.
Unless otherwise specified the minimum and max-
Figure 54. Pin input voltage
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C ST7 PIN
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design VIN
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
16.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V
voltage range) and V DD=3.3V (for the 3V≤VDD≤4V
voltage range). They are given only as design
guidelines and are not tested.
16.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
16.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 53.
Figure 53. Pin loading conditions

ST7 PIN

CL

106/151
ST72334J/N, ST72314J/N, ST72124J

16.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating
mum ratings” may cause permanent damage to conditions for extended periods may affect device
the device. This is a stress rating only and func- reliability.
tional operation of the device under these condi-
16.2.1 Voltage Characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 6.5
VDDA - VSSA Analog Reference Voltage 6.5
V
Input voltage on true open drain pin VSS-0.3 to 6.5
VIN 1) & 2)
Input voltage on any other pin VSS-0.3 to VDD+0.3
|∆VDDx| and |∆VSSx| Variations between different digital power pins 50
VDDX- VDDA mV
Variations between digital and analog power pins 50
|VSSA - VSSx|
VESD(HBM) Electro-static discharge voltage (Human Body Model) see Section 16.7.2 "Absolute Electri-
VESD(MM) Electro-static discharge voltage (Machine Model) cal Sensitivity" on page 123

16.2.2 Current Characteristics

Symbol Ratings Maximum value Unit
3)
IVDD Total current into VDD power lines (source) 150
3)
IVSS Total current out of VSS ground lines (sink) 150
Output current sunk by any standard I/O and control pin 25
IIO Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
mA
Injected current on ISPSEL pin ±5
Injected current on RESET pin ±5
IINJ(PIN) 2) & 4)
Injected current on OSC1 and OSC2 pins ±5
5) & 6)
Injected current on any other pin ±5
ΣIINJ(PIN) 2)
Total injected current (sum of all I/O and control pins) 5)
± 20

Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.

107/151
ST72334J/N, ST72314J/N, ST72124J

ABSOLUTE MAXIMUM RATINGS (Cont’d)

16.2.3 Thermal Characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
Maximum junction temperature (see Section 18 "DEVICE CONFIGURATION AND ORDER-
TJ
ING INFORMATION" on page 143 )

108/151
ST72334J/N, ST72314J/N, ST72124J

16.3 OPERATING CONDITIONS

16.3.1 General Operating Conditions
Symbol Parameter Conditions Min Max Unit
VDD Supply voltage see Figure 55 and Figure 56 3.2 5.5 V
VDD≥3.5V for ROM devices
0 1) 16
fOSC External clock frequency VDD≥4.5V for FLASH devices MHz
VDD≥3.2V 0 1) 8
1 Suffix Version 0 70
6 Suffix Version -40 85
TA Ambient temperature range °C
7 Suffix Version -40 105
3 Suffix Version -40 125

Figure 55. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for ROM devices 2)

FUNCTIONALITY
NOT GUARANTEED
fOSC [MHz] FUNCTIONALITY
IN THIS AREA AT TA > 85°C
GUARANTEED
IN THIS AREA

16
FUNCTIONALITY
NOT GUARANTEED 12
IN THIS AREA FUNCTIONALITY
NOT GUARANTEED
8 IN THIS AREA
WITH RESONATOR 1)

4
1
0 SUPPLY VOLTAGE [V]
2.5 3.2 3.5 3.85 4 4.5 5 5.5

Figure 56. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for FLASH devices 2)
FUNCTIONALITY
NOT GUARANTEED
fOSC [MHz] IN THIS AREA AT TA > 85°C FUNCTIONALITY
GUARANTEED
IN THIS AREA 3)

16
FUNCTIONALITY
NOT GUARANTEED 12
IN THIS AREA FUNCTIONALITY
NOT GUARANTEED
8 IN THIS AREA
WITH RESONATOR 1)

1
0 SUPPLY VOLTAGE [V]
2.5 3.2 3.5 3.85 4 4.5 5 5.5

Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with TA=-40 to +125°C.
3. FLASH programming tested in production at maximum TA with two different conditions: VDD=5.5V, fCPU=6MHz and
VDD=3.2V, fCPU=4MHz.

109/151
ST72334J/N, ST72314J/N, ST72124J

OPERATING CONDITIONS (Cont’d)

16.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V DD, fOSC, and TA.
Symbol Parameter Conditions Min Typ 1) Max Unit
High Threshold 4.10 2) 4.30 4.50
VIT+ Reset release threshold (VDD rise) Med. Threshold 3.75 2) 3.90 4.05
Low Threshold 3.25 2) 3.35 3.55
V
High Threshold 3.852) 4.05 4.30
VIT- Reset generation threshold (VDD fall) Med. Threshold 3.502) 3.65 3.95
Low Threshold4) 3.00 3.10 3.35
Vhys LVD voltage threshold hysteresis VIT+-VIT- 200 250 300 mV
VtPOR VDD rise time rate 3) 0.2 50 V/ms
tg(VDD) Filtered glitch delay on VDD 2) Not detected by the LVD 40 ns

Figure 57. High LVD Threshold Versus VDD and fOSC for FLASH devices 3)
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
fOSC [MHz] FOR TEMPERATURES HIGHER THAN 85°C FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
DEVICE UNDER 16
RESET 12
IN THIS AREA 8 FUNCTIONAL AREA

0 SUPPLY VOLTAGE [V]

VIT-≥3.85
2.5 3 3.5 4 4.5 5 5.5

Figure 58. Medium LVD Threshold Versus VDD and fOSC for FLASH devices 3)
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
fOSC [MHz] FOR TEMPERATURES HIGHER THAN 85°C FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
DEVICE UNDER 16
RESET 12
IN THIS AREA 8 FUNCTIONAL AREA

0 SUPPLY VOLTAGE [V]

2.5 3 VIT-≥3.5V 4 4.5 5 5.5

Figure 59. Low LVD Threshold Versus VDD and f OSC for FLASH devices 2)4)
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
fOSC [MHz] FOR TEMPERATURES HIGHER THAN 85°C FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
16
12
DEVICE UNDER 8 FUNCTIONAL AREA
RESET
SEE NOTE 4
IN THIS AREA
0 SUPPLY VOLTAGE [V]
2.5 VIT-≥3V 3.2 3.5 4 4.5 5 5.5
Notes:
1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. Data based on characterization results, not tested in production.
3. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
4.If the low LVD threshold is selected, when VDD falls below 3.2V, (VDD minimum operating voltage), the device is guar-
anteed to continue functioning until it goes into reset state. The specified VDD min. value is necessary in the device power
on phase, but during a power down phase or voltage drop the device will function below this min. level.

110/151
ST72334J/N, ST72314J/N, ST72124J

FUNCTIONAL OPERATING CONDITIONS (Cont’d)

Figure 60. High LVD Threshold Versus VDD and fOSC for ROM devices 2)

fOSC [MHz] FUNCTIONALITY

NOT GUARANTEED
IN THIS AREA
DEVICE UNDER 16
RESET
IN THIS AREA 8 FUNCTIONAL AREA

0 SUPPLY VOLTAGE [V]

VIT-≥3.85
2.5 3 3.5 4 4.5 5 5.5

Figure 61. Medium LVD Threshold Versus VDD and fOSC for ROM devices 2)

fOSC [MHz] FUNCTIONALITY

NOT GUARANTEED
IN THIS AREA
DEVICE UNDER 16
RESET
IN THIS AREA 8 FUNCTIONAL AREA

0 SUPPLY VOLTAGE [V]

2.5 3 VIT-≥3.5V 4 4.5 5 5.5

Figure 62. Low LVD Threshold Versus VDD and f OSC for ROM devices 2)3)

fOSC [MHz] FUNCTIONALITY

NOT GUARANTEED
IN THIS AREA
16

DEVICE UNDER 8 FUNCTIONAL AREA

RESET
IN THIS AREA
0 SUPPLY VOLTAGE [V]
2.5 VIT-≥3.00V 3.5 4 4.5 5 5.5

Notes:
1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
3. If the low LVD threshold is selected, when VDD falls below 3.2V, (VDD minimum operating voltage), the device is guar-
anteed to continue functioning until it goes into reset state. The specified VDD min. value is necessary in the device power
on phase, but during a power down phase or voltage drop the device will function below this min. level.

111/151
ST72334J/N, ST72314J/N, ST72124J

16.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for vice consumption, the two current values must be
the ST7 functional operating modes over tempera- added (except for HALT mode for which the clock
ture range does not take into account the clock is stopped).
source current consumption. To get the total de-
Symbol Parameter Conditions Max Unit
∆IDD(∆Ta) Supply current variation vs. temperature Constant VDD and fCPU 10 %

16.4.1 RUN and SLOW Modes

Symbol Parameter Conditions Typ 1) Max 2) Unit
fOSC=2MHz, fCPU=1MHz 1.2 1.8
Supply current in RUN mode 3)

4.5V≤VDD≤5.5V
fOSC=4MHz, fCPU=2MHz 2.1 3.5
(see Figure 63) fOSC=8MHz, fCPU=4MHz 3.9 7.0
fOSC=16MHz, fCPU=8MHz 7.4 14.0
fOSC=2MHz, fCPU=62.5kHz 0.4 0.9
Supply current in SLOW mode 4) fOSC=4MHz, fCPU=125kHz 0.5 1.1
(see Figure 64) fOSC=8MHz, fCPU=250kHz 0.7 1.4
fOSC=16MHz, fCPU=500kHz 1.0 2.0
IDD mA
fOSC=2MHz, fCPU=1MHz 0.3 1
3)
3.2V≤VDD≤3.6V

Supply current in RUN mode fOSC=4MHz, fCPU=2MHz 0.8 1.5

(see Figure 63) fOSC=8MHz, fCPU=4MHz 1.6 3
fOSC=16MHz, fCPU=8MHz 3.5 7
fOSC=2MHz, fCPU=62.5kHz 0.1 0.3
Supply current in SLOW mode 4) fOSC=4MHz, fCPU=125kHz 0.2 0.5
(see Figure 64) fOSC=8MHz, fCPU=250kHz 0.3 0.6
fOSC=16MHz, fCPU=500kHz 0.5 1.0

Figure 63. Typical IDD in RUN vs. fCPU Figure 64. Typical IDD in SLOW vs. fCPU

IDD [mA] IDD [mA]

1.2 500kHz 125kHz
8
250kHz 62.5kHz
8MHz 2MHz
7
4MHz 1MHz 1

6
0.8
5

4 0.6

3
0.4

2
0.2
1

0 0
3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5
VDD [V] VDD [V]

Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) and VDD=3.4V (3.2V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

112/151
ST72334J/N, ST72314J/N, ST72124J

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

16.4.2 WAIT and SLOW WAIT Modes
Symbol Parameter Conditions Typ 1) Max 2) Unit
fOSC=2MHz, fCPU=1MHz 0.35 0.6
Supply current in WAIT mode 3)

4.5V≤VDD≤5.5V
fOSC=4MHz, fCPU=2MHz 0.7 1.2
(see Figure 65) fOSC=8MHz, fCPU=4MHz 1.3 2.1
fOSC=16MHz, fCPU=8MHz 2.5 4.0
mA
fOSC=2MHz, fCPU=62.5kHz 0.05 0.1
Supply current in SLOW WAIT mode 4)
fOSC=4MHz, fCPU=125kHz 0.1 0.2
(see Figure 66) fOSC=8MHz, fCPU=250kHz 0.2 0.4
fOSC=16MHz, fCPU=500kHz 0.5 1.0
IDD
fOSC=2MHz, fCPU=1MHz 45 100
Supply current in WAIT mode 3)

3.2V≤VDD≤3.6V
fOSC=4MHz, fCPU=2MHz 150 300
(see Figure 65) fOSC=8MHz, fCPU=4MHz 300 600
fOSC=16MHz, fCPU=8MHz 500 1000
µA
fOSC=2MHz, fCPU=62.5kHz 6 20
4)
Supply current in SLOW WAIT mode fOSC=4MHz, fCPU=125kHz 40 100
(see Figure 66) fOSC=8MHz, fCPU=250kHz 80 160
fOSC=16MHz, fCPU=500kHz 120 250

Figure 65. Typical IDD in WAIT vs. f CPU Figure 66. Typical IDD in SLOW-WAIT vs. fCPU

IDD [mA] IDD [mA]

3 8MHz 2MHz 0.35 500kHz 125kHz
4MHz 1MHz 250kHz 62.5kHz
0.3
2.5

0.25
2

0.2
1.5
0.15

1
0.1

0.5
0.05

0 0
3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5
VDD [V] VDD [V]

Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) and VDD=3.4V (3.2V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1)
driven by external square wave, CSS and LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD
disabled.

113/151
ST72334J/N, ST72314J/N, ST72124J

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

16.4.3 HALT and ACTIVE-HALT Modes
Symbol Parameter Conditions Typ 1) Max Unit
-40°C≤TA≤+85°C 10
VDD=5.5V
-40°C≤TA≤+125°C 150
Supply current in HALT mode 2) <2
IDD -40°C≤TA≤+85°C 6 µA
VDD=3.6V
-40°C≤TA≤+125°C 100
Supply current in ACTIVE-HALT mode 3) 50 150

16.4.4 Supply and Clock Managers

The previous current consumption specified for source current consumption. To get the total de-
the ST7 functional operating modes over tempera- vice consumption, the two current values must be
ture range does not take into account the clock added (except for HALT mode).
Symbol Parameter Conditions Typ 1) Max 4) Unit
Supply current of internal RC oscillator 500 750
Supply current of external RC oscillator 5) 525 750
LP: Low power oscillator 200 400
IDD(CK) MP: Medium power oscillator 300 550
Supply current of resonator oscillator 5) & 6) µA
MS: Medium speed oscillator 450 750
HS: High speed oscillator 700 1000
Clock security system supply current 150 350
IDD(LVD) LVD supply current HALT mode 100 150

16.4.5 On-Chip Peripherals

Symbol Parameter Conditions Typ Unit
VDD=3.4V 50
IDD(TIM) 16-bit Timer supply current 7) fCPU=8MHz
VDD=5.0V 150
VDD=3.4V 250
IDD(SPI) SPI supply current 8) fCPU=8MHz µA
VDD=5.0V 350
VDD=3.4V 800
IDD(ADC) ADC supply current when converting 9) fADC=4MHz
VDD=5.0V 1100

Notes:
1. Typical data are based on TA=25°C.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), CSS and LVD disabled. Data based on charac-
terization results, tested in production at VDD max. and fCPU max.
3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode
with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled.
4. Data based on characterization results, not tested in production.
5. Data based on characterization results done with the external components specified in Section 16.5.3 and Section
16.5.4, not tested in production.
6. As the oscillator is based on a current source, the consumption does not depend on the voltage.
7. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (selecting external clock capability). Data valid for one timer.
8. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica-
tion (data sent equal to 55h).
9. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.

114/151
ST72334J/N, ST72314J/N, ST72124J

16.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V DD, fOSC, and TA.
16.5.1 General Timings
Symbol Parameter Conditions Min Typ 1) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time
fCPU=8MHz 250 375 1500 ns
Interrupt reaction time 2) 10 22 tCPU
tv(IT)
tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 1.25 2.75 µs

16.5.2 External Clock Source

Symbol Parameter Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage 0.7xVDD VDD
V
VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD
tw(OSC1H)
OSC1 high or low time 3) see Figure 67 15
tw(OSC1L)
ns
tr(OSC1)
OSC1 rise or fall time 3) 15
tf(OSC1)
IL OSCx Input leakage current VSS≤VIN≤VDD ±1 µA

Figure 67. Typical Application with an External Clock Source

90%
VOSC1H
10%

VOSC1L

tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)

OSC2
Not connected internally

fOSC
EXTERNAL
IL
CLOCK SOURCE
OSC1
ST72XXX

Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.

115/151
ST72334J/N, ST72314J/N, ST72124J

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

16.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four close as possible to the oscillator pins in order to
different Crystal/Ceramic resonator oscillators. All minimize output distortion and start-up stabiliza-
the information given in this paragraph are based tion time. Refer to the crystal/ceramic resonator
on characterization results with specified typical manufacturer for more details (frequency, pack-
external components. In the application, the reso- age, accuracy...).
nator and the load capacitors have to be placed as
Symbol Parameter Conditions Min Max Unit
LP: Low power oscillator 1 2
MP: Medium power oscillator >2 4
fOSC Oscillator Frequency 3) MHz
MS: Medium speed oscillator >4 8
HS: High speed oscillator >8 16
RF Feedback resistor 20 40 kΩ
RS=200Ω LP oscillator 38 56
CL1 Recommended load capacitance ver-
RS=200Ω MP oscillator 32 46
sus equivalent serial resistance of the pF
CL2 RS=200Ω MS oscillator 18 26
crystal or ceramic resonator (RS)
RS=100Ω HS oscillator 15 21
VDD=5V LP oscillator 40 100
VIN=VSS MP oscillator 110 190
i2 OSC2 driving current µA
MS oscillator 180 360
HS oscillator 400 700

16.5.3.1 Typical Crystal Resonators

Option CL1 CL2 tSU(osc)
Byte Reference Freq. Characteristic 1)
Config. [pF] [pF] [ms] 2)

LP S-200-30-30/50 2MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=200Ω 33 34 10~15

JAUCH

MP SS3-400-30-30/30 4MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=60Ω 33 34 7~10

MS SS3-800-30-30/30 8MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=25Ω 33 34 2.5~3
HS SS3-1600-30-30/30 16MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=15Ω 33 34 1~1.5

Figure 68. Application with a Crystal Resonator

i2

fOSC
CL1 OSC1

RESONATOR RF
CL2
OSC2
ST72XXX

Notes:
1. Resonator characteristics given by the crystal manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal manufacturer for more details.

116/151
ST72334J/N, ST72314J/N, ST72124J

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

16.5.3.2 Typical Ceramic Resonators
Symbol Parameter Conditions Typ Unit
LP 2MHz 4.2
MP 4MHz 2.1
tSU(osc) Ceramic resonator start-up time ms
MS 8MHz 1.1
HS 16MHz 0.7

Note:
tSU(OSC) is the typical oscillator start-up time measured between V DD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).

Figure 69. Application with Ceramic Resonator

WHEN RESONATOR WITH
INTEGRATED CAPACITORS i2

fOSC
CL1 OSC1

RESONATOR

RF(EXT) RF
CL2
OSC2
ST72XXX
RD
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to Table 22 and Table 23 and to the ceramic resonator manufacturer’s documentation for more details.

117/151
ST72334J/N, ST72314J/N, ST72124J

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

Table 22. Typical Ceramic Resonators
Option Byte fOSC CL1 CL2 RFEXT RD
Resonator Part Number1)
Config. (MHz) [pF]3 [pF]3 kΩ [kΩ]
CSB1000JA
1 100 100 3.3
CSBF1000JA
LP
CSTS0200MGA06
2
CSTCC2.00MGA0H6
CSTS0200MGA06
2
CSTCC2.00MGA0H6
MP
CSTS0400MGA06
4
CSTCC4.00MGA0H6
(47) (47)
CSTS0400MGA06
4
CSTCC4.00MGA0H6
MS Open
CSTS0800MGA06
8
CSTCC8.00MGA0H6
0
CSTS0800MGA06
8
CSTCC8.00MGA0H6
CST10.0MTWA 30 30
10
CSTCC10.0MGA (15) (15)
CST12.0MTWA 30 30
HS 12
CSTCS12.0MTA (30) (30)
CSA16.00MXZA040 15 15
CST16.00MXWA0C3 (15) (15)
162)
CSACV16.00MXA040Q 15 15
10
CSTCV16.00MXA0H3Q (15) (15)

Table 23. Resonator Frequency Correlation Factor

Option Corre- Option Corre-
Refer- Refer-
Byte Resonator1) lation Byte Resonator1) lation
ence IC ence IC
Config. % Config. %
CSB1000JA +0.03 4069UBE CSTS0400MGA06 -0.03
LP CSTS0200MGA06 -0.20 CSTCC4.00MGA0H6 -0.05
MS
CSTCC2.00MGA0H6 -0.16 CSTS0800MGA06 +0.03
74HCU04
CSTS0200MGA06 -0.21 CSTCC4.00MGA0H6 +0.02
74HCU04
CSTCC2.00MGA0H6 -0.19 CSTS0800MGA06 +0.02
MP
CSTS0400MGA06 0.02 CSTCC8.00MGA0H6 +0.01
CSTCC4.00MGA0H6 -0.05 CSTS10.0MTWA +0.38
CSTCC10.0MGA +0.61
HS 4069UBE
CST12.0MTWA +0.38
CSTCS12.0MTA +0.42
CSA16.00MXZA040 +0.10
74HCU04
CSACV16.00MXA040Q +0.08

Notes:
1. Murata Ceralock
2. VDD 4.5 to 5.5V
3. Values in parentheses refer to the capacitors integrated in the resonator

118/151
ST72334J/N, ST72314J/N, ST72124J

CLOCK CHARACTERISTICS (Cont’d)

16.5.4 RC Oscillators
The ST7 internal clock can be supplied with an RC or external components (selectable by option
oscillator. This oscillator can be used with internal byte).
Symbol Parameter Conditions Min Typ Max Unit
1)
Internal RC oscillator frequency see Figure 71 3.60 5.10
fOSC MHz
External RC oscillator frequency 2) 1 14
Internal RC Oscillator Start-up Time 3) 2.0
REX=47KΩ, CEX=”0”pF 1.0
tSU(OSC) 3) REX=47KΩ, CEX=100pF 6.5 ms
External RC Oscillator Start-up Time
REX=10KΩ, CEX=6.8pF 0.7
REX=10KΩ, CEX=470pF 3.0
REX Oscillator external resistor 4) 10 47 KΩ
see Figure 72
CEX Oscillator external capacitor 0 5) 470 pF

Figure 70. Typical Application with RC oscillator

ST72XXX
INTERNAL RC VDD

Current copy

EXTERNAL RC
VREF + fOSC
REX OSC1 -

CEX OSC2
Voltage generator
CEX discharge

Figure 71. Typical Internal RC Oscillator Figure 72. Typical External RC Oscillator
fosc [MHz]
fosc [MHz] Rex=10KOhm
-40°C +85°C 20
4.3 Rex=15KOhm
+25°C +125°C
Rex=22KOhm
4.2 15
Rex=33KOhm
4.1 Rex=39KOhm
10
Rex=47KOhm
4

3.9 5

3.8
3.2 5.5 0
0 6.8 22 47 100 270 470
VDD [V]
Cex [pF]
Notes:
1. Data based on characterization results.
2. Guaranteed frequency range with the specified CEX and REX ranges taking into account the device process variation.
Data based on design simulation.
3. Data based on characterization results done with VDD nominal at 5V, not tested in production.
4. REX must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
5. Important: when no external CEX is applied, the capacitance to be considered is the global parasitic capacitance which
is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by
trying out several resistor values.

119/151
ST72334J/N, ST72314J/N, ST72124J

CLOCK CHARACTERISTICS (Cont’d)

16.5.5 Clock Security System (CSS)
Symbol Parameter Conditions Min Typ Max Unit
TA=25°C, VDD=5.0V 250 340 550
fSFOSC Safe Oscillator Frequency 1) kHz
TA=25°C, VDD=3.4V 190 260 450
fGFOSC Glitch Filtered Frequency 2) 30 MHz

Figure 73. Typical Safe Oscillator Frequencies

fosc [kHz] -40°C +85°C

400 +25°C +125°C

350

300

250

200
3.2 5.5
VDD [V]

Note:
1. Data based on characterization results, tested in production between 90KHz and 600KHz.
2. Filtered glitch on the fOSC signal. See functional description in Section 9.4 on page 30 for more details.

120/151
ST72334J/N, ST72314J/N, ST72124J

16.6 MEMORY CHARACTERISTICS

16.6.1 RAM and Hardware Registers
Symbol Parameter Conditions Min Typ Max Unit
1)
VRM Data retention mode HALT mode (or RESET) 1.6 V

16.6.2 EEPROM Data Memory

Symbol Parameter Conditions Min Typ Max Unit
-40°C≤TA≤+85°C 20
tprog Programming time for 1~16 bytes 3) ms
-40°C≤TA≤+125°C 25
tret Data retention 5) TA=+55°C 4) 20 Years
NRW Write erase cycles 5)
TA=+25°C 300 000 Cycles

16.6.3 FLASH Program Memory

Symbol Parameter Conditions Min Typ Max Unit
2) 0 25 70
TA(prog) Programming temperature range °C
Programming time for 1~16 bytes 3) TA=+25°C 8 25 ms
tprog
Programming time for 4 or 8kBytes TA=+25°C 2.1 6.4 sec
tret Data retention 5) TA=+55°C 4) 20 years
NRW Write erase cycles 5) TA=+25°C 100 cycles

Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Data based on characterization results, tested in production at TA=25°C.
3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device)
4. The data retention time increases when the TA decreases.
5. Data based on reliability test results and monitored in production.

121/151
ST72334J/N, ST72314J/N, ST72124J

16.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba- ■ ESD: Electro-Static Discharge (positive and
sis during product characterization. negative) is applied on all pins of the device until
16.7.1 Functional EMS a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the and negative) is applied to V DD and VSS through
product (toggling 2 LEDs through I/O ports), the a 100pF capacitor, until a functional disturbance
product is stressed by two electro magnetic events occurs. This test conforms with the IEC 1000-4-
until a failure occurs (indicated by the LEDs). 4 standard.
A device reset allows normal operations to be re-
sumed.
Symbol Parameter Conditions Neg 1) Pos 1) Unit
Voltage limits to be applied on any I/O pin VDD=5V, TA=+25°C, fOSC=8MHz
VFESD -1 1
to induce a functional disturbance conforms to IEC 1000-4-2
Fast transient voltage burst limits to be ap- kV
VDD=5V, TA=+25°C, fOSC=8MHz
VFFTB plied through 100pF on VDD and VDD pins -4 4
conforms to IEC 1000-4-4
to induce a functional disturbance

Figure 74. EMC Recommended star network power supply connection 2)

ST72XXX
10µF 0.1µF VDD

ST7
DIGITAL NOISE
FILTERING
VSS

VDD
POWER VSSA
SUPPLY
SOURCE
EXTERNAL
NOISE
FILTERING VDDA

0.1µF

Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance trade-off. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

122/151
ST72334J/N, ST72314J/N, ST72124J

EMC CHARACTERISTICS (Cont’d)

16.7.2 Absolute Electrical Sensitivity Machine Model Test Sequence
Based on three different tests (ESD, LU and DLU) – CL is loaded through S1 by the HV pulse gener-
using specific measurement methods, the product ator.
is stressed in order to determine its performance in – S1 switches position from generator to ST7.
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note. – A discharge from CL to the ST7 occurs.
16.7.2.1 Electro-Static Discharge (ESD) – S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
Electro-Static Discharges (3 positive then 3 nega- charge state. S2 must be opened at least 10ms
tive pulses separated by 1 second) are applied to prior to the delivery of the next pulse.
the pins of each sample according to each pin
combination. The sample size depends of the – R (machine resistance), in series with S2, en-
number of supply pins of the device (3 parts*(n+1) sures a slow discharge of the ST7.
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 75 and the following test sequences.
Human Body Model Test Sequence
– C L is loaded through S1 by the HV pulse gener-
ator.
– S1 switches position from generator to R.
– A discharge from CL through R (body resistance)
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
Symbol Ratings Conditions Maximum value 1) Unit
Electro-static discharge voltage
VESD(HBM) TA=+25°C 3000
(Human Body Model)
V
Electro-static discharge voltage
VESD(MM) TA=+25°C 400
(Machine Model)

Figure 75. Typical Equivalent ESD Circuits

S1 R=1500Ω S1
R=10k~10MΩ

HIGH VOLTAGE HIGH VOLTAGE

PULSE CL=100pF
ST7 S2 PULSE ST7
GENERATOR GENERATOR

CL=200pF S2

HUMAN BODY MODEL MACHINE MODEL

Notes:
1. Data based on characterization results, not tested in production.

123/151
ST72334J/N, ST72314J/N, ST72124J

EMC CHARACTERISTICS (Cont’d)

16.7.2.2 Static and Dynamic Latch-Up should be noted that good EMC performance is
■ LU: 3 complementary static tests are required highly dependent on the user application and the
on 10 parts to assess the latch-up performance. software in particular.
A supply overvoltage (applied to each power Therefore it is recommended that the user applies
supply pin), a current injection (applied to each EMC software optimization and prequalification
input, output and configurable I/O pin) and a tests in relation with the EMC level requested for
power supply switch sequence are performed his application.
on each sample. This test conforms to the EIA/
Software recommendations:
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note. The software flowchart must include the manage-
■ DLU: Electro-Static Discharges (one positive
ment of runaway conditions such as:
then one negative test) are applied to each pin – Corrupted program counter
of 3 samples when the micro is running to – Unexpected reset
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical – Critical Data corruption (control registers...)
values, the oscillator is connected as near as Prequalification trials:
possible to the pins of the micro and the Most of the common failures (unexpected reset
component is put in reset mode. This test and program counter corruption) can be repro-
conforms to the IEC1000-4-2 and SAEJ1752/3 duced by manually forcing a low state on the RE-
standards and is described in Figure 76. For SET pin or the Oscillator pins for 1 second.
more details, refer to the AN1181 ST7
application note. To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
16.7.2.3 Designing hardened software to avoid specification values. When unexpected behaviour
noise problems is detected, the software can be hardened to pre-
EMC characterization and optimization are per- vent unrecoverable errors occurring (see applica-
formed at component level with a typical applica- tion note AN1015).
tion environment and simplified MCU software. It
Electrical Sensitivities
Symbol Parameter Conditions Class 1)
TA=+25°C A
LU Static latch-up class
TA=+85°C A
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A

Figure 76. Simplified Diagram of the ESD Generator for DLU

RCH=50MΩ RD=330Ω DISCHARGE TIP VDD

VSS
CS=150pF HV RELAY
ST7
ESD
GENERATOR 2) DISCHARGE
RETURN CONNECTION

Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.

124/151
ST72334J/N, ST72314J/N, ST72124J

EMC CHARACTERISTICS (Cont’d)

16.7.3 ESD Pin Protection Strategy Standard Pin Protection
To protect an integrated circuit against Electro- To protect the output structure the following ele-
Static Discharge the stress must be controlled to ments are added:
prevent degradation or destruction of the circuit el- – A diode to VDD (3a) and a diode from VSS (3b)
ements. The stress generally affects the circuit el- – A protection device between VDD and V SS (4)
ements which are connected to the pads but can
also affect the internal devices when the supply To protect the input structure the following ele-
pads receive the stress. The elements to be pro- ments are added:
tected must not receive excessive current, voltage – A resistor in series with the pad (1)
or heating within their structure. – A diode to VDD (2a) and a diode from VSS (2b)
An ESD network combines the different input and – A protection device between VDD and V SS (4)
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 77 and Figure 78 for standard
pins and in Figure 79 and Figure 80 for true open
drain pins.
Figure 77. Positive Stress on a Standard Pad vs. VSS
VDD VDD

(3a) (2a)

(1)
OUT (4) IN

Main path
(3b) (2b)
Path to avoid

VSS VSS

Figure 78. Negative Stress on a Standard Pad vs. VDD

VDD VDD

(3a) (2a)

(1)
OUT (4) IN

Main path
(3b) (2b)

VSS VSS

125/151
ST72334J/N, ST72314J/N, ST72124J

EMC CHARACTERISTICS (Cont’d)

True Open Drain Pin Protection Multisupply Configuration
The centralized protection (4) is not involved in the When several types of ground (VSS, V SSA, ...) and
discharge of the ESD stresses applied to true power supply (VDD, VDDA, ...) are available for any
open drain pads due to the fact that a P-Buffer and reason (better noise immunity...), the structure
diode to V DD are not implemented. An additional shown in Figure 81 is implemented to protect the
local protection between the pad and V SS (5a & device against ESD.
5b) is implemented to completely absorb the posi-
tive ESD discharge.
Figure 79. Positive Stress on a True Open Drain Pad vs. VSS
VDD VDD

Main path
(1)
Path to avoid OUT (4) IN

(5a) (3b) (2b) (5b)

VSS VSS

Figure 80. Negative Stress on a True Open Drain Pad vs. VDD
VDD VDD

Main path
(1)
OUT (4) IN

(3b) (3b) (2b) (3b)

VSS VSS

Figure 81. Multisupply Configuration

VDD VDDA

VDDA

VSS
BACK TO BACK DIODE
BETWEEN GROUNDS
VSSA VSSA

126/151
ST72334J/N, ST72314J/N, ST72124J

16.8 I/O PORT PIN CHARACTERISTICS

16.8.1 General Characteristics
Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ 1) Max Unit
2)
VIL Input low level voltage 0.3xVDD
V
VIH Input high level voltage 2) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 3) 400 mV
IL Input leakage current VSS≤VIN≤VDD ±1
µA
IS Static current consumption 4) Floating input mode 200
VDD=5V 62 120 250
RPU Weak pull-up equivalent resistor 5) VIN=VSS kΩ
VDD=3.3V 170 200 300
CIO I/O pin capacitance 5 pF
tf(IO)out Output high to low level fall time 6) CL=50pF 25
ns
tr(IO)out Output low to high level rise time 6) Between 10% and 90% 25
tw(IT)in External interrupt pulse time 7) 1 tCPU

Figure 82. Two typical Applications with unused I/O Pin

VDD ST72XXX
UNUSED I/O PORT
10kΩ 10kΩ
UNUSED I/O PORT
ST72XXX

Figure 83. Typical IPU vs. VDD with V IN=VSS

Ipu [µA]
70
Ta=-40°C Ta=85°C
60
Ta=25°C Ta=125°C
50
40
30
20

10
0
3.2 3.5 4 4.5 5 5.5
Vdd [V]

Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 82). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 83). This data is based on characterization results, tested in production at VDD max.
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

127/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORT PIN CHARACTERISTICS (Cont’d)

16.8.2 Output Driving Current
Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
IIO=+5mA TA≤85°C 1.3
Output low level voltage for a standard I/O pin TA≥85°C 1.5
when 8 pins are sunk at same time
(see Figure 84 and Figure 87) IIO=+2mA TA≤85°C 0.65
TA≥85°C 0.75
VOL 1)
IIO=+20mA,TA≤85°C 1.5

VDD=5V
Output low level voltage for a high sink I/O pin TA≥85°C 1.7
when 4 pins are sunk at same time V
(see Figure 85 and Figure 88) IIO=+8mA TA≤85°C 0.75
TA≥85°C 0.85
IIO=-5mA, TA≤85°C VDD-1.6
Output high level voltage for an I/O pin TA≥85°C VDD-1.7
2)
VOH when 4 pins are sourced at same time
(see Figure 86 and Figure 89) IIO=-2mA T A≤85°C VDD-0.8
TA≥85°C VDD-1.0

Figure 84. Typical VOL at VDD=5V (standard) Figure 86. Typical VOH at VDD=5V
Vol [V] at Vdd=5V Voh [V] at Vdd=5V
2.5 6
Ta=-40°C Ta=85°C
2 5
Ta=25°C Ta=125°C
1.5 4

3 Ta=-40°C Ta=85°C
1

0.5 2 Ta=25°C Ta=125°C

0 1
0 2 4 6 8 10 -8 -6 -4 -2 0
Iio [mA] Iio [mA]

Figure 85. Typical VOL at VDD=5V (high-sink)

Vol [V] at Vdd=5V
2
Ta=-40°C Ta=85°C
1.5
Ta=25°C Ta=125°C

0.5

0
0 5 10 15 20 25 30
Iio [mA]
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.

128/151
ST72334J/N, ST72314J/N, ST72124J

I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 87. Typical VOL vs. VDD (standard I/Os)

Vol [V] at Iio=2mA Ta=-40°C Ta=85°C Vol [V] at Iio=5mA Ta=-40°C Ta=85°C
0.5 1.4
Ta=25°C Ta=125°C 1.3 Ta=25°C Ta=125°C
0.45
1.2
0.4 1.1
1
0.35
0.9
0.3 0.8
0.7
0.25
0.6
0.2 0.5
3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5
Vdd [V] Vdd [V]

Figure 88. Typical VOL vs. VDD (high-sink I/Os)

Vol [V] at Iio=8mA Ta=-40°C Ta=85°C Vol [V] at Iio=20mA Ta=-40°C Ta=85°C
0.55 1.5
Ta=25°C Ta=125°C Ta=25°C Ta=125°C
0.5
1.3
0.45
0.4 1.1

0.35 0.9
0.3
0.7
0.25
0.2 0.5
3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5
Vdd [V] Vdd [V]

Figure 89. Typical VOH vs. VDD

Voh [V] at Iio=-2mA Voh [V] at Iio=-5mA

5.5 5
5
4
4.5
4 3

3.5 Ta=-40°C Ta=85°C 2 Ta=-40°C Ta=85°C

3
Ta=25°C Ta=125°C 1 Ta=25°C Ta=125°C
2.5
2 0
3.2 3.5 4 4.5 5 5.5 3.5 4 4.5 5 5.5
Vdd [V] Vdd [V]

129/151
ST72334J/N, ST72314J/N, ST72124J

16.9 CONTROL PIN CHARACTERISTICS

16.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ 1) Max Unit
2)
VIL Input low level voltage 0.3xVDD
V
VIH Input high level voltage 2) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 3) 400 mV
4) IIO=+5mA 0.68 0.95
Output low level voltage
VOL VDD=5V V
(see Figure 92, Figure 93) IIO=+2mA 0.28 0.45
VDD=5V 20 40 60
RON Weak pull-up equivalent resistor 5) VIN=VSS kΩ
VDD=3.4V 80 100 120
External pin or 6 1/fSFOSC
tw(RSTL)out Generated reset pulse duration
internal reset sources 30 µs
th(RSTL)in External reset pulse hold time 6) 20 µs
tg(RSTL)in Filtered glitch duration 7) 100 ns

Figure 90. Typical Application with RESET pin 8)

ST72XXX
VDD
L
NA

VDD VDD
IO
PT

INTERNAL
O

RON
RESET CONTROL
USER 0.1µF 4.7kΩ
EXTERNAL RESET
RESET
CIRCUIT 8)
0.1µF WATCHDOG RESET
LVD RESET

Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-
scribed in Figure 91). This data is based on characterization results, not tested in production.
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).

130/151
ST72334J/N, ST72314J/N, ST72124J

CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 91. Typical ION vs. VDD with VIN=VSS Figure 92. Typical VOL at VDD=5V (RESET)

Ion [µA] Vol [V] at Vdd=5V Ta=-40°C Ta=85°C

200 Ta=-40°C Ta=85°C 2
Ta=25°C Ta=125°C Ta=25°C Ta=125°C
150 1.5

100 1

50 0.5

0 0
3.2 3.5 4 4.5 5 5.5 0 1 2 3 4 5 6 7 8

Vdd [V] Iio [mA]

Figure 93. Typical VOL vs. VDD (RESET)

Vol [V] at Iio=2mA Ta=-40°C Ta=85°C Vol [V] at Iio=5mA Ta=-40°C Ta=85°C
0.55
Ta=25°C Ta=125°C 1.2 Ta=25°C Ta=125°C
0.5
0.45
1
0.4
0.35
0.8
0.3
0.25 0.6
0.2
0.15 0.4
3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5
Vdd [V] Vdd [V]

131/151
ST72334J/N, ST72314J/N, ST72124J

CONTROL PIN CHARACTERISTICS (Cont’d)

16.9.2 ISPSEL Pin
Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
VIL Input low level voltage 1) VSS 0.2
V
VIH Input high level voltage 1) VDD-0.1 12.6
IL Input leakage current VIN=VSS ±1 µA

Figure 94. Two typical Applications with ISPSEL Pin 2)

ISPSEL ISPSEL
PROGRAMMING
TOOL
10kΩ
ST72XXX ST72XXX

Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to VSS.

132/151
ST72334J/N, ST72314J/N, ST72124J

16.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for V DD, Refer to I/O port characteristics for more details on
fOSC, and TA unless otherwise specified. the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
16.10.1 Watchdog Timer
Symbol Parameter Conditions Min Typ Max Unit
12,288 786,432 tCPU
tw(WDG) Watchdog time-out duration
fCPU=8MHz 1.54 98.3 ms

16.10.2 16-Bit Timer

Symbol Parameter Conditions Min Typ Max Unit
tw(ICAP)in Input capture pulse time 1 tCPU
2 tCPU
tres(PWM) PWM resolution time
fCPU=8MHz 250 ns
fEXT Timer external clock frequency 0 fCPU/4 MHz
fPWM PWM repetition rate 0 fCPU/4 MHz
ResPWM PWM resolution 16 bit

133/151
ST72334J/N, ST72314J/N, ST72124J

16.11 COMMUNICATION INTERFACE CHARACTERISTICS

16.11.1 SPI - Serial Peripheral Interface Refer to I/O port characteristics for more details on
Subject to general operating conditions for V DD, the input/output alternate function characteristics
fOSC, and TA unless otherwise specified. (SS, SCK, MOSI, MISO).

Symbol Parameter Conditions Min Max Unit

Master fCPU/128 fCPU/4
fSCK fCPU=8MHz 0.0625 2
SPI clock frequency MHz
1/tc(SCK) Slave fCPU/2
0
fCPU=8MHz 4
tr(SCK)
SPI clock rise and fall time see I/O port pin description
tf(SCK)
tsu(SS) SS setup time Slave 120
th(SS) SS hold time Slave 120
tw(SCKH) Master 100
SCK high and low time
tw(SCKL) Slave 90
tsu(MI) Master 100
Data input setup time
tsu(SI) Slave 100
ns
th(MI) Master 100
Data input hold time
th(SI) Slave 100
ta(SO) Data output access time Slave 0 120
tdis(SO) Data output disable time Slave 240
tv(SO) Data output valid time 120
Slave (after enable edge)
th(SO) Data output hold time 0
tv(MO) Data output valid time 0.25
Master (before capture edge) tCPU
th(MO) Data output hold time 0.25

Figure 95. SPI Slave Timing Diagram with CPHA=0 3)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=0
SCK INPUT

CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
tf(SCK)
MISO OUTPUT see
see note 2 MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

134/151
ST72334J/N, ST72314J/N, ST72124J

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 96. SPI Slave Timing Diagram with CPHA=11)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=0
SCK INPUT

CPOL=0
CPHA=0
CPOL=1

ta(SO) tw(SCKH) tdis(SO)

tw(SCKL) tv(SO) th(SO)
tr(SCK)
tf(SCK)
MISO OUTPUT see see
note 2 HZ MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Figure 97. SPI Master Timing Diagram 1)

SS INPUT
tc(SCK)

CPHA=0
CPOL=0
CPHA=0
SCK INPUT

CPOL=1

CPHA=1
CPOL=0

CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tw(SCKL) tf(SCK)

tsu(MI) th(MI)

MISO INPUT MSB IN BIT6 IN LSB IN

tv(MO) th(MO)

MOSI OUTPUT see note 2 MSB OUT BIT6 OUT LSB OUT see note 2

Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

135/151
ST72334J/N, ST72314J/N, ST72124J

COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)

16.11.2 SCI - Serial Communications Interface

Subject to general operating condition for VDD, fO-
SC , and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(RDI and TDO).
Conditions
Baud
Symbol Parameter Accuracy Standard Unit
fCPU Prescaler Rate
vs. Standard
Conventional Mode
TR (or RR)=64, PR=13 300 ~300.48
TR (or RR)=16, PR=13 1200 ~1201.92
TR (or RR)= 8, PR=13 2400 ~2403.84
TR (or RR)= 4, PR=13 4800 ~4807.69
~0.16% TR (or RR)= 2, PR=13 9600 ~9615.38
fTx
Communication frequency 8MHz TR (or RR)= 8, PR= 3 10400 ~10416.67 Hz
fRx
TR (or RR)= 1, PR=13 19200 ~19230.77
Extended Mode
ETPR (or ERPR) = 13 38400 ~38461.54
Extended Mode
~0.79%
ETPR (or ERPR) = 35 14400 ~14285.71

136/151
ST72334J/N, ST72314J/N, ST72124J

16.12 8-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ 1) Max Unit
fADC ADC clock frequency 4 MHz
2)
VAIN Conversion range voltage VSSA VDDA V
3)
RAIN External input resistor 10 kΩ
CADC Internal sample and hold capacitor 6 pF
tSTAB Stabilization time after ADC enable 0 4)
µs
Conversion time (Sample+Hold) 3
fCPU=8MHz, fADC=4MHz
tADC - Sample capacitor loading time 4
1/fADC
- Hold conversion time 8

Figure 98. Typical Application with ADC

VDD

VT
0.6V
RAIN AINx
VAIN ADC
VT
CIO 0.6V IL
~2pF ±1µA
VDD
VDDA

0.1µF
VSSA
ST72XXX

Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS .
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.

137/151
ST72334J/N, ST72314J/N, ST72124J

8-BIT ADC CHARACTERISTICS (Cont’d)

ADC Accuracy
VDD=5V, 2) VDD=5.0V, 3) VDD=3.3V, 3)
Symbol Parameter fCPU=1MHz fCPU=8MHz fCPU=8MHz Unit
Min Max Min Max Min Max
|ET| Total unadjusted error 1) 2.0 2.0 2.0
EO Offset error 1) 1.5 1.5 1.5
EG Gain Error 1) 1.5 1.5 1.5 LSB
|ED| Differential linearity error 1) 1.5 1.5 1.5
|EL| Integral linearity error 1) 1.5 1.5 1.5

Figure 99. ADC Accuracy Characteristics

Digital Result ADCDR EG
(1) Example of an actual transfer curve
255
(2) The ideal transfer curve
254 V –V
DDA SSA (3) End point correlation line
1LSB = -----------------------------------------
253 IDE AL 256

(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
Vin (LSBIDEAL)
0
1 2 3 4 5 6 7 253 254 255 256
VSSA VDDA

Notes:
1. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.
2. Data based on characterization results with TA=25°C.
3. Data based on characterization results over the whole temperature range.

138/151
ST72334J/N, ST72314J/N, ST72124J

17 PACKAGE CHARACTERISTICS

17.1 PACKAGE MECHANICAL DATA

Figure 100. 64-Pin Thin Quad Flat Package

D A mm inches
Dim.
D1 A2 Min Typ Max Min Typ Max
A1 A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b b 0.30 0.37 0.45 0.012 0.015 0.018
c 0.09 0.20 0.004 0.008
D 16.00 0.630
e
D1 14.00 0.551
E1 E
E 16.00 0.630
E1 14.00 0.551
e 0.80 0.031
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L
L1 1.00 0.039
L1
c Number of Pins

h N 64

Figure 101. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width

mm inches
Dim.
Min Typ Max Min Typ Max
E A 6.35 0.250
A1 0.38 0.015
A2 A
A2 3.18 4.95 0.125 0.195
A1 C
E1 b 0.41 0.016
eA
b2 b e
eB b2 0.89 0.035
D
E C 0.20 0.38 0.008 0.015
0.015 D 50.29 53.21 1.980 2.095
GAGE PLANE E 15.01 0.591
E1 12.32 14.73 0.485 0.580
e 1.78 0.070
eA 15.24 0.600
eB
eB 17.78 0.700
L 2.92 5.08 0.115 0.200
Number of Pins
N 56

139/151
ST72334J/N, ST72314J/N, ST72124J

PACKAGE MECHANICAL DATA (Cont’d)

Figure 102. 44-Pin Thin Quad Flat Package

mm inches
D A Dim.
Min Typ Max Min Typ Max
D1 A2
A 1.60 0.063
A1 A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.30 0.37 0.45 0.012 0.015 0.018
b
C 0.09 0.20 0.004 0.000 0.008
D 12.00 0.472
e D1 10.00 0.394
E1 E
E 12.00 0.472
E1 10.00 0.394
e 0.80 0.031
θ 0° 3.5° 7° 0° 3.5° 7°

c L 0.45 0.60 0.75 0.018 0.024 0.030

L1
L1 1.00 0.039
L
h Number of Pins
N 44
Jedec Ref. MS-

Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width

mm inches
Dim.
E Min Typ Max Min Typ Max
A 5.08 0.200
A2 A A1 0.51 0.020
A2 3.05 3.81 4.57 0.120 0.150 0.180
A1 L c E1
b 0.38 0.46 0.56 0.015 0.018 0.022
b2 b e eA

eB
b2 0.89 1.02 1.14 0.035 0.040 0.045
D
E c 0.23 0.25 0.38 0.009 0.010 0.015
D 36.58 36.83 37.08 1.440 1.450 1.460
0.015
E 15.24 16.00 0.600 0.630
GAGE PLANE
E1 12.70 13.72 14.48 0.500 0.540 0.570
e 1.78 0.070
eA 15.24 0.600
eC eB 18.54 0.730
eB
eC 1.52 0.000 0.060
L 2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N 42

Figure
Notes: 104. THERMAL CHARACTERISTICS
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)

140/151
ST72334J/N, ST72314J/N, ST72124J

Symbol Ratings Value Unit

Package thermal resistance (junction to ambient)
TQFP64 60
RthJA SDIP56 45 °C/W
TQFP44 52
SDIP42 55
PD Power dissipation 1) 500 mW
TJmax Maximum junction temperature 2) 150 °C

and PPORT is the port power dissipation determined by the user.

2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.

141/151
ST72334J/N, ST72314J/N, ST72124J

17.2 SOLDERING AND GLUEABILITY INFORMATION

Recommended soldering information given only Recommended glue for SMD plastic packages
as design guidelines in Figure 105 and Figure 106. dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955

■ Loctite: 3615, 3298

Figure 105. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)

250
COOLING PHASE
200 5 sec (ROOM TEMPERATURE)

SOLDERING
150 80°C PHASE
Temp. [°C]
100
PREHEATING
PHASE
50

0 Time [sec]
20 40 60 80 100 120 140 160

Figure 106. Recommended Reflow Soldering Oven Profile (MID JEDEC)

250
Tmax=220+/-5°C
for 25 sec
200

150 sec above 183°C

150 90 sec at 125°C
Temp. [°C]
100 ramp down natural
ramp up 2°C/sec max
50 2°C/sec for 50sec

0 Time [sec]
100 200 300 400

142/151
ST72334J/N, ST72314J/N, ST72124J

18 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- USER OPTION BYTE 1
grammable versions (FLASH) as well as in factory Bit 7 = CSS Clock Security System disable
coded versions (ROM). E 2PROM data memory This option bit enables or disables the CSS fea-
and FLASH devices are shipped to customers with tures.
a default content (FFh), while ROM factory coded 0: CSS enabled
parts contain the code supplied by the customer. 1: CSS disabled
This implies that FLASH devices have to be con-
figured by the customer using the Option Bytes Bit 6:4 = OSC[2:0] Oscillator selection
while the ROM devices are factory-configured. These three option bits can be used to select the
main oscillator as shown in Table 24.
18.1 OPTION BYTES Bit 3:2 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a se-
The two option bytes allow the hardware configu- lected threshold as shown in Table 25.
ration of the microcontroller to be selected. Bit 1 = WDG HALT Watchdog and halt mode
The option bytes have no address in the memory This option bit determines if a RESET is generated
map and can be accessed only in programming when entering HALT mode while the Watchdog is
mode (for example using a standard ST7 program- active.
ming tool). The default content of the FLASH is 0: No Reset generation when entering Halt mode
fixed to FFh. 1: Reset generation when entering Halt mode
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option Bit 0 = WDG SW Hardware or software watchdog
list). This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
USER OPTION BYTE 0 1: Software (watchdog to be enabled by software)
Bit 7:2 = Reserved, must always be 1. Table 24. Main Oscillator Configuration
Bit 1 = 56/42 Package Configuration. Selected Oscillator OSC2 OSC1 OSC0
This option bit allows to configured the device ac- External Clock (Stand-by) 1 1 1
cording to the package.
0: 42 or 44 pin packages ~4 MHz Internal RC 1 1 0
1: 56 or 64 pin packages 1~14 MHz External RC 1 0 X
Bit 0 = FMP Full memory protection. Low Power Resonator (LP) 0 1 1
This option bit enables or disables external access Medium Power Resonator (MP) 0 1 0
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (by over- Medium Speed Resonator (MS) 0 0 1
writing with the currently latched values) of the High Speed Resonator (HS) 0 0 0
whole memory (not including the option bytes).
0: Program memory not read-out protected Table 25. LVD Threshold Configuration
1: Program memory read-out protected Configuration LVD1 LVD0
Note: The data E2PROM is not protected by this LVD Off 1 1
bit in flash devices. In ROM devices, a protection
can be selected in the Option List (see page 145). Highest Voltage Threshold (∼4.50V) 1 0
Medium Voltage Threshold (∼4.05V) 0 1
Lowest Voltage Threshold (∼3.45V) 0 0

USER OPTION BYTE 0 USER OPTION BYTE 1

7 0 7 0
OSC OSC OSC WDG WDG
Reserved 56/42 FMP CSS LVD1 LVD0
2 1 0 HALT SW
Default
1 1 1 1 1 1 X 0 1 1 1 0 1 1 1 1
Value

143/151
ST72334J/N, ST72314J/N, ST72124J

DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

18.2 TRANSFER OF CUSTOMER CODE

Customer code is made up of the ROM contents The selected options are communicated to STMi-
and the list of the selected options (if any). The croelectronics using the correctly completed OP-
ROM contents are to be sent on diskette, or by TION LIST appended.
electronic means, with the hexadecimal file in .S19 The STMicroelectronics Sales Organization will be
format generated by the development tool. All un- pleased to provide detailed information on con-
used bytes must be set to FFh. tractual points.
Figure 107. ROM Factory Coded Device Types

TEMP.
DEVICE PACKAGE RANGE / XXX
Code name (defined by STMicroelectronics)

1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105 °C
3= automotive -40 to +125 °C

B = Plastic DIP
T = Plastic TQFP

ST72334J2, ST72334J4, ST72334N2, ST72334N4,

ST72314J2, ST72314J4, ST72314N2, ST72314N4,
ST72124J2

Figure 108. FLASH User Programmable Device Types

TEMP.
DEVICE PACKAGE RANGE XXX
Code name (defined by STMicroelectronics)

1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105 °C
3= automotive -40 to +125 °C

B = Plastic DIP
T = Plastic TQFP

ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4,

ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4,
ST72C124J2

144/151
ST72334J/N, ST72314J/N, ST72124J

MICROCONTROLLER OPTION LIST

Customer: ...................................................................................
Address: ...................................................................................

Contact: ...................................................................................
Phone No: ...................................................................................
Reference/ROM code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*The ROM or FASTROM code name is assigned by STMicroelectronics.
ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
STMicroelectronics references
ROM Type/Memory Size/Package (check only 1 option):
-------------------------------------------------------------------------------------------
ROM DEVICE: | 8K | 16K
------------------------------------------------------------------------------------------- |
SDIP42: | [ ] ST72124J2B | |
| [ ] ST72314J2B | [ ] ST72314J4B |
| [ ] ST72334J2B | [ ] ST72334J4B |
TQFP44: | [ ] ST72124J2T | |
| [ ] ST72314J2T | [ ] ST72314J4T |
| [ ] ST72334J2T | [ ] ST72334J4T |
SDIP56: | [ ] ST72314N2B | [ ] ST72314N4B |
| [ ] ST72334N2B | [ ] ST72334N4B |
TQFP64: | [ ] ST72314N2T | [ ] ST72314N4T |
| [ ] ST72334N2T | [ ] ST72334N4T |
-------------------------------------------------------------------------------------------
FASTROM
------------------------------------------------------------------------------------------- |
DEVICE:| 8K | 16K
SDIP42: | [ ] ST72P124J2B | |
| [ ] ST72P314J2B | [ ] ST72P314J4B |
| [ ] ST72P334J2B | [ ] ST72P334J4B |
TQFP44: | [ ] ST72P124J2T | |
| [ ] ST72P314J2T | [ ] ST72P314J4T |
| [ ] ST72P334J2T | [ ] ST72P334J4T |
SDIP56: | [ ] ST72P314N2B | [ ] ST72P314N4B |
| [ ] ST72P334N2B | [ ] ST72P334N4B |
TQFP64: | [ ] ST72P314N2T | [ ] ST72P314N4T |
| [ ] ST72P334N2T | [ ] ST72P334N4T |

Conditioning (specify for TQFP only): [ ] Tape & Reel [ ] Tray

Marking: [ ] Standard marking [ ] Special marking (ROM only):

TQFP (10 char. max) : _ _ _ _ _ _ _ _ _ _
SDIP (16 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Please consult your local STMicroelectronics sales office for other marking details if required.

Temperature Range: [ ] 0°C to +70°C [ ] -40°C to +85°C [ ] -40°C to +105°C [ ] -40°C to +125°C

Clock Source Selection:

Resonator: [ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
RC Network: [ ] Internal [ ] External
External Clock: []

Clock Security System: [ ] Disabled [ ] Enabled

LVD Reset: [ ] Disabled [ ] Enabled: [ ] Highest threshold

[ ] Medium threshold
[ ] Lowest threshold

Watchdog Selection: [ ] Software Activation [ ] Hardware Activation

Halt when Watchdog on: [ ] Reset [ ] No reset

Program Readout Protection: [ ] Disabled [ ] Enabled

Data E2PROM Readout Protection*: [ ] Disabled [ ] Enabled
*available on ST72334 only

Comments:
Supply Operating Range in the application:
Notes:
Date:
Signature:

145/151
ST72334J/N, ST72314J/N, ST72124J

18.3 DEVELOPMENT TOOLS

STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
port: see Table 26 and Table 27 for more details.

Table 26. STMicroelectronics Tool Features

In-Circuit Emulation Programming Capability1) Software Included
Yes. (Same features as ST7 CD ROM with:
ST7 Development Kit HDS2 emulator but without Yes (DIP packages only) – ST7 Assembly toolchain
logic analyzer) – STVD7 and WGDB7 powerful
Yes, powerful emulation Source Level Debugger for Win
ST7 HDS2 Emulator features including trace/ No 3.1, Win 95 and NT
logic analyzer – C compiler demo versions
– ST Realizer for Win 3.1 and Win
95.
ST7 Programming Board No Yes (All packages) – Windows Programming Tools
for Win 3.1, Win 95 and NT

Table 27. Dedicated STMicroelectronics Development Tools

Supported Products ST7 Development Kit ST7 HDS2 Emulator ST7 Programming Board

ST72(C)334J2,
ST72(C)334J4,
ST72(C)334N2,
ST72(C)334N4, ST7MDT2-EPB2/EU
ST72(C)314J2, ST7MDT2-DVP2 ST7MDT2-EMU2B ST7MDT2-EPB2/US
ST72(C)314J4, ST7MDT2-EPB2/UK
ST72(C)314N2,
ST72(C)314N4,
ST72(C)124J2

Note:
1. In-Situ Programming (ISP) interface for FLASH devices.

146/151
ST72334J/N, ST72314J/N, ST72124J

DEVELOPMENT TOOLS (Cont’d)

18.3.1 Suggested List Of Socket Types
Table 28. Suggested List of TQFP64 Socket Types
Package / Probe Adaptor / Socket Reference Socket type
ENPLAS OTQ-64-0.8-02 Open Top
TQFP64
YAMAICHI IC51-0644-1240.KS-14584 Clamshell
EMU PROBE YAMAICHI IC149-064-008-S5 SMC

Suggested List of TQFP44 Socket Types

Package / Probe Adaptor / Socket Reference Socket type
ENPLAS OTQ-44-0.8-04 Open Top
TQFP44
YAMAICHI IC51-0444-467-KS-11787 Clamshell
TQFP44
YAMAICHI IC149-044-*52-S5 SMC
EMU PROBE

147/151
ST72334J/N, ST72314J/N, ST72124J

18.4 ST7 APPLICATION NOTES

IDENTIFICATION DESCRIPTION
EXAMPLE DRIVERS
AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971 I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSO‹D)
AN1042 ST7 ROUTINE FOR IÝC SLAVE MODE MANAGEMENT
AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045 ST7 S/W IMPLEMENTATION OF IÝC BUS MASTER
AN1046 UART EMULATION SOFTWARE
AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048 ST7 SOFTWARE LCD DRIVER
AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105 ST7 PCAN PERIPHERAL DRIVER
AN1129 PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
AN1130
WITH THE ST72141
AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149 HANDLING SUSPEND MODE ON A USB MOUSE
AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD
AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1150 BENCHMARK ST72 VS PC16
AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION

148/151
ST72334J/N, ST72314J/N, ST72124J

IDENTIFICATION DESCRIPTION
AN 982 USING ST7 WITH CERAMIC RENATOR
AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
PROGRAMMING AND TOOLS
AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985 EXECUTING CODE IN ST7 RAM
AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
AN1039 ST7 MATH UTILITY ROUTINES
AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
AN1179
GRAMMING)
AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR

18.5 TO GET MORE INFORMATION

To get the latest information on this product please use the ST web server: http://mcu.st.com/

149/151
ST72334J/N, ST72314J/N, ST72124J

19 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.

Revision Main changes Date

Changed voltage characteristics table on page 107.
Changed IDD typical value in halt mode (Section 16.4.3 on page 114).
Changed title of Figure 86 on page 128 and Figure 89 on page 129.
2.4 Added paragraph “Designing hardened software to avoid noise problems” on page 124. July-02
Changed description of FMP option bit in Section 18.1 on page 143.
Changed option list on page 145.
Changed Section 18.3 on page 146.

150/151
ST72334J/N, ST72314J/N, ST72124J

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

151/151
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.