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Unit 2

Combinational logic circuits can be either combinational or sequential. A combinational circuit consists of input variables, logic gates, and output variables. A half adder performs addition of two bits and produces a sum and carry output. A full adder performs the addition of three bits (two inputs and a carry) and is implemented using two half adders and an OR gate. Ripple carry adders are built by cascading full adders but have long propagation delays. Carry lookahead adders use generate and propagate signals to predict the carry, improving speed over ripple carry adders. Decoders and multiplexers are also basic combinational logic circuits.

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109 views

Unit 2

Combinational logic circuits can be either combinational or sequential. A combinational circuit consists of input variables, logic gates, and output variables. A half adder performs addition of two bits and produces a sum and carry output. A full adder performs the addition of three bits (two inputs and a carry) and is implemented using two half adders and an OR gate. Ripple carry adders are built by cascading full adders but have long propagation delays. Carry lookahead adders use generate and propagate signals to predict the carry, improving speed over ripple carry adders. Decoders and multiplexers are also basic combinational logic circuits.

Uploaded by

toshgangwar
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Combinational Logic

Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output variables.

Binary Adder-Subtractor

A combinational circuit that performs the addition of two bits is called a half adder. The truth table for the half adder is listed below:

S: Sum C: Carry

S = xy + xy C = xy
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Implementation of Half-Adder

Full-Adder

One that performs the addition of three bits(two significant bits and a previous carry) is a full adder.

Simplified Expressions

S = xyz + xyz + xyz + xyz C = xy + xz + yz


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Full adder implemented in SOP

Another implementation

Full-adder can also implemented with two half adders and one OR gate (Carry Look-Ahead adder).
S = z (x y) = z(xy + xy) + z(xy + xy) = xyz + xyz + xyz + xyz C = z(xy + xy) + xy = xyz + xyz + xy

Binary adder

This is also called Ripple Carry Adder ,because of the construction with full adders are connected in cascade.

Carry Propagation

Fig.4-9 causes a unstable factor on carry bit, and produces a longest propagation delay.
The signal from Ci to the output carry Ci+1, propagates through an AND and OR gates, so, for an n-bit RCA, there are 2n gate levels for the carry to propagate from input to output.

Carry Propagation

Because the propagation delay will affect the output signals on different time, so the signals are given enough time to get the precise and stable outputs.

The most widely used technique employs the principle of carry look-ahead to improve the speed of the algorithm.

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Boolean functions
Pi = Ai Bi steady state value Gi = AiBi steady state value Output sum and carry Si = Pi Ci Ci+1 = Gi + PiCi Gi : carry generate Pi : carry propagate C0 = input carry C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C3 does not have to wait for C2 and C1 to propagate.


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Logic diagram of carry look-ahead generator

C3 is propagated at the same time as C2 and C1.

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4- Bits adder

Binary subtractor
M = 1subtractor ; M = 0adder

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BCD Adder

BCD Adder

When the sum of two digits is less than or equal to 9 then the ordinary 4-bit adder can be used But if the sum of two digits is greater than 9 then a correction must be added I.e adding 0110 We need to design a circuit that is capable of doing the correct addition

BCD Adder

The cases where the sum of two 4-bit numbers is greater than 9 are in the following table:
S4 0 0 0 0 0 0 1 1 1 S3 1 1 1 1 1 1 0 0 0 S2 0 0 1 1 1 1 0 0 0 S1 1 1 0 0 1 1 0 0 1 S0 0 1 0 1 0 1 0 1 0 10 11 12 13 14 15 16 17 18

BCD Adder
Whenever S4=1 (sums greater than 15) Whenever S3=1 and either S2 or S1 or both are 1 (sums 10 to 15) The previous table can be expressed as: X = S4 + S3 ( S2 + S1) So, whenever X = 1 we should add a correction of 0110 to the sum.

Inputs:[A]=0101, [B]= 0011, Co=0

0011

0101 0 0 1 0 0 1000 1 1 0 0 0 0000 0 0 0

Inputs:[A]=0111, [B]= 0110, Co=0

0110

0111
0 1 1 1 1 1101 1 0 0 1 1 0110 1 0 1

Cascading BCD Adders

The previous circuit is used for adding two decimal digits only. That is, 7 + 6 = 13. For adding numbers with several digits, a separate BCD adder for each digit position must be used. BCD Adder For example: BCD Adder 2 4 7 5 3 8 + -------------------? BCD Adder

Cascading BCD Adders

Example

Determine the inputs and the outputs when the above circuit is used to add 538 to 247. Assume a CARRY IN = 0 Solution:

Represent the decimal numbers in BCD


247 = 0010 0100 0111 538 = 0101 0011 1000 Put these numbers in registers [A] and [B] [A] = 0010 0100 0111 [B] = 0101 0011 1000

Example

0 0 1 0 0 0111 0

0 1 0 0 1

0 1 1 1

0 1000 0101

0 1 0 1

0 0 1 1

1 0 0 0

Overflow

It is worth noting Fig.4-13 that binary numbers in the signed-complement system are added and subtracted by the same basic addition and subtraction rules as unsigned numbers. Overflow is a problem in digital computers because the number of bits that hold the number is finite and a result that contains n+1 bits cannot be accommodated.

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Rules of BCD adder

When the binary sum is greater than 1001, we obtain a non-valid BCD representation. The addition of binary 6(0110) to the binary sum converts it to the correct BCD representation and also produces an output carry as required. To distinguish them from binary 1000 and 1001, which also have a 1 in position Z8, we specify further that either Z4 or Z2 must have a 1. C = K + Z8Z4 + Z8Z2
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Implementation of BCD adder

A decimal parallel adder that adds n decimal digits needs n BCD adder stages.

The output carry from one stage must be connected to the input carry of the next higherorder stage.

If =1

0110

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Magnitude comparator

The equality relation of each pair of bits can be expressed logically with an exclusive-NOR function as: A = A3A2A1A0 ; B = B3B2B1B0 xi=AiBi+AiBi for i = 0, 1, 2, 3 (A = B) = x3x2x1x0

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Magnitude comparator

We inspect the relative magnitudes of pairs of MSB. If equal, we compare the next lower significant pair of digits until a pair of unequal digits is reached. If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B.

(A>B)= A3B3+x3A2B2+x3x2A1B1+x3x2x1A0B0 (A<B)= A3B3+x3A2B2+x3x2A1B1+x3x2x1A0B0


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Decoders

The decoder is called n-to-m-line decoder, where m2n . the decoder is also used in conjunction with other code converters such as a BCD-to-seven_segment decoder. 3-to-8 line decoder: For each possible input combination, there are seven outputs that are equal to 0 and only one that is equal to 1.

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Implementation and truth table

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Decoder with enable input

Some decoders are constructed with NAND gates, it becomes more economical to generate the decoder minterms in their complemented form. As indicated by the truth table , only one output can be equal to 0 at any given time, all other outputs are equal to 1.

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Demultiplexer

A decoder with an enable input is referred to as a decoder/demultiplexer. The truth table of demultiplexer is the same with decoder. A B

D0 E

Demultiplexer

D1 D2 D3
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3-to-8 decoder with enable implement the 4-to-16 decoder

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Implementation of a Full Adder with a Decoder

From table 4-4, we obtain the functions for the combinational circuit in sum of minterms: S(x, y, z) = (1, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7)

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Decoders: Implementing Functions

Example: Full adder S(x, y, z) = S m(1,2,4,7) C(x, y, z) = S m(3,5,6,7)

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

C S 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

3x8 Dec x y z
S2 S1 S0

0 1 2 3 4 5 6 7

From Figure

Multiplexers
S = 0, Y = I0 S = 1, Y = I1 Truth Table S 0 1 Y I0 I1 Y = SI0 + SI1

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4-to-1 Line Multiplexer

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