Chapter 5: Memory Management

⚫ Background
⚫ Swapping
⚫ Contiguous Allocation
⚫ Paging
⚫ Segmentation
⚫ Segmentation with Paging
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Background
⚫ Address Binding:
◦ Program resides on disk.

◦ Program must be brought into memory and placed within a process for it to be run.

⚫ Input queue – collection of processes on the disk that are waiting to be brought

into memory to run the program.

⚫ User programs go through several steps before being run.

⚫ Addresses in source program are symbolic. e.g. count.

⚫ Compiler binds Symbolic address to relocatable address.

⚫ Linkage editor / loader binds relocatable address to absolute (physical )address.

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Binding of Instructions and Data to Memory

Address binding of instructions and data to memory addresses can

happen at three different stages.

⚫ Compile time: If memory location known a priori, absolute code

can be generated; must recompile code if starting location changes.

⚫ Load time: Must generate relocatable code if memory location is

not known at compile time.

⚫ Execution time: Binding delayed until run time if the process can be
moved during its execution from one memory segment to another.
Need hardware support for address maps (e.g., base and limit
registers).

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Dynamic Loading
⚫ Routine is not loaded until it is called

⚫ Calling routine first checks whether other routine is loaded then it

loads.

⚫ Better memory-space utilization; unused routine is never loaded.

⚫ Useful when large amounts of code are needed to handle infrequently

occurring cases. e.g. error handling.

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Dynamic Linking
⚫ Linking postponed until execution time.

⚫ Small piece of code, stub, used to locate the appropriate

memory-resident library routine.

⚫ Stub replaces itself with the address of the routine, and

executes the routine.

⚫ Operating system needed to check if routine is in

processes’ memory address.

⚫ Dynamic linking is particularly useful for libraries.

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Logical vs. Physical Address Space
⚫ The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management.

◦ Logical address – generated by the CPU; also referred to as virtual

address.

◦ Physical address – address seen by the memory unit.

⚫ Logical and physical addresses are the same in compile-time and

load-time address-binding schemes; logical (virtual) and physical
addresses differ in execution-time address-binding scheme.

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Memory-Management Unit (MMU)
⚫ Hardware device that maps virtual to physical address.

⚫ In MMU scheme, the value in the relocation register is added to

every address generated by a user process at the time it is sent to
memory.

⚫ The user program deals with logical addresses; it never sees the
real physical addresses.

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Dynamic relocation using a relocation register

Relocation is base register

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Swapping
⚫ A process can be swapped temporarily out of memory to a backing store,
and then brought back into memory for continued execution.

⚫ Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these memory
images.

⚫ Roll out, roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority process
can be loaded and executed.

⚫ Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped.

⚫ Modified versions of swapping are found on many systems, i.e., UNIX,

Linux, and Windows.
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Schematic View of Swapping

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Contiguous Allocation
⚫ Main memory usually into two partitions:
◦ Resident operating system, usually held in low memory with interrupt
vector.

◦ User processes then held in high memory.

⚫ Single-partition allocation
◦ OS is need to be protected from malicious user processes & protect processes
from each other.
OS
◦ Relocation-register scheme used to protect user processes from each other, and

User
from changing operating-system code and data.

◦ Relocation register contains value of smallest physical address; limit register

contains range of logical addresses – each logical address must be less than the
limit register.
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Hardware Support for Relocation and Limit Registers

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Contiguous Allocation (Cont.)
⚫ Multiple-partition allocation

◦ Hole – block of available memory; holes of various size are scattered

throughout memory.

◦ When a process arrives, it is allocated memory from a hole large enough to

accommodate it.

◦ Operating system maintains information about:

a) allocated partitions b) free partitions (hole)
OS OS OS
OS
process 5 process 5
process 5 process 5
process 9
process 9
process 8
process 10

process 2 process 2 process 2 process 2

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Multiple partition Allocation

⚫ How to satisfy request of size n from list of free holes?

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Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes.

⚫ First-fit: Allocate the first hole that is big enough.

⚫ Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size. Produces the smallest leftover hole.

⚫ Worst-fit: Allocate the largest hole; must also search entire list.
Produces the largest leftover hole.

First-fit and best-fit better than worst-fit in terms of speed and

storage utilization.

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Fragmentation
⚫ External Fragmentation – total memory
space exists to satisfy a request, but it is not
contiguous. It is fragmented into a large
number of small holes.

⚫ Example: We have a total external

fragmentation of (300+260)=560KB.

⚫ If P5 is 500KB, then this space would be large

enough to run P5.

⚫ But the space is not contiguous.

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Fragmentation
⚫ Internal Fragmentation – allocated memory
may be slightly larger than requested memory;
this size difference is memory internal to a
partition, but not being used.

⚫ Example: Assume next request is for 18462 bytes.

⚫ – If we allocate exactly the requested block, we

are left with a hole of 2 bytes.

⚫ The overhead to keep track of this hole will be

larger than the hole itself. So, we ignore this small
hole (internal fragmentation).

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External fragmentation: Solution

⚫ Reduce external fragmentation by compaction

◦ Shuffle memory contents to place all free

memory together in one large block.

◦ Compaction is possible only if relocation is

dynamic, and is done at execution time.

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Paging
⚫ Logical address space of a process can be noncontiguous; process is
allocated physical memory whenever the latter is available.

⚫ Divide physical memory into fixed-sized blocks called frames (size is

power of 2, between 512 bytes and 8192 bytes).

⚫ Divide logical memory into blocks of same size called pages.

⚫ Keep track of all free frames.

⚫ To run a program of size n pages, need to find n free frames and load
program.

⚫ Set up a page table to translate logical to physical addresses.

⚫ Internal fragmentation: No external fragmentation, but have some

internal fragmentation.(if pages are 512 bytes, a process of 1280 bytes
would need 2 pages plus 256 bytes.)3/7/2017
Address Translation Scheme
⚫ Address generated by CPU is divided into:
◦ Page number (p) – used as an index into a page table which
contains base address of each page in physical memory.
◦ Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit.
Page number page offset
P d
(m–n) n

Higher bits Lower bits

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Address Translation Architecture

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Paging Example

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Paging Example:
for a 32-byte memory with 4 byte pages

Logical memory space=24=16 bytes

Page table contains frame no.
Page size=22=4 bytes
m=4
n=2
m-n = page no bits
N=offset bits

Logical address 0, is page 0, offset = 0

So physical address= (5 * 4) + 0 = 20
Logical address 3, is page 0, offset = 3
So physical address = ( 5 * 4) + 3 = 23

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● As a concrete (although minuscule) example, consider the
memory in Figure 8.9.

● Here, in the logical address, n= 2 and m = 4. Using a page size

of 4 bytes and a physical memory of 32 bytes (8 pages), we
show how the user's view of memory can be mapped into
physical memory. Logical address 0 is page 0, offset 0.

● Indexing into the page table, we find that page 0 is in frame 5.

Thus, logical address 0 maps to physical address 20 [= (5 x 4) +
0].
● Logical address 3 (page 0, offset 3) maps to physical address
23 [ = (5 x 4) + 3].

● Logical address 4 is page 1, offset 0; according to the page

table, page 1 is mapped to
● frame 6.

● Thus, logical address 4 maps to physical address 24 [ = ( 6 x 4)

+ O].
● Logical address 13 maps to physical address 9.
Free Frames

Before allocation 3/7/2017

After allocation
Memory Protection
⚫ Memory protection implemented by associating protection bit with each
frame.

⚫ One bit can define a page to be read-write or read only. Every reference
to memory goes through the page table to find correct frame number.
While computing physical address, protection bits are checked to verify,
no writers are being made to read-only page.

⚫ Illegal attempts are trapped by OS. One more bit is Valid-invalid bit

⚫ Valid-invalid bit attached to each entry in the page table:

◦ “valid” indicates that the associated page is in the process’ logical

address space, and is thus a legal page.

◦ “invalid” indicates that the page is not in the process’ logical address
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space.
Valid (v) or Invalid (i) Bit In A Page Table
Consider a system with 14 bit address space (0 - 16383)
1 page = 2 KB = 211 = 2048 bytes
A program requires address space 0 - 10468

Here only 0-5 pages are valid,

attempts to access page 6 & 7

2047 set protection bit to invalid.

4095 Page 5 is classified as valid so,
6143 addresses upto 12, 287 are valid
8191
& addresess from 12288-16383
10239
are invalid.
Internal
Fragmentation

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Segmentation
⚫ Memory-management scheme that supports user view of memory.

⚫ User prefer to see memory as collection of variable length segments than logical

address space as array of bytes.

⚫ A program is a collection of segments. A segment is a logical unit such as:

main program,

procedure,

function, Compiler automatically

method, constructs segments of

input program.
object,

local variables, global variables,

common block,

stack,

symbol table, arrays 3/7/2017

User’s View of a Program

Segments without caring

what addresses in memory
these elements occupy

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Logical View of Segmentation
1
1
4
2

3
4
2

user physical memory

space space
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Segmentation Architecture
⚫ Logical address space is collection of segments. Each segment has name & length.

⚫ Logical address consists of a two tuple:

<segment-number, offset>,

for simplicity segment number than name

⚫ Segment table – maps two-dimensional physical addresses; each table entry has:

◦ Segment base – contains the starting physical address where the segments

reside in memory.

◦ Segment limit – specifies the length of the segment.

⚫ Segment-table base register (STBR) points to the segment table’s location in

memory.

⚫ Segment-table length register (STLR) indicates number of segments used by a

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program;
Segmentation Hardware
Segment no as index

Offset must be
less than limit

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Example of Segmentation

Segment 2 is 400 bytes long & begins at 4300, byte 53

will be mapped to 4300+53=4353.
1222 byte of segment 0 will generate error.
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Sharing of Segments

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Segment Protection and Sharing
⚫ With each entry of segment table associate:
◦ Validation bit = 0 => illegal segment

◦ Read/write/execute privilege

⚫ Protection bits associated with segments; code sharing occurs a

segment level.

⚫ Sharing is simple but subtle consideration. Code segment contain

references. Conditional branching may give transfer address and
segment number of code segment is segment number of transfer
address. Sqrt( ) function may get segment no 4 in one process & seg
no 17 by another process.

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Fragmentation
⚫ Segmentation cause external fragmentation, when all blocks of free
memory are too small to accommodate a segment.

⚫ In this case, the process may simply have to wait :

◦ until more memory (or at least a larger hole) becomes available, or

◦ until compaction creates a larger hole.

⚫ Solution:

⚫ Define each process to be one segment, which reduces to the variable-

sized partition scheme.

⚫ At the other extreme, each byte as segment . Then every byte need a base
register for its relocation, doubling memory use!

⚫ Next logical solution is fixed-sized, small segments ---is paging.

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Segmentation with Paging
⚫ This solution differs from pure segmentation in that the segment-table
entry contains not the base address of the segment, but rather the base
address of a page table for this segment.

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Segmentation with Paging – Intel 386
⚫ The 386 uses segmentation with paging for memory management.

⚫ Maximum number of segments per process = 16 KB

⚫ Each segment can be as large as 4 GB= 232 bytes..

⚫ Page size is 4 KB.

⚫ Logical-address space of a process is divided into 2 partitions.

⚫ Up to 8 KB segments that are private to that process. kept in the local

descriptor table (LDT)
a) Up to 8 KB segments that are shared among

b) all the processes. kept in the global descriptor table (GDT).

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Segmentation with Paging – Intel 386
⚫ Each segment is paged.

⚫ Logical address is pair of (selector, offset).

S g P

Segment no GDT or LDT Protection bit

⚫ First logical address is converted into linear address to give page

directory, page and offset.

⚫ Then linear address is converted into physical address

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Intel 30386 Address Translation

Segmentation
mechanism

Paging mechanism