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DSP Module 5

This document discusses digital signal processor architecture and hardware units such as multipliers and accumulators and shifters. It also covers fixed-point and floating-point data formats for DSP applications including Q-format representation. Examples are provided for converting between decimal and Q-15 fixed-point number formats.

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62 views

DSP Module 5

This document discusses digital signal processor architecture and hardware units such as multipliers and accumulators and shifters. It also covers fixed-point and floating-point data formats for DSP applications including Q-format representation. Examples are provided for converting between decimal and Q-15 fixed-point number formats.

Uploaded by

shilpa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Module 5

Digital Signal Processors


Digital Signal Processor Architecture
• Digital signal (DS) processors have special
features that require operations such as fast
Fourier transform (FFT), filtering, convolution
and correlation, and real-time sample-based
and block-based processing.
• Therefore, DS processors use a different
dedicated hardware architecture.
Digital Signal Processor Hardware Units

• Multiplier and Accumulator(MAC)


• Shifters
• Address Generators
Multiplier and Accumulator(MAC)
Shifters
• In digital filtering, to prevent overflow, a scaling operation is
required.
• A simple scaling-down operation shifts data to the right,
while a scaling-up operation shifts data to the left.
• Shifting data to the right is the same as dividing the data by 2
and truncating the fraction part; shifting data to the left is
equivalent to multiplying the data by 2
• As an example, for a 3-bit data word (011) 2=310
• , shifting 011 to the right gives (001) 2=1
• , that is, 3/2=1.5, and truncating 1.5 results in 1. Shifting the
same number to the left, we have (110) 2=610
• , that is, 3 x2 = 6
Address Generators
• The DS processor generates the addresses for
each datum on the data buffer to be
processed.
• A special hardware unit for circular buffering is
used.
• Figure describes the basic mechanism of
circular buffering for a buffer having eight data
samples
Fixed-Point and Floating-Point Formats
• In order to process real-world data, we need to
select an appropriate DS processor, as well as a DSP
algorithm or algorithms for a certain application.
• A fixed-point DS processor represents data in 2’s
complement integer format and manipulates data
using integer arithmetic
• a floating-point processor represents numbers using
a mantissa (fractional part) and an exponent in
addition to the integer format and operates data
using floating-point arithmetic
Fixed-Point Format
Q-format number representation
• Q-format number representation is the most
common one used in fixed-point DSP
implementation.
• Q-15 means that the data are in a sign
magnitude form in which there are 15 bits for
magnitude and one bit for sign.
• Note that after the sign bit, the dot shown in
Figure implies the binary point.
• Example a. Find the signed Q-15
representation for the decimal number
0.560123.

We yield the Q-15 format representation as


0:100011110110010:
• In this way, it follows that (0.560123)x 215
=18354
• Converting 18354 to its binary representation
will achieve the same answer
• Example a. Find the signed Q-15 representation
for the decimal number 0.160123.
• Soln:Converting the Q-15 format for the
corresponding positive number with the same
magnitude using the procedure described in
previous example,
• we have 0.160123 =0.001010001111110: Then,
after applying 2’s complement, the Q-15
format becomes 0.160123= 1.110101110000010
• Example
• Convert the Q-15 signed number
1.110101110000010 to the decimal number.
Soln: Since the number is negative, applying the
2’s complement yields 0.001010001111110:
Then the decimal number is
• Convert the Q-15 signed number
0.100011110110010 to the decimal number.
Fixed-Point Digital Signal Processors
Floating-Point Processors
Finite Impulse Response and Infinite
Impulse Response Filter Implementations in Fixed-Point Systems

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