System Verilog

• We need to verify the design to make sure that the design is an accurate
representation of the specification without any bugs. Verification is
carried out to ensure the correctness of design, to avoid surprises at a
later time, to avoid a re-spin of the chip and to enter the market on time
with good quality.
• Hardware Description Languages (HDL) like Verilog and VHDL are used to
describe hardware behavior so that it can be converted to digital blocks
made up of combinational gates and sequential elements. In order to
verify that the hardware description in HDL is correct, there is a need for
a language with more features in OOP that will support complicated
testing procedures and is often called a Hardware Verification Language.
• SystemVerilog is an extension of Verilog with many such verification
features that allow engineers to verify the design using complex
testbench structures and random stimuli in simulation.
Introduction
• SystemVerilog is commonly used in the semiconductor.
It is a hardware description and hardware verification
language used to model, design, simulate testbench.
• SystemVerilog is based on Verilog and some
extensions.
Verification process
• In the process of verification, we are going to verify modules, SOC’s (System
On Chip) by driving the input to check the design behavior. we should check
the behavior of the design by driving correct and an error input, in both
cases need to observe the design as it is behaving as expected, if not then
there will be a bug.
In verification, we use the Testbench/Verification environment to determine
the correctness of the design under test (DUT).
below is the functionality of the Testbench/Verification environment,
• Generate stimulus
• Apply stimulus to the DUT
• Capture the response
• Check for the correctness
• Measure progress against the overall verification goals
WHY SYSTEM VERILOG ?
VERIFICATION FLOW:
Verification
flow
Testbench components
1.Transaction
2.Generator
3.Driver
4.Monitor
5.Agent
6.Scoreboard
7.Environment
8.Testbench top
9.Test
Transaction

• The transaction is a packet that is driven to the DUT or monitored by

the monitor as a pin-level activity.
• In simple terms, the transaction is a class that holds a structure that is
used to communicate with DUT.
Generator
• The generator creates or generates randomized transactions or stimuli
and passes them to the driver
Driver
• The driver interacts with DUT. It receives randomized transactions from
the generator and drives them to the driven as a pin level activity.
Monitor
• The monitor observes pin-level activity on the connected interface at
the input and output of the design. This pin-level activity is converted
into a transaction packet and sent to the scoreboard for checking
purposes.
Agent
• An agent is a container that holds the generator, driver, and
monitor. This is helpful to have a structured hierarchy based on the
protocol or interface requirement.
Scoreboard
• The scoreboard receives the transaction packet from the monitor
and compares it with the reference model. The reference module is
written based on design specification understanding and design
behavior.
Environment
• An environment allows a well-mannered hierarchy and container
for agents, scoreboards, coverage.
• Testbench top
• The testbench top is a top-level component that
includes interface and DUT instances. It connects design
with the testbench.
Difference between Verilog and system verilog

S.No. VERILOG SYSTEMVERILOG

SystemVerilog is a combination of both Hardware Description Language (HDL) and
01. Verilog is a Hardware Description Language (HDL). Hardware Verification Language (HVL).

SystemVerilog language is used to model, design, simulate, test and implement electronic
02. Verilog language is used to structure and model electronic systems. system.

03. It supports structured paradigm. It supports structured and object-oriented paradigm.

04. Verilog is based on module level testbench. SystemVerilog is based on class level testbench.

05. It is standardized as IEEE 1364. It is standardized as IEEE 1800-2012.

06. Verilog is influenced by C language and Fortran programming language. SystemVerilog is based on Verilog, VHDL and c++ programming language.

07. It has file extension .v or .vh It has file extension .sv or .svh

08. It supports Wire and Reg datatype. It supports various datatypes like enum, union, struct, string, class.

09. It is based on hierarchy of modules. It is based on classes.

10. It was began in 1983 as proprietary language for hardware modelling. It was originally intended as an extension to Verilog in the year 2005.
Data types
• 2 state data type: It has bits 0 and 1
• 4 state data type: It has bits 0, 1, X, and Z

Signed and Unsigned

• Unsigned: can hold positive values alone.
• Signed: can hold both positive and negative values.
• Logic
• Two-state data types
• Struct and union
• Enum
• String
Logic
• It is a new data type added in system Verilog
• Like reg data type in Verilog
• It is 4 state data type (x,z,0,1),Default value of logic is X
• No need to mention the direction (input or output), it
can be driven in both procedural and continuous
assignment.
• We can’t use for in-out
2-state data types
• In simulations for some signals, we want only 0 or 1
• Improves the simulation performance.
• Bit , byte(8-bit signed integer) , shortint(16-bit signed) ,
int (32-bit signed), longint(64-bit signed)
int 2 state data type, 32-bit signed integer
integer 4 state data type, 32-bit signed integer
shortint 2 state data type, 16-bit signed integer
longint 2 state data type, 64-bit signed integer
Integer 2 state data type, unsigned, user-defined
data bit
vector size

type byte
2 state data type, 8-bit signed integer or
ASCII character
4 state data type, unsigned, user-defined
logic
vector size
4 state data type, unsigned, user-defined
reg
vector size
4 state data type, 64-bit unsigned
time
integer
Struct
• This data-type allows you to create custom data-type
structure by grouping together by different data-type in
single name
• Ex-
Struct {
string name;
int age;
byte number }student_info;
• Packed structures -: Similar to a packed array, if memory
allocated for variables in a structure is contiguous, then it is
called a packed structure.
• Only packed data types are allowed in packed structures
• A string is not a packed data type, so code will not compile.
To use string as a data type in structure, unpack structures
can be used.
typedef struct packed {
bit[31:0] salary;
integer id;
} employee;
• Unpacked structures -:An unpacked structure is not
as memory efficient as packed data structures.
• By default, a structure is unpacked in nature
• Syntax -:
typedef struct {
string name;
bit[31:0] salary;
integer id } empluee;
module struct_example;
struct {
string name;
bit[31:0] salary;
integer id;
} employee;
initial begin
employee.name = "Alex";
employee.salary = 'h10000;
employee.id = 'd1234;
$display("employee: %p", employee);
// Accessing individual struct member
$display("employee: name = %s, salary = 0x%0h, id = %0d", employee.name, employee.salary, employee.id);
end
endmodule
Unions

• Unions are similar to structures that can contain

different data types members except they share the
same memory location. Hence, it is memory efficient
data structure. But it also restricts the user to use one
member at a time
• Syntax -:
typedef union {
bit[15:0] salary;
integer id;
} employee;
Typedef

• Typedef allows users to create their own names for type definitions that
they will use frequently in their code.
• Typedefs can be very convenient when building up complicated array
definitions.
Syntax -:
typedef reg[7:0] type_def_data;
Above typedef same as reg[7:0] a;
Enum

• SystemVerilog also introduces enumerated types, It is used to define a set of integral values that
represents the states or values
for example, Typedef enum {red, yellow, green} light1,light2;

Methods:
o first( )
o last( )
o next( )
o prev( )
o num( )

Enumerations allow you to define a data type whose values have names. Such data types are
appropriate and useful for representing state values, opcodes and other such non-numeric or
symbolic data.
Typedef is commonly used together with enum, like this:

light1 col;
String
• The string data type is an ordered collection of characters. The length of a string
variable is the no.of characters in the collection.
• Example:
string s0 = “hi aiit”;
string s1 = “hi\0aiit”;
bit[11:0] b = 12’ha41;
string s2 = string’(b);
• A single ASCII character requires 8-bits (1 byte) and to store a string we would need
as many bytes as there are number of characters in the string.
reg [16*8-1:0] my_string; // Can store 16 characters
my_string = "How are you"; // 5 zeros are padded from MSB, and 11 char
are stored
my_string = "How are you doing?"; // 19 characters; my_string will get "w are
you doing?"
String Operators
Returns 1 if the two strings
Equality Str1 == Str2 are equal and 0 if they are
not
Returns 1 if the two strings
Inequality Str1 != Str2 are not equal and 0 if they
are
Str1 < Str2
Returns 1 if the correspondig
Str1 <= Str2
Comparison condition is true and 0 if
Str1 > Str2
false
Str1 >= Str2
All strings will be
Concatenation {Str1, Str2, ..., StrN} concatenated into one
resultant string
Replicates the string N
Replication {multiplier{Str}} number of times, where N is
specified by the multiplier
Returns a byte, the ASCII
code at the given index. If
Indexing Str[index]
given index is out of range,
it returns 0
The dot(.) operator is used
Methods Str.method([args])
Real, shortreal, and realtime data types

• Real, shortreal, and realtime data types – Known as real variables.

• real – same as double datatype in C
• shortreal – same as a float in C
• realtime – interchangeably used with the real data type.

void data type

• Non-existence data is known as a void data type. It is usually used with functions where
it’s return type is void.
Event data type:
• System Verilog events provide handle to a synchronization object.
Example:
event e; // declaration of event
-> e; // triggering an event
@(event name); // do something when triggered
wait ( event name); // wait for the trigger to be happened
Event based synchronization:
Example:
gen data -> send data -> receive data -> compare data.
Assignment
• Check what is the default values for all data types
• Initialize all the data types to 0 and the check weather initialized
properly or not, finally overwrite the data to some decimal values
• Practice with the methods of typedef enum data types & strings