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NOP (code)

From Wikipedia, the free encyclopedia
This article is about the "No Operation" computer instruction. For Null statement, see Null function. For Do nothing instruction, see Do Nothing (disambiguation). For other uses, see NOOP (disambiguation) and NOP (disambiguation).
Machine code
General concepts
Instructions

In computer science, a NOP, no-op, or NOOP (pronounced "no op"; short for no operation) is a machine language instruction and its assembly language mnemonic, programming language statement, or computer protocol command that does nothing.

Machine language instructions

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Some computer instruction sets include an instruction whose purpose is to not change the state of any of the programmer-accessible registers, status flags, or memory. It often takes a well-defined number of clock cycles to execute. In other instruction sets, there is no explicit NOP instruction, but the assembly language mnemonic NOP represents an instruction which acts as a NOP; e.g., on the SPARC, sethi 0, %g0.

A NOP must not access memory, as that could cause a memory fault or page fault.

A NOP is most commonly used for timing purposes, to force memory alignment, to prevent hazards, to occupy a branch delay slot, to render void an existing instruction such as a jump, as a target of an execute instruction, or as a place-holder to be replaced by active instructions later on in program development (or to replace removed instructions when reorganizing would be problematic or time-consuming). In some cases, a NOP can have minor side effects; for example, on the Motorola 68000 series of processors, the NOP opcode causes a synchronization of the pipeline.[1]

Listed below are the NOP instruction for some CPU architectures:

CPU architecture Instruction mnemonic Bytes Opcode Notes
Intel x86 CPU family NOP 1 0x90[2] 0x90 is the one-byte encoding for XCHG AX,AX in 16-bit code and XCHG EAX,EAX in 32-bit code. In long mode, XCHG RAX,RAX requires two bytes, as it would begin with an REX.W prefix, making the encoding 0x48 0x90. However, 0x90 is interpreted as a NOP in long mode regardless of whether it is preceded by 0x48.[2]
multi-byte NOP 2–9 for Pentium Pro and later Intel processors, and all AMD AMD64 processors 0x66 0x90

0x0F 0x1F 0x00

0x0F 0x1F 0x40 0x00

0x0F 0x1F 0x44 0x00 0x00

0x66 0x0F 0x1F 0x44 0x00 0x00

0x0F 0x1F 0x80 0x00 0x00 0x00 0x00

0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00

0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00[2]

0x66 is the operand-size override prefix.

0x0F 0x1F is a two-byte NOP opcode that takes a ModR/M operand upon which no memory is accessed and no registers are written. Operands added to this are:

0x00 is [EAX]

0x40 0x00 is [EAX + 00H]

0x44 0x00 0x00 is [EAX + EAX*1 + 00H]

0x80 0x00 0x00 0x00 0x00 is [EAX + 00000000H]

0x84 0x00 0x00 0x00 0x00 0x00 is [EAX + EAX*1 + 00000000H][2]

Intel 8008 LAA 1 0xC0 Load A from A
Intel 8051 / MCS-51 family NOP 1 0x00
Intel 8080, Intel 8085, Z80 NOP 1 0x00
Intel i860 NOP 4 0xA0000000 Core no-operation. Opcode for shl r0,r0,r0, an instruction to left-shift the all-0s register by itself.[3]
FNOP 4 0xB0000000 Floating-point no-operation. Opcode for shrd r0,r0,r0, a shift-right-double instruction that takes the all-0s register as input and output.[3]
Intel i960 MOV g0,g0 4 0x5C801610 Move global register g0 to itself. Suggested opcode for cases where a no-op is needed.[4]
Intel IA-64 (Itanium) (qp) NOP.b imm21 41 bits 0x04000000000 On IA-64, the NOP instruction has five forms, each of which can be executed only on a particular execution unit type.[5]

All five NOP forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s - which is common but not required).

The NOP.x form of the instruction additionally consumes a second 41-bit instruction slot - the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits.

(qp) NOP.f imm21 41 bits 0x00008000000
(qp) NOP.i imm21
(qp) NOP.m imm21
(qp) NOP.x imm62 41+41 bits 0x00008000000 imm41
32-bit ARM (A32) NOP 4 0x*320F000 Architectural ARM A32 NOP ("true" nop, with no register dependencies). Introduced with ARMv6K (ARM 1176, released in 2003), and present in all later ARM A32 processors. (The * indicates a 4-bit field that may take any value other than 0xF.)[6]
MOV r0,r0/NOP 4 0xE1A00000 Recommended A32 no-operation encoding for older 32-bit ARM processors that pre-date ARMv6K. Assemblers for A32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6K or later versions of the ARM architecture.[7][8]
ANDEQ r0,r0,r0 4 0x00000000 Bitwise-AND r0 with itself if equal. Commonly used no-op encoding due to the simplicity of its encoding.[9]
MOVNV r0,r0 4 0xF1A00000 Move r0 to itself never. Obsolete no-op encoding that used to be recommended for the ARM2/ARM3 processors in older Acorn Archimedes computers.[9][10] Makes use of the NV ("never") condition code — which has been deprecated since 1993,[11] with support fully removed with ARMv5.[12]
Thumb MOV r8,r8/NOP 2 0x46C0 Recommended Thumb no-operation encoding for older 32-bit Thumb processors that pre-date ARMv6T2. Assemblers for T32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6T2 or later versions of the ARM Thumb architecture.[7][8]
Thumb-2 (T32) NOP 2 0xBF00 Architectural ARM T32 (Thumb-2) NOPs ("true" nops, with no register dependencies). Introduced with ARMv6T2 (ARM 1156, released in 2003), and present in all later ARM T32 processors.[6]
NOP.W 4 0xF3AF8000
64-bit ARM (A64) NOP 4 0xD503201F Architectural NOP.
DEC Alpha NOP 4 0x47FF041F Integer NOP. Opcode for BIS r31,r31,r31, an instruction that bitwise-ORs the always-0 register with itself.[13]
FNOP 4 0x5FFF041F Floating-point NOP. Opcode for CPYS f31,f31,f31, an instruction that performs copy-sign with the always-0 register as source for both sign and exponent/mantissa, and stores the result in the always-0 register.[13]
UNOP 4 0x2FFE0000 Universal NOP. Opcode for LDQ_U r31,0($sp). The LDQ_U (unaligned load) opcode is, on 21164 and later, special-cased so that when used with the always-0 register as a destination register, no memory access is performed.[13][14] The address register and displacement may take any value, but is most commonly given as 0($sp) which is stack pointer + zero.[15]
AMD 29k NOP 4 0x70400101 Opcode for aseq 0x40,gr1,gr1, an instruction that asserts that the stack register is equal to itself.[16]
AVR NOP 2 0x0000 one clock cycle
COP400 NOP 1 0x44
COP8 NOP 1 0xB8
IBM System/360, IBM System/370, IBM System/390, z/Architecture, UNIVAC Series 90 NOP 4 0x47000000 or 0x470nnnnn or 0x47n0nnnn where "n" is any 4-bit value. The NOP ("No-Op") and NOPR ("No-Op Register") are a subset of the "Branch on Condition" or "Branch on Condition Register" instructions, respectively; both versions have two options for generating a NO-OP.

In the case of both the NOP and NOPR instructions, the first 0 in the second byte is the "mask" value, the condition to test such as equal, not equal, high, low, etc. If the mask is 0, no branch occurs.

In the case of the NOPR instruction, the second value in the second byte is the register to branch on. If register 0 is chosen, no branch occurs regardless of the mask value. Thus, if either of the two values in the second byte is 0, the branch will not happen. If the first 0 in the second byte is 0, the value of the second value in the second byte is irrelevant on most processors; however, on the IBM System/360 Model 91, if that value refers to register 15, the instruction will wait for all previously-decoded instructions to complete before continuing.[17]

In the case of the NOP instruction, the second value in the second byte is the "base" register of a combined base register, displacement register and offset address. If the base register is also 0, the branch is not taken regardless of the value of the displacement register or displacement address.

NOPR 2 0x0700 or 0x070n or 0x07n0 where "n" is any 4-bit value.
LoongArch NOP 4 0x03400000 Opcode for andi r0,r0,0, an instruction that bitwise-ANDs the always-0 register with zero.[18]
MIPS NOP 4 0x00000000 Stands for sll r0,r0,0, meaning: Logically shift register 0 zero bits to the left and store the result in register 0. Writes to register 0 are ignored; it always contains 0.
MIPS-X NOP 4 0x60000019 (extended opcode for add r0,r0,r0)
MIX NOP 1 word ± * * * * 0 The * bytes are arbitrary, and can be anything from 0 to the maximum byte (required to be in the range 63-99). MIX uses sign-magnitude representation.
MMIX SWYM 4 0xFD****** SWYM stands for "Sympathize with your machinery". The * digits can be chosen arbitrarily.
MOS Technology 65xx (e.g. 6502) NOP 1 0xEA NOP consumes two clock cycles. Undefined opcodes in the NMOS versions of the 65xx family were converted to be NOPs of varying instruction lengths and cycle times in the 65C02.
Motorola 6800 NOP 1 0x01
Motorola 68000 family NOP 2 0x4E71 This synchronizes the pipeline and prevents instruction overlap.[1]: 3-21 [1]: 4-147 
TRAPF,
TRAPF.W #data,
TRAPF.L #data 		2,
4,
6 		0x51FC,
0x51FA 0xnnnn,
0x51FB 0xnnnn 0xnnnn 		Trap if false.

Suggested opcode for 68020 and later 68k processors if a NOP without pipeline synchronization is desired. ('n' may take any 4-bit value.)[1]: 3-21 [1]: 4-189 

Motorola 6809 NOP 1 0x12
Motorola 88000 family BCND lt0,r0,X,
ADD r0,r0,r0,
TB1 0,r0,x 		4 0xE980xxxx,
0xF4007000,
0xF000D8xx 		Branch if always-0 register is less than 0,
Add always-0 register to itself,
Trap if bit 0 of always-0 register is 1 (serializing).[19]
MSP430 NOP 2 0x4303 Opcode for mov #0,r3 or mov r3,r3, an instruction that performs a move from a "constant generation register" to itself.[20]
PA-RISC NOP 4 0x08000240 Opcode for OR 0,0,0.[21]
LDI 26,0 4 0x34000034 Palindromic NOP - that is, an instruction that executes as NOP regardless of whether byte order is interpreted as little-endian or big-endian. Some PA-RISC system instructions are required to be followed by seven palindromic NOPs.[21]
PDP-10 JFCL 0, (conventional)
JUMP, SETA, SETAI, CAI, TRN, TLN 		1 word 25500******* (octal) Jump never
Jump never, set nothing, skip never
PDP-11 NOP 2 000240 (octal) Clear none of the condition codes
PIC microcontroller NOP 12 bits 0b000000000000
POWER, PowerPC, Power ISA NOP 4 0x60000000 Opcode for ori r0,r0,0.

Under the Power ISA, many apparent no-op instruction encodings have significant side-effects − therefore, no-op encodings other than ori r0,r0,0 should be carefully avoided unless these side-effects are specifically intended. For example:[22]

  • ori r31,r31,0 is a serializing instruction.
  • or rX,rX,rX with X=1,2,3,5,6,7 or 31 sets thread priority based on X.
  • or r26,r26,r26 is a memory store writeback hint.
  • xori r0,r0,0 is an explicitly unoptimized no-op for use in timing-loops.
  • and rX,rX,rX with X=0,1 are performance-probe no-ops.
  • or rX,rX,rX with X=28,29,30,31 will stall instruction dispatch for a fixed number of CPU cycles on IBM PPE based processors.[23]
  • ori rX,rX,0 with X=1,2 are "group ending NOP"s in some POWER CPUs[24][25]
RISC-V NOP 4 0x00000013 ADDI x0, x0, 0
C.NOP 2 0x0001 C.ADDI x0, 0. Only available on RISC-V CPUs that support the "C" (compressed instructions) extension.[26]
Signetics 8X300 MOV AUX, AUX 16 bits 0x0000 Move AUX to AUX with no rotate
SPARC NOP 4 0x01000000 Stands for sethi 0, %g0 which zeroes the hardwired-to-zero %g0 register[27]
Sunplus S+core NOP 4 0x80008000 Architectural NOPs[28]
NOP! 2 0x0000
SuperH NOP 2 0x0009 [29]
NOP 4 0x6FF0FFF0 32-bit NOP, present on SH-5 only.[30]
Tensilica Xtensa NOP, _NOP 3 0x0020F0 Assemblers may convert "NOP" to "NOP.N" - the "_NOP" mnemonic (with a leading underscore) can be used to prevent such conversion.[31]
NOP.N 2 0xF03D
VAX NOP 1 0x01 Delay is dependent on processor type
WD16 NOP 2 0x0000

From a hardware design point of view, unmapped areas of a bus are often designed to return zeroes; since the NOP slide behavior is often desirable, it gives a bias to coding it with the all-zeroes opcode.

Code

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A function or a sequence of programming language statements is a NOP or null statement if it has no effect. Null statements may be required by the syntax of some languages in certain contexts.

Ada

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In Ada, the null statement serves as a NOP.[32] As the syntax forbids that control statements or functions be empty, the null statement must be used to specify that no action is required. (Thus, if the programmer forgets to write a sequence of statements, the program will fail to compile.)

C and derivatives

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The simplest NOP statement in C is the null statement, which is just a semi-colon in a context requiring a statement.

Most C compilers generate no code for null statements, which has historical and performance reasons. 

  ;

An empty block (compound statement) is also a NOP, and may be more legible, but will still have no code generated for it by the compiler. 

  {}

In some cases, such as the body of a function, a block must be used, but this can be empty. In C, statements cannot be empty—simple statements must end with a ; (semicolon) while compound statements are enclosed in {} (braces), which does not itself need a following semicolon. Thus in contexts where a statement is grammatically required, some such null statement can be used.

The null statement is useless by itself, but it can have a syntactic use in a wider context, e.g., within the context of a loop: 

  while (getchar() != '\n') {}

alternatively, 

  while (getchar() != '\n')
      ;

or more tersely: 

  while (getchar() != '\n');

(note that the last form may be confusing, and as such generates a warning with some compilers or compiler options, as semicolon usually indicates an end of function call instruction when placed after a parenthesis on the end of line).

The above code continues calling the function getchar() until it returns a \n (newline) character, essentially fast-forwarding the current reading location of standard input to the beginning of next line.

Fortran

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In Fortran, the CONTINUE statement is used in some contexts such as the last statement in a DO loop, although it can be used anywhere, and does not have any functionality.

JavaScript

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The JavaScript language does not have a built-in NOP statement. Many implementations are possible:

  • Use the ; empty statement[33] or the {} empty block statement the same way as in the C and derivatives examples;
  • Use the undefined or the null expression as a complete statement (an expression statement) when the previous methods are not allowed by the syntax.

Alternatives, in situations where a function is required, are:

  • Use the Function.prototype() built-in function, that accepts any arguments and returns undefined;[34]
  • Use a NOP function available in a third-party library —see below;
  • Define a custom NOP function, as in the following example (using the ES6 arrow function syntax):
const noop = () => {};

AngularJS

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The AngularJS framework provides angular.noop function that performs no operations.

jQuery

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The jQuery library provides a function jQuery.noop(), which does nothing.[35]

Lodash

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The Lodash library provides a function _.noop(), which returns undefined and does nothing.[36]

Pascal

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As with C, the ; used by itself can be used as a null statement in Pascal. In fact, due to the specification of the language, in a BEGIN / END block, the semicolon is optional before the END statement, thus a semicolon used there is superfluous.

Also, a block consisting of BEGIN END; may be used as a placeholder to indicate no action, even if placed inside another BEGIN / END block.

Python

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The Python programming language has a pass statement which has no effect when executed and thus serves as a NOP. It is primarily used to ensure correct syntax due to Python's indentation-sensitive syntax; for example the syntax for definition of a class requires an indented block with the class logic, which has to be expressed as pass when it should be empty.

Shell scripting (bash, zsh, etc.)

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The ':' [colon] command is a shell builtin that has similar effect to a "NOP" (a do-nothing operation). It is not technically an NOP, as it changes the special parameter $? (exit status of last command) to 0. It may be considered a synonym for the shell builtin 'true', and its exit status is true (0).[37][38][39]

TeX macro language (ConTeXt, LaTeX, etc.)

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The TeX typographical system's macro language has the \relax command.[40] It does nothing by itself, but may be used to prevent the immediately preceding command from parsing any subsequent tokens.[41]

NOP protocol commands

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Many computer protocols, such as telnet, include a NOP command that a client can issue to request a response from the server without requesting any other actions. Such a command can be used to ensure the connection is still alive or that the server is responsive. A NOOP command is part of the following protocols (this is a partial list):

Note that unlike the other protocols listed, the IMAP4 NOOP command has a specific purpose—it allows the server to send any pending notifications to the client.

While most telnet or FTP servers respond to a NOOP command with "OK" or "+OK", some programmers have added quirky responses to the client. For example, the ftpd daemon of MINIX responds to NOOP with the message:[42] 

200 NOOP to you too!

Cracking

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NOPs are often involved when cracking software that checks for serial numbers, specific hardware or software requirements, presence or absence of hardware dongles, etc. in the form of a NOP slide. This process is accomplished by altering functions and subroutines to bypass security checks and instead simply return the expected value being checked for. Because most of the instructions in the security check routine will be unused, these would be replaced with NOPs, thus removing the software's security functionality without altering the positioning of everything which follows in the binary.

Security exploits

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The NOP opcode can be used to form a NOP slide, which allows code to execute when the exact value of the instruction pointer is indeterminate (e.g., when a buffer overflow causes a function's return address on the stack to be overwritten).

See also

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References

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  1. ^ a b c d e Motorola 68000 Programmer's Reference Manual (PDF).
  2. ^ a b c d "Intel 64 and IA-32 Architectures Software Developer's Manual: Instruction Set Reference A-Z". Retrieved 2012-03-01.
  3. ^ a b i860 64-bit Microprocessor Programmer's Reference Manual (PDF). Intel. February 1989. pp. 68, 172. order no. 240329-002.
  4. ^ i960 Hx Microprocessor Developer's Manual] (PDF). Intel. September 1998. see appendix B on p. 487 and appendix C on pp. 495-497 for instruction encoding, and appendix E.2.7.8 on p. 575 for the use of MOV g0,g0 as a padding-NOP. order no. 272484-002. Archived from the original (PDF) on 15 April 2003.
  5. ^ Intel Itanium Architecture Software Developer's Manual rev 2.3 (PDF). Intel. May 2010. Book 3 section 2.2 on page 1092, section 4.3.4.1 on page 1218, section 4.4.11 on page 1248, section 4.5.3.2 on page 1255, section 4.6.9.2 on page 1264 and section 4.7.4 on page 1267. Archived (PDF) from the original on 8 December 2011.
  6. ^ a b ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition. ARM. 29 March 2018. section A8.8.120 on page 511. ARM DDI 0406C.d. Archived from the original on 27 September 2023.
  7. ^ a b ARM Software Development Toolkit Version 2.50 Reference Guide. ARM. November 1998. see sections 5.5.6 and 5.6.4 for NOPs in ARM/Thumb assembly. ARM DUI 0041C. Archived from the original on 1 June 2022.
  8. ^ a b "NOP instruction". ARM Compiler toolchain Assembler Reference v5.03. ARM. Archived from the original on 16 March 2025.
  9. ^ a b O. Smith (12 December 1996). "StrongARM multiply speed". Newsgroup: comp.sys.arm. Archived from the original on 16 March 2025.
  10. ^ Acorn Assembler Release 2 (PDF). Acorn Computers. May 1991. MOVNV listed on page 218. Archived (PDF) from the original on 25 Oct 2018.
  11. ^ ARM610 32 Bit RISC Microprocessor (PDF). ARM. August 1993. p. 20. ARM DDI 0004D.
  12. ^ ARM Architecture Reference Manual (PDF). ARM. February 2000. section 3.2.1 on page 69. ARM DDI 0100D. Archived (PDF) from the original on 16 March 2025.
  13. ^ a b c Alpha Architecture Handbook version 4 (PDF). Compaq. October 1998. see section A.4.4.1 on p.285 for NOP forms and sections 3.3 on p.50 and C.1 on p.303 for instruction encodings. order no: EC–QD2KC–TE. Archived from the original (PDF) on 27 August 2004.
  14. ^ JH Edmondson (April 1995). "Superscalar Instruction Execution in the 21164 Alpha Microprocessor" (PDF). p. 6. Archived (PDF) from the original on 5 January 2023.
  15. ^ Digital UNIX Assembly Language Programmer's Guide (PDF). Digital. March 1996. see section C.7 on p.219. order no. AA-PS31D-TE. Archived from the original (PDF) on 1 October 2000.
  16. ^ AMD, "Am29050 Microprocessor User's Manual" (PDF). 1991. pp. 223, 257.
  17. ^ "IBM System/360 Model 91 Functional Characteristics" (PDF). Systems Reference Library. IBM. p. 16. Retrieved 17 January 2025.
  18. ^ LoongArch Reference Manual, Volume 1: Basic Architecture, version 1.10 (PDF). Loongson. Section 2.2.1.10 on page 23 and appendix B on page 190.
  19. ^ MC88110 32-bit Microprocessor Design Specification, Revision 2.0 (PDF). Motorola. see section 2.1.2.3 on page 11 for a listing of recommended NOPs, and pages 10, 170 and 171 for instruction encodings. Archived (PDF) from the original on 19 March 2025.
  20. ^ MSP430F2xx, MSP430G2xx Family User's Guide (PDF). Texas Instruments. December 2004. sections 3.24 on page 47, 3.4.5 on page 63, 3.4.6.33 on page 98. Archived (PDF) from the original on 1 September 2022.
  21. ^ a b PA-RISC 2.0 Architecture (PDF). Hewlett-Packard. 1995. pp. 2–21, 7–103. Archived from the original (PDF) on June 21, 2020.
  22. ^ Power ISA version 3.1C (PDF). OpenPOWER Foundation. 26 May 2024. Book 1 section 3.3.13 on pages 97-99; book 2 section 3.2 on page 987 and section 4.3.3 on page 1005; book 3 section 5.4.3 on page 1100, section 9.2.1 on page 1244 and section 11.3 on page 1253. Archived from the original (PDF) on 10 September 2024.
  23. ^ Cell Broadband Engine Programming Handbook, version 1.1 (PDF). IBM. 24 April 2007. section 10.6.2.2 on page 316. Archived (PDF) from the original on 24 May 2008.
  24. ^ "SCINET Briefing: Compiling for Power6" (PDF). IBM. February 2009. slide 9. Archived (PDF) from the original on 23 March 2025.
  25. ^ POWER8 Processor User's Manual for the Single-Chip Modul, version 1.3 (PDF). IBM. 16 March 2016. Section 10.1.8 on page 209. Archived (PDF) from the original on 28 December 2018.
  26. ^ The RISC-V Instruction Set Manual, Volume 1: User-Level ISA, version 2.2 (PDF). RISC-V Foundation. 7 May 2017. p. 79.
  27. ^ Weaver, D. L.; Germond, T., eds. (1994). The SPARC Architecture Manual, Version 9 (PDF). Prentice Hall. ISBN 0-13-825001-4. Archived from the original (PDF) on 2012-01-18. Retrieved 2014-01-09. Note that NOP is a special case of the SETHI instruction, with imm22 = 0 and rd = 0.
  28. ^ "S+core7 Programming Guide v1.4" (PDF). Sunplus Technology Co. Ltd. 22 March 2007. pp. 12, 90, 166. Archived from the original (PDF) on 15 November 2012.
  29. ^ SH-5 CPU Core, Volume 3: SHcompact (PDF). SuperH Inc. 22 February 2002. p. 219. Archived from the original (PDF) on 20 March 2009.
  30. ^ SH-5 CPU Core, Volume 2: SHmedia (PDF). SuperH Inc. 22 February 2000. p. 260. Archived from the original (PDF) on 20 March 2009.
  31. ^ Xtensa Instruction Set Architecture Reference Manual (PDF). Tensilica. April 2010. pp. 459–460. Archived (PDF) from the original on 5 March 2016.
  32. ^ Ada Reference Manual. Dynamic Semantics. The execution of a null_statement has no effect.
  33. ^ "Empty statement". Mozilla Developer Network JavaScript reference. 13 March 2025. The empty statement is a semicolon (;) indicating that no statement will be executed, even if JavaScript syntax requires one.
  34. ^ "Properties of the Function Prototype Object". ECMAScript Language Specification – Edition 5.1.
  35. ^ jQuery.noop() from jQuery API documentation
  36. ^ "Lodash Documentation". lodash.com. Retrieved 2017-12-15.
  37. ^ "Chapter 3. Special Characters". Advanced Bash-Scripting Guide.
  38. ^ bash manpage > SHELL BUILTIN COMMANDS
  39. ^ zsh manpage (zshbuiltins) > SHELL BUILTIN COMMANDS
  40. ^ Bausum, David (2002). "TeX Primitive Control Sequences". TeX Reference Manual. Kluwer Academic Publishers. Retrieved 1 April 2020. According to The TeXbook, 'TeX does nothing' when it encounters \relax. Actually, \relax may tell TeX, 'This is the end of what you've been doing'.
  41. ^ TeX wikibook – relax
  42. ^ "ftpd.c". Retrieved 2016-06-19.
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