SU510782A1 - Cyclic code encoding device - Google Patents

Description

and

The invention relates to a data transmission technique and can be used in group data transmission systems.

A cyclic coding device (CODES, containing summators modulo 2 AND shift register.

However, the known device, when used in group information transmission systems serving a large number of channels, is characterized by an unproductive waste of time on shifting information in the shift register during division, which reduces its speed.

The purpose of the invention is to increase the speed of the device.

This is achieved by the fact that a block of memory is inserted into the proposed device, the outputs of the k bits of which are connected via the adders to the inputs of the corresponding bits of the cd1VA | These, the first "of which is the input of the device, in addition, the output of the +1 bit of the memory block through the first adder is connected simultaneously to the second inputs of all k-1 adders modulo 2.

The drawing shows a structural electrical circuit of the proposed device.

Cyclic code encoding device

consists of memory block 1, the number of memory cells in which is equal to the number of data paths of the data, the shift register 2 with parallel input-output information,

whose width is paiBHa of the degree of the generating polynomial k, adders 3 modulo 2. The outputs of the memory block 1, from which information is removed when read, are connected to the same inputs of the bits of the register 2, i.e. the i-th output of the memory block is connected to the input of the i-th register bit. The output of the i-ro bit of register 2 is connected to the input of memory 1, to which information is fed during recording. In particular, depending on the structure (formula) of the generating polynomial of the connections x, adders are included: 3 modulo- 2. The second input of each adder 3, except the first, is given a signal iC of the output of the first sum of the matrix 3, and one of

the inputs of the first adder 3 is connected to the outputs of the memory unit 1.

Since the formula of the generating polynomial can be different, adders 3 modulo 2 can stand in different circuits according to the formula of the generating polynomial. The drawing shows adders 3 in all bits, although in each particular circuit the number and 1 place of switching on adders 3 is determined by the particular generating polynomial.

The device works as follows.

When working in multiplex mode, each subscriber receives one bit of information for one switching on for the data channel. When the device is connected to the "a; to whom or the direction of data transfer, the following actions are performed.

The information is read from the memory location of the memory block 1 corresponding to the data transmission direction to the shift register 2. In this case, the information passes through the adders 3 modulo 2. The information from register 2 is then written to the same cell of memory 1, and the first bit of memory cell 1 is written to a bit of information that is output simultaneously to a binary data transfer.

Due to the communication structure (| memory block and register and memory block), during one cycle of accessing one cell of memory block 1 (reading, writing), the information in this cell is divided into a generating polynomial and shifted by one bit. and the next bit of information is recorded in the younger bit of the cell. When dividing, the shift effect does not occur due to a special shift operation in shift register 2, but due to the structure of communications (from memory block 1 memory block 1 —with one bit shift; however, the shift does not require time-consuming, which gives an increase in the speed of the device.

Claims (1)

Invention Formula A cyclic code coding device comprising modulators "2" and a shift register, different in that in order to increase the speed, it introduced a checkpoint, a mti, the outputs of the k bits of which, through the coolants, are connected to the inputs of the corresponding bits of the shift register, and the outputs of the shift register bits, in its the queue is connected to the inputs of the corresponding bits of the memory block, the first of which is the input of the device, in addition, the output k - {- l bits of the memory block through the first adder is connected simultaneously to the second inputs of all k-1 MODULER adders “2.